Digital down conversion design method of ride-free architecture

Abstract

The application discloses a digital down conversion design method of a ride-free architecture, belongs to the field of digital down conversion, and inputs a digital intermediate frequency signal, which is down-converted to a baseband by a mixing module, and then is subjected to a low-pass digital decimation filter module to complete a down-sampling function and filter out high-frequency components. In wideband / narrowband channel multiplexing high-speed sampling, in order to reduce the mixing operation complexity and take into account subsequent signal processing, the relationship between the local oscillator signal frequency and the sampling frequency of the radio frequency receiving system is coordinated, the carrier frequency of the intermediate frequency signal is set as f LO =f s / 8, and the frequency band of interest is down-converted to a low-frequency band; the integrator module in the CIC filter is subjected to polyphase decomposition, and 12 times decimation is realized after being converted into 4-way parallel data. The comb filter module adopts a half-byte serial algorithm and multiplexing technology, so as to reduce power consumption and area; the four-way parallel signals after filtering are subjected to linear combination, and the CSD coding algorithm is utilized, so as to finally linearly combine the 4-way data to separate real and imaginary signals.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of digital down conversion, and particularly relates to a digital down conversion design method of a multiplication-free architecture. BACKGROUND

[0002] With the rapid development of integrated circuit technology and signal processing technology, oversampling Sigma-Delta analog-to-digital converter (ADC) becomes an effective choice for data conversion. Unlike traditional ADCs with Nyquist frequency limitation, oversampling ADCs sample analog signals at a sampling rate higher than the Nyquist rate. Not only do they have smaller silicon area, lower power consumption and higher resolution, but also have efficient architecture and are easy to implement in VLSI technology.

[0003] The digital down conversion module, as an important module in the Sigma-Delta ADC, needs to improve the mixing module in terms of area and power consumption to meet the requirements of efficient design. Usually, an NCO (Numerical Controlled Oscillator) module is used to generate a digital quadrature local oscillator signal, which is multiplied by the input intermediate frequency digital signal to complete the mixing operation. The look-up table method and the CORDIC (Coordinate Rotation Digital Compute) algorithm are usually used to generate the carrier signal. Using the look-up table method to generate discrete sine and cosine signals is the simplest, but it consumes too many hardware resources. Using the CORDIC algorithm to implement the NCO does not require a multiplier, but the introduction of the pipeline increases the system delay and also consumes a large amount of logic resources, and there is quantization error.

[0004] In wideband / narrowband channel multiplexing high-speed sampling, in order to reduce the complexity of the mixing operation and take into account the subsequent signal processing, it is urgent to design a multiplication-free architecture digital down conversion. SUMMARY

[0005] The present application aims to provide a multiplication-free architecture digital down conversion design method to solve the problems of consuming too many resources and system delay in implementing the mixing module based on the look-up table method or the CORDIC algorithm in traditional digital down conversion.

[0006] To solve the above technical problems, the present application provides a multiplication-free architecture digital down conversion design method, which comprises a mixing module and a low-pass digital decimation filter module.

[0007] The input digital intermediate frequency signal is down-converted to baseband by the mixing module, and then the low-pass digital decimation filter module is used to complete the down-sampling function and filter out high-frequency components.

[0008] In one implementation, down-converting the signal of interest to baseband via a mixer module includes the following steps:

[0009] S11. In the downconversion process, discretized sine and cosine signals are generated by the NCO, and their expressions are as follows:

[0010]

[0011]

[0012] Where n takes values ​​of 0, 1, 2, ..., f s f is the sampling rate of the signal stream to be processed. LO The local carrier signal frequency;

[0013] S12, Take carrier frequency f LO =f s / 8, with a phase shift of 0, the discretized negative sine carrier signal and cosine carrier signal are respectively and Since the amplitude of the sine and cosine signals is 0, ±1 can convert a periodic carrier signal into a linear combination as shown in the following equation:

[0014]

[0015]

[0016] Within a 2π period, the amplitude values ​​of the four signals A, B, C, and D are all combinations of 0 and ±1, where A is (1,0,0,0,-1,0,0,0), B is (0,1,0,0,0,-1,0,0), C is (0,0,1,0,0,0,-1,0), and D is (0,0,0,1,0,0,0,-1).

[0017] S13. Observe the characteristics of sequences A, B, C and D, extract 1 and -1 from the four sequences, and convert the four sequences into one sequence (1,1,1,1,-1,-1,-1,-1,-1). This sequence is used as a carrier signal and will be multiplied with the input data stream. Due to the special nature of the carrier signal amplitude, the multiplication operation can be avoided by periodically inverting the input data, thus completing the mixing.

[0018] In one implementation, the process of performing downsampling and filtering out high-frequency components via a low-pass digital decimation filter module includes the following steps:

[0019] S21. Using the CIC decimation filter as the first-stage low-pass digital filter, since the integrator module of the CIC decimation filter will cause data overflow, the maximum bit width inside the CIC decimation filter is determined according to equation (5):

[0020] B max =Nlog2 (RM) +B in (5)

[0021] wherein, B in is the input signal word length, R is the decimation multiple, N is the cascade number, and M is the delay factor. In addition, Nlog2 (RM) needs to be rounded up;

[0022] S22, the integrator cascade number N is configured as 4, and the transfer function H(z) thereof is obtained as:

[0023]

[0024] Z-transformation is a mathematical transformation on a discrete sequence, which utilizes the sparsity of integral chain data, wherein N is 4, and polyphase decomposition is performed on the CIC filter, as follows:

[0025]

[0026] wherein:

[0027] P0(Z) = 1 + 31Z -4 + 31Z -8 + Z -12 (8)

[0028] P1(Z) = 4 + 40Z -4 + 20Z -8 (9)

[0029] P2(Z) = 10 + 44Z -4 + 10Z -8 (10)

[0030] P3(Z) = 20 + 40Z -4 + 4Z -8 (11)

[0031] S23, the four-way parallel data P0, P1, P2 and P3 after polyphase decomposition are down-sampled and decimated;

[0032] S24, based on the principle of half-byte serial algorithm, each data in the four-way parallel data after decimation is sequentially split from LSB to MSB into four data serial outputs with consistent bit width, so as to optimize the bit width inside the register, and finally output four-way parallel data S0, S1, S2 and S3;

[0033] S25, the comb filter module filters the four parallel input data streams S0, S1, S2, and S3, with a delay factor M configured to 1. Since a half-byte serial algorithm is used to split the extracted data, the state equation is as follows:

[0034] y(n)=x(n)-x(n-4) (12)

[0035] S26. Perform serial-to-parallel conversion on the four parallel data F0, F1, F2 and F3 output by the comb filter module, and recombine each of the four data into a complete data to obtain the four parallel recombined data channels 0, 1, 2 and 3.

[0036] S27. The recombined four parallel data channels 0, 1, 2, and 3 are linearly combined according to equations (3) and (4) to separate the real data stream Q and the imaginary data stream I. By performing fixed-point quantization on the coefficients, the linear combination formula is obtained as follows:

[0037] I=239*channel0+169*channel1-169*channel3 (13)

[0038] Q=-239*channel2-169*channel1-169*channel3 (14).

[0039] In the multiplication-free digital downconversion design method provided by this invention, the carrier frequency f of the local oscillator signal is configured by coordinating the relationship between the local oscillator signal frequency and the sampling frequency of the radio frequency receiving system. LO =fs / 8, which lowers the frequency band of interest to a lower frequency band; in addition, combining the mixer module with the digital decimation filter module can effectively reduce design complexity and design cost. This invention achieves a design trade-off with the goal of reducing area and power consumption, and uses an integral comb filter (CIC) without multipliers or coefficient memory, which only requires addition / subtraction operations, as the first-stage filter of the digital decimation filter, which can reduce design complexity and storage requirements. Attached Figure Description

[0040] Figure 1 This is a structural diagram of a digital downconverter with a no-passenger-passenger architecture provided by the present invention;

[0041] Figure 2 It is the overall structure of the mixer module;

[0042] Figure 3 This is a diagram of a traditional mixer and a digital filter structure;

[0043] Figure 4 is the structure diagram of improved mixing and digital filter;

[0044] Figure 5 is the structure diagram of improved mixing and digital filter;

[0045] Figure 6 is the overall structure diagram of CIC decimation filter;

[0046] Figure 7 is the implementation structure diagram of traditional CIC decimation filter;

[0047] Figure 8 is the structure diagram of integrator;

[0048] Figure 9 is the structure diagram for comb filter. DETAILED DESCRIPTION

[0049] The digital down conversion design method of the ride-free architecture is further described in detail below in combination with the drawings and specific embodiments. The advantages and features of the present application will be more apparent according to the following description. It should be noted that the drawings are very simplified and use non-precise proportions, only for the purpose of conveniently and clearly assisting the description of the embodiments of the present application.

[0050] For a specific digital signal processing system, the signal frequency and bandwidth are usually fixed, and by reasonably designing the system working clock, complex operations and large resource consumption can be avoided during frequency conversion processing, and real-time and efficient frequency conversion processing can be completed.

[0051] The present application provides a digital down conversion design method of ride-free architecture, as shown in Figure 1 The overall structure diagram of digital down conversion is shown, the input digital intermediate frequency signal is down-converted to baseband by the mixing module, and then the low-pass digital decimation filter module is used to complete the down-sampling function and filter out high-frequency components.

[0052] The mixing module is shown in Figure 2 NCO (numerical control oscillator) generates discrete sine and cosine signals. Let f s be the sampling rate of the signal stream to be processed, f LO be the local carrier signal frequency, then T s = 1 / f s , t = n*T s , the discrete sine y(n) and cosine x(n) signal expressions are respectively:

[0053]

[0054]

[0055] As Figure 3 shown, if the sampling frequency is 8 times the local oscillator frequency, i.e. f s = 8f LO , the discrete cosine carrier signal is The value of n is an integer, and in a period, there are:

[0056]

[0057] The added sinusoidal discrete signal is In a period, there are:

[0058]

[0059] It is observed from equations (3) and (4) that the amplitude value is 0, ±1 combination, in a period, the carrier signal can be converted to amplitude 0 and ±1 combination and multiplied by , as shown in equations (5) and (6):

[0060]

[0061]

[0062]

[0063] From equations (5) and (6), the sequences E, F, H, G are as follows:

[0064] E: 1 0 0 0 -1 0 0 0

[0065] F: 0 1 0 -1 0 -1 0 1

[0066] G: 0 0 -1 0 0 0 1 0

[0067] H: 0 -1 0 -1 0 1 0 1

[0068] Substituting sequences E, F, H, G into equations (3) and (4) gives:

[0069]

[0070]

[0071] The linear combination of sequences E, F, H, G can be converted to sequences A, B, C, D as follows:

[0072] A: 1 0 0 0 -1 0 0 0

[0073] B: 0 1 0 0 0 -1 0 0

[0074] C: 0 0 1 0 0 0 -1 0

[0075] D: 0 0 0 1 0 0 0 -1

[0076] Where E = A, F = BD, H = -C, G = -BD. Substituting E = A, F = BD, H = -C, G = -BD into equations (7) and (8) respectively yields the sine and cosine carrier signals of sequences E, F, G, H replaced by sequences A, B, C, and D, as shown in equations (9) and (10):

[0077]

[0078]

[0079] The digital downconversion described above, as follows Figure 4 As shown, observing the characteristics of sequences A, B, C, and D, and extracting 1 and -1 from the four sequences, the four sequences can be transformed into a single sequence (1,1,1,1,-1,-1,-1,-1,-1), as shown. Figure 5 As shown, this sequence, acting as a carrier signal, is multiplied with the input intermediate frequency (IF) signal to complete the mixing. Due to the special characteristics of the carrier signal amplitude, inverting the last four consecutive data points in every eight input IF signals eliminates the need for multiplication, thereby reducing design complexity and saving resources.

[0080] like Figure 6 As shown, a traditional CIC decimation filter consists of an integrator, a decimator, and a comb filter. Using a CIC decimation filter as the first-stage low-pass digital filter, the specific structure of the low-pass digital decimation filter module is as follows... Figure 7 As shown, it includes an integrator module, an FIR filter module, a decimation module, an encoding module, a comb filter module, a reassembly module, and a linear combination module.

[0081] The integrator module will cause data overflow due to continuous accumulation operations. Therefore, the maximum bit width B inside the CIC decimation filter needs to be determined according to equation (11). max :

[0082] B max =Nlog2 (RM) +B in (11)

[0083] Configure the input signal word length B respectively in The value is 4, the extraction factor R is 12, the number of cascades N is 4, and the delay factor M is 1. Since Nlog2 (RM) The signal needs to be rounded up, so the expanded signal width is 19.

[0084] The integrator cascade number N is 4, and its transfer function H(z) is:

[0085]

[0086] To further reduce power consumption, the four-order integrator is polyphase decomposed by using the sparsity of integrator data, and the decomposition is as follows:

[0087]

[0088] Wherein:

[0089] P0(Z) = 1 + 31Z -4 + 31Z -8 + Z -12 (14)

[0090] P1(Z) = 4 + 40Z -4 + 20Z -8 (15)

[0091] P2(Z) = 10 + 44Z -4 + 10Z -8 (16)

[0092] P3(Z) = 20 + 40Z -4 + 4Z -8 (17).

[0093] As Figure 8 shown, the above polyphase decomposition converts the integrator with a delay factor of 1 into an integrator with a delay factor of 4 and four FIR filters. To reduce resource usage, the multiplication operation involved in the four FIR filters can be realized by simple shift operation. The multiplication coefficients are CSD coded to obtain more 0 bits, thereby optimizing the area of the multiplier. Wherein: represents -1. Therefore, the data is left shifted by 6 bits and then added to the data after inversion to complete the multiplication operation of the operand multiplied by the coefficient 31, and finally four parallel data P0, P1, P2 and P3 are output.

[0094] The decimator needs to complete 12 times downsampling. Since the polyphase decomposition process of the integrator has completed the 4 times downsampling function, the four parallel signals P0, P1, P2 and P3 output are respectively subjected to 3 times decimation.

[0095] The coding module expands the bit width of the extracted 4-way parallel data from 19 to 20 based on the principle of nibble serial algorithm, and then sequentially splits the data with the expanded bit width from LSB to MSB into 4 data strings with a bit width of 5 for serial output, so as to optimize the bit width of the register, further reduce power consumption and design area, and finally output 4-way parallel data S0, S1, S2 and S3.

[0096] The comb filter module filters the input four-way parallel data S0, S1, S2 and S3 as shown in Figure 9 , and outputs four-way parallel filtered data F0, F1, F2 and F3. Since the nibble serial algorithm is used to encode the data with a bit width of 20 bits into 4 data with a bit width of 5 bits, the delay factor M changes from 1 to 4, and the state equation is as follows:

[0097] y(n)=x(n)-x(n-4) (18)

[0098] In order to simplify the circuit structure of the operator, the data x(n-4) is inverted, and the subtraction operation is converted into addition operation.

[0099] The reorganization module reorganizes the filtered four-way data F0, F1, F2 and F3. Every four-bit data with a length of 5 bits is combined from high to low into a complete signal with a bit length of 20 bits, and finally four-way reorganized data channel0, channel1, chane2 and channel3 are obtained.

[0100] The linear combination module linearly combines the reorganized four-way parallel data channel0, channel1, chane2 and channel3 according to formula (9) and formula (10), and can separate out real data stream Q and imaginary data stream I. The coefficients in formula (9) and formula (10) are fixed-point quantized to In order to simplify the design, the coefficients 1 and are respectively expanded by 239 times, so the signal bit width needs to be expanded from 20 bits to 28 bits, and the linear combination formula is as follows:

[0101] I=239*channel0+169*channel1-169*channel3 (19)

[0102] Q=-239*channel2-169*channel1-169*channel3 (20)

[0103] In order to optimize the area of the multiplier, the multiplication coefficients are also CSD coded to obtain more 0 bits; wherein 169(d) = 10101001 (b).

[0104] The above description is only a description of the preferred embodiments of the present application, and is not intended to limit the scope of the present application. Any modification, change or improvement made by those skilled in the art based on the above disclosure should be within the scope of the claims of the present application.

Claims

1. A digital downconverter design method with a no-multiplication architecture, characterized in that, Includes a mixer module and a low-pass digital decimation filter module; The input digital intermediate frequency signal is down-converted to baseband by the mixer module, and then the low-pass digital decimation filter module completes the downsampling function while filtering out high-frequency components. The down-conversion of the signal of interest to baseband via the mixer module includes the following steps: S11. In the downconversion process, discretized sine and cosine signals are generated by the NCO, and their expressions are as follows: x(n) = cos(2 n) (1) y(n) = sin(2 n) (2) Where n takes values ​​of 0, 1, 2, ..., f s f is the sampling rate of the signal stream to be processed. LO The local carrier signal frequency; S12, Obtain carrier frequency f LO = f s / 8 If the phase shift is 0, then the discretized negative sinusoidal carrier signal and cosine carrier signal are respectively and Since the amplitude values ​​of sine and cosine signals are 0 and ± ±1 converts the periodic carrier signal into a linear combination as shown in the following equation: (3) (4) Within a 2π period, the amplitude values ​​of the four signals A, B, C, and D are all combinations of 0 and ±1, where A is (1,0,0,0,-1,0,0,0), B is (0,1,0,0,0,-1,0,0), C is (0,0,1,0,0,0,-1,0), and D is (0,0,0,1,0,0,0,-1). S13. Observe the characteristics of sequences A, B, C, and D, extract 1 and -1 from the four sequences, and convert the four sequences into one sequence (1,1,1,1,-1,-1,-1,-1). This sequence will be used as a carrier signal to perform multiplication with the input data stream. Due to the special nature of the carrier signal amplitude, periodically inverting the input data can eliminate the multiplication operation, thus completing the mixing. The process of downsampling and filtering out high-frequency components via a low-pass digital decimation filter module includes the following steps: S21. Using the CIC decimation filter as the first-stage low-pass digital filter, since the integrator module of the CIC decimation filter will cause data overflow, the maximum bit width inside the CIC decimation filter is determined according to equation (5): B max = Nlog 2 (RM) +B in (5) Among them, B in Where R is the input signal word length, N is the decimation factor, N is the number of cascades, and M is the delay factor; furthermore... Nlog 2 (RM) It needs to be rounded up; S22, with the integrator cascade number N configured as 4, its transfer function is obtained. for: (6) The Z-transform is a mathematical transformation applied to discrete sequences. It utilizes the sparsity of the integral chain data, where N is 4, to perform polyphase decomposition on the CIC filter, as follows: (7) in: (8) (9) (10) (11) S23. Downsample the four parallel data P0, P1, P2 and P3 after multiphase decomposition. S24. Based on the principle of half-byte serial algorithm, each data in the extracted 4 parallel data is split into 4 data with the same bit width from LSB to MSB and serially output. This optimizes the internal bit width of the register and finally outputs 4 parallel data S0, S1, S2 and S3. S25, the comb filter module filters the four parallel input data streams S0, S1, S2, and S3, with a delay factor M configured to 1. Since a half-byte serial algorithm is used to split the extracted data, the state equation is as follows: y(n) = x(n) - x(n-4) (12) S26. Perform serial-to-parallel conversion on the four parallel data F0, F1, F2 and F3 output by the comb filter module, and recombine each of the four data into a complete data to obtain the four parallel recombined data channels 0, 1, 2 and 3. S27. The recombined four parallel data channels 0, 1, 2, and 3 are linearly combined according to equations (3) and (4) to separate the real data stream Q and the imaginary data stream I. By performing fixed-point quantization on the coefficients, the linear combination formula is obtained as follows: I = 239* channel0 + 169* channel1 - 169* channel3 (13) Q = -239* channel2 - 169* channel1 - 169* channel3 (14)。

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