Memristor convolutional neural network hardware system

Abstract

The application relates to an artificial intelligence neural network, and particularly discloses a memristor convolutional neural network hardware system, which comprises a memristor array and an input module, and the memristor array is formed by a plurality of memristor arrays; characterized in that: each two devices constitute a differential circuit, and the two devices constituting each differential circuit are bound into a neuron; at least one of the two devices comprises a memristor; the weight of the neuron is mapped based on the difference between the electrical parameters of the two devices constituting each differential circuit; and the input module is used for applying a forward single-step electric pulse or a negative single-step electric pulse to the memristor according to a signal fed back by an external computing unit based on the update direction of the weight of the neuron. The above scheme simplifies the weight update calculation process of the memristor neural network system, reduces the consumption of calculation resources in the process, and accelerates the hardware calculation speed.

Description

Technical Field

[0001] This application relates to the field of spiking neural network technology, and in particular to a memristor-based convolutional neural network hardware system. Background Technology

[0002] Memristors are a novel type of two-port nanodevice with a certain degree of memory in their conductance, hence the name memory resistors (i.e., memristors). Memristor arrays can utilize Ohm's law and Kirchhoff's laws to achieve high-performance, low-power multiplication and accumulation, which is highly compatible with the core operation (matrix multiplication) in neural network computing systems. Therefore, memristors provide a new research approach for the hardware implementation of neural networks and have attracted widespread attention from researchers.

[0003] like Figure 1 The diagram illustrates the inference process (forward propagation) of a neural network. Memristor networks can easily perform matrix multiplication using Ohm's law and Kirchhoff's laws. For the network training process (backward propagation), the weights to be updated can be calculated using the stochastic gradient descent (SGD) algorithm, and the synaptic weights can be updated by applying a corresponding number of electrical pulses to the device terminals.

[0004] However, memristor devices and arrays have almost unavoidable drawbacks such as random fluctuations in conductance and nonlinear weight update characteristics, making them difficult to apply directly to the online learning process of neural networks. This also significantly reduces their accuracy in offline inference processes.

[0005] The nonlinear update characteristic of a memristor refers to the phenomenon that the change in conductance of a memristor is nonlinearly related to the number of pulses in its conductance-pulse modulation curve (as follows). Figure 2 (As shown). Generally, the nonlinearity is expressed as an exponential function. The conductance state function of a memristor can be represented by five parameters: Gmax (maximum conductance), Gmin (minimum conductance), Pmax (number of conductance states), Ap (nonlinearity during the weighted LTP process) - see [link to relevant documentation]. Figure 2 (a) Ad (Nonlinearity in the weight reduction LTD process) - see Figure 2 (b). Can be expressed as follows:

[0006]

[0007] In the above formula, x represents the current state parameter of the device, and 0≤x≤Pmax; A is equal to Ap in the weight increase process (LTP process); and equal to Ad in the weight decrease process (LTD process).

[0008] The online learning scheme for memristor neural networks is roughly as follows: Figure 3 As shown. First, the error is calculated by forward propagation. Then, the required update amount for the current weights is calculated according to the standard neural network back propagation algorithm and gradient descent (SGD) algorithm. Next, the required number of pulses is calculated according to the nonlinear update characteristic curve of the memristor device. Then, a certain number of electrical pulses are applied across the memristor by gating to adjust the current conductance value of the memristor.

[0009] Current memristor-based systems have at least the following drawbacks:

[0010] 1. Learning schemes that require external computer configuration of memristor neural networks are too complex: the network needs to calculate the number of electrical pulses required before updating, which will greatly increase the computational complexity of the system. Especially for large-scale convolutional neural networks, the number of parameters is often in the millions or even hundreds of millions. This nonlinear calculation process will consume huge amounts of computing resources and energy.

[0011] 2. Memristor network arrays cannot perform the task of updating electrical pulses on their own; a large number of external control logic circuits are required to implement this. For example, the calculation of the required weight update amount and number of pulses is often provided by a computer with calculation software installed, and then the calculation and conversion of the device's conductance weight update are assisted by software and hardware control methods such as MATLAB and microcontroller (MCU).

[0012] 3. No effective measures were taken to address the nonlinear update characteristics inherent in the memristor: After applying a certain number of electrical pulses to update the conductance weights, the actual conductance state of the memristor deviates from the ideal state, resulting in low learning performance of the memristor neural network. Summary of the Invention

[0013] To simplify the weight update calculation process of memristor neural networks and reduce the consumption of computing resources in this process, thereby accelerating hardware computing speed and reducing power consumption, this application provides a memristor convolutional neural network hardware system, which adopts the following technical solution:

[0014] The memristor convolutional neural network hardware system includes a memristor array and an input module. The memristor array is formed by several memristor arrays. Every two devices constitute a differential circuit, and the two devices that make up each differential circuit are bound together to form a neuron. At least one of the two devices includes a memristor.

[0015] The weights of neurons are mapped based on the difference in electrical parameters between the two devices that make up each differential circuit.

[0016] The input module is used to apply a positive or negative single-step electrical pulse to the memristor based on the signal fed back by the external computing unit based on the update direction of the neuron weights.

[0017] By adopting the above technical solution, the input module applies a single pulse to the two ends of the memristors in the differential circuit of the memristor array each time. The direction of the pulse is determined based on the signal fed back by the external computing unit. This solution is mainly applicable to memristor convolutional neural network hardware systems with differential circuit architecture, such as 1T1R-1T1R differential circuits and 1T1R-1R differential circuits. Compared with related technologies, it eliminates the calculation of learning rate, weight update amount, and the number of pulses required. After obtaining the direction of weight update through the gradient descent algorithm, the weight is updated using a single pulse scheme. Knowing the direction of weight update in each learning process, a pulse is applied to the corresponding memristor device to complete the weight update for this time. During each weight update (learning) process, by applying a single-step pulse to the memristors with large changes in conductance, the weight parameters can be made to approach the optimal value with a certain step size until they reach or infinitely approach the optimal value. This kind of system, which continuously and automatically adjusts the processing method according to the different characteristics of the processed data during the data processing process, so that it is always in or approaching the optimal operating state, is called an adaptive system, and the learning method based on the adaptive system is called an adaptive learning method. For memristor neural networks, a certain learning ability is required, and the network parameters need to be continuously adjusted using the network's capabilities. Providing parameter update suggestions (whether weights need to be increased or decreased) solely based on the gradient descent algorithm significantly reduces the computational complexity of the updates and is also easier to implement in hardware.

[0018] As one implementation of the above scheme, optionally, both devices constituting the differential circuit include memristors; the parameters of the two memristors forming the differential circuit are different, so as to obtain a conductance value with a predictable trend of change after an electrical pulse is applied.

[0019] The weights of neurons are mapped based on the conductance values ​​of the two memristors that make up each differential circuit;

[0020] The input module is used to apply at least a positive or negative single-step electrical pulse to a memristor with a large change in conductance, based on the signal fed back from the external computing unit according to the update direction of the neuron weights.

[0021] By adopting the above technical solution, a novel memristor differential circuit architecture is proposed. Two memristor devices with different parameters are introduced and then combined into a new differential architecture unit. During each update of the network weights, the two devices constituting the differential pair change in the same direction, but their magnitudes are unequal. This means that it cannot be guaranteed that the new weight change obtained after each pulse application will be consistent with the expected weight change. However, appropriate parameter design can ensure that the above requirement is met under high probability conditions. Therefore, the weight values ​​in the network are likely updated according to the requirements given by the algorithm, meaning that the update of the weights in the network is likely successful.

[0022] After obtaining the direction of weight updates using the gradient descent algorithm, a single-step pulse scheme is employed for weight updates. Knowing the direction of weight updates in each learning iteration, a pulse is applied to the corresponding memristor device to complete the weight update. During each weight update (learning) process, the weight parameters approach the optimal value with a certain step size until they reach or are infinitely close to the optimal value. During data processing, the processing method is continuously and automatically adjusted based on the different characteristics of the data, ensuring it remains in or approaches the optimal operating state. For memristor neural networks, a certain learning ability is required, and the network parameters must be continuously adjusted using the network's capabilities until the preset convergence condition is met.

[0023] In related technologies, the update amount of each weight is determined by the backpropagation mechanism and the stochastic gradient descent algorithm. However, simply using memristors as variable resistors fails to fully utilize their inherent characteristics. Furthermore, due to limitations such as the inherent conductance fluctuations of memristors and the limited number of conductance states, errors generated during weight updates accumulate layer by layer in the neural network, inevitably limiting the performance of networks implemented using this approach. Based on these considerations, the hardware system of the aforementioned scheme can eliminate calculations for learning rate, weight update amount, and the number of pulses required in the update process. The external computing unit only needs to provide parameter suggestions based on the gradient descent algorithm to indicate the update direction (whether the weights need to be increased or decreased). This significantly reduces the computational complexity of the update and is more conducive to computer hardware implementation.

[0024] Optionally, in each of the differential circuits, one memristor is larger than the other memristor.

[0025] By adopting the above technical solution, the dimensions here are mainly the area parameters of the two memristors. By differentiating the area parameters, the conductance values ​​of the two memristors under the applied pulse state show obvious changing trends. This changing trend can be used to effectively predict the weights of neurons, and then the weight training of each neuron in the neural network can be simplified by using the prediction of this changing trend.

[0026] Optionally, in each of the differential circuits, the parameter of one memristor is twice the parameter of the other memristor.

[0027] By adopting the above technical solution, experiments have shown that when the difference is twice, the system's weights are closest to the optimal value.

[0028] Optionally, the parameters include cross-sectional area, longitudinal cross-sectional area, or surface area to length ratio.

[0029] By adopting the above technical solution, when the cross-sectional area, longitudinal cross-sectional area, or surface area to length ratio of the memristor is measured, the nonlinear characteristics of the memristor are significant, and the change in conductivity is relatively obvious, which is beneficial to accelerating the convergence process of iterative training.

[0030] Optionally, each of the memristors is connected in series with an NMOS transistor to form a 1T1R device; the differential circuit forms a 1T1R-1T1R differential circuit.

[0031] By adopting the above technical solution, a differential circuit structure with a 1T1R-1T1R (1-transistor-1-memristor+1-transistor-1-memristor) structure is constructed, which further reduces the circuit complexity and circuit area of ​​the memristor neural network chip.

[0032] As another embodiment of this application, optionally, another device constituting the differential circuit includes a shared resistor, the resistance value of which is constant.

[0033] By adopting the above technical solution, the number of memristors is greatly reduced due to the shared resistor, which in turn significantly reduces the circuit area.

[0034] Optionally, the resistance value of the shared resistor is half the sum of the maximum and minimum conductance values ​​of the memristor.

[0035] By adopting the above technical solution, it is beneficial to accelerate the iterative convergence process, and the error between the optimized weight and the optimal weight is small.

[0036] Optionally, each memristor is connected in series with an NMOS transistor to form a 1T1R device; each row of memristors in the memristor array is provided with a shared resistor, and each memristor in the row and the shared resistor form a differential circuit, and the differential circuit forms a 1T1R-1R differential circuit.

[0037] By adopting the above technical solution, the 1T1R-1R (1-transistor-1-memristor+1-resistor) differential circuit structure significantly reduces the circuit area. This is because the 1T1R-1T1R structure requires twice the number of devices, while different differential circuit pairs in the 1T1R-1R structure can share the same resistor. The 1T1R-1R structure shares one 1R device in each row. Assuming the number of input and output neurons is M and N respectively, the total number of devices in the 1T1R-1T1R structure is Num_1 = M*N*2, and the total number of devices in the 1T1R-1R structure is Num_2 = (M+1)*N. Therefore, the ratio is (M+1) / 2M. Theoretically, using this circuit structure, the same network can reduce circuit area consumption by 50%.

[0038] Optionally, the system further includes:

[0039] The memristor control module is used to write single-step pulse signals into the memristor array;

[0040] The memristor array internally stores weight data, which is combined with a single-step pulse signal to calculate and output the collected current value.

[0041] The sensitive amplifier module is used to combine the pooled current value of the memristor array output with the reference threshold current to output a high-level voltage or a low-level voltage.

[0042] Output buffer: Receives high-level or low-level voltage, stores it, or outputs it externally.

[0043] By adopting the above technical solution, the neuron function of the convolutional neural network is simulated in hardware, solving the problems of complex computation, high energy consumption, and large area of ​​the neural network hardware acceleration architecture.

[0044] Optionally, the system further includes:

[0045] An external computing unit is used to obtain the update direction of neuron weights during the process of updating neuron weights by applying a single-step pulse to the input module, and to feed back the direction of the single-step pulse signal based on the update direction of neuron weights.

[0046] By adopting the above technical solution, it is only necessary to provide the parameter update direction (whether the weights need to be increased or decreased) based on the gradient descent algorithm. This can significantly reduce the computational complexity required for the update, make it easier for computer hardware to implement, achieve hardware acceleration of the network system, and reduce power consumption. Attached Figure Description

[0047] Figure 1 This is a diagram of the forward propagation process of a memristor neural network in related technologies.

[0048] Figure 2 (a) is a diagram of the update model for the nonlinear weighting process of memristors in related technologies.

[0049] Figure 2 (b) is a diagram of the update model for the nonlinear weight reduction process of memristors in related technologies.

[0050] Figure 3 This is a flowchart of the memristor neural network weight training process in related technologies.

[0051] Figure 4 This is a framework diagram of the memristor convolutional neural network hardware system provided in Embodiment 1 of this application.

[0052] Figure 5 This is a framework diagram of the memristor convolutional neural network hardware system provided in Embodiment 2 of this application.

[0053] Figure 6 This is a hardware architecture diagram of a memristor convolutional neural network for a 1T1R-1T1R differential circuit provided in Embodiment 2 of this application.

[0054] Figure 7 (a) is the differential circuit architecture used in the memristor neural network in the weight training method of the memristor convolutional neural network provided in Embodiment 2 of this application.

[0055] Figure 7 (b) is a graph showing the trend of the conductance of two memristors under the applied electrical pulse state in the memristor convolutional neural network weight training method provided in Embodiment 2 of this application.

[0056] Figure 8 (a) is a diagram of the nonlinear weight increase process update model of two memristors in the memristor convolutional neural network weight training method provided in Embodiment 2 of this application.

[0057] Figure 8 (b) is a diagram of the nonlinear weight reduction process update model of the two memristors in the memristor convolutional neural network weight training method provided in Embodiment 2 of this application.

[0058] Figure 9 This is a graph showing the ratio of the maximum conductance of the two memristors in Example 2 and the probability of successful weight updates each time.

[0059] Figure 10 This is a framework diagram of the memristor convolutional neural network weight hardware system provided in Embodiment 3 of this application.

[0060] Figure 11 This is a hardware architecture diagram of the memristor convolutional neural network of the 1T1R-1R differential circuit provided in Embodiment 3 of this application.

[0061] Figure 12 This is a diagram illustrating the accuracy of neural network weight optimization using different algorithms.

[0062] Figure 13 This is a schematic diagram illustrating the accuracy of LeNet-5 networks trained using different schemes under different nonlinearities Ap and Ad. Detailed Implementation

[0063] The present application will be further described in detail below with reference to the accompanying drawings.

[0064] This specific embodiment is merely an explanation of this application and is not intended to limit it. Those skilled in the art, after reading this specification, can make modifications to this embodiment without contributing any inventive step, but such modifications are protected by patent law as long as they fall within the scope of the claims of this application. To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without inventive effort are within the scope of protection of this application.

[0065] Furthermore, the term "and / or" in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, the character " / " in this article, unless otherwise specified, generally indicates that the preceding and following related objects have an "or" relationship.

[0066] The embodiments of the memristor convolutional neural network hardware system of this application will be described in further detail below with reference to the accompanying drawings.

[0067] Example 1

[0068] See Figure 4 A memristor convolutional neural network hardware system includes an external computing unit, an input module, a memristor control module, a memristor array, a current-to-voltage conversion circuit, and a computing circuit. The memristor array is formed by a plurality of memristor arrays. Every two devices constitute a differential circuit. At least one of the two devices constituting each differential circuit includes a memristor. The weights of neurons are mapped based on the difference in electrical parameters between the two devices constituting each differential circuit. The input module is used to apply a positive single-step electrical pulse or a negative single-step electrical pulse to the memristor according to the signal fed back by the external computing unit based on the update direction of the neuron weights.

[0069] The external computer unit has peripheral circuits and / or software programs installed. The two devices that make up each differential circuit are bound together in the software system as a neuron. The connections between neurons form a convolutional neural network. The connections between neurons are represented by weights. The weights of the neurons are mapped based on the difference in electrical parameters of the two devices that make up each differential circuit. It should be noted that the electrical parameters here are different in different differential circuit architectures. Specifically, they are resistive parameters. If it is a memristor, the conductance value is used, and if it is a resistor, the resistance value is used.

[0070] The input module of this application applies a single pulse to each row of memristors in the memristor array to update the weights of each neuron. The method for calculating the neuron weights during the update process can employ existing gradient descent algorithms, such as linear SGD or nonlinear SGD. Unlike related technologies, each update inputs a single-step pulse, eliminating the need to calculate the number of electrical pulses applied to each memristor. Instead, it only needs to obtain the weight update direction for each neuron, and then determine the direction for the next single-step pulse application based on this direction. This significantly simplifies the weight update process and reduces computational load, thereby saving computational resources.

[0071] The input module receives data output from the external computing unit as input data. This input data can be image data, which can be a pulse input image obtained by converting the original input image into floating-point data and storing it as 0 / 1 bits. The pulse input image can be converted into an input pulse sequence for the neural network to correspond to the input memristor array and applied to both ends of each row of memristors.

[0072] The control module (not shown in the figure) provides the decoding longitudinal signal and control bus signal to the memristor control module. The memristor control module is used to write the corresponding image input data into the memristor array according to the decoding longitudinal signal and the control longitudinal signal. Both the control module and the memristor control module can adopt existing known technologies, and this solution does not involve any improvement to them.

[0073] Example 2

[0074] See Figure 5 As a first preferred embodiment, both devices constituting the differential circuit include memristors; the parameters of the two memristors forming the differential circuit are different to ensure that the conductance value with a predictable trend of change after the application of an electrical pulse is obtained; the weights of neurons are mapped based on the conductance values ​​of the two memristors constituting each differential circuit; the input module is used to apply a positive single-step electrical pulse or a negative single-step electrical pulse to at least the memristor with a larger change in conductance value according to the signal fed back by the external computing unit based on the update direction of the neuron weights.

[0075] It should be noted that the parameters include any one of the cross-sectional area, longitudinal cross-sectional area, and the difference between surface area and length. The requirement is that a conductivity value with a predictable trend of change in the magnitude of the change is achieved after the application of an electrical pulse.

[0076] See Figure 6 In a specific embodiment of this scheme, each memristor is connected in series with an NMOS transistor to form a basic unit for performing multiplication calculations; the differential circuit forms a 1T1R-1T1R differential circuit.

[0077] The image input data controls the conduction or closure of the NMOS transistor in the 1T1R three-terminal device unit. In a single 1T1R three-terminal device unit, the gate of the NMOS transistor is the word terminal, the source is the source terminal, and the drain is connected to one end of a memristor. The other end of the memristor is the bit terminal. Connecting the word, source, and bit terminals of different 1T1R three-terminal device units forms the memristor array line, source line, and word line. See also... Figure 7 (a) Each column of memristors in the memristor array is connected to a sensitive amplifier and a corresponding capacitor, forming a pulse neural computing unit with each column of memristors. The current collected from each column of memristors is amplified and output as a digital level, with a high level of 1 and a low level of 0.

[0078] Since memristors have no negative conductance, while the weights in a neural network can be negative (generally, the number of positive and negative weights in a network is roughly equal), a differential pair design is typically used in memristor neural networks. This involves binding two memristors (denoted as w1 and w2) together to form a new set of weights w = w1 - w2 for network computation. Specifically, as follows: Figure 7 As shown in (a), the two memristor arrays respectively use current-to-voltage conversion circuits to calculate their respective voltage output data. and The difference between the two values ​​is then calculated using a computational circuit, yielding the final output of the neuron.

[0079] The conventional scheme (which we'll call "Scheme 0") updates weights as follows: If the weight *w* is to be increased, the standard SGD algorithm is used to calculate the weight change and the corresponding number of electrical pulses required. Several positive electrical pulses are then applied to device *w1*, while *w2* remains idle. If the weight *w* is to be decreased, the standard SGD algorithm is used to calculate the weight change and the corresponding number of electrical pulses required. Several negative electrical pulses are then applied to device *w1*, while *w2* also remains idle. As described in Part 4, this complex calculation significantly reduces the system's energy efficiency. Secondly, the second memristor (*w2*) is never operated during the update process, failing to meet the design principle of maximizing resource utilization. Furthermore, there is no compensation for the performance loss caused by the nonlinear characteristics of the devices.

[0080] Based on the above considerations, this application proposes a novel memristor differential circuit architecture, such as... Figure 7 As shown in (b), we introduce memristor devices w1 and w2 with different parameters and then combine them into a new differential architecture unit. In the neural network, we first pre-set half of the weight parameters to be positive and the rest to be negative. Because the online learning process of a neural network is essentially a process of solving a system of multivariable equations, the number of unknowns is far greater than the number of equations, resulting in an infinite number of solutions that satisfy the conditions. This is the source of the robustness of the neural network. Therefore, pre-setting half of the weight parameters to be positive and the other half to be negative will not affect the final performance of the network.

[0081] In the preset positive definite weights, we use a circuit scheme of memristor w1-memristor w2 (i.e., w1-w2); in the preset negative definite weights, we use a circuit scheme of memristor w2-memristor w1 (i.e., w2-w1). The device parameters (such as the cross-sectional area of ​​the devices) of memristor w1 and memristor w2 are different.

[0082] In the conventional scheme ("Scheme 0"), the two memristors (w1 and w2) in each differential device group are physically identical. However, the scheme provided in this patent specifies from the initial circuit design that the two memristors have different area dimensions (for example, the area of ​​w1 can be designed to be twice the area of ​​w2). Therefore, the intrinsic conductivity of device w1 will (with a high probability) be greater than the conductivity of w2. In this case, device w = w1 - w2 is set as the positive weight mapping of the network, and device w = w2 - w1 is set as the negative weight mapping. It is worth noting that in the above settings, due to the random initialization of the weights, the weight values ​​in the positive weight mapping are only likely to be positive, not guaranteed to be positive. The same applies to the negative weight mapping. This introduces a certain degree of probabilistic update behavior, which can serve as a compensation mechanism for network weight updates. This probability is named Probability 1.

[0083] This probability value can be calculated as follows: Assuming w1 and w2 are randomly initialized according to the functional distribution of f(x), the range of w1 is [Gmin1, Gmax1], and the range of w2 is [Gmin2, Gmax2], then the probability of w = w1 - w2 > 0 can be expressed as:

[0084]

[0085] Specifically, if f(x) represents a uniform distribution and Gmin1 = Gmin2 = 0, Gmax1 = 2, Gmax2 = 1, the probability value is 75%.

[0086] After the above settings, the memristor network uses our learning algorithm for parameter training. Specifically, in each update process, the two devices constituting the difference pair change in the same direction, but their change magnitudes are unequal. This means that it cannot be guaranteed that the new weight change obtained after each pulse application will be consistent with the expected weight change. However, appropriate parameter design (mainly the area parameters of devices w1 and w2) can ensure that the above requirements are met with a high probability. For example, when the device area of ​​device w1 is twice that of device w2, the change magnitude of device w1 is likely to be greater than that of device w2. Therefore, the weight values ​​in the network are likely to be updated according to the requirements given by the algorithm, that is, the update of the weights in the network is likely to be successful. This setting introduces another probabilistic update behavior, which can serve as another compensation mechanism for network weight updates. This probability is named Probability 2.

[0087] In the single-pulse update scheme, we cannot guarantee the amount of new weight change (Δw) obtained after each pulse application. actual ) and the expected change in weight (Δw) predict While the direction of updates may not be consistent, proper parameter design (primarily the area parameters of devices w1 and w2) can ensure that the above requirements are met under high probability conditions. Below, we will derive the solution method for this probability using a positive update of a positive weight as an example.

[0088] above Figure 8 (a) Taking the update process of the "positive weights" in the network when Δw>0 as an example, the conductivity value can be expressed as:

[0089] W old =w 1_old -w 2_old =G(x1)-G(x2))(3)

[0090] W new =w 1_new -w2_new =G(x1+1)-G(x2+1) (4)

[0091] ΔW=W new -W old >0 (5)

[0092] Where G(x) is the memristor conductance-pulse state function in formula (1), and x represents the pulse state of the memristor. Formula (5) represents that the weight parameter has been successfully updated in this round of weight update. It can be approximated by the low-order expansion of the Taylor function. For the first-order linear approximation, it can be equivalent to:

[0093] ΔW=[G(x1+1)-G(x1)]-[G(x2+1)-G(x2)]≈G'(x1)-G'(x2)>0 (6)

[0094] Where G'(x) is the derivative of formula (1). By iterating through x1 and x2, the probability of a successful update in one step can be obtained by integration:

[0095]

[0096] Where Pmax represents the number of conductance states of devices w1 and w2, which can be understood as the final number of single-step pulses applied. In this scheme, the number of conductance states of devices w1 and w2 is the same, that is, one single pulse is applied to both devices each time. A1 is the nonlinear coefficient of device w1 in the weight update process, Gmax1 is the maximum conductance value of device w1, and Gmin1 is the maximum conductance value of device w1; A2 is the nonlinear coefficient of device w2 in the weight update process, Gmax2 is the maximum conductance value of device w2, and Gmin2 is the maximum conductance value of device w2. Here, device w1 can be understood as the first memristor, and device w2 can be understood as the second memristor. Temporary variables are defined as:

[0097]

[0098]

[0099] We found that the probability of G'(x1)-G'(x2)>0 is related to the ratio of Gmax1 and Gmax2, G. max1 / G max2 They have a close relationship. For example, when the ratio of Gmax1 to Gmax2... (at the same time When the maximum conductance of device w1, Gmax1, is twice the maximum conductance of device w2, Gmax2, the probability of G'(x1) - G'(x2) > 0 will reach 50%, which is consistent with our intuitive understanding. When the maximum conductance of device w1, Gmax1, is twice the maximum conductance of device w2, Gmax2, this probability will reach [a higher value]. Figure 9The figure shown is 95.4%. This means that after a single-pulse update, W actually... new The value is likely greater than W. old The value of , meaning the probability of a successful weight update is quite high, ensures that the neural network can complete the learning process well and ultimately achieve good network performance.

[0100] By calculation, the probability of G'(x1)-G'(x2)>0 is the ratio of Gmax1 and Gmax2, G. max1 / G max2 The relationship is as follows: Figure 9 As shown, the greater the ratio of the maximum conductance values ​​of the two memristors constituting the same differential circuit, the higher the probability of a successful weight update in a single operation. Figure 8 When Δw < 0 in (b), the same conclusion can be obtained through the derivation of the above formula, which will not be repeated here.

[0101] Example 3

[0102] See Figure 10 As a second preferred embodiment of the first embodiment, the difference from the second embodiment is that another device constituting the differential circuit includes a shared resistor, the resistance of which is a constant value.

[0103] See Figure 11 As a specific implementation of this application, each memristor is connected in series with an NMOS transistor to form a 1T1R device; each row of memristors in the memristor array is provided with a shared resistor, and each memristor in the row and the shared resistor form a differential circuit, and the differential circuit forms a 1T1R-1R differential circuit.

[0104] The conductance of a memristor exhibits a non-linear change when receiving electrical pulses. Utilizing this characteristic, each neuron maps its weights to the difference between the memristor's conductance and the resistance of the shared resistor in the differential circuit. The value of the shared resistor can be initialized, with the assigned value ranging between the memristor's minimum and maximum conductance.

[0105] As the first specific implementation scheme of Example 3, the resistance value R of the shared resistor is randomly initialized, where Gmin≤R≤Gmax, where Gmax is the maximum conductance of the memristor and Gmin is the minimum conductance of the memristor. It should be noted that the resistance value of the shared resistor in each row is randomly set by the system. Once it is set for the first time, it will not change during subsequent training. Therefore, it can be considered a constant value. However, the resistance value of the shared resistor in each row may be different.

[0106] For each row of memristors in the memristor array, each memristor in that row is bound to a shared resistor in that row to form a neuron. If there are N rows of memristors in the memristor array, the hardware system is configured with N shared resistors, one for each row of memristors. During the binding process, row-specific memristors are paired in an orderly manner. Compared to Embodiment 2, this scheme significantly reduces the number of devices, circuit area, and power consumption because the shared resistors change the connection relationship of the differential circuit.

[0107] As a second specific implementation of Embodiment 3, the resistance of the shared resistor is half the sum of the maximum and minimum conductance values ​​of the memristor. The difference from the first implementation is that the shared resistors in each row here have the same resistance value, which is always the maximum conductance value G of the memristor. max With minimum conductivity G min Half of the sum.

[0108] Each memristor is connected in series with an NMOS transistor to form a 1T1R device; each row of memristors in the memristor array is provided with a shared resistor, and each memristor in the row and the shared resistor form a differential circuit, which forms a 1T1R-1R differential circuit.

[0109] Our algorithm simplifies the calculations of network weight updates in traditional memristor network algorithms. In the original "Scheme 0" update scheme, the update amount of each weight is determined by the backpropagation mechanism and the stochastic gradient descent algorithm, and the learning rate, as a hyperparameter of the network, is also introduced into the memristor neural network, which is consistent with the research approach of neural networks in the conventional field of artificial intelligence. However, as a specialized circuit architecture of artificial neural networks, if the forward and backward propagation mechanisms of memristor neural networks are completely copied from the original artificial neural networks, and the memristor device is only used as a variable resistor, the characteristics of the memristor itself cannot be fully utilized. In addition, due to the limitations of the memristor's own conductance fluctuations and the limited number of conductance states, the errors generated during the weight update process will accumulate layer by layer in the neural network, and the network performance achieved by this scheme will inevitably have an upper limit. Based on these considerations, we will eliminate the calculations of learning rate, weight update amount, and the number of pulses required in the update scheme, and only provide parameter suggestions on the update direction (whether the weight needs to be increased or decreased) based on the gradient descent algorithm. This will undoubtedly significantly reduce the computational complexity required for the update and is also more conducive to hardware implementation.

[0110] After obtaining the direction of weight updates using the gradient descent algorithm, we also propose a single-pulse scheme for weight updates. Knowing the direction of weight updates in each learning iteration, a pulse is applied to the corresponding memristor device to complete the weight update. During each weight update (learning) process, the weight parameters move towards the optimal value with a certain step size until they reach or are infinitely close to the optimal value. This system, which continuously and automatically adjusts the processing method according to the different characteristics of the processed data, thereby keeping it in or approaching the optimal operating state, is called a system, and the learning method based on the system is called a learning method. For memristor neural networks, a certain learning ability is required, and the network parameters must be continuously adjusted using the network's capabilities.

[0111] Based on this algorithm, we propose four different weight update schemes based on two different circuit structures. We name them Scheme 1, Scheme 2, Scheme 3, and Scheme 4, and we will describe them one by one below:

[0112] Scheme 1 and Scheme 2 based on 1T1R-1T1R circuit structure:

[0113] Schemes 1 and 2 are based on a differential circuit structure of 1T1R-1T1R (1-transistor-1-memristor+1-transistor-1-memristor). However, some modifications have been made. In the original "Scheme 0", the two memristors (w1 and w2) in each group of differential devices are physically identical. However, Schemes 1 and 2 will limit their area dimensions to be different from the beginning of the circuit design (for example, the area of ​​w1 can be designed to be twice the area of ​​w2). Therefore, the intrinsic conductance of device w1 will (with a high probability) be greater than the conductance of w2. In this case, device w = w1 - w2 is set as the positive weight mapping of the network, and device w = w2 - w1 is set as the negative weight mapping of the network. It is worth noting that in the above settings, the weight values ​​in the positive weight mapping are only likely to be positive, and are not guaranteed to be positive. The same applies to the negative weight mapping. This introduces a certain degree of probabilistic update behavior, which can be used as a compensation mechanism for network weight updates. This probability is named Probability 1.

[0114] After the above settings are established, the memristor network is trained using the learning algorithm proposed in this application. Although Scheme 1 and Scheme 2 have the same circuit architecture, they differ in that the conductance of the two devices constituting the differential pair changes differently during each weight update.

[0115] Specifically, in Scheme 1, the two devices constituting the difference pair change in the same direction during each update of the network weights, but their magnitudes are unequal. This means it cannot be guaranteed that the new weight change obtained after each pulse application will match the expected weight change. However, appropriate parameter design (mainly the area parameters of devices w1 and w2) can ensure that the above requirement is met with a high probability. For example, when the area of ​​device w1 is twice that of device w2, the magnitude of the change in device w1 is likely to be greater than that of device w2. Therefore, the weight values ​​in the network are likely updated according to the requirements given by the algorithm, meaning the weight update in the network is likely successful. This setting introduces another probabilistic update behavior, which can serve as another compensation mechanism for network weight updates. This probability is named Probability 2.

[0116] The update method for Scheme 1 is shown in Table 1 below:

[0117] Table 1. Weight update steps for Scheme 1

[0118]

[0119] The weight update method for Scheme 1 is as follows:

[0120] Step 1: Randomly assign two weights to the network: "positive weights" and "negative weights". For "positive weights", the differential pair in the hardware circuit is designed as "w = w1 - w2". Conversely, for "negative weights", the differential pair in the hardware circuit is designed as "w = w2 - w1". Devices w1 and w2 have different device sizes, and the device size of w1 is larger than that of w2.

[0121] Step 2: Randomly initialize network weights. Because the device area of ​​device w1 is larger than that of device w2, the maximum conductance value Gmax1 of device w1 is greater than the maximum conductance value Gmax2 of device w2. Assuming the range of w1 is [Gmin1, Gmax1] and the range of w2 is [Gmin2, Gmax2], then Gmax1 > Gmax2.

[0122] Step 3: Update the network weights using a single-step pulse update method. The standard SGD algorithm is used to obtain the update direction of the weights, determining the sign of Δw. Specifically: If Δw > 0, a positive pulse is applied to the two devices w1 and w2 in the difference pair representing "positive weights" in the network, and a negative pulse is applied to the two devices w1 and w2 in the difference pair representing "negative weights" in the network. If Δw < 0, a negative pulse is applied to the two devices w1 and w2 in the difference pair representing "positive weights" in the network, and a positive pulse is applied to the two devices w1 and w2 in the difference pair representing "negative weights" in the network.

[0123] Step 4: Determine if all iterations have been completed. If so, stop the learning process.

[0124] Scheme 2 has the same circuit structure as Scheme 1. The difference between Scheme 2 and Scheme 1 lies in the "third step" mentioned above. The steps for updating the weights in Scheme 2 are as follows:

[0125] Step 1: Randomly assign two weights to the network: "positive weights" and "negative weights". "Positive weights" mean that the differential pairs in the hardware circuit are designed as "w = w1 - w2" and "negative weights" mean that the differential pairs in the hardware circuit are designed as "w = w2 - w1", where the device size of w1 is larger than the device size of w2.

[0126] Step 2: Randomly initialize network weights. The conductance of device w1 ranges from [Gmin1, Gmax1], and the conductance of w2 ranges from [Gmin2, Gmax2]. Similar to Scheme 1, Gmax1 > Gmax2.

[0127] Step 3: Update the network weights using a single-step pulse update method. The standard SGD algorithm is used to obtain the update direction of the weights, determining the sign of Δw. Specifically: If Δw > 0, a positive pulse is applied to device w1 in the difference pair representing "positive weights" in the network, and a negative pulse is applied to device w2. Conversely, a negative pulse is applied to device w1 in the difference pair representing "negative weights" in the network, and a positive pulse is applied to device w2. If Δw < 0, a negative pulse is applied to device w1 in the difference pair representing "positive weights" in the network, and a positive pulse is applied to device w2. Conversely, a positive pulse is applied to device w1 in the difference pair representing "negative weights" in the network, and a negative pulse is applied to device w2.

[0128] Step 4: Determine if all iterations have been completed. If so, stop the learning process.

[0129] Schemes 3 and 4 are based on the 1T1R-1R circuit structure:

[0130] Following Schemes 1 and 2, we subsequently proposed two more schemes (Schemes 3 and 4) based on different circuit structures, further reducing the circuit complexity and area of ​​the memristor neural network chip. Compared to the 1T1R-1T1R circuit structure of Schemes 1 and 2, Schemes 3 and 4 adopt a differential circuit structure based on 1T1R-1R (1-transistor-1-memristor+1-resistor), which significantly reduces the circuit area. This is because the 1T1R-1T1R structure requires twice the number of components, while different differential pairs in the 1T1R-1R structure can share the same resistor. Theoretically, this circuit structure can reduce the circuit area consumption by 50% for the same network. Meanwhile, the weight update schemes of Schemes 3 and 4 still use the learning methods from Schemes 1 and 2, which can improve the performance, area, and power consumption of the memristor neural network chip.

[0131] The difference between Scheme 3 and Scheme 4 lies in the initial method of the resistance values. Specifically, in Scheme 3, all resistance values ​​(corresponding to device w2) are randomly initialized at the beginning, and these values ​​remain unchanged (equal to the initial values) throughout the weight update process, which is very similar to the original "Scheme 0". For Scheme 4, all resistance values ​​are fixed throughout the weight update process, and their values ​​are fixed at (G max / 2+G min / 2).

[0132] The weight update schemes in the four different modes described above differ from the weight update method in "Scheme 0" primarily because they do not require calculating the specific number of voltage pulses. What we need to do is determine the sign of the weight update amount Δw during training. This simple learning rule enables the gimbal network to update its parameters efficiently, thereby achieving self-optimization capabilities.

[0133] Below, we will summarize the four weight update schemes. The implementation details of the four schemes are shown in Table 2 below:

[0134] Table 2 Four weight update schemes

[0135]

[0136] We trained the classic LeNet-5 convolutional neural network using the algorithm proposed in this application and other memristor-based algorithms, and tested the recognition accuracy on the MNIST handwritten digit dataset, comparing the network performance under different algorithms.

[0137] From above Figure 12As can be seen, our algorithm achieves a recognition accuracy comparable to the standard linear stochastic gradient descent algorithm, with a similar learning rate. It also significantly surpasses the recognition accuracy obtained using the nonlinear SGD algorithm, and its convergence speed is faster.

[0138] Furthermore, we conducted a comprehensive and detailed comparison of the network performance using four different weight update schemes. We tested experimental results for 49 typical combinations of Ap (LTP process nonlinearity) and Ad (LTD process nonlinearity) values ​​under the four schemes. Ap ranged from 0 to 6, and Ad ranged from 0 to -6, as detailed below. Figure 13 As shown.

[0139] From above Figure 13 We can observe that Scheme 1 exhibits the best network performance, while Scheme 2 shows worse performance. This is because in Scheme 2's weight update method, the weight update amount is obtained from the difference between the two devices in the difference pair after updating in opposite directions. This will likely result in an actual update amount greater than the amount required by the algorithm. This situation is very similar to choosing an excessively large learning rate in the stochastic gradient descent algorithm. We know that in stochastic gradient descent, if the learning rate is too large, it will cause the network to oscillate around the extreme point, resulting in difficulty in convergence. Scheme 2 is similar; in each iteration, the excessively large weight update amount causes the weights to oscillate around the optimal value. However, unlike the stochastic gradient descent algorithm, due to the algorithm used in this paper, through continuous iterative training, Scheme 2 can gradually bring the weights closer to the optimal value and eventually stop near it, achieving near-convergence. Figure 12 In Scheme 2, with Ap = 1 and Ad = -1, the network's recognition accuracy exceeds 90%, which proves that the network trained using Scheme 2 is convergent.

[0140] Schemes 3 and 4 employ a 1T1R-1R differential pair architecture designed to reduce circuit area. In both weight update schemes, the second weight (w2) in the differential pair is never involved. Therefore, their performance is lower than that of Scheme 1. Nevertheless, they still demonstrate good network performance.

[0141] Table 3 below shows the specific recognition accuracy values ​​for seven typical Ap and Ad combinations of four weight update schemes:

[0142] Table 3. Accuracy of LeNet-5 networks trained using different schemes at typical Ap and Ad values.

[0143]

[0144] The table above demonstrates that our algorithm is well-suited for memristor networks, and all four weight update schemes based on this algorithm exhibit good network performance. Even scheme 2, with typical nonlinearity Ap and Ad values ​​of ±1, still achieves a network recognition accuracy as high as 92.42%. This proves that the algorithm largely suppresses the weight update error caused by the nonlinear weight update characteristics of memristors.

[0145] Simulation results demonstrate that, compared to conventional learning schemes based on memristor neural networks, our algorithm effectively reduces weight update errors caused by the nonlinear characteristics of memristors, exhibiting better network performance. Furthermore, since the algorithm adopted in this patent does not require calculating the specific number of pulses corresponding to weight changes, it avoids complex peripheral circuits caused by redundant calculations, thus making it more hardware-friendly.

[0146] The above description of the embodiments is only used to provide a detailed introduction to the technical solutions of this application. However, the description of the above embodiments is only for the purpose of helping to understand the methods and core ideas of this application, and should not be construed as a limitation of this application. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the protection scope of this application.

Claims

1. A hardware system for a memristor convolutional neural network, comprising a memristor array and an input module, wherein the memristor array is formed by a plurality of memristor arrays; characterized in that, Each pair of devices forms a differential circuit, and the two devices that make up each differential circuit are bound together to form a neuron; at least one of the two devices includes a memristor; The weights of neurons are mapped based on the difference in electrical parameters between the two devices that make up each differential circuit. The input module is used to apply a single-step electrical pulse corresponding to the update direction of the neuron weights to the memristor based on the signal fed back by the external computing unit based on the update direction of the neuron weights. When the weight update direction is increasing, a positive single-step electrical pulse is applied; when the weight update direction is decreasing, a negative single-step electrical pulse is applied.

2. The memristor convolutional neural network hardware system according to claim 1, characterized in that, Both components of the differential circuit include memristors; the parameters of the two memristors forming the differential circuit are different to ensure that the conductance value with a predictable trend of change after an electrical pulse is applied. The weights of neurons are mapped based on the conductance values ​​of the two memristors that make up each differential circuit; The input module is used to apply at least a positive or negative single-step electrical pulse to a memristor with a large change in conductance, based on the signal fed back from the external computing unit according to the update direction of the neuron weights.

3. The memristor convolutional neural network hardware system according to claim 2, characterized in that, The parameters include the difference between cross-sectional area, longitudinal cross-sectional area, or surface area and length.

4. The memristor convolutional neural network hardware system according to claim 3, characterized in that, In each of the differential circuits, the parameter of one memristor is twice the parameter of the other memristor.

5. The memristor convolutional neural network hardware system according to claim 3, characterized in that, Each memristor is connected in series with an NMOS transistor to form a 1T1R device; the differential circuit forms a 1T1R1T1R differential circuit.

6. The memristor convolutional neural network hardware system according to claim 1, characterized in that, Another component constituting the differential circuit includes a shared resistor, the resistance of which is constant.

7. The memristor convolutional neural network hardware system according to claim 6, characterized in that, The resistance value of the shared resistor is half the sum of the maximum and minimum conductance values ​​of the memristor.

8. The memristor convolutional neural network hardware system according to claim 6, characterized in that, Each memristor is connected in series with an NMOS transistor to form a 1T1R device; each row of memristors in the memristor array is provided with a shared resistor, and each memristor in the row and the shared resistor form a differential circuit, which forms a 1T1R1R differential circuit.

9. The memristor convolutional neural network hardware system according to any one of claims 1-8, characterized in that, The system also includes: The memristor control module is used to write single-step pulse signals into the memristor array; The memristor array internally stores weight data, which is combined with a single-step pulse signal to calculate and output the collected current value. A current-to-voltage conversion circuit is used to combine the pooled current value output by the memristor array with the reference threshold current to output a high-level voltage or a low-level voltage. The computing circuit receives high-level or low-level voltages, performs differential calculations using a differential circuit, and then stores or outputs the result.

10. The memristor convolutional neural network hardware system according to claim 1, characterized in that, The system further includes an external computing unit, used to obtain the update direction of the neuron weights during the process of updating the neuron weights by applying a single-step pulse to the input module, and to feed back the direction of the single-step pulse signal based on the update direction of the neuron weights.

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