High dynamic range image processing with fixed calibration settings

Abstract

In various examples, apparatuses, systems, and techniques for performing offline image signal processing of source image data to generate target image data. In at least one embodiment, data collection is performed using exposure and calibration settings of an image sensor to generate source image data, which is then processed by using offline image signal processing to generate target data.

Description

Background Technology

[0001] In high dynamic range imaging (HDRI), HDR images provide an increased ratio of possible pixel values ​​(e.g., the maximum possible brightness value relative to the minimum possible brightness value) compared to conventional imaging methods. For example, pixels with smaller brightness values ​​are rendered as darker (e.g., blacker) areas of the encoded image, while pixels with larger brightness values ​​are rendered as brighter (e.g., whiter) areas of the image. Furthermore, conventional tone-mapped HDR image data methods may produce suboptimal results if the camera's auto-exposure (AE) settings are not properly configured when capturing HDR image data. In some cases, the camera's AE settings may fail, leading to a degraded image quality when processing HDR image data. For example, when the AE settings are suboptimal, various aspects controlling the HDR image and / or the image encoded by tone-mapped HDR image data may negate many of the benefits associated with HDRI, resulting in images that appear "faded," less realistic, or less visually appealing. Therefore, using such images in various applications, such as training models, may lead to suboptimal results. Attached Figure Description

[0002] The fixed-position image capture processing system and method of the present invention will now be described in detail with reference to the accompanying drawings, wherein:

[0003] Figure 1 A schematic diagram of a fixed-configuration image capture processing system according to some embodiments of the present disclosure is shown;

[0004] Figure 2 A schematic diagram of an image signal processing system for fixing captured data according to some embodiments of the present disclosure is shown;

[0005] Figure 3 A schematic diagram of a high dynamic range imaging system according to some embodiments of the present disclosure is shown;

[0006] Figure 4 The diagram shows low-tone, mid-tone, high-tone, and flare-suppression control points embedded in a two-dimensional (2D) space spanned by a first basis vector in a first dimension corresponding to the pixel values ​​of the source image data and a second basis vector in a second dimension corresponding to the pixel values ​​of the target image data.

[0007] Figure 5 Non-limiting embodiments of tone mapping function graphs according to various embodiments are shown;

[0008] Figure 6 This is a flowchart illustrating a method for performing image signal processing using a capture with fixed settings, according to some embodiments of the present disclosure;

[0009] Figure 7 This is a flowchart illustrating a method for tone mapping high dynamic range image data according to some embodiments of the present disclosure;

[0010] Figure 8 This is a flowchart illustrating a method for generating low dynamic range image data from high dynamic range image data according to some embodiments of the present disclosure;

[0011] Figure 9 This is a flowchart illustrating a method for distributing tone mapping operations according to some embodiments of the present disclosure;

[0012] Figure 10A The inference and / or training logic according to at least one embodiment is illustrated;

[0013] Figure 10B The inference and / or training logic according to at least one embodiment is illustrated;

[0014] Figure 11 The training and deployment of a neural network according to at least one embodiment are illustrated;

[0015] Figure 12 An example data center system according to at least one embodiment is shown;

[0016] Figure 13A An example of an autonomous vehicle according to at least one embodiment is shown;

[0017] Figure 13B The illustration shows an embodiment according to at least one of the embodiments. Figure 13A Examples of camera positions and field of view for autonomous vehicles;

[0018] Figure 13C This is an illustration based on at least one embodiment. Figure 13A A block diagram of an example system architecture for an autonomous vehicle;

[0019] Figure 13D The illustration, according to at least one embodiment, is for one or more cloud-based servers and Figure 13A A diagram of a system for communication between autonomous vehicles;

[0020] Figure 14 This is a block diagram illustrating a computer system according to at least one embodiment;

[0021] Figure 15 This is a block diagram illustrating a computer system according to at least one embodiment;

[0022] Figure 16 A computer system according to at least one embodiment is shown;

[0023] Figure 17 A computer system according to at least one embodiment is shown;

[0024] Figure 18A A computer system according to at least one embodiment is shown;

[0025] Figure 18B A computer system according to at least one embodiment is shown;

[0026] Figure 18C A computer system according to at least one embodiment is shown;

[0027] Figure 18D A computer system according to at least one embodiment is shown;

[0028] Figure 18E and Figure 18F A shared programming model according to at least one embodiment is shown;

[0029] Figure 19 An exemplary integrated circuit and a related graphics processor according to at least one embodiment are shown.

[0030] Figures 20A-20B An exemplary integrated circuit and an associated graphics processor according to at least one embodiment are shown.

[0031] Figure 21A and Figure 21B Additional exemplary graphics processor logic according to at least one embodiment is shown;

[0032] Figure 22 A computer system according to at least one embodiment is shown;

[0033] Figure 23A A parallel processor according to at least one embodiment is shown;

[0034] Figure 23B A partitioning unit according to at least one embodiment is shown;

[0035] Figure 23C A processing cluster according to at least one embodiment is shown;

[0036] Figure 23D A graphics multiprocessor according to at least one embodiment is shown;

[0037] Figure 24 A multi-graphics processing unit (GPU) system according to at least one embodiment is illustrated;

[0038] Figure 25 A graphics processor according to at least one embodiment is shown;

[0039] Figure 26 It is a block diagram illustrating a processor microarchitecture for a processor according to at least one embodiment;

[0040] Figure 27 A deep learning application processor according to at least one embodiment is shown;

[0041] Figure 28 A block diagram of an example neuromorphic processor is shown according to at least one embodiment;

[0042] Figure 29 At least a portion of a graphics processor according to one or more embodiments is shown;

[0043] Figure 30 At least a portion of a graphics processor according to one or more embodiments is shown;

[0044] Figure 31 At least a portion of a graphics processor according to one or more embodiments is shown;

[0045] Figure 32 A block diagram of a graphics processing engine of a graphics processor is shown according to at least one embodiment;

[0046] Figure 33 This is a block diagram illustrating at least a portion of a graphics processor core according to at least one embodiment;

[0047] Figure 34A and Figure 34B The diagram illustrates thread execution logic according to at least one embodiment, which includes an array of processing elements of a graphics processor core.

[0048] Figure 35 A parallel processing unit (“PPU”) according to at least one embodiment is shown;

[0049] Figure 36 A general-purpose processing cluster (“GPC”) according to at least one embodiment is illustrated;

[0050] Figure 37 A memory partition unit of a parallel processing unit (“PPU”) according to at least one embodiment is shown;

[0051] Figure 38 A streaming multiprocessor according to at least one embodiment is shown.

[0052] Figure 39 This is an example data flow diagram of an advanced computing pipeline according to at least one embodiment;

[0053] Figure 40This is a system diagram of an example system for training, adapting, instantiating, and deploying machine learning models in an advanced computing pipeline, according to at least one embodiment;

[0054] Figure 41 Example illustrations include an advanced computing pipeline 4010A for processing imaging data according to at least one embodiment;

[0055] Figure 42A Includes example data flow diagrams of virtual instruments supporting ultrasound equipment according to at least one embodiment;

[0056] Figure 42B Includes example data flow diagrams of virtual instruments supporting CT scanners according to at least one embodiment;

[0057] Figure 43A A data flow diagram illustrating the process for training a machine learning model according to at least one embodiment is shown; and

[0058] Figure 43B This is an example illustration of a client-server architecture that utilizes a pre-trained annotation model to enhance an annotation tool, according to at least one embodiment. Detailed Implementation

[0059] Embodiments of this disclosure relate to processing high dynamic range (HDR) images captured using fixed calibration settings. Systems and methods for obtaining HDR image data from an image sensor using fixed calibration settings (e.g., exposure settings) are disclosed, which are decoupled from pipelines for generating image data suitable for various applications (e.g., image signal processor (ISP), FPGA, or ASIC).

[0060] Compared to conventional systems, in various embodiments, the configuration of digital gain functions, ISP settings, and / or other imaging device settings decouples raw data collection (e.g., sensor data) from image signal processing, rather than relying on automatic exposure (AE) settings. This allows for better control over the resulting image (HDR image, standard dynamic range (SDR) image, and / or low dynamic range (LDR) image) that can be tailored to specific applications. Furthermore, in some embodiments, this decoupling of raw data collection allows for improvements, fixes, tuning changes, and other adjustments to the ISP pipeline without recollecting the raw data.

[0061] In one example, when capturing raw data from a camera device mounted on a vehicle, the camera's AE settings or other settings may result in images that are too bright, too dark, or otherwise produce suboptimal results. In various embodiments, the ability to capture raw data using fixed exposure settings and / or other fixed calibration settings of the camera device can be replaced by one or more components of an offline image signal processing pipeline. For example, the AE function of the camera device may be replaced by a tone mapping function of an ISP. Furthermore, in various embodiments, an offline image signal processing pipeline that may include specific algorithms can be tuned, added to, and / or removed to produce different results (e.g., image data with various properties) without collecting new raw data using the same raw data (e.g., raw data collected using fixed settings).

[0062] In one embodiment, adjusting an offline image signal processing pipeline includes modifying one or more parameters of a tone mapping function. For example, the tone mapping function may be a parametric function that defines a curve (e.g., a global tone curve), where the parameters of the function are fitted such that the curve is constrained through (or includes) low-tone points, mid-tone points, and high-tone points. As a result, in embodiments where the offline image signal processing pipeline includes a tone mapping function, the parameters of the function are adjusted to generate different image data from the same raw data.

[0063] Furthermore, in various embodiments, images generated by the offline image signal processing pipeline (e.g., image data with low dynamic range) are used to train the neural network. In one example, these images are used to train the neural network to perform object detection for an autonomous vehicle. In some embodiments, the results of inference operations performed by the neural network are also used to adjust, improve, or otherwise modify the offline image signal processing pipeline. For example, if a trained neural network performs poorly in low-light environments when performing inference, the offline image signal processing pipeline is adjusted, and the raw data is reprocessed to produce training data (e.g., images) that, when used to retrain the neural network, result in better performance.

[0064] refer to Figure 1 , Figure 1This describes an environment 100 that includes a fixed-position capture system 102 and image signal processing 140, according to some embodiments of this disclosure. It should be understood that such and other arrangements described herein are merely illustrative examples. Other arrangements and elements (e.g., machines, interfaces, functions, commands, functional groups, etc.) may be used in addition to or instead of those shown, and some elements may be omitted entirely. Furthermore, many of the elements described herein are functional entities that can be implemented as discrete or distributed components or in combination with other components, and implemented in any suitable combination and location. The various functions described herein as being performed by entities can be performed by hardware, firmware, and / or software. In one example, various functions are performed by logical devices, such as, but not limited to, a general-purpose processor 122 and / or an image signal processor (ISP) 124 executing instructions stored in memory. In another example, various functions (e.g., image signal processing 140) are performed by a server (e.g., hereinafter referred to as...). Figure 15 The components of server 1512 (which may be described in more detail) and / or services provided by a computing resource service provider are used to perform this function.

[0065] In various embodiments, the fixed-set capture system 102 captures high dynamic range (HDR) image data (e.g., raw data, bitmaps, raster graphics, or other data structures representing a set of pixels) at least in part based on digital exposure calibration data 110. Furthermore, various embodiments include image signal processing 140 to perform tone mapping on the HDR image data. For example, by controlling the brightness of the image encoded by the HDR image data and / or the image encoded by the tone-mapped image data.

[0066] In one embodiment, the result of image signal processing 140 includes image data for performing model training 112. In one example, tone-mapped HDR image data is converted to standard dynamic range (SDR) image data or low dynamic range (LDR) image data by compression of pixel values ​​(e.g., by applying a gamma compression function to the tone-mapped HDR image data). In various embodiments, these SDR and LDR images are used to train one or more neural networks to perform various tasks, such as those described below in conjunction with autonomous vehicles. A non-limiting embodiment includes capturing and / or receiving source image data using a fixed exposure setting of an image sensor. For example, the source image data may be HDR image data and may represent and / or encode the source image.

[0067] In various embodiments, image signal processing 140 processes image data acquired from a fixed-set capture system 102 based at least in part on applications that will use the image data and / or train models. As shown in environment 100, example applications include manned or unmanned land vehicles (e.g., vehicle 104), manned or unmanned aerial vehicles (e.g., drone 106), or wearable devices (e.g., smart glasses 108). For example, image signal processing 140 processes the captured image data to train a model to perform flight operations of drone 106. In another example, image signal processing 140 processes the captured image data to train a model to perform object detection for use by smart glasses 108. In one embodiment, as part of processing the captured image data for a specific application, image signal processing 140 determines tone control points based at least in part on source pixel values ​​of the captured image data. In one example, the determined tone control points include low-tone points, mid-tone points, and / or high-tone points. In some embodiments, tone control points also include glare suppression points. In at least one embodiment, additional tone control points are determined.

[0068] although Figure 1 The fixed-set capture system 102 shown is illustrated as a single camera, but this is not intended to be limiting. In various embodiments, there can be any number of camera computing devices, including... Figure 1 A camera computing device not explicitly shown. In various embodiments, the fixed-set capture system 102 includes a computing device comprising one or more image sensors and / or cameras capable of implementing digital exposure calibration data 110. In one example, the fixed-set capture system 102 includes a dashcam with a fixed exposure setting. In another example, the fixed-set capture system 102 includes multiple image sensors positioned such that images depicting a 360-degree scene are captured using the digital exposure calibration data 110.

[0069] Furthermore, in various embodiments, Figure 1 The camera computing device depicted (e.g., the camera devices included in 102-108) includes one or more image sensors capable of capturing high dynamic range (HDR) image data, as discussed throughout. In various embodiments, environment 100 includes other computing devices, such as, but not limited to, server computing devices. In one example, the server computing device implements image signal processing 140. Vehicle 104 and / or drone 106 may be at least partially manually operated vehicles and / or partially autonomous when driven by a human. In some embodiments, when unmanned, vehicle 104 and drone 106 may be autonomous, partially autonomous, and / or remotely controlled vehicles. Figures 13A-13D Various embodiments of this vehicle are discussed.

[0070] Combination Figure 11-14 Various embodiments of the computing device have been discussed, including but not limited to computing devices 102-108 and those implementing image signal processing 140. However, briefly here, in one embodiment, combined with Figure 1 The described computing devices include one or more logic devices. For example, a fixed capture system 102 is shown to include a logic device 118. In one embodiment, the logic device 118 includes a general-purpose processor 122 (e.g., a central processing unit (CPU), microcontroller, microprocessor, etc.), an image signal processor (ISP) 124, an application-specific integrated circuit (ASIC) 126, and / or a field-programmable gate array (FPGA) 128. Although Figure 1 Not shown, but in some embodiments, logic device 118 includes a graphics processing unit (GPU). It should be noted that in various embodiments, any computing devices 102-108 and those implementing image signal processing 140 include one or more such logic devices. In various embodiments, image signal processor (ISP) 124, as a component of the computing device, implements image signal processing 140 or a component thereof. For example, a server computer system includes or otherwise simulates image signal processor (ISP) 124 or a component thereof.

[0071] In one embodiment, various components of environment 100 (e.g., computing devices 102-108) communicate through one or more networks. For example, one or more networks include wide area networks (WANs) (e.g., the Internet, the Public Switched Telephone Network (PSTN), etc.), local area networks (LANs) (e.g., Wi-Fi, ZigBee, Z-Wave, Bluetooth, Bluetooth Low Energy (BLE), Ethernet, etc.), low-power wide area networks (LPWANs) (e.g., LoRaWAN, Sigfox, etc.), global navigation satellite system (GNSS) networks (e.g., Global Positioning System (GPS)), and / or other network types.

[0072] Furthermore, in various embodiments, one or more computing devices 102-108 implement, operate, or otherwise perform the functions and / or operations of image signal processing 140. Figure 1In the example shown, a fixed capture system 102 is illustrated as implementing image signal processing 140. For example, the fixed capture system 102 includes one or more image sensors and a logic device 118 implementing image signal processing 140 (e.g., part of an autonomous or partially autonomous vehicle capturing training images of various environments). However, any computing device described in this disclosure can implement image signal processing 140. Furthermore, in various embodiments, any logic device 118 can implement at least some of the functions, operations, and / or actions of image signal processing 140.

[0073] Image signal processing 140 can implement various methods for tone mapping of HDR image data, and control the brightness of an image encoded from HDR image data and / or tone-mapped image data. To perform such functions, in various embodiments, image signal processing 140 includes one or more components, modules, devices, etc., below. Figure 2 and Figure 3 Example image signal processing 140 is described. In some embodiments, the image signal processing 140 is described in conjunction with or hereinafter referred to as image signal processing 140. Figure 2 and Figure 3 Any of the components, modules, and / or devices described may be optional.

[0074] As discussed throughout, in various embodiments, image signal processing 140 implements and / or performs a combination of Figure 5-8 Methods 500, 600, 700, and 800 discuss at least a portion of the processes, actions, and / or operations. Therefore, one or more logic devices 118 may implement and / or perform at least a portion of methods 500, 600, 700, and / or 800.

[0075] In various embodiments, the fixed-position capture system 102 includes one or more HDR image sensors 144 capable of capturing image data as HDR image data. For example, the captured HDR image data encodes an image or scene imaged by the HDR image sensor 144. In one embodiment, the pixel depth of the HDR image data may be equal to or greater than 96 bits (32 bits per color channel). In various embodiments, the image data captured by the HDR image sensor 144 is referred to as source image data. For example, source image data includes multiple images captured using digital exposure calibration data 110. As described above, in various embodiments, the HDR image sensor 144 that captures the source image data is mounted on a vehicle (e.g., vehicle 104 or drone 106). For example, the vehicle includes an autonomous or at least partially autonomous vehicle controlled at least partially based on source image data and / or target image data. In some embodiments, the source image data is encoded in a linear color space lacking non-linear mapping.

[0076] In various embodiments, the HDR image sensor 144 includes, is influenced by, and is constrained by digital exposure calibration data 110. In one embodiment, the digital exposure calibration data 110 is a fixed, static, and / or other constant exposure setting. For example, the digital exposure calibration data 110 includes exposure settings, aperture, shutter speed, depth of field, image sensor sensitivity, white balance, flash settings, color settings, or any other settings of the image sensor, camera, or computing device (e.g., computing devices 104-108 including the image sensor). In at least one embodiment, the user manually sets at least a portion of the digital exposure calibration data 110, which remains unchanged during the capture of the source image data.

[0077] In various embodiments, source image data is provided via a network to image signal processing 140, which is implemented at and / or by one or more services of a server computing device. That is, while in one example the source HDR image data is captured by a fixed-set capture system 102, tone mapping and brightness control of the image data can be performed offline on the server computing device. In other words, tone mapping of the HDR image data can be offloaded to another computing device, such as, but not limited to, a server computing device that does not capture image data. Various embodiments enable or at least facilitate the enabling of various machine and / or computer vision features of autonomous vehicles, such as, but not limited to, vehicle 104 or drone 106. Embodiments can be deployed to enable machine and / or computer vision features of other applications, such as, but not limited to, robotic applications.

[0078] In various embodiments, once the source image data (e.g., data collection for machine learning training and inference) is collected and stored, the source image data is processed by image signal processing 140 to generate target image data. For example, this decoupling of image signal processing and data collection allows enhancements and repairs 120 and / or tuning modifications 122 to be applied to one or more components of image signal processing 140, such as tone mapping functions. According to the embodiments described in this disclosure, this enables the source data to be reused over longer time intervals without performing additional, costly, and time-consuming data collection. Furthermore, enhancements and repairs 120 and / or tuning modifications 122 can be applied to any component of image signal processing 140 as described below, such as... Figure 2 , 3The improvements and fixes described in sections 1 and 4. Furthermore, in various embodiments, improvements and fixes 120 and / or tuning modifications 122 include adding additional components and / or image processing algorithms to image signal processing 140. In one example, improvement and fix 120 includes adding a new tone mapping function to image signal processing 140. In yet another example, tuning modifications 122 include altering the tone mapping function to produce different characteristics of the target image data (e.g., brighter, darker, color values, color saturation, compression ratio, dynamic range, etc.).

[0079] In various embodiments, the tone mapping function is determined at least in part based on at least a portion of the control points. For example, the tone mapping function may be a parametric function that defines a curve (e.g., a global tone curve). The parameters of the function may be fitted such that the curve is constrained to pass through (or include) low-tone points, mid-tone points, and high-tone points. In some embodiments, the curve is further constrained to pass through at least a portion of additionally determined points.

[0080] In at least one embodiment, determining the tone mapping function may further be based at least in part on a gain value. In one example, the gain value is determined at least in part on at least one other tone control point among the midtone point and tone control points, such as, but not limited to, a glare suppression point. The gain value may be determined as equal to the slope of a gain line passing through the midtone point and the glare suppression point. In one embodiment, the fitting of the tone mapping function is further constrained such that the derivative and / or instantaneous rate of change of the function evaluated at one of the components of the midtone point are at least approximately equal to the gain value. In various embodiments, image signal processing 140 generates target image data (e.g., images used to perform model training 112) by applying a tone mapping function to the captured image data to at least transform the captured image data. For example, the target image data includes target pixel values ​​defined by applying a tone mapping function to the pixel values ​​of the captured image data.

[0081] Compared to traditional methods, various embodiments of the image capture system utilize fixed digital exposure calibration data 110 without relying on automatic exposure (AE) settings to achieve extensive image signal processing (e.g., offline image processing). As described below, tone-mapped images may have more detail and contrast. Furthermore, the various embodiments are able to control the overall image brightness of HDR images and / or tone-mapped images without applying a digital gain function. Moreover, since the image data captured with fixed settings (e.g., raw data) is uniform, various image processing algorithms (e.g., tone mapping) can be applied consistently and modibly. Therefore, images generated by the various embodiments can be reprocessed, optimized, or otherwise modified, at least in part, based on various factors (e.g., application, results of training models, image quality, etc.). For example, a particular captured image can be reprocessed to suppress glare (e.g., positive black points or errors in black level subtraction in the image data) and to compress highlights in HDR image data (e.g., pixels with significant brightness values).

[0082] In various embodiments, digital exposure calibration data 110 includes exposure settings or periods for capturing multiple images. In one example, a fixed-set capture system 102 is attached to a vehicle and captures images while the vehicle is in motion to generate training data for model training 112. In one embodiment, an HDR image (encoded by HDR image data) is generated from pixel values ​​of multiple SDR images (e.g., captured by the fixed-set capture system 102). In various embodiments, the digital exposure calibration data 110 is determined such that the resulting image can be modified for optimal use in a particular application or multiple applications. For example, using a longer exposure setting for the digital exposure calibration data 110 allows the pixel values ​​of the HDR image (e.g., after image signal processing) to capture darker areas of the imaging scene with more detail. Pixel values ​​generated using a longer exposure time can capture more detail and contrast in darker areas of the scene. In another example, using a shorter exposure setting for the digital exposure calibration data 110 allows the HDR pixel values ​​(e.g., after image signal processing) to capture brighter areas of the imaging scene. Using pixel values ​​generated by a shorter exposure time can prevent “fading” or overexposure effects in brighter or more overexposed areas of the scene. In other embodiments, HDR image data can be generated from a single image, where an image sensor (e.g., camera pixels) captures the image using digital exposure calibration data 110.

[0083] As described above, conventional HDR cameras and systems rely on the user to properly configure their camera's AE settings. Such AE settings may include automatic exposure bracketing (AEB) settings and / or various AE modes (e.g., night and day AE modes). These AE settings may not be changed or may be changed inappropriately to match the current environment. For example, a conventional HDR camera may not offer separate AE modes for sunny, cloudy, or states in between. Therefore, by capturing multiple images (e.g., training images) using fixed settings (e.g., digital exposure calibration data 110), image signal processing 140 is able to perform improvements and repairs 120, as well as tuning modifications to the images. Image signal processing 140 improves image quality without needing to capture all new images.

[0084] For example, when the AE mode cannot adequately provide exposure settings consistent with the lighting conditions of multiple scenes at the time of shooting, the overall brightness of the HDR image may not accurately reflect the scene's lighting conditions. For instance, the HDR image may fail to render the scene as bright, or it may appear as a faded HDR image (even after image signal processing), which is suboptimal for various applications. Furthermore, to compensate for this lighting mismatch, conventional HDR cameras and systems typically employ digital gain functions to adjust or increase the brightness of HDR pixel values. The gain value applied to a pixel can be significant under various lighting conditions and / or AE settings. Such a large gain often saturates and / or clips brighter areas of the HDR image, potentially making these areas appear faded or overexposed. In various embodiments, consistent and optimal results were obtained by using digital exposure calibration data 110 for capturing multiple scenes as a result of image signal processing 140.

[0085] Furthermore, conventional tone mapping can result in lossy compression of HDR image data, and in many cases, the quality of lower dynamic range (HDR) or standard dynamic range (SDR) images can be significantly reduced compared to HDR images. More specifically, conventional tone mapping may be limited in its ability to preserve critical information from HDR image data. Conventional tone mapping may fail to retain a significant amount of critical information from HDR image data, especially when the aforementioned AE settings and / or modes are unsuitable for the current lighting conditions of the scene. For example, when imaging a dimly lit scene, a user may not be able to switch a conventional HDR camera from daytime mode to nighttime mode. HDR images may be underexposed because HDR image data cannot encode most of the detail and contrast in the darker areas of the imaged scene. As a result, when generating an SDR (or LDR) image from underexposed HDR image data, the underexposure of the SDR image may be more pronounced. Therefore, in various embodiments, by performing image signal processing "offline" (e.g., after capturing an image using fixed calibration settings), critical information is preserved, and image signal processing 140 is able to generate higher quality, more detailed images, resulting in better performance.

[0086] Furthermore, even when the AE settings are suitable for the current lighting conditions, these conditions may be dynamic over time, while the AE settings may remain constant or respond slowly to changes in conditions. For example, conditions can change from bright and sunny to cloudy and overcast, and changes in AE settings may not adequately account for these changes and / or may change quickly enough. As a result, conventional tone mapping, applied at the frame level, may not readily account for dynamic conditions. For instance, during the capture of HDR video image data, relatively bright objects (e.g., highly reflective objects or objects that include light sources) may enter the scene, and the current AE settings may not be suitable for introducing such bright objects. Conventional tone mapping may render dynamically bright objects as overexposed, and the overall brightness of the video image data may fluctuate. However, in various embodiments, using fixed settings in the capture system 102 allows the image signal processing 140 to accurately process and / or adjust the image to address such dynamic conditions.

[0087] In various embodiments, the tone mapping function applied by image signal processing 140 includes a global tone mapping (GTM) function and / or a global tone curve (GTC). For example, the tone mapping function is determined dynamically and / or globally, at least in part, based on the HDR image, the application that will use the image, or other considerations. Therefore, the tone mapping function can be used to dynamically and globally tone map HDR image data. When applied to HDR image data, the tone mapping function maps the hue (e.g., brightness) of the HDR image data such that the tone-transformed HDR image data can encode image brightness that matches the lighting conditions of the imaging scene. The tone mapping function can also minimize visual artifacts (e.g., glare suppression and specular compression) caused by HDR imaging.

[0088] In various embodiments, after tone mapping, HDR image data is compressed into SDR or LDR image data by filtering the least significant bit (LSB) of the HDR pixel values. In some embodiments, the tone-mapped HDR image data is color-compressed using a gamma compression function before pixel depth reduction. For example, HDR image data is captured using a fixed exposure setting (e.g., digital exposure calibration data 110), and the captured HDR image data is referred to as source image data. The tone mapping function may be dynamically determined by image signal processing 140 (or components thereof, as described in more detail below) based at least in part on the analysis of the pixel values ​​of the source image data. In one embodiment, the tone mapping function is a nonlinear function that maps source pixel values ​​of the source image data to target pixel values ​​of the target image data. For nonlinear embodiments, the nonlinear tone mapping function and / or GTM function is plotted in 2D coordinates as a Global Tone Curve (GTC).

[0089] In various embodiments, to generate the tone mapping function, image signal processing 140 (or components thereof) determines a plurality of control points, at least in part, based on dynamic analysis of the source image data. For example, control points are defined in a plane spanned by ranges of source and target pixel values. In some embodiments, control points are defined at least in part based on regions of interest (ROIs) of the source image data. In one example, the tone mapping function defines a one-to-one nonlinear mapping between the values ​​of source and target image pixels. For example, the tone mapping function defines (or at least evaluates to be a numerical approximation of) a curve in the source / target plane. In one embodiment, the curve is an approximation of a curve (e.g., a plurality of piecewise linear segments with varying slopes). In one example, the tone mapping function is a spline function comprising a polynomial of degree greater than 1. In some embodiments, the tone mapping function is a one-to-one linear mapping function. For example, control points in the plane define one or more constraints on the tone mapping function. In some embodiments, a parameterized tone mapping function is fitted at least in part based on one or more constraints (e.g., the parameters defining the tone mapping can be selected by minimizing a difference or cost function). More specifically, the cost function may be defined by one or more constraints. For example, a spline function with polynomial piecewise divisions of any degree is fitted at least in part based on one or more constraints.

[0090] In various embodiments, at least a portion of the control points indicate constraints on the tone mapping of a specific and finite number of source pixel values ​​and corresponding target pixel values. To suppress glare and compress highlights, in various embodiments, some control points define glare suppression or highlight compression thresholds for the source image data. In one embodiment, at least some control points are used to constrain the derivative (or at least its numerical approximation) of the tone mapping function evaluated at one or more control points. That is, some control points can be used to constrain the slope of the gain (e.g., gain value) of the tone mapping function at one or more other control points.

[0091] In some embodiments, at least three control points are determined: a low-tone point, a mid-tone point, and a high-tone point. For example, the low-tone point defines the tone mapping between the lowest pixel value of the source image data and the lowest pixel value of the target image data, as well as a glare suppression threshold for the source image data. Similarly, for example, the high-tone point defines the tone mapping between the highest pixel value of the source image data and the highest pixel value of the target image data, as well as a highlight compression threshold for the source image data. The mid-tone point, for example, defines the tone mapping between mid-tone values ​​of the source image data and mid-tone values ​​of the target image data. As discussed below, in some embodiments, the mid-tone point is also used to constrain the derivative of the tone mapping function.

[0092] In some embodiments, because low-tone points define a mapping between the tonal values ​​of the darkest or "black" pixels in the source and target image data, low-tone points can be the mapped "black points" (BP). Similarly, because high-tone points can define a mapping between the tonal values ​​of the brightest or "white" pixels in the source and target image data, in some embodiments, high-tone points are the mapped "white points" (WP). In some embodiments, when fitting a tone mapping function, tone mapping parameters are selected to force the tone mapping function to evaluate (or at least approximate) these control points. In other embodiments, the tone mapping function is limited to evaluating (or at least approximating) additional control points.

[0093] In at least some embodiments, the derivative of the tone mapping function (or at least its numerical approximation) is constrained at the midtone point or any other such control point. That is, the slope of the midtone gain (defined by the tone mapping function) can be limited and / or set at the midtone point. To constrain the derivative of the tone mapping function (or its numerical approximation) at the midtone point, additional control points are defined in various embodiments. For example, the derivative of the tone mapping function evaluated at the midtone point is constrained to be at least approximately equal to the slope (e.g., the gain value) of a line passing through the midtone point and the additional control point. In one such example, the additional control point is the maximum glare removal (MFR) point, which specifies a threshold of the source pixel value for glare removal.

[0094] As a further example, the slope of the midtone gain is constrained to be at least approximately equal to the ratio of the midtones of the target image data to the midtones of the source image data. As an even further example, the slope of the midtone gain is set by other methods (e.g., user-configurable settings). For example, after user observation, the slope of the midtone gain or other parameters of the image signal processing 140 is modified to achieve improved results. In various embodiments, when fitting a parameterized tone mapping function, parameters are selected to force the derivative of the tone mapping function evaluated at the midtone point to be at least close to the midtone gain defined in these or any other ways.

[0095] In one embodiment, once the tone mapping function is determined, image signal processing 140 generates target image data by applying the tone mapping function to source image data (e.g., raw data captured by a fixed-set capture system 102). In some embodiments, statistical measures of the source image data are determined, and control points are determined from the statistical measures. Some disclosed embodiments are deployed in in-vehicle imaging devices (e.g., dashcams). Furthermore, various embodiments are deployed in autonomous vehicle applications or other such machine vision applications. Embodiments can be deployed in any application employing one or more machine and / or computer vision methods. For example, embodiments can be deployed to enable any of the various machine vision features of autonomous vehicles (see [link to documentation]). Figures 13A-13DImplementations can be deployed to enable machine vision in robots, such as, but not limited to, manufacturing robots.

[0096] Figure 2 An environment 200 according to at least one embodiment is illustrated, wherein offline image signal processing 240 is performed on raw data acquired during data collection 202. In various embodiments, data collection 202 includes capturing raw data representing one or more environments using one or more image sensors 244. For example, data collection 202 includes capturing a set of images of objects in the context, such as pedestrians, traffic signals, construction sites, equipment, or other objects. In various embodiments, the image sensors 244 include one or more different types of sensors, such as global navigation satellite system sensors, radio detection and ranging (RADAR) sensors, ultrasonic sensors, light detection and ranging (LIDAR) sensors, inertial measurement unit (IMU) sensors, stereo cameras, wide-angle cameras, infrared cameras, surround cameras, long-range and / or medium-range cameras, and / or combinations thereof. Figures 13A-13D Other sensor types will be described in more detail below. In other embodiments, image sensor 244 includes a variety of sensors, such as those described below. Figure 3 The HDR image sensor 344 is described. Furthermore, for example, as... Figure 2 As shown, the image sensor 244 operates according to the exposure setting 242. In various embodiments, the exposure setting 242 includes a fixed exposure setting for the image sensor 244 used during data collection 202. In one example, the exposure setting 242 includes settings for a computing device including the image sensor 244, such as those described above. Figure 1 The described digital exposure calibration data is 110.

[0097] In various embodiments, offline image signal processing 240 includes various components, such as image processing 258, statistics module 252, tone mapping 256, and / or other processing 250. The various components of offline image signal processing 240 may include, for example, dedicated hardware and / or executable code or other instructions that, when executed by one or more processors of a computing device, cause the computing device to perform the operations described in this disclosure. In one embodiment, image processing 258 includes performing operations on source image data (e.g., raw data collected during data collection 202) to prepare the source image data for tone mapping 256. For example, image processing 258 includes data transformation (e.g., converting raw data from one format to another), adjusting black levels, color values, saturation, depigmenting, noise removal, or other operations to prepare the source image data to be processed by the tone mapping function.

[0098] In embodiments that include and / or enable the statistics module 252, the statistics module 252 determines and / or generates multiple statistical measures based at least in part on the pixel values ​​of the source image data (or pixel values ​​of a portion of the source image data). In one example, the multiple statistical measures include statistical measures based at least in part on the pixel values ​​of the source image data. In various embodiments, the statistical measures include one or more parameters that characterize any continuous or discrete statistical distribution and / or histogram that can be constructed from the source image data. For example, such parameters include the mean, median, and / or standard deviation of one or more statistical distributions derived from the pixel values ​​of the source image data.

[0099] In various embodiments, once the raw data has been processed (e.g., image processing 258), the system performing offline image signal processing 240 performs tone mapping 256. In yet another embodiment, tone mapping 256 is performed without processing or otherwise modifying the raw data. In various embodiments, tone mapping 256 includes applying one or more tone mapping functions to the source image data to generate target image data. Various tone mapping functions, such as those described below, can be used in conjunction with the various embodiments described in this disclosure. Furthermore, various tone mapping functions are described in U.S. Patent Application Publication No. 2021 / 0035273 by Deng et al., which, by reference, as set forth herein, can be used as examples of tone mapping function 256.

[0100] In one embodiment, the system performing offline image signal processing 240 performs other processing 250. For example... Figure 2 As shown, other processes 250 in various embodiments are optional and may be included or removed, at least in part, based on the application of the results. For example, other processes 250 include image transformation (e.g., image formatting), data transformation (e.g., metadata), image filtering, pixelation, image filling, affine transformation, white balance, color correction, or any other pre- or post-image processing or other data processing techniques. Once offline image signal processing 240 is complete (e.g., after execution by a computer system), it produces a set of results including the target image data. Figure 2 As shown, in various embodiments, the results include image 256 (e.g., target image data) and neural network 262.

[0101] In various embodiments, image 260 includes target image data comprising target pixel values ​​defined by applying tone mapping function 256 (and / or other image processing 250) to pixel values ​​of source image data. For example, image 260 may include an LDR or HDR image generated by offline image signal processing 240. In various embodiments, neural network 262 includes a neural network trained at least in part on image 260. In one example, neural network 262 includes various neural networks described below in conjunction with 13D. In at least one embodiment, neural network 262 includes one or more neural networks (or other models) that classify one or more aspects of input data (e.g., image 260) at least in part. That is, for example, neural network 262 includes one or more neural networks to perform an imaging processing task of classifying one or more features of imaging data (e.g., target image data). In one embodiment, neural network 262 includes various types of machine learning models (e.g., operations to be performed by neural network 262) depending on the implementation. In other words, neural network 262 may include, for example, one or more machine learning models using linear regression, logistic regression, decision trees, support vector machines (SVM), Naive Bayes, k-nearest neighbors (Knn), K-means clustering, random forests, dimensionality reduction algorithms, gradient boosting algorithms, neural networks (e.g., autoencoders, convolutional, residual, recurrent, perceptrons, long / short-term memory (LSTM), Hopfield, Boltzmann, deep belief, deconvolution, generative adversarial, liquid machines, etc.) and / or other types of machine learning models. More specifically, as examples, convolutional neural networks (CNNs) include region-based or region convolutional neural networks (RCNNs) and fast RCNNs (e.g., for object detection) or other types of CNNs. Furthermore, in various embodiments, neural network 262 includes multiple models that may be static or at least dynamically determined based on the application (e.g., object detection, autonomous vehicles, etc.).

[0102] In various embodiments, the evaluation results (e.g., image 260 and / or neural network 262) determine improvements and repairs 266 and / or tuning changes 264 to offline image signal processing 240 or its components. In one example, a user examines image 260 to determine if image 260 has one or more problems that need to be corrected by improvements and repairs 266 and / or tuning changes 264. Similarly, in another example, the results generated by neural network 262 are evaluated to determine if there are one or more problems related to offline image signal processing 240 or its components that need to be corrected by improvements and repairs 266 and / or tuning changes 264. In various embodiments, one or more problems include bright and / or dark areas of image 260, quality problems of image 260, performance problems of neural network 262 (e.g., failures under certain lighting conditions), inference problems 262 performed by neural network (e.g., misclassification of input data), or any other problems associated with image 260 and / or neural network 262, which can be corrected by improving and fixing 266 and / or tuning changes 264 to offline image signal processing 240.

[0103] In various embodiments, improvements and repairs 266 and / or tuning changes 264 are applied to offline image signal processing 240, and the same raw data (e.g., source image data used to generate target image data corresponding to the result) is reprocessed using improvements and repairs 266 and / or tuning changes 264. For example, as a result of using a fixed exposure setting 242, improvements and repairs 266 and / or tuning changes 264 can be applied to offline image signal processing 240 without performing additional data collection 202. In various embodiments, data collection 202 is separated from image signal processing (e.g., by performing offline image signal processing 240), and the same raw data can be used to generate different results by at least applying improvements and repairs 266 and / or tuning changes 264. For example, by using the same exposure settings for data collection 202, offline image signal processing 240 can be applied to the source data to generate predictable and consistent target data (e.g., similar illumination levels, color balance, etc.). As a result, in various embodiments, the results of offline image signal processing 240 (e.g., image 260 and / or neural network 262) are evaluated, improvements and repairs 266 and / or tuning changes 264 are applied, and then new target image data is generated using the source image data, thus eliminating the need to collect new source image data (e.g., perform additional data collection 202).

[0104] In various embodiments, tuning change 264 includes modifications to tone mapping 256 or other image processing algorithms used during offline image signal processing 240. In one example, various components of tone mapping 256, such as control points, glare suppression, gain curves, gain lines, tone mapping functions, or other components of one or more tone mapping functions as described in this disclosure (e.g., Figure 3-4 The modification is at least in part based on tuning change 264. In one embodiment, improvement and repair 266 modifies one or more other components of offline image signal processing 240. In one example, improvement and repair 266 modifies, adds, or removes components of image processing 258 and / or other processing 250 of the source image data. In one embodiment, improvement and repair 266 and tuning change 264 comprise a single set of modifications to offline image signal processing 240.

[0105] refer to Figure 3 , Figure 3 Schematic diagrams of a system 300 according to some embodiments of the present disclosure are provided. For example, system 300 includes a high dynamic range imaging (HDRI) system. It should be understood that such and other arrangements described herein are merely illustrative examples. Other arrangements and elements (e.g., machines, interfaces, functions, commands, functional groups, etc.) may be used in addition to or instead of those shown, and some elements may be omitted entirely. Furthermore, many of the elements described herein are functional entities that can be implemented as discrete or distributed components or in combination with other components, and implemented in any suitable combination and location. The various functions described herein as being performed by entities can be performed by hardware, firmware, and / or software. For example, various functions can be performed by logic devices, such as, but not limited to, a general-purpose processor 322 and / or an image signal processor (ISP) 324 executing instructions stored in memory.

[0106] In various embodiments, system 300 may in particular include a computing device comprising one or more image sensors (e.g., cameras). Such computing devices include, for example, mobile or fixed cameras (e.g., handheld cameras, smartphones, tablets, etc.), manned or unmanned land vehicles (e.g., vehicle 304), manned or unmanned aerial vehicles (e.g., drones 306), or wearable devices (e.g., smart glasses 308). Such computing devices including one or more image sensors are collectively referred to herein as camera computing devices 302-308. For example, a camera computing device includes one or more HDR image sensors 344 and HDR sensor exposure settings 342.

[0107] In various embodiments, the HDR image sensor 344 captures image data including HDR image data. For example, the captured HDR image data encodes an image or scene imaged by the HDR image sensor 344. In various embodiments, the image data captured by the HDR image sensor 344 is referred to as source image data. Thus, in at least one example, the source image data includes HDR image data encoded from an HDR source image. As discussed throughout, in one embodiment, the HDR image sensor 344 that captures the source image data is mounted on a vehicle (e.g., a land vehicle 304 or a drone 306). For example, the vehicle may be autonomous or at least partially autonomous and may be controlled at least partially based on the source image data and / or target image data 360. In some embodiments, the source image data is encoded in a linear color space lacking a non-linear mapping. According to at least one embodiment, the HDR image sensor 344 includes one or more HDR sensor exposure settings 342, and is influenced by and / or constrained by these one or more HDR sensor exposure settings 342. As described above, in various embodiments, the HDR sensor exposure settings 342 are fixed, static, and / or constant exposure settings. In such embodiments, at least a portion of the value of the HDR sensor exposure setting 342 is determined at least partially based on the lighting conditions and / or other environmental conditions of the scene to be imaged. For example, the HDR sensor exposure setting 342 is determined such that the HDR image sensor 344 captures a sufficient amount of data for different environmental and lighting conditions (e.g., rain, clear sky, nighttime images, bright daytime, etc.). In at least one embodiment, the user manually sets at least a portion of the HDR sensor exposure setting 342 to be fixed during the duration of data collection.

[0108] Despite Figure 3 Some camera computing devices are shown, but this is not intended to be limiting. In any example, there can be any number of camera computing devices and / or... Figure 3 Camera computing devices not explicitly shown. For example, various computing devices including one or more image sensors, cameras and / or other sensors can be included in the system 300 described according to various embodiments.

[0109] In various embodiments, camera computing devices 302-308 (or other camera computing devices included in system 300) include one or more image sensors capable of capturing high dynamic range (HDR) image data, as discussed throughout. For example, camera computing devices 302-308 are used to perform various data collection operations, such as capturing images of different environments and / or different conditions for training one or more models. In one embodiment, system 300 includes other computing devices, such as, but not limited to, server computing device 330. In one example, server computing device 330 does not include image sensors. However, in other embodiments, server computing device 330 includes image sensors (e.g., auxiliary cameras). Land vehicle 304 and / or drone 306 may be at least partially manually operated vehicles and / or partially autonomous when driven by a human. In some embodiments, when unmanned, vehicle 304 and drone 306 are autonomous, partially autonomous, and / or remotely controlled vehicles. Figures 13A-13D Various embodiments of this vehicle are discussed.

[0110] Combination Figure 13A The computing device 1300 discusses various embodiments of computing devices, including but not limited to camera computing devices 302-308 and / or server computing device 330. However, briefly herein, camera computing devices 302-308 and / or server computing device 330 may, for example, include one or more logic devices. For example, server computing device 330 is shown as including logic device 320. In various embodiments, logic device 320 includes a general-purpose processor 322 (e.g., a central processing unit (CPU), microcontroller, microprocessor, etc.), an image signal processor (ISP) 324, an application-specific integrated circuit (ASIC) 326, and / or a field-programmable gate array (FPGA) 328. Although... Figure 3 Not shown, but in some embodiments, logic device 320 includes a graphics processing unit (GPU) and / or a data processing unit (DPU). It should be noted that any of camera computing devices 302-308 and / or server computing device 330 may include one or more such logic devices.

[0111] In various embodiments, components of the HDRI system 300 (e.g., camera computing devices 302-308 and / or server computing device 330) communicate via network 332. Network 332 includes, for example, wide area networks (WANs) (e.g., the Internet, Public Switched Telephone Network (PSTN), etc.), local area networks (LANs) (e.g., WiFi, ZigBee, Z-Wave, Bluetooth, Bluetooth Low Energy (BLE), Ethernet, etc.), low-power wide area networks (LPWANs) (e.g., LoRaWAN, Sigfox, etc.), global navigation satellite system (GNSS) networks (e.g., Global Positioning System (GPS)), and / or other network types. In one example, components of the HDRI system 300 communicate with one or more other components via one or more networks 332. For example, camera computing devices 302-308 perform data collection and transmit source image data to server computing device 330 via one or more networks 332.

[0112] In various embodiments, server computing device 330 implements, operates, or otherwise performs the functions and / or operations of high dynamic range (HDR) engine 340. Figure 3 In the example shown, server computing device 330 is shown to implement HDR engine 340. However, in other examples, any camera computing device 302-308 may implement HDR engine 340 (e.g., any logical device 320 included in camera computing devices 302-308), and may implement at least some of the functions, operations, and / or actions of HDR engine 340.

[0113] In one embodiment, the HDR engine 340 enables various methods of tone mapping of HDR image data, and controls the brightness of the image encoded by the HDR image data and / or tone-mapped image data. To perform such functions, the HDR engine 340 may include, for example, one or more components, modules, devices, etc. In various embodiments, such components, modules, and / or devices include, but are not limited to, a region of interest (ROI) locator 348, a delay unit 350, a statistics module 352, a control point selector 354, a tone map generator 356, and / or a tone map applicator 358. In some embodiments, any of these components, modules, and / or devices are optional. For example, in one embodiment, the ROI locator 348, the delay unit 350, and the statistics module 352 are optional.

[0114] Such as combination Figure 3 The enumeration of components, modules, and / or devices of the HDR engine 340 discussed herein is not intended to be exhaustive. In other embodiments, the HDR engine 340 may include fewer or more components, modules, and / or devices. As discussed throughout, the HDR engine 340 may be implemented and / or perform combinations thereof. Figure 5 , 6 Methods 500, 600, 700, and 800 discuss at least a portion of the processes, actions, and / or operations. Therefore, in various embodiments, one or more of the logic devices 320 implement and / or perform at least a portion of methods 500, 600, 700, and 800.

[0115] Some computing devices in the HDRI system 300 may not include image sensors and / or cameras (e.g., server computing device 330). In such embodiments, an HDR image sensor included in any of the camera computing devices 302-308 is used to capture source image data. As described above, in at least one embodiment, the source image data is provided via network 332 to an HDR engine 340 implemented at and / or by the server computing device 330. That is, although in various embodiments the source HDR image data is captured by at least one of the camera devices 302-308, tone mapping, image signal processing, controlling the brightness of the image data, and / or otherwise modifying the properties of the image data are performed offline on the server computing device 330. Because the camera computing devices 302-308 may include one or more manned or unmanned vehicles (e.g., ground vehicle 304 and drone 306), the source image data is captured, for example, by cameras included or mounted on the vehicles. As described above, the vehicles may be autonomous or at least partially autonomous. Various embodiments implement or at least facilitate the implementation of various machine and / or computer vision features of autonomous vehicles, such as, but not limited to, ground vehicle 304 or drone 306. Embodiments can be deployed to enable machine and / or computer vision features of other applications to perform all or part of the operations described in this disclosure, such as, but not limited to, robotic applications and / or model training (e.g., neural networks). For example, target image data 360 can be used to train a neural network to perform object detection used in a robotic application.

[0116] like Figure 3 As shown, the HDR engine 340 includes two parallel pipelines for source image data, as indicated by the arrows. More specifically, the HDR engine 340 includes image data pipeline 362 and image data pipeline 364. In various embodiments, the two pipelines operate in parallel. The two pipelines schematically branch between the HDR image sensor 344 and the ROI locator 348. The two branching pipelines schematically converge at the tone mapping applicator 358.

[0117] In one embodiment, image data pipeline 362 is responsible for determining and / or generating tone mapping functions (e.g., global tone mapping (GTM) functions, local tone mapping functions, or other tone mapping functions). In various embodiments, image data pipeline 362 (via delay unit 350 or tone mapping generator 356) provides tone mapping functions to image data pipeline 364 via tone mapping applicator 358. In one embodiment, image data pipeline 364 is responsible for applying tone mapping functions to source image data (e.g., from HDR image data buffer 346) to generate target image data 360. As described above, one or more HDR image sensors 344 capture source image data and provide the source image data to image data pipelines 362 and 364. In various embodiments, image data pipelines 362 and 364 include a set of functions, the output of which is input to another function. Figure 3 In a non-limiting embodiment, as indicated by the pipeline flow arrows, source image data is provided to image data pipeline 362 via ROI locator 348, and source data is provided to image data pipeline 364 via HDR image data buffer 346. In other embodiments, image data pipeline 362 and image data pipeline 364 are executed serially (e.g., HDR image data buffer 346 provides data directly to ROI locator 348). Although pipelines are used for illustrative purposes, other image processing architectures are considered to be within the scope of this disclosure. For example, the output of functions (e.g., ROI locator 348, HDR image data buffer 346, tone map generator 356, etc.) can be provided to multiple functions that perform operations serially and / or in parallel. In one example, statistics module 352 provides data to control point selector 354 and tone map generator 356. In this example, tone mapping generator 356 can process all or part of the data in parallel with control point selector 354, and can process additional data (e.g., data from control point selector 354) serially (e.g., after control point selector 354 has generated output).

[0118] In embodiments involving the capture of multiple frames of source image data (e.g., HDR video embodiments), the tone mapping function is generated at least in part based on the first frame of the source image data and applied to the second (e.g., consecutive and / or discontinuous) frames of the source image data. That is, in such embodiments, the tone mapping function is generated at least in part based on the first frame of the source image data and is applicable and suitable for additional frames of the source image data because the HDR sensor exposure setting 342 is fixed. In these embodiments, there may be a one-frame lag between the source data for which the tone mapping function is generated and the source image data for which the tone mapping function is applied. For example, the frame of the source image data used to generate the tone mapping function may be a frame preceding the frame of the source image data for which the tone mapping function is applied. In such embodiments, the delay unit 350 of the image data pipeline 362 buffers one (or more) frame-buffered tone mapping functions, and the tone mapping is applied to the next consecutive frame of the source image data when the tone mapping function is provided to the tone mapping applicator 358 of the image data pipeline 364. In other embodiments, the delay is greater than a single frame, and the delay unit 350 buffers tone mapping functions for multiple frames of source image data. In at least one embodiment, the same tone mapping function is applied to more than one frame of source image data. For example, the same tone mapping function is applied to five consecutive frames of source image data. In such an embodiment, image data pipeline 362 generates a tone mapping function for every five frames.

[0119] like Figure 3 As shown, the HDR engine 340 outputs target image data 360. As discussed throughout, in various embodiments, the target image data 360 encodes an image encoded from the source image data. However, the pixel values ​​of the target image data 360 are not the pixel values ​​of the source image data captured by the HDR image sensor 344, but are defined by applying a tone mapping function (determined by the image data pipeline 362) to the source image data (via the image data pipeline 364). That is, the pixel values ​​of the target image data 360 may represent a tone-mapped version of the pixel values ​​of the source image data. In some embodiments, the output target image data 360 may be HDR, standard dynamic range (SDR) image data, or low dynamic range (LDR) image data. In some embodiments, at least a portion of the operation of the image data pipeline 362 is performed by a first logic device (e.g., a general-purpose processor 322), and at least a portion of the operation of the image data pipeline 364 is performed by a second logic device (e.g., an ISP 324). In at least one embodiment, one or more pipelines within the ISP 324 are employed by the image data pipeline 364 of the HDR engine 340.

[0120] like Figure 3As shown, at least a portion of the source image data can be provided and / or received by the image data pipeline 364 via the HDR image data buffer 346. The HDR image data buffer 346, for example, buffers or at least temporarily stores the source image data. As discussed in more detail below, according to at least one embodiment, the image data pipeline 362 generates a tone mapping function and provides the tone mapping function to the image data pipeline 364. More specifically, as... Figure 3 As shown, the delay unit buffers the tone mapping function for at least one frame and then provides the tone mapping function to the tone mapping applicator 358 of the image data pipeline 364. In various embodiments, the tone mapping applicator 358 obtains source image data from the HDR image data buffer 346 and applies the tone mapping function to the source image data to generate target image data 360.

[0121] As described above, the source image data received by tone mapping applicator 358 can be the next frame of the source image data compared to the frame in the source image data used to generate the tone mapping function. In embodiments excluding the delay unit 350, the source image data is provided directly from tone mapping generator 356 to tone mapping applicator 358. In such embodiments, the tone mapping function is applied to the same frame of source image data used to generate the tone mapping function.

[0122] In embodiments including ROI locator 348, source image data is provided to and / or received by image data pipeline 362 via ROI locator 348. Since ROI locator 348 is not included, but statistics module 352 is included, source image data is provided to image data pipeline 362 via statistics module 352. Due to the absence of ROI locator 348 and statistics module 352, source image data is provided to image data pipeline 362 via control point selector 354. It should be noted that while this may include ROI locator 348 and / or statistics module 352, their operability may be optional. For example, a user may choose to enable the operability of one or both of ROI locator 348 and / or statistics module 352 via one or more software switches and / or flags. Similarly, a user may choose to disable the operability of one or both of ROI locator 348 and / or statistics module 352 via one or more software switches and / or flags.

[0123] Therefore, including and / or enabling the operability of ROI locator 348, ROI locator 348 determines ROIs within the source image data. For example, one or more methods related to computer vision and / or image processing (e.g., the ROI may be the output of a neural network trained to recognize ROIs) determine the region of interest (e.g., a region of an image, including the subject and / or focus of the image) within the image encoded by the source image data. For example, an ROI is a region within an image that contains more contrast, detail, and / or more varied pixel values ​​than other regions. For various reasons, an ROI is a region in an image whose pixel values ​​have a maximized, or at least increased, dynamic range compared to other regions in the image.

[0124] In various summaries, a Region of Interest (ROI) is a region of an image that includes or corresponds to the subject or focal point of the image. In some way, the ROI locator 348 includes a filter or mask that blocks pixels outside the identified ROI. Therefore, as image data travels along the image data pipeline 362, the image data in this way includes only the pixel values ​​corresponding to the ROI. In one example, the determination of control points and the generation of tone mapping functions, as well as other operations of the image data pipeline 362 (e.g., the determination of statistical measures and / or the determination of control point elevation), are based at least in part on portions of the source image data corresponding to the ROIs in the source image, rather than the entire source image data encoding the source image.

[0125] In embodiments that include and / or enable the statistics module 352, the statistics module 352 determines and / or generates multiple statistical measures based at least in part on pixel values ​​of the source image data (or pixel values ​​corresponding to a portion of the source image data encoding the ROI of the source image). The multiple statistical measures include, for example, statistical measures based at least in part on the pixel values ​​of the source image data. In one embodiment, the statistical measures include one or more parameters characterizing a continuous or discrete statistical distribution and / or a histogram constructed from the source image data. For example, such parameters include the mean, median, and / or standard deviation of one or more statistical distributions derived from the pixel values ​​of the source image data.

[0126] In various embodiments, source image data, a portion of the source image data corresponding to the ROI, and / or one or more statistical measures are provided to the control point selector 354. In one embodiment, the control point selector 354 is responsible for determining a plurality of tone control points based at least in part on the source image data, the portion of the source image data corresponding to the ROI, and / or one or more statistical measures. More specifically, according to at least one embodiment, at least a portion of the tone control points are determined based at least in part on pixel values ​​of the source image data, statistical measures determined and / or derived from the pixel values, or a combination thereof. In one embodiment, the control point selector 354 employs a general-purpose processor 322 to determine the plurality of tone control points.

[0127] In various embodiments, the plurality of control points includes one or more of low-tone points, mid-tone points, and high-tone points. In one embodiment, the plurality of control points includes glare suppression points. In some embodiments, the plurality of tone control points includes additional tone control points. For example, tone control points may include 2D points and / or 2D vectors comprising two scalar values ​​(e.g., x-component and y-component), although other dimensions may be added. Thus, in such an example, tone control points may be represented by vector notation (TC_x, TC_y), where TC_x and TC_y are scalar values. In various embodiments, the abscissa scalar value (e.g., x-component and / or x-value) of the tone control point is indicated as TC_x. According to at least one embodiment, the ordinate scalar value (e.g., y-component and / or y-value) of the tone control point is indicated as TC_y. For example, the 2D space in which the control points are embedded is spanned by an orthogonal basis, including an abscissa basis vector (e.g., x-axis) corresponding to the pixel values ​​of the source image data and a ordinate basis vector (e.g., y-axis) corresponding to the pixel values ​​of the target image data.

[0128] In various embodiments, low-tone, mid-tone, and high-tone control points indicate specific mappings from pixel values ​​in source image data to pixel values ​​in target image data. For example, a low-tone point indicates the lowest pixel value (e.g., the pixel value corresponding to the darkest or blackest pixel) of the source image data to be tone-mapped to the target image data. Similarly, in one example, a high-tone point represents the highest pixel value (e.g., the pixel value corresponding to the brightest or whitest pixel) of the source image data to be tone-mapped to the target image data. In one embodiment, the low-tone point is referred to as the black point (BP), and the high-tone point is referred to as the white point (WP). Furthermore, in another example, a mid-tone point represents the pixel value of the source image data to be tone-mapped to the middle pixel value of the target image data. In various embodiments, the determination of the mid-tone point controls the overall mid-tone brightness (or hue) of the target image encoded by the tone-mapped target image data 360, while the low-tone point controls the hue of the blackest (or darkest) pixel in the target image data, and the high-tone point controls the hue of the whitest (or brightest) pixel in the target image data 360.

[0129] refer to Figure 4 , Figure 4 The diagram illustrates low-tone, mid-tone, high-tone, and glare suppression control points embedded in a 4D space spanned by a first basis vector in a first dimension corresponding to pixel values ​​of the source image data (e.g., the x-axis) and a second basis vector in a second dimension corresponding to pixel values ​​of the target image data (e.g., the y-axis). Figure 4 In a non-limiting embodiment, the pixel values ​​of the source image data and the target image data have been normalized to have the range [0, 1]. However, in other embodiments, the pixel values ​​may be normalized to other ranges, or may not need to be normalized. For example, the raw pixel values ​​of the captured image data are used as the source image data. In other embodiments, the raw pixel values ​​are provided in conjunction with the above... Figure 3 The image data pipeline 364 of the HDR engine 340 described above is normalized and / or preprocessed beforehand.

[0130] Figure 4 In the chromatic arithmetic, low-tone points are represented as: LT = (B_s, B_t), mid-tone points as: MT = (M_s, M_t), and high-tone points as: HT = (W_s, W_t), where the x and y components are non-negative scalar values. More specifically, in Figure 4 In a non-limiting embodiment, LT = (B_s, 0) and HT = (W_s, 1), where 0.0 < B_s < W_s < 1.0. In other examples, B_t need not be equal to 0.0 and W_t need not be equal to 1. Figure 4Another control point, the glare suppression point, is shown, denoted as: FS = (F_s, F_t), where F_t is set to 0.0. The glare suppression point will be discussed further below.

[0131] In one embodiment, with respect to midtone points, pixel tones in the source image data whose pixel values ​​are equal to M_s are mapped to M_t values ​​in the target image data via a tone mapping function. According to an embodiment, the determination and / or selection of M_t controls the midtone brightness of the target image. Thus, for example, the determination of M_t is based at least in part on the midtone pixel values ​​of the pixel values ​​in the target image data. In some embodiments, M_t = 0.5. In other embodiments, M_t includes other values. In some examples, the user selects or sets the value of M_t. In a further example, M_s is determined by a linearly weighted average of the pixel values ​​in the source image data. In another example, M_s is determined by a logarithmic average (e.g., a logarithmic mean) of the pixel values ​​in the source image data. In such examples, the logarithmic mean can be performed with one or more bases (e.g., a logarithmic base of 10). In other embodiments, the logarithmic function used to convert the source image data to logarithmic values ​​includes a natural logarithm function. In one embodiment, the logarithmic mean of the pixel values ​​can then be raised to a power (via the corresponding base) to determine M_s. For example, the pixel values ​​of the source image data for logarithmic transformation are determined at least in part based on the pixel values ​​of the source image data. In one embodiment, the average value of the logarithmically transformed image data is determined by a linear weighted sum of the logarithmically transformed image data values. In one example, M_s is determined at least in part based on the power of the average value of the logarithmically transformed image data.

[0132] In some embodiments, a portion of the source image data is used to determine M_s. For example, pixels of the source image data having the highest and lowest values ​​can be rejected and / or filtered from the analysis. That is, for example, a high-tone threshold (or filter value) can be used to reject high-tone pixels from the determination of M_s. Similarly, a low-tone threshold (or filter or filter value) can be used to reject low-tone pixels from the determination of M_s. In various embodiments, M_s is determined at least in part based on a linear or logarithmic average of the pixel values ​​passed through the low-tone and high-tone filters (e.g., pixel values ​​for which no threshold is set from the analysis). In one example, the threshold for the filter is a relative threshold (e.g., a percentage) or an absolute value. In some embodiments, it is at least in part based on... Figure 3 The statistical measures generated by the statistical module 352 are used to determine M_s and / or M_t. In some embodiments, the various methods discussed above for determining M_s and / or M_t can be combined with statistical measures to determine M_s and / or M_t. In at least one embodiment, at least in part, is based on... Figure 1The digital exposure and calibration data 110 are used to determine M_s and / or M_t. For example, the prediction model for M_s and / or M_t is generated at least in part based on the analysis of historical, training and / or learning data generated by aggregating statistical measures from at least a large amount of source image data and / or target image data.

[0133] In various embodiments, regarding low-tone points, pixel tones in the source image data having pixel values ​​equal to (or less than) B_s can be mapped to B_t values ​​in the target image data. That is, according to at least one embodiment, pixel values ​​in the source image data less than B_s are cropped and set to pixel values ​​with B_s. For example, the determination and / or selection of B_t controls the low-tone brightness of the target image. Thus, in one embodiment, the determination of B_t is based at least in part on the minimum pixel value of the target image data. In some embodiments, B_t = 0. In other embodiments, B_t includes positive values ​​less than M_t. In some examples, the user selects or otherwise sets the value of B_t. In one example, positive black pixel values ​​may be caused by glare or other errors (e.g., sensor black level subtraction error) in the image sensor capturing the pixel's source image data. Therefore, because the source image data having pixel values ​​less than B_s is cropped and set to B_s, in such examples, the selection of B_s controls glare suppression. Therefore, B_s can be referred to as the glare suppression threshold.

[0134] In the example, B_s is determined at least in part based on the pixels of the source image data having the lowest pixel value. For example, a low-tonal subset of the pixel values ​​of the source image data is determined at least in part based on a low-tonal point threshold. In various embodiments, pixel values ​​included in the low-tonal subset are less than or equal to the low-tonal point threshold. Furthermore, in such embodiments, pixel values ​​excluded from the low-tonal subset are greater than the low-tonal point threshold. For example, the low-tonal point threshold may be an absolute threshold or a relative threshold. In various embodiments, the value of B_s is determined at least in part based on the pixel values ​​included in the low-tonal subset of pixel values. For example, B_s is set as a weighted average (possibly including an average) of the pixel values ​​in the low-tonal subset. In another embodiment, B_s is set as a percentage of the pixel values ​​in the low-tonal subset. In some embodiments, at least in part based on... Figure 3The statistical measures generated by the statistical module 352 are used to determine B_s and / or B_t. Any of the various methods described above for determining B_s and / or B_t can be combined with statistical measures to determine B_s and / or B_t. In at least one embodiment, B_s and / or B_t are determined at least in part based on the exposure settings of the HDR image sensor 344. In one embodiment, the prediction model for B_s and / or B_t is generated at least in part based on the analysis of training and / or learning data generated by aggregating statistical measures from a large amount of source image data and / or target image data.

[0135] In various embodiments, regarding hue points, pixels in the source image data having a pixel value equal to (or greater than) W_s are hue-mapped to a W_t value in the target image data. That is, for example, pixel values ​​in the source image data greater than W_s are cropped and set to have a value of W_s. Therefore, because the source image data with pixel values ​​greater than W_s is cropped and set to W_s, according to at least one embodiment, the selection of W_s controls highlight suppression (e.g., pixels with large pixel values). Therefore, W_s can be referred to as a highlight suppression threshold. For example, the determination and / or selection of W_t controls the high-hue brightness of the target image. Therefore, in various embodiments, the determination of W_t is at least partially based on the maximum pixel value of the target image data. In some embodiments, W_t = 1. In other embodiments, W_t includes positive values ​​less than 1 but greater than M_t. In some examples, the user selects or otherwise sets the value of W_t. In other examples, W_s is determined at least partially based on the pixel with the highest pixel value in the source image data. For example, a hue subset of pixel values ​​in the source image data can be determined at least in part based on a hue point threshold. In various embodiments, pixel values ​​included in the high hue subset are greater than or equal to a high hue point threshold. In such embodiments, pixel values ​​excluded from the high hue subset are less than the high hue point threshold.

[0136] For example, the high-tone threshold can be an absolute threshold or a relative threshold. In various embodiments, the value of W_s is determined at least in part based on pixel values ​​included in the high-tone subset of pixel values. For example, W_s is set as a weighted average of the pixel values ​​in the high-tone subset. As another example, W_s is set as a percentage of the pixel values ​​in the high-tone subset. In some embodiments, W_s and / or W_t can be at least in part based on the high-tone values... Figure 3The statistical measures generated by the statistical module 352 are used to determine W_s and / or W_t. Any of the various methods discussed above for determining W_s and / or W_t can be combined with statistical measures to determine W_s and / or W_t. In at least one embodiment, W_s and / or W_t are determined at least in part based on the HDR sensor exposure settings 342. In one embodiment, the prediction model for W_s and / or W_t is determined at least in part based on the analysis of training and / or learning data generated by aggregating statistical measures from a large amount of source image data and / or target image data.

[0137] Figure 4 A glare suppression point is also shown: FS = (F_s, 0). In various embodiments, F_s indicates the maximum glare removal threshold. In some embodiments, F_s is user-specified and / or selected. In other embodiments, F_s is determined dynamically, at least in part, based on statistical measures of the source image data. In at least one embodiment, F_s is determined at least in part based on a percentage of M_s and / or a percentage of the lowest pixel value of the source image data.

[0138] return Figure 3 In various embodiments, the control point selector 354 determines one or more additional tone control points. For example, the additional tone control points are determined based at least in part on multiple statistical measures. In various embodiments, the tone map generator 356 is responsible for determining a tone mapping function based at least in part on multiple control points. For example, the tone map generator 356 utilizes an HDR image sensor 344 to determine the tone mapping function. For example, to determine the tone mapping function, the tone map generator 356 generates and / or determines a gain line. In one embodiment, the generation of the gain line is based at least in part on a portion of multiple tone control points. For example, the gain value is determined as the slope, derivative, and / or rate of change of the gain line. In some embodiments, the gain line is determined as a unique line that includes or passes through at least two control points. Figure 4 In the example shown, the gain line is a line that includes the midtone point and the glare suppression point. In one embodiment, the gain value is equal to the slope of the gain line.

[0139] In various embodiments, tone mapping generator 356 determines a tone mapping function based at least in part on a gain value and at least a portion of a plurality of tone control points. For example, the tone mapping function maps pixel values ​​of source image data to pixel values ​​of target image data. Thus, the tone mapping function can be a scalar function of a single scalar variable (e.g., pixel values), where the value of the function is the pixel value of the target image data, corresponding to the pixel value of the source image data, which is the parameter (or independent variable) of the function. In one example, the tone mapping is a non-linear mapping. In some embodiments, tone mapping generator 356 performs a fitting of the tone mapping function to one or more tone control points. In one example, the tone mapping function is limited to including or approximately including one or more tone control points. In at least one embodiment, the tone mapping function is limited to including low-tone points, mid-tone points, and / or high-tone points. In some embodiments, the tone mapping function is constrained by a gain value. According to at least one embodiment, the derivative or instantaneous rate of change of the tone mapping function (evaluated at one or more tone control points) is constrained at least in part based on the gain value. For example, the fitting of the tone mapping function is constrained so that the derivative or instantaneous rate of change of the tangent at the mid-tone control point is at least approximately equal to the gain value.

[0140] Turning Figure 5 , Figure 5 Non-limiting examples of tone mapping function graphs according to various embodiments are shown. In various embodiments, Figure 5 The tone mapping function is constrained such that its graph includes low-tone points, mid-tone points, and high-tone points. In such an embodiment, the tone mapping function is further constrained such that the derivative or instantaneous rate of change of the tangent at the mid-tone control point equals the gain value. Although not in Figure 5 As shown, but it should be noted that, according to at least one embodiment, the tone mapping function can be further constrained at least in part based on additional tone control points. Figure 5 It also displays the corresponding low-tone point, mid-tone point, high-tone point, and gain line.

[0141] In various embodiments, to determine the tone mapping function, one or more parametric functions are fitted, wherein the fit is constrained by at least a portion of a plurality of tone control points. For example, the parametric functions include one or more polynomials of at least degree. In some embodiments, the fit of the tone mapping function is constrained such that the tone mapping function includes and / or intersects with at least low-tone points, mid-tone points, and high-tone points. In further embodiments, the fit of the tone mapping function is constrained such that the tone mapping function includes and / or intersects with additional tone control points. In some embodiments, the fit of the tone mapping function is constrained such that the derivative and / or instantaneous rate of change of the tone mapping function evaluated at the x-component of the mid-tone point equals the gain value.

[0142] In at least one example, various spline methods are employed to fit and / or generate the tone mapping function. In various embodiments, generating the tone mapping function includes generating and / or constructing a nonlinear curve. For example, the nonlinear curve is a Global Tone Curve (GTC). In one embodiment, the curve comprises multiple linear or curve segments (e.g., multiple splines). In other embodiments, the curve comprises a Bézier curve, such as a quadratic or cubic Bézier curve. For example, the curve can be constructed using second-, third-, or higher-order parametric equations. In various embodiments, various spline methods are employed to generate the curve. Furthermore, in such embodiments, the connections between splines or line segments are configured to ensure that the derivative of the tone mapping function is continuous.

[0143] In various embodiments, a tone mapping applicator receives source image data and a tone mapping function. In such embodiments, a tone mapping application applies the tone mapping function to the source image data to generate target image data. That is, for example, the tone mapping applicator transforms the source image data (e.g., the source image data frame used to generate the tone mapping function and / or one or more subsequent frames of the source image data) to generate the target image data. In various embodiments, the tone mapping applicator utilizes an ISP to apply the tone mapping function to the source image data. In some embodiments, a pipeline of the ISP is used to apply the tone mapping function to the source image data. As described above, the tone mapping function can provide a non-linear mapping from pixel values ​​in the source image data to pixel values ​​in the target image data. In some embodiments, the mapping is a one-to-one mapping. In other embodiments, the tone mapping is not a one-to-one mapping. For example, in embodiments where the x-component of a low hue point is greater than 0.0 and / or the x-component of a high hue point is less than 1, the source image data is cropped by the corresponding x-component.

[0144] In some embodiments, the tone mapping applicator converts tone-mapped target image data into SDR or LDR target image data. In such embodiments, a gamma compression function is applied to the tone-mapped target image data to generate color-compressed target image data. According to at least one embodiment, the SDR or LDR target image data may be output by the HDR engine based at least in part on the color-compressed target image data.

[0145] Now for reference Figure 6-9The framework of methods 600, 700, 800, and 900 described in this disclosure includes computational processes that can be performed using any combination of hardware, firmware, and / or software. For example, various functions can be performed by a processor executing instructions stored in memory. The method can also be embodied as computer-usable instructions stored on a computer storage medium. These methods can be provided by standalone applications, services, or managed services (standalone or in combination with another managed service) or plug-ins to another product, to name a few. Furthermore, by way of example, methods 600, 700, 800, and 900 are about combining... Figure 2 The methods described herein are based on offline signal processing systems. However, these methods may be additionally or alternatively performed by any system or any combination of systems, including but not limited to those described herein. Furthermore, the blocks of methods 600, 700, 800, and 900 may be performed in various sequences, including serial and / or parallel, and one or more blocks may be omitted.

[0146] Figure 6 This is a flowchart illustrating a method 600 for performing offline signal processing according to some embodiments of the present disclosure. At block B602, method 600 includes capturing source image data using a fixed exposure calibration. In various embodiments, the source image data is captured during data collection. For example, a camera device integrated and / or mounted on a vehicle captures source image data (e.g., HDR images and / or video). In one embodiment, the source image data is captured and stored until image signal processing is performed. In other embodiments, the source image data is processed simultaneously or nearly simultaneously with the capture.

[0147] In box B604, the system performing method 600 performs image signal processing using source image data. In various embodiments, image signal processing includes the above-described... Figure 2 The offline image signal processing 240 described and / or combined with the above Figure 3 The HDR engine 340 described herein includes one or more components. For example, image signal processing determines and applies a tone mapping function to the source image data to generate the target image data as described above.

[0148] In block B606, the system performing method 600 obtains target image data. In one example, the system performing method 600 obtains the target image data from an ISP. In another example, the system performing method 600 obtains the target image data from a server computer system (e.g., implementing an ISP) via a network. In block B610, the system performing method 600 determines whether the target image data is optimal. In various embodiments, the target image data is optimal if it is suitable for a particular application. In one example, the target image data is optimal if the brightness of the image included in the target image data is within a range that allows the image to have sufficient detail (e.g., not too dark to cause loss of detail or too bright to cause the image to fade). In another example, the target image data can be considered optimal if it can be used to train a model. In various embodiments, this determination is made by a user. For example, the user examines the target image data and indicates whether the target image data is optimal. In other embodiments, a model (e.g., a neural network) is trained to determine whether the target image data is optimal.

[0149] If the target image data is not optimal, the system executing method 600 continues to block B608. In block B608, the system executing method 600 modifies the image signal processing. In various embodiments, the modification to the image signal processing includes improvements and repairs 266 and / or tuning changes 264, as described above. Figure 2 As described. In one example, modifications to image signal processing include modifications to one or more control points of the tone mapping function. In other examples, modifications to image signal processing include the addition and / or removal of image processing algorithms. In various embodiments, the tone mapping function applied to source image data to generate target image data is modified, added to, or removed to produce improved results (e.g., optimal target image data).

[0150] However, if the target image data is optimal, the system executing method 600 proceeds to box B612. In box B612, the system executing method 600 trains the neural network based at least in part on the target image data. For example, the target image data can be used to train an object detection model or in combination with... Figure 13A and 13D Other models described. In one embodiment, a neural network is trained to determine features and / or aspects of target image data. In box B614, the system performing method 600 obtains results from the neural network. For example, the system performing method 600 performs one or more tests on the neural network before deploying it. In another example, the trained neural network is deployed and the results include information indicating the performance of the trained neural network.

[0151] In box B616, the system executing method 600 determines whether the result is optimal. For example, the system executing method 600 determines whether the trained neural network performs the task as expected. In another example, the system executing method 600 determines the success rate of the trained neural network (e.g., how successfully the neural network classifies objects of a particular category). In various embodiments, the user determines whether the result of the trained neural network is optimal. In still other embodiments, the determination is made at least in part based on a set of rules and / or heuristics. For example, if the success rate of the trained neural network reaches or exceeds a threshold, the result is optimal.

[0152] If the result is not optimal, the system executing method 600 returns to block B608. As described above, in block B608, one or more modifications are made to the image signal processing, and the source data is reprocessed in block B604. In various embodiments, the modifications are determined by the user. In other embodiments, the modifications are determined by a model (e.g., a neural network) or otherwise determined without user input (e.g., rules, heuristics, etc.). If the result is optimal, the system executing method 600 continues to block B618. In block B618, the system executing method 600 performs inference using a neural network. In various embodiments, the neural network is deployed to perform the task. For example, the neural network is deployed in a vehicle, such as in conjunction with... Figures 13A-13D As stated above.

[0153] Figure 7 This is a flowchart illustrating a method 700 for tone mapping high dynamic range image data according to some embodiments of the present disclosure. Method 700 begins at block B702, where the source image data is generated by one or more image sensors (e.g., ...). Figure 1 The HDR image sensor 144 captures the data. In one example, the source image data is HDR image data. In one embodiment, the source image data includes a first frame of the source image data (e.g., a frame of video). In at least some embodiments (e.g., video embodiments), one or more additional and / or consecutive frames of source image data (e.g., second consecutive frames of source image data) are captured after the first frame of the source image data. For example, the source image data encodes a source image depicting a scene. If additional frames of the source image data are captured, these additional frames encode one or more additional source images in this example. Therefore, capturing source image data in box B702 may include capturing one or more frames of the source image data. For example, during the data collection described above.

[0154] In various embodiments, the source image data is mounted on a manned or unmanned ground or aircraft (e.g., [missing information]). Figure 1The image is captured by at least one image sensor (e.g., a camera device) on vehicle 104 and / or drone 106. As described above, the vehicle can be a manually operated vehicle, an autonomous vehicle, a partially autonomous vehicle, and / or a remotely controlled vehicle. In at least some embodiments, the vehicle is controlled at least partially based on target image data generated at box B714 (e.g., target image data used to train one or more models to perform one or more operations corresponding to the vehicle's perception, planning, or control). However, the image sensor described herein can be part of any suitable device, such as a handheld or fixed camera, dashboard camera, security camera, mobile device, or other device that includes one or more image sensors. In at least one embodiment, the image sensor is included in one or more robots.

[0155] In box B702, in various embodiments, source image data is received and / or provided to an offline signal processing system, for example, but not limited to, […]. Figure 2 Offline signal processing 240. In at least one embodiment, source image data may be provided to and / or provided to and / or received by at least one of the following: HDR image data buffer, ROI locator, statistics module 252, control point selector and / or image processing 258 of offline signal processing 240.

[0156] In option B704, apply a Region of Interest (ROI) filter to the received source image data. For example, Figure 3 The ROI locator 348 determines the ROI of the source image data. In one embodiment, the ROI locator 348 applies filters and / or masks to the source image data pixels corresponding to the ROI of the source image, such that the filtered source image data includes only the image data corresponding to the determined ROI of the source image. Note that box B704 is optional and does not need to filter and / or analyze the source image data at least in part based on the ROI.

[0157] In option B706, generate and / or determine one or more statistical measures from the filtered (or unfiltered) source image data. For example, Figure 3 The statistics module 352 determines and / or generates multiple statistical measures based at least in part on the pixel values ​​of the source image data (or the pixel values ​​of a portion of the source image data corresponding to the ROI of the encoded source image).

[0158] In box B708, multiple tone control points are determined for the source image data. For example, the control point selector 354 of the HDR engine 340 determines and / or selects low-tone points, mid-tone points, and / or high-tone points based at least partially on the source image data. In embodiments where the source image data is filtered at least partially based on the ROI, tone control points are determined at least partially based on the portion of the source image data corresponding to the ROI of the source image. In embodiments where multiple statistical measures are determined in box B706, at least a portion of the tone control points are determined based at least partially on a portion of the statistical measures. In at least some embodiments, additional control points are determined in box B708. For example, at least one glare suppression control point is additionally determined in box B708. At least in combination Figure 8 Method 800 discusses various embodiments for determining multiple control points. Combined with... Figure 4 Further embodiments for determining the low-tone point, mid-tone point, high-tone point, and glare suppression point are discussed.

[0159] In box B710, the tone mapping function is determined at least in part based on tone control points. For example, Figure 3 The tone mapping generator 356 determines and / or generates a tone mapping function based at least in part on tone control points. Therefore, the tone mapping function may be based at least in part on source image data corresponding to the ROI of the source image and / or multiple statistical measures of the source image data.

[0160] At least combine Figure 4 , 5 Section 8 discusses various embodiments for determining the tone mapping function. In one embodiment, the gain line is determined at least in part based on at least a mid-tone point and a glare suppression point. In one example, the gain value is determined at least in part based on the gain line. More specifically, in one embodiment, the gain value is at least approximately equal to the slope of the gain line, which is a line that includes the mid-tone point and the glare suppression point. In various embodiments, the tone mapping function is based at least on the low-tone point, the mid-tone point, the high-tone point, and the gain value. For example, the tone mapping function is a fitted function constrained to include and / or pass through each of the low-tone point, the mid-tone point, and the high-tone point.

[0161] In at least one embodiment, the fitting of the tone mapping function is constrained such that the derivative and / or instantaneous rate of change of the tone mapping function, when evaluated at the mid-tone point, are at least approximately equal to the gain value. In at least one embodiment, a first logic device (e.g., Figure 3 A general-purpose processor 322) determines the tone mapping function. In at least one embodiment, the logic device for determining and / or generating the tone mapping function is a general-purpose processor of a computer system, separate from the camera device that captures the source image data.

[0162] As described throughout, a tone mapping function provides a mapping from pixel values ​​in source image data to pixel values ​​in target image data. Therefore, in one embodiment, the tone mapping function is a scalar function that depends on a single scalar variable (e.g., the scalar value of a single pixel in the source image data). For example, the scalar value of the function evaluated at the scalar pixel value in the source image data is the tone-mapped scalar value of the corresponding pixel in the target image data. As described throughout, the mapping can be a one-to-one non-linear mapping. Because the tone mapping function may be constrained to include low-tone points, it can map pixels in the source image with scalar values ​​of the x-component at low-tone points to scalar values ​​of the y-component at low-tone points.

[0163] In some embodiments, any pixel in the source image data having an x-component value less than the low hue point is cropped, such that the value of the cropped pixel is set to the x-component of the low hue point. In at least one embodiment, pixels in the source image data having an x-component value less than the glare suppression point are cropped, such that the value of the cropped pixel is set to the x-component of the glare suppression point. Because the tone mapping function is constrained to include a mid-hue point in various embodiments, the tone mapping function can map pixels of the source image with scalar values ​​of the x-component of the mid-hue point to scalar values ​​of the y-component of the mid-hue point. Similarly, because the tone mapping function is constrained to include a high hue point in other embodiments, the tone mapping function maps pixels of the source image with scalar values ​​of the x-component of the high hue point to scalar values ​​of the y-component of the high hue point. In some embodiments, any pixel in the source image data having an x-component value greater than the hue point is cropped, thereby setting the value of the cropped pixel to the x-component of the hue point. A non-limiting embodiment of the non-linear tone mapping function is... Figure 5 As shown in the image.

[0164] In optional box B712, a frame delay is used. For example, Figure 3 The delay unit 350 buffers the tone mapping function, while the HDR image sensor 144 captures one or more additional frames of source image data (e.g., subsequent and / or consecutive second frames of source image data). In one example, the frame delay of box B712 includes buffering the first frame of image data (for generating the tone mapping in box B710) while capturing the second frame of image data, or at least until the second frame of image data is provided for offline image signal processing.

[0165] In block B714, target image data is generated at least in part based on source image data and a tone mapping function. For example, tone mapping applicator 358 applies a tone mapping function to the source image data. In various embodiments, the target image data encodes a target image, wherein the pixel values ​​of the target image data are defined by a tone mapping function applied to the source image data. For example, applying a tone mapping function to the source image data includes applying the tone mapping function to the pixel values ​​of the source image data. In one embodiment, applying a tone mapping function to the source image data includes transforming and / or mapping the source image data to the target image data through a non-linear and one-to-one mapping and / or correspondence between the source image data and the target image data provided by the tone mapping function. In embodiments including frame delay, the tone mapping function is applied to a source image data frame (e.g., a second frame of source image data) that follows and / or succeeds a source image data frame used to generate the tone mapping function (e.g., a first frame of source image data).

[0166] In some embodiments, generating target image data includes generating standard dynamic range (SDR) or low dynamic range (LDR) target image data. For example, the SDR or LDR target image data is at least partially based on a tone mapping function and / or pixel values ​​of the tone-mapped target image data. In one embodiment, a gamma compression function is applied to the tone-mapped target image data to generate color-compressed target image data. In such embodiments, the SDR or LDR target image data is generated at least partially based on the color-compressed target image data.

[0167] Figure 8 This is a flowchart illustrating a method 800 for generating low dynamic range image data from high dynamic range image data according to some embodiments of the present disclosure. Blocks B802-B810 of method 800 include selecting and / or determining a plurality of tone control points. As described throughout, this can be achieved through... Figure 3 The control point selector 354 is used to select and / or define multiple tone control points. Combined with... Figure 8 Method 800, at least block B808, discusses various embodiments for determining multiple control points. In various embodiments, the determination of multiple control tone points is based at least in part on pixel values ​​of source image data, pixel values ​​of portions of source image data corresponding to ROIs in the source image, and / or at least in part on multiple statistical measures of pixel values ​​of source image data. Also, as described throughout, in various examples, the multiple tone control points include at least low tone points, mid tone points, and / or high tone points. In some embodiments, the multiple tone control points further include glare suppression points. Such tone control points at least... Figure 4-5 As shown in the diagram. It should also be noted that portions of method 800 can be derived from a first logic device (e.g., Figure 3The general-purpose processor 322) executes the method, and other parts of the method 800 can be executed by a second logic device (e.g., Figure 3 The image signal processor (ISP) 324) executes the signal.

[0168] In some embodiments, prior to the initialization of method 800, the pixel values ​​of the source image data are normalized such that the normalized pixel values ​​of the source image data range from [0,1]. Method 800 begins at block B802, wherein a midtone point is determined at least in part based on the source image data. In some embodiments, to determine the x-component of the midtone point, the source image data is filtered through a high-tone filter and a low-tone filter to generate filtered source image data. The high-tone filter removes portions of the source image data containing pixel values ​​greater than a high-tone threshold. The low-tone filter removes portions of the source image data containing pixel values ​​less than a low-tone threshold. In one embodiment, the x-component of the midtone point is determined by averaging the pixel values ​​of the remaining portion of the source image data after applying the high-tone and low-tone filters. In other embodiments, the high-tone and low-tone filters are not applied to the source image data.

[0169] In some embodiments, averaging pixel values ​​includes logarithmic averaging of the pixel values. In such embodiments, logarithmically transformed image data pixel values ​​are generated by applying a logarithmic function to filtered or unfiltered source image data. In one embodiment, the base of the logarithmic function is selected based at least in part on the source image data. In one embodiment, the base of the logarithmic function is ten. In other embodiments, the logarithmic function is the natural logarithm. In various embodiments, an average value of the logarithmically transformed pixel values ​​is determined. In one example, the average value of the logarithmically transformed pixel values ​​is raised to the power of the corresponding base of the logarithmic function. In various embodiments, the x-component of the midtone point is set to the power of the average value of the logarithmically transformed pixel values ​​of the source image data. Furthermore, in some embodiments, the y-component of the midtone point is set to a specified midtone value of the target image data.

[0170] In box B804, the hue point is determined at least in part based on the source image data. In one non-limiting embodiment, a subset of pixel values ​​from the source image data is determined and / or generated, including pixel values ​​in the subset that are less than the values ​​of pixels excluded from the subset. That is, the source image data can be filtered by a low-hue filter such that the only remaining pixel values ​​after filtering are those pixel values ​​less than a low-hue threshold. In one non-limiting embodiment, the x-component of the low-hue point is determined at least in part based on a subset of pixel values. For example, the x-component of the low-hue point is determined by averaging the pixel values ​​that survive the low-hue filtering process. In one non-limiting embodiment, the y-component of the low-hue point is determined and / or selected as the minimum pixel value of the target image data. In at least one embodiment, the y-component of the low-hue point is set to 0.0. For example, the low-hue point may be a black dot.

[0171] In block B806, the hue point is determined at least in part based on the source image data. In one non-limiting embodiment, a subset of pixel values ​​of the source image data is determined and / or generated, including pixel values ​​in the subset that are greater than the values ​​of pixels excluded from the subset. That is, the source image data can be filtered by a high-hue filter such that the only pixel value remaining after filtering is a pixel with a value greater than a high-hue threshold. In one embodiment, the x-component of the high-hue point is determined at least in part based on a subset of pixel values. For example, the pixel values ​​after the high-hue filtering process are averaged to determine the x-component of the high-hue point. In one embodiment, the y-component of the high-hue point is determined and / or selected as the maximum pixel value of the target image data. In at least one embodiment, the y-component of the low-hue point is set to 1.0. For example, the high hue can be a white point. In one embodiment, by setting the y-component of the low-hue point to 0.0 and setting the y-component of the high-hue point to a value, the target image data is normalized to the range [0,1].

[0172] In box B808, a glare suppression point is determined. In one embodiment, the x-component of the glare suppression point is set to the value of the maximum glare to be suppressed in the tone. In some embodiments, the x-component of the glare suppression point is user-selected. In other embodiments, the x-component is dynamically determined at least in part based on pixel values ​​of the source image and / or multiple statistical measures of the determined source image data. For example, the x-component of the glare suppression point is set at least in part based on a percentage of mid-tone pixel values ​​or the value of low-tone thresholded pixel values. In various embodiments, the x-component of the glare suppression point is selected to be greater than the x-component of the low-tone point but less than the x-component of the mid-tone point. In various non-limiting embodiments, the y-component of the glare suppression point is set to 0.0. In other embodiments, the y-component of the glare suppression point is set or selected to be greater than 0.0 but less than the y-component of the mid-tone point.

[0173] In optional box B810, one or more additional control points are determined at least partially based on the source image data. In box B812, in one example, the source data is preprocessed at least partially based on the control points. For example, pixels in the source image data whose pixel values ​​are less than the x-component of the low-tone point are cropped such that the pixel values ​​of these pixels are set to the scalar value of the x-component of the low-tone point. In at least one embodiment, pixels in the source image data whose pixel values ​​are less than the x-component of the glare suppression point are cropped such that the pixel values ​​of these pixels are set to the scalar value of the x-component of the glare suppression point. Furthermore, in various embodiments, each pixel in the source image data whose pixel value is greater than the x-component of the high-tone point is cropped such that the pixel values ​​of these pixels are set to the scalar value of the x-component of the high-tone point.

[0174] In box B814, the gain value is determined at least in part based on the midtone point and the glare suppression point. For example, a gain line is constructed using the midtone point and the glare suppression point. In one embodiment, the gain value is set as the slope of the gain value line. In various embodiments, the slope is positive. Figure 4 An example of a gain curve and its corresponding slope is shown.

[0175] In block B816, the tone mapping function is determined at least in part based on the low-tone point, mid-tone point, and high-tone point. In some embodiments, the determination of the tone mapping function is further based at least in part on gain values. In yet another embodiment, the determination of the tone mapping function is further based at least in part on one or more additional tone control points determined in block B810. In various embodiments, the following may be employed: Figure 3 The tone mapping generator 356 determines the tone mapping function. More specifically, the tone mapping generator 356 can employ... Figure 3 The general-purpose processor 322 is used to generate tone mapping functions.

[0176] In various embodiments, to determine the tone mapping function, one or more parametric functions are fitted, wherein the fit is constrained by at least a portion of various tone control points. For example, the parametric functions include one or more polynomials, which can indeed be of any degree. In some embodiments, the fit of the tone mapping function is constrained such that the tone mapping function includes and / or intersects with low-tone points, mid-tone points, and high-tone points. In further embodiments, the fit of the tone mapping function is constrained such that the tone mapping function includes and / or intersects with additional tone control points. In some embodiments, the fit of the tone mapping function is constrained such that the derivative and / or instantaneous rate of change of the tone mapping function evaluated at the x-component of the mid-tone point equals the gain value. Figure 5 An example of a tone mapping function is shown.

[0177] In various embodiments, spline methods are employed to fit and / or generate tone mapping functions. According to at least one embodiment, generating the tone mapping function includes generating and / or constructing a nonlinear curve. In various embodiments, the nonlinear curve is a global tone curve (GTC). For example, the curve comprises multiple linear or curved segments (e.g., multiple splines). The curve may be a Bézier curve, such as a quadratic or cubic Bézier curve. In yet another example, the curve is constructed using second-, third-, or higher-order parametric equations.

[0178] In box B818, a tone mapping function is applied to generate the target image data. In various embodiments, Figure 3 The tone mapping applicator 358 is used to convert source image data into target image data through a tone mapping function. In various embodiments, the tone mapping applicator 358 enables... Figure 3 The ISP 324 applies a nonlinear transformation to the source image data. In at least one embodiment, the pipeline of the ISP 324 is used to apply the transformation and generate the target image data.

[0179] Boxes B820 and B822 are optional boxes for generating SDR target image data or LDR image data from tone-mapped target image data. In box B820, a gamma compression function is applied to the tone-mapped image data to generate color-compressed image data. In box B822, SDR or LDR target image data is generated at least in part based on the color-compressed source image data.

[0180] Figure 9 This is a flowchart illustrating a method 900 for distributing tone mapping according to some embodiments of the present disclosure. In block B902, a first logic device determines a tone mapping function. In block B902, the first logic device includes... Figure 3 Any logic device 320, such as, but not limited to, a general-purpose processor 322, an image signal processor (ISP) 324, an ASIC 326, and / or an FPGA 328. In some embodiments, the first logic device for determining the tone mapping function is the general-purpose processor 322. In at least one embodiment, a graphics processing unit (GPU) is used to determine the tone mapping function.

[0181] In block B904, a second logic device is used to apply a tone mapping function to the source image data and generate target image source data. In block B904, the second logic device includes any logic device 320, such as, but not limited to, a general-purpose processor 322, an ISP 324, an ASIC 326, and / or an FPGA 328. In some embodiments, the second logic device for applying the tone mapping function is an ISP 324. The pipeline of the ISP 324 applies the tone mapping function and converts the source image data into target image data. In at least one embodiment, a GPU is used to determine the tone mapping function.

[0182] Reasoning and training logic

[0183] Figure 10A Inference and / or training logic 1015 for performing inference and / or training operations associated with one or more embodiments is shown. The following is in conjunction with... Figure 10A and / or Figure 10B Provide details about reasoning and / or training logic 1015.

[0184] In at least one embodiment, the inference and / or training logic 1015 may include, but is not limited to, code and / or data storage 1001 for storing forward and / or output weights and / or input / output data, and / or other parameters for configuring neurons or layers of a neural network trained for and / or used for inference in one or more embodiments. In at least one embodiment, the training logic 1015 may include or be coupled to code and / or data storage 1001 for storing graph code or other software to control timing and / or sequence, wherein weight and / or other parameter information is loaded to configure logic, including integer and / or floating-point units (collectively, arithmetic logic units (ALUs)). In at least one embodiment, code (such as graph code) loads weight or other parameter information into the processor ALU based on the architecture of the neural network to which the code corresponds. In at least one embodiment, the code and / or data storage 1001 stores weight parameters and / or input / output data of each layer of a neural network trained or used in one or more embodiments during forward propagation of input / output data and / or weight parameters during training and / or inference using one or more embodiments. In at least one embodiment, any portion of the code and / or data storage 1001 may be included within other on-chip or off-chip data storage, including the processor's L1, L2, or L3 cache or system memory.

[0185] In at least one embodiment, any portion of the code and / or data storage 1001 may be internal or external to one or more processors or other hardware logic devices or circuits. In at least one embodiment, the code and / or data storage 1001 may be a cache memory, dynamic random-addressable memory (“DRAM”), static random-addressable memory (“SRAM”), non-volatile memory (e.g., flash memory), or other storage. In at least one embodiment, the choice of whether the code and / or data storage 1001 is internal or external to the processor, for example, or composed of DRAM, SRAM, flash memory, or some other storage type, may depend on the available on-chip or off-chip storage space, the latency requirements of the training and / or inference functions being performed, the batch size of the data used in the inference and / or training of the neural network, or some combination of these factors.

[0186] In at least one embodiment, the inference and / or training logic 1015 may include, but is not limited to, code and / or data storage 1005 for storing backpropagation and / or output weights and / or input / output data neural networks corresponding to neurons or layers of a neural network trained and / or used for inference in one or more embodiments. In at least one embodiment, during training and / or inference using one or more embodiments, the code and / or data storage 1005 stores weight parameters and / or input / output data for each layer of a neural network trained or used in one or more embodiments during backpropagation of input / output data and / or weight parameters. In at least one embodiment, the training logic 1015 may include or be coupled to code and / or data storage 1005 for storing graph code or other software to control timing and / or sequence, wherein weight and / or other parameter information is loaded to configure logic including integer and / or floating-point units (collectively, arithmetic logic units (ALUs)).

[0187] In at least one embodiment, code (such as graph code) causes the architecture of the neural network corresponding to that code to load weights or other parameter information into the processor ALU. In at least one embodiment, any portion of the code and / or data storage 1005 may be included together with other on-chip or off-chip data storage, including the processor's L1, L2, or L3 cache or system memory. In at least one embodiment, any portion of the code and / or data storage 1005 may be internal or external to one or more processors or other hardware logic devices or circuits. In at least one embodiment, the code and / or data storage 1005 may be cache memory, DRAM, SRAM, non-volatile memory (e.g., flash memory), or other storage. In at least one embodiment, the choice between the code and / or data storage 1005 being internal or external to the processor, for example, whether it consists of DRAM, SRAM, flash memory, or some other type of storage, depends on whether the available storage is on-chip or off-chip, the latency requirements of the training and / or inference functions being performed, the data batch size used in the inference and / or training of the neural network, or some combination of these factors.

[0188] In at least one embodiment, code and / or data storage 1001 and code and / or data storage 1005 may be separate storage structures. In at least one embodiment, code and / or data storage 1001 and code and / or data storage 1005 may be the same storage structure. In at least one embodiment, code and / or data storage 1001 and code and / or data storage 1005 may be partially combined and partially separated. In at least one embodiment, any portion of code and / or data storage 1001 and code and / or data storage 1005 may be included with other on-chip or off-chip data storage, including the processor's L1, L2, or L3 cache or system memory.

[0189] In at least one embodiment, the inference and / or training logic 1015 may include, but is not limited to, one or more arithmetic logic units (“ALUs”) 1010 (including integer and / or floating-point units) for performing logical and / or mathematical operations at least in part based on or instructed by training and / or inference code (e.g., graph code), the results of which may produce activations (e.g., output values ​​from layers or neurons within a neural network) stored in activation storage 1020, which are functions of input / output and / or weight parameter data stored in code and / or data storage 1001 and / or code and / or data storage 1005. In at least one embodiment, activation is activated in response to execution instructions or other code, and linear algebraic and / or matrix-based mathematical generation performed by ALU 1010 is stored in activation storage 1020, wherein weight values ​​stored in code and / or data storage 1005 and / or code and / or data storage 1001 are used as operands with other values, such as bias values, gradient information, momentum values, or other parameters or hyperparameters, and any or all of these can be stored in code and / or data storage 1005 or code and / or data storage 1001 or other on-chip or off-chip storage.

[0190] In at least one embodiment, one or more processors or other hardware logic devices or circuits include one or more ALUs 1010, while in another embodiment, one or more ALUs 1010 may be located outside the processor or other hardware logic device or the circuitry using them (e.g., a coprocessor). In at least one embodiment, one or more ALUs 1010 may be included within an execution unit of a processor, or otherwise included in a group of ALUs accessible by the execution unit of the processor, which may be within the same processor or distributed among different processors of different types (e.g., a central processing unit, a graphics processing unit, a fixed-function unit, etc.). In at least one embodiment, code and / or data storage 1001, code and / or data storage 1005, and activation storage 1020 may share a processor or other hardware logic device or circuitry, while in another embodiment, they may be located in different processors or other hardware logic devices or circuitry, or in some combination of the same and different processors or other hardware logic devices or circuitry. In at least one embodiment, any portion of activation storage 1020 may be included together with other on-chip or off-chip data storage, including the processor's L1, L2, or L3 cache or system memory. Furthermore, inference and / or training code may be stored together with other code accessible to the processor or other hardware logic or circuitry, and may be retrieved and / or processed using the processor’s fetch, decode, schedule, execute, exit, and / or other logic circuitry.

[0191] In at least one embodiment, the active memory 1020 may be a cache memory, DRAM, SRAM, non-volatile memory (e.g., flash memory), or other memory. In at least one embodiment, the active memory 1020 may be wholly or partially located inside or outside one or more processors or other logic circuits. In at least one embodiment, the choice of whether the active memory 1020 is internal to or external to the processor may depend on the available on-chip or off-chip storage, the latency requirements for training and / or inference functions, the batch size of data used in inference and / or training the neural network, or some combination of these factors. For example, it may include DRAM, SRAM, flash memory, or other memory types.

[0192] In at least one embodiment, Figure 10A The inference and / or training logic 1015 shown can be used in conjunction with an application-specific integrated circuit (“ASIC”), such as those from Google. Processing unit, from Graphcore TM Inference processing units (IPUs) or from Intel Corp. (e.g., "Lake Crest") processor. In at least one embodiment, Figure 10A The inference and / or training logic 1015 shown can be used in conjunction with central processing unit (“CPU”) hardware, graphics processing unit (“GPU”) hardware or other hardware (such as field programmable gate array (“FPGA”)).

[0193] Figure 10B An inference and / or training logic 1015 according to at least one embodiment is illustrated. In at least one embodiment, the inference and / or training logic 1015 may include, but is not limited to, hardware logic, wherein computational resources are dedicated or otherwise uniquely used in conjunction with weight values ​​or other information corresponding to one or more layers of neurons within a neural network. In at least one embodiment, Figure 10B The inference and / or training logic 1015 shown can be used in conjunction with an application-specific integrated circuit (ASIC), such as those from Google. Processing unit, from Graphcore TM Inference processing units (IPUs) or from Intel Corp. (e.g., "Lake Crest") processor. In at least one embodiment, Figure 10BThe inference and / or training logic 1015 shown can be used in conjunction with central processing unit (CPU) hardware, graphics processing unit (GPU) hardware, or other hardware (e.g., field-programmable gate array (FPGA)). In at least one embodiment, the inference and / or training logic 1015 includes, but is not limited to, code and / or data storage 1001 and code and / or data storage 1005, which can be used to store code (e.g., graph code), weight values, and / or other information, including bias values, gradient information, momentum values, and / or other parameter or hyperparameter information. Figure 10B In at least one embodiment shown, each of code and / or data storage 1001 and code and / or data storage 1005 is associated with dedicated computing resources (e.g., computing hardware 1002 and computing hardware 1006), respectively. In at least one embodiment, each of computing hardware 1002 and computing hardware 1006 includes one or more ALUs that perform mathematical functions (e.g., linear algebraic functions) only on the information stored in code and / or data storage 1001 and code and / or data storage 1005, respectively, and the results of the function execution are stored in activation storage 1020.

[0194] In at least one embodiment, each of the code and / or data storage 1001 and 1005 and the corresponding computing hardware 1002 and 1006 corresponds to a different layer of the neural network, such that activations obtained from one “store / computation pair 1001 / 1002” of the code and / or data storage 1001 and computing hardware 1002 provide input as input to the next “store / computation pair 1005 / 1006” of the code and / or data storage 1005 and computing hardware 1006, in order to reflect the conceptual organization of the neural network. In at least one embodiment, each store / computation pair 1001 / 1002 and 1005 / 1006 may correspond to more than one neural network layer. In at least one embodiment, additional store / computation pairs (not shown) may be included in the inference and / or training logic 1015 following or paralleling the store / computation pairs 1001 / 1002 and 1005 / 1006.

[0195] Neural network training and deployment

[0196] Figure 11Training and deployment of a deep neural network according to at least one embodiment are illustrated. In at least one embodiment, an untrained neural network 1106 is trained using a training dataset 1102. In at least one embodiment, the training framework 1104 is the PyTorch framework, while in other embodiments, the training framework 1104 is TensorFlow, Boost, Caffe, Microsoft Cognitive Toolkit / CNTK, MXNet, Chainer, Keras, Deeplearning4j, or other training frameworks. In at least one embodiment, the training framework 1104 trains the untrained neural network 1106 and enables it to be trained using the processing resources described herein to generate a trained neural network 1108. In at least one embodiment, the weights may be randomly selected or pre-trained using a deep belief network. In at least one embodiment, training may be performed in a supervised, partially supervised, or unsupervised manner.

[0197] In at least one embodiment, supervised learning is used to train an untrained neural network 1106, wherein the training dataset 1102 includes inputs paired with desired outputs for input, or wherein the training dataset 1102 includes inputs with known outputs and the neural network 1106 is manually graded output. In at least one embodiment, the untrained neural network 1106 is trained in a supervised manner, and inputs from the training dataset 1102 are processed, and the resulting outputs are compared with a set of expected or desired outputs. In at least one embodiment, errors are then propagated back through the untrained neural network 1106. In at least one embodiment, a training framework 1104 adjusts the weights controlling the untrained neural network 1106. In at least one embodiment, the training framework 1104 includes tools for monitoring the degree to which the untrained neural network 1106 converges to a model (e.g., a trained neural network 1108) adapted to generate the correct answer (e.g., result 1114) based on input data (e.g., a new dataset 1112). In at least one embodiment, the training framework 1104 repeatedly trains the untrained neural network 1106 while adjusting the weights to improve the output of the untrained neural network 1106 using a loss function and tuning algorithm (e.g., stochastic gradient descent). In at least one embodiment, the training framework 1104 trains the untrained neural network 1106 until the untrained neural network 1106 reaches the desired accuracy. In at least one embodiment, the trained neural network 1108 can then be deployed to implement any number of machine learning operations.

[0198] In at least one embodiment, unsupervised learning is used to train an untrained neural network 1106, wherein the untrained neural network 1106 attempts to train itself using unlabeled data. In at least one embodiment, the unsupervised learning training dataset 1102 will include input data without any associated output data or "ground truth" data. In at least one embodiment, the untrained neural network 1106 can learn groupings within the training dataset 1102 and can determine how each input relates to the untrained dataset 1102. In at least one embodiment, unsupervised training can be used to generate a self-organizing graph in a trained neural network 1108, which is capable of performing operations useful for reducing the dimensionality of the new dataset 1112. In at least one embodiment, unsupervised training can also be used to perform anomaly detection, which allows the identification of data points in the new dataset 1112 that deviate from the normal patterns of the new dataset 1112.

[0199] In at least one embodiment, semi-supervised learning can be used, a technique in which a mixture of labeled and unlabeled data is included in the training dataset 1102. In at least one embodiment, the training framework 1104 can be used to perform incremental learning, for example, through transfer learning techniques. In at least one embodiment, incremental learning enables the trained neural network 1108 to adapt to the new dataset 1112 without forgetting the knowledge injected into the trained neural network 1108 during initial training.

[0200] Data Center

[0201] Figure 12 An example data center 1200 that can be used with at least one embodiment is shown. In at least one embodiment, the data center 1200 includes a data center infrastructure layer 1210, a framework layer 1220, a software layer 1230, and an application layer 1240.

[0202] In at least one embodiment, such as Figure 12As shown, the data center infrastructure layer 1210 may include a resource coordinator 1212, packet computing resources 1214, and node computing resources (“nodes CR”) 1216(1)-1216(N), where “N” represents a positive integer (which may be an integer “N” different from the integers used in other diagrams). In at least one embodiment, nodes CR 1216(1)-1216(N) may include, but are not limited to, any number of central processing units (“CPUs”) or other processors (including accelerators, field-programmable gate arrays (FPGAs), graphics processors, etc.), memory storage devices 1218(1)-1218(N) (e.g., dynamic read-only memory, solid-state drives, or disk drives), network input / output (“NW I / O”) devices, network switches, virtual machines (“VMs”), power modules, and cooling modules, etc. In at least one embodiment, one or more nodes CR 1216(1)-1216(N) may be servers having one or more of the aforementioned computing resources.

[0203] In at least one embodiment, the grouped computing resource 1214 may include individual groups (not shown) of node CRs housed within one or more racks, or a plurality of racks (also not shown) housed within data centers in various geographical locations. In at least one embodiment, the individual groups of node CRs within the grouped computing resource 1214 may include computing, networking, memory, or storage resources that can be configured or allocated to support groups of one or more workloads. In at least one embodiment, several node CRs, including CPUs or processors, may be grouped within one or more racks to provide computing resources to support one or more workloads. In at least one embodiment, the one or more racks may also include any number of power modules, cooling modules, and network switches, in any combination.

[0204] In at least one embodiment, resource coordinator 1212 may be configured or otherwise control one or more nodes CR1216(1)-1216(N) and / or grouped computing resources 1214. In at least one embodiment, resource coordinator 1212 may include a Software Design Infrastructure (“SDI”) management entity for data center 1200. In at least one embodiment, resource coordinator 1012 may include hardware, software, or some combination thereof.

[0205] In at least one embodiment, such as Figure 12As shown, framework layer 1220 includes a job scheduler 1222, a configuration manager 1224, a resource manager 1226, and a distributed file system 1228. In at least one embodiment, framework layer 1220 may include a framework of software 1232 supporting software layer 1230 and / or one or more applications 1242 supporting application layer 1240. In at least one embodiment, software 1232 or application 1242 may respectively include web-based service software or applications, such as services or applications provided by Amazon Web Services, Google Cloud, and Microsoft Azure. In at least one embodiment, framework layer 1220 may be, but is not limited to, a free and open-source software web application framework, such as Apache Spark, which can utilize distributed file system 1228 for large-scale data processing (e.g., "big data"). TM (Hereinafter referred to as "Spark"). In at least one embodiment, the job scheduler 1222 may include a Spark driver to facilitate the scheduling of workloads supported by various layers of data center 1200. In at least one embodiment, the configuration manager 1224 may be able to configure different layers, such as software layer 1230 and framework layer 1220 including Spark and a distributed file system 1228 for supporting large-scale data processing. In at least one embodiment, the resource manager 1226 is able to manage cluster or group computing resources mapped to or allocated to support distributed file system 1228 and job scheduler 1222. In at least one embodiment, cluster or group computing resources may include group computing resources 1214 on data center infrastructure layer 1210. In at least one embodiment, the resource manager 1226 may coordinate with resource coordinator 1212 to manage these mapped or allocated computing resources.

[0206] In at least one embodiment, the software 1232 included in the software layer 1230 may include software used by at least a portion of the nodes CR1216(1)-1216(N), the grouped computing resources 1214, and / or the distributed file system 1228 of the framework layer 1220. In at least one embodiment, one or more types of software may include, but are not limited to, Internet web page search software, email virus scanning software, database software, and streaming video content software.

[0207] In at least one embodiment, one or more applications 1242 included in application layer 1240 may include one or more types of applications used by at least a portion of nodes CR1216(1)-1216(N), grouped computing resources 1214, and / or the distributed file system 1228 of framework layer 1220. In at least one embodiment, one or more types of applications may include, but are not limited to, any number of genomics applications, cognitive computing, applications, and machine learning applications, including training or inference software, machine learning framework software (e.g., PyTorch, TensorFlow, Caffe, etc.), or other machine learning applications used in conjunction with one or more embodiments.

[0208] In at least one embodiment, any of the configuration manager 1224, resource manager 1226, and resource coordinator 1212 can perform any number and type of self-modification actions based on any amount and type of data acquired in any technically feasible manner. In at least one embodiment, self-modification actions can mitigate potentially poor configuration decisions by data center operators of data center 1200 and can prevent underutilization and / or poor performance of the data center.

[0209] In at least one embodiment, data center 1200 may include tools, services, software, or other resources to train one or more machine learning models or to use one or more machine learning models to predict or infer information according to one or more embodiments described herein. For example, in at least one embodiment, a machine learning model can be trained by calculating weight parameters based on a neural network architecture using the software and computing resources described above with respect to data center 1200. In at least one embodiment, information can be inferred or predicted using trained machine learning models corresponding to one or more neural networks using the resources described above with respect to data center 1200, by using weight parameters calculated through one or more training techniques described herein.

[0210] In at least one embodiment, the data center may use a CPU, application-specific integrated circuit (ASIC), GPU, FPGA, or other hardware to utilize the aforementioned resources to perform training and / or inference. Furthermore, one or more of the aforementioned software and / or hardware resources may be configured as a service to allow a user to train or perform information inference, such as image recognition, speech recognition, or other artificial intelligence services.

[0211] Inference and / or training logic 1015 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 10A and / or Figure 10BDetails regarding the inference and / or training logic 1015 are provided. In at least one embodiment, the inference and / or training logic 1015 can be implemented in the system. Figure 12 Used in this context for inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or the neural network use cases described herein. In various embodiments, the inference and / or training logic 1015 utilizes target image data generated by offline image signal processing 240, as described above in conjunction with... Figure 2 As stated above.

[0212] Autonomous vehicles

[0213] Figure 13A An example of an autonomous vehicle 1300 according to at least one embodiment is shown. In at least one embodiment, the autonomous vehicle 1300 (which may alternatively be referred to herein as "vehicle 1300") may be, but is not limited to, a passenger vehicle, such as a car, truck, bus, and / or another type of vehicle capable of accommodating one or more passengers. In at least one embodiment, vehicle 1300 may be a semi-tractor-trailer for hauling goods. In at least one embodiment, vehicle 1300 may be an aircraft, robotic vehicle, or other type of vehicle.

[0214] Autonomous vehicles can be described according to the levels of automation defined by the National Highway Traffic Safety Administration (“NHTSA”) and the Society of Automotive Engineers (“SAE”) of the U.S. Department of Transportation in their standard “Taxonomy and Definitions for Terms Related to Driving Automation Systems for On-Road Motor Vehicles” (e.g., standard number J3016-201806, published June 15, 2018; standard number J3016-201609, published September 30, 2016; and previous and future versions of this standard). In at least one embodiment, vehicle 1300 may be able to function according to one or more of the levels of autonomous driving from Level 1 to Level 5. For example, in at least one embodiment, vehicle 1300 may be able to perform conditional automation (Level 3), high automation (Level 4), and / or full automation (Level 5).

[0215] In at least one embodiment, vehicle 1300 may include, but is not limited to, components such as chassis, body, wheels (e.g., 2, 4, 6, 8, 18, etc.), tires, axles, and other vehicle components. In at least one embodiment, vehicle 1300 may include, but is not limited to, propulsion system 1350, such as an internal combustion engine, a hybrid powertrain, an all-electric motor, and / or another type of propulsion system. In at least one embodiment, propulsion system 1350 may be connected to the drivetrain of vehicle 1300, which may include, but is not limited to, a transmission, to enable propulsion of vehicle 1300. In at least one embodiment, propulsion system 1350 may be controlled in response to receiving a signal from throttle / accelerator 1352.

[0216] In at least one embodiment, when the propulsion system 1350 is operating (e.g., when the vehicle 1300 is traveling), the steering system 1354 (which may include, but is not limited to, a steering wheel) is used to steer the vehicle 1300 (e.g., along a desired path or route). In at least one embodiment, the steering system 1354 may receive signals from the steering actuator 1356. In at least one embodiment, the steering wheel may be optional for fully automated (Level 5) functionality. In at least one embodiment, the brake sensor system 1346 may be used to operate the vehicle brakes in response to signals received from the brake actuator 1348 and / or brake sensors.

[0217] In at least one embodiment, the controller 1336 may include, but is not limited to, one or more system-on-chips (“SoCs”). Figure 13AA controller 1336 (not shown) and / or a graphics processing unit (“GPU”) provides signals (e.g., representing commands) to one or more components and / or systems of vehicle 1300. For example, in at least one embodiment, controller 1336 may send signals to operate vehicle braking via brake actuator 1348, to operate steering system 1354 via one or more steering actuators 1356, and to operate propulsion system 1350 via one or more throttles / accelerators 1352. In at least one embodiment, one or more controllers 1336 may include one or more onboard (e.g., integrated) computing devices that process sensor signals and output operating commands (e.g., signals representing commands) to enable autonomous driving and / or assist a driver in driving vehicle 1300. In at least one embodiment, one or more controllers 1336 may include a first controller for autonomous driving functions, a second controller for functional safety functions, a third controller for artificial intelligence functions (e.g., computer vision), a fourth controller for infotainment functions, a fifth controller for redundancy in emergency situations, and / or other controllers. In at least one embodiment, a single controller may handle two or more of the functions described above, and two or more controllers may handle a single function and / or any combination thereof.

[0218] In at least one embodiment, one or more controllers 1336 provide signals for controlling one or more components and / or systems of vehicle 1300 in response to sensor data received from one or more sensors (e.g., sensor inputs). In at least one embodiment, sensor data can be received from sensors, including but not limited to one or more Global Navigation Satellite System (“GNSS”) sensors 1358 (e.g., one or more Global Positioning System sensors), one or more RADAR sensors 1360, one or more ultrasonic sensors 1362, one or more LIDAR sensors 1364, one or more inertial measurement unit (IMU) sensors 1366 (e.g., one or more accelerometers, one or more gyroscopes, one or more magnetic compasses, one or more magnetometers, etc.), one or more microphones 1396, one or more stereo cameras 1368, one or more wide-angle cameras 1370 (e.g., fisheye cameras), one or more infrared cameras 1372, one or more surround cameras 1374 (e.g., 360-degree cameras), and remote cameras (…). Figure 13A (not shown in the image), medium-range camera ( Figure 13A(Not shown in the image) One or more speed sensors 1344 (e.g., for measuring the speed of vehicle 1300), one or more vibration sensors 1342, one or more steering sensors 1340, one or more brake sensors (e.g., as part of brake sensor system 1346) and / or other sensor types are received.

[0219] In at least one embodiment, one or more controllers 1336 may receive input (e.g., represented by input data) from the dashboard 1332 of the vehicle 1300 and provide output (e.g., represented by output data, display data, etc.) via a human-machine interface (“HMI”) display 1334, a voice signaler, a speaker, and / or other components of the vehicle 1300. In at least one embodiment, the output may include information such as vehicle speed, velocity, time, map data (e.g., high-definition map). Figure 13A The HMI display 1334 may display information such as (not shown in the image), location data (e.g., the location of vehicle 1300, for example, on a map), direction, the location of other vehicles (e.g., occupancy raster), information about objects, and the state of objects sensed by one or more controllers 1336. For example, in at least one embodiment, the HMI display 1334 may display information about the presence of one or more objects (e.g., road signs, warning signs, traffic light changes, etc.) and / or information about driving operations that the vehicle has already made, is making, or will make (e.g., changing lanes now, exiting exit 34B within two miles, etc.).

[0220] In at least one embodiment, vehicle 1300 further includes a network interface 1324 that can communicate over one or more networks using one or more wireless antennas 1326 and / or one or more modems. For example, in at least one embodiment, network interface 1324 may be able to communicate over Long Term Evolution (“LTE”), Wideband Code Division Multiple Access (“WCDMA”), Universal Mobile Telecommunications System (“UMTS”), Global System for Mobile Communications (“GSM”), IMT-CDMA Multicarrier (“CDMA2000”) networks, etc. In at least one embodiment, one or more wireless antennas 1326 may also enable communication between objects in the environment (e.g., vehicles, mobile devices) using one or more local area networks (e.g., Bluetooth, Bluetooth Low Energy (LE), Z-Wave, ZigBee, etc.) and / or one or more low-power wide area networks (hereinafter “LPWAN”) (e.g., LoRaWAN, SigFox, etc. protocols).

[0221] Inference and / or training logic 1015 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 10Aand / or Figure 10B Details regarding the inference and / or training logic 1015 are provided. In at least one embodiment, the inference and / or training logic 1015 can be implemented in the system. Figure 13A The inference and / or training logic 1015 is used to infer or predict operations based at least in part on weight parameters calculated using neural network training operations, neural network functions and / or architecture, or neural network use cases described herein. In various embodiments, the inference and / or training logic 1015 utilizes target image data generated by offline image signal processing 240, as described above. Figure 2 As stated above. Furthermore, the above is combined with... Figure 2 The data collection 202 described is performed by vehicle 1300 in various embodiments.

[0222] Figure 13B The illustration shows an embodiment according to at least one of the embodiments. Figure 13A Examples of camera positions and fields of view for an autonomous vehicle 1300. In at least one embodiment, the camera and its respective field of view are an example embodiment and are not intended to be limiting. For example, in at least one embodiment, additional and / or alternative cameras may be included and / or the cameras may be located at different positions on the vehicle 1300.

[0223] In at least one embodiment, the camera type used for the camera may include, but is not limited to, a digital camera suitable for use with components and / or systems of vehicle 1300. In at least one embodiment, one or more cameras may operate at Automotive Safety Integrity Level (“ASIL”) B and / or other ASILs. In at least one embodiment, the camera type may have any image capture rate, such as 60 frames per second (fps), 1220 fps, 240 fps, etc. In at least one embodiment, the camera may be able to use a rolling shutter, a global shutter, another type of shutter, or a combination thereof. In at least one embodiment, the color filter array may include a red-to-clear (“RCCC”) color filter array, a red-to-clear-blue (“RCCB”) color filter array, a red-blue-green (“RBGC”) color filter array, a Foveon X3 color filter array, a Bayer sensor (“RGGB”) color filter array, a monochrome sensor color filter array, and / or other types of color filter arrays. In at least one embodiment, a transparent pixel camera, such as a camera with an array of RCCC, RCCB and / or RBGC color filters, may be used to improve photosensitivity.

[0224] In at least one embodiment, one or more cameras may be used to perform advanced driver assistance system (“ADAS”) functions (e.g., as part of a redundancy or fail-safe design). For example, in at least one embodiment, a multi-function mono camera may be installed to provide functions including lane departure warning, traffic sign assist, and intelligent headlight control. In at least one embodiment, one or more cameras (e.g., all cameras) may simultaneously record and provide image data (e.g., video).

[0225] In at least one embodiment, one or more cameras may be mounted in a mounting assembly, such as a custom-designed (3D-printed) assembly, to cut out stray light and reflections within the vehicle 1300 (e.g., reflections from the dashboard in the windshield mirror), which may interfere with the camera's image data capture capabilities. Regarding the rearview mirror mounting assembly, in at least one embodiment, the rearview mirror assembly may be 3D-printed custom-made such that the camera mounting plate matches the shape of the rearview mirror. In at least one embodiment, one or more cameras may be integrated into the rearview mirror. In at least one embodiment, for side-view cameras, one or more cameras may also be integrated within four pillars at each corner of the cabin.

[0226] In at least one embodiment, a camera (e.g., a forward-facing camera) having a field of view including a portion of the environment in front of the vehicle 1300 can be used for surround view and, with the assistance of one or more controllers 1336 and / or control SoCs, to help identify forward paths and obstacles, thereby providing information crucial for generating an occupancy grid and / or determining a preferred vehicle path. In at least one embodiment, the forward-facing camera can be used to perform many ADAS functions similar to LIDAR, including but not limited to emergency braking, pedestrian detection, and collision avoidance. In at least one embodiment, the forward-facing camera can also be used for ADAS functions and systems, including but not limited to lane departure warning (“LDW”), adaptive cruise control (“ACC”), and / or other functions (e.g., traffic sign recognition).

[0227] In at least one embodiment, various cameras can be used in a forward-facing configuration, including, for example, a monocular camera platform including a CMOS (“complementary metal-oxide-semiconductor”) color imager. In at least one embodiment, a wide-angle camera 1370 can be used to sense objects entering from the periphery (e.g., pedestrians, crosswalkers, or bicycles). Although in Figure 13BOnly one wide-angle camera 1370 is shown; however, in other embodiments, the vehicle 1300 may have any number (including zero) of wide-angle cameras. In at least one embodiment, any number of remote cameras 1398 (e.g., a pair of remote stereo cameras) can be used for depth-based object detection, especially for objects for which a neural network has not yet been trained. In at least one embodiment, the remote camera 1398 can also be used for object detection and classification, as well as basic object tracking.

[0228] In at least one embodiment, any number of stereo cameras 1368 may also be included in a forward configuration. In at least one embodiment, one or more stereo cameras 1368 may include an integrated control unit comprising a scalable processing unit that may provide programmable logic (“FPGA”) and a multi-core microprocessor with a controller area network (“CAN”) or Ethernet interface integrated on a single chip. In at least one embodiment, such a unit may be used to generate a 3D map of the environment of the vehicle 1300, including distance estimates for all points in the image. In at least one embodiment, one or more stereo cameras 1368 may include, but are not limited to, a compact stereo vision sensor, which may include, but is not limited to, two camera lenses (one on the left and one on the right) and an image processing chip that can measure the distance from the vehicle 1300 to a target object and use the generated information (e.g., metadata) to activate autonomous emergency braking and lane departure warning functions. In at least one embodiment, other types of stereo cameras 1368 may also be used in addition to those described herein.

[0229] In at least one embodiment, a camera (e.g., a side-view camera) having a field of view including a portion of the environment on the side of the vehicle 1300 can be used for surround viewing, thereby providing information for creating and updating the occupied grid, and generating a side collision warning. For example, in at least one embodiment, a surround camera 1374 (e.g., such as...) Figure 13B The four surround cameras shown can be positioned on vehicle 1300. In at least one embodiment, one or more surround cameras 1374 can include, but are not limited to, any number and combination of wide-angle cameras, one or more fisheye lenses, one or more 360-degree cameras, and / or similar cameras. For example, in at least one embodiment, four fisheye lens cameras can be located at the front, rear, and sides of vehicle 1300. In at least one embodiment, vehicle 1300 can use three surround cameras 1374 (e.g., left, right, and rear) and can utilize one or more other cameras (e.g., forward-facing cameras) as a fourth surround-view camera.

[0230] In at least one embodiment, a camera (e.g., a rear-view camera) having a field of view including a portion of the environment behind the vehicle 1300 can be used for parking assistance, surround view, rear collision warning, and creating and updating occupancy raster. In at least one embodiment, a wide variety of cameras can be used, including but not limited to cameras that are also suitable as one or more forward-facing cameras (e.g., long-range camera 1398 and / or one or more mid-range cameras 1376, one or more stereo cameras 1368, one or more infrared cameras 1372, etc.), as described herein.

[0231] The inference and / or training logic 1015 is used to perform inference and / or training operations associated with one or more embodiments. Figure 10A and / or Figure 10B This document provides details regarding inference and / or training logic 1015. In at least one embodiment, inference and / or training logic 1015 can... Figure 13B Used in systems for inferring or predicting operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein. In various embodiments, the inference and / or training logic 1015 utilizes target image data generated by offline image signal processing 240, as described above in conjunction with... Figure 2 As stated above. Furthermore, the above is combined with... Figure 2 The data collection 202 described is performed by vehicle 1300 in various embodiments.

[0232] Figure 13C The illustration shows an embodiment according to at least one of the embodiments. Figure 13A A block diagram of an example system architecture for an autonomous vehicle 1300. In at least one embodiment, Figure 13C Each of one or more components, one or more features, and one or more systems of vehicle 1300 is shown as connected via bus 1302. In at least one embodiment, bus 1302 may include, but is not limited to, a CAN data interface (which may alternatively be referred to herein as “CAN bus”). In at least one embodiment, CAN may be a network within vehicle 1300 used to help control various features and functions of vehicle 1300, such as brake actuation, acceleration, braking, steering, windshield wipers, etc. In one embodiment, bus 1302 may be configured to have dozens or even hundreds of nodes, each node having its own unique identifier (e.g., CAN ID). In at least one embodiment, bus 1302 can be read to find steering wheel angle, ground speed, engine rotation speed (“RPM”), button position, and / or other vehicle status indicators. In at least one embodiment, bus 1302 may be an ASIL B compliant CAN bus.

[0233] In at least one embodiment, FlexRay and / or Ethernet protocols may be used in addition to or from CAN. In at least one embodiment, there may be any number of molded buses 1302, which may include, but are not limited to, zero or more CAN buses, zero or more FlexRay buses, zero or more Ethernet buses, and / or zero or more other types of buses using other protocols. In at least one embodiment, two or more buses may be used to perform different functions and / or may be used for redundancy. For example, a first bus may be used for a collision avoidance function, and a second bus may be used for actuation control. In at least one embodiment, each of the buses 1302 may communicate with any component of the vehicle 1300, and two or more buses 1302 may communicate with corresponding components. In at least one embodiment, each of any number of System-on-Chip (“SoC”) 1304 (e.g., SoC 1304(A) and SoC 1304(B)), each of one or more controllers 1336, and / or each computer within the vehicle may access the same input data (e.g., input from sensors of the vehicle 1300) and may be connected to a common bus, such as a CAN bus.

[0234] In at least one embodiment, vehicle 1300 may include one or more controllers 1336, such as those described herein. Figure 13A As described above. In at least one embodiment, controller 1336 can be used for a variety of functions. In at least one embodiment, controller 1336 can be coupled to any of various other components and systems of vehicle 1300 and can be used to control vehicle 1300, artificial intelligence of vehicle 1300, infotainment and / or other functions of vehicle 1300.

[0235] In at least one embodiment, vehicle 1300 may include any number of SoCs 1304. In at least one embodiment, each of the SoCs 1304 may include, but is not limited to, a central processing unit (“one or more CPUs”) 1306, a graphics processing unit (“one or more GPUs”) 1308, one or more processors 1310, one or more caches 1312, one or more accelerators 1314, one or more data storage 1316, and / or other components and features not shown. In at least one embodiment, one or more SoCs 1304 may be used to control vehicle 1300 on various platforms and systems. For example, in at least one embodiment, one or more SoCs 1304 may be combined with a high-definition (“HD”) map 1322 in a system (e.g., the system of vehicle 1300), the high-definition map 1322 being accessible from one or more servers via a network interface 1324. Figure 13C (Not shown in the image) Get map refresh and / or update.

[0236] In at least one embodiment, one or more CPUs 1306 may include CPU clusters or CPU complexes (which may alternatively be referred to herein as “CCPLEX”). In at least one embodiment, one or more CPUs 1306 may include multiple cores and / or a secondary (“L2”) cache. For example, in at least one embodiment, one or more CPUs 1306 may include eight cores in an intercoupled multiprocessor configuration. In at least one embodiment, one or more CPUs 1306 may include four dual-core clusters, each cluster having a dedicated L2 cache (e.g., 2MB L2 cache). In at least one embodiment, one or more CPUs 1306 (e.g., CCPLEX) may be configured to support simultaneous cluster operation, such that any combination of clusters of one or more CPUs 1306 can be active at any given time.

[0237] In at least one embodiment, one or more CPUs 1306 may implement power management functions, including but not limited to one or more of the following features: automatic clock gating of individual hardware modules to conserve dynamic power when idle; clock gating of each core when the core is not actively executing instructions due to executing Wait for Interrupt (“WFI”) / Event Wait (“WFE”) instructions; independent power supply for each core; independent clock gating for each core cluster when all cores are clock-gated or power-gated; and / or independent power gating for each core cluster when all cores are power-gated. In at least one embodiment, one or more CPUs 1306 may further implement an enhanced algorithm for managing power states, wherein allowed power states and expected wake-up times are specified, and the hardware / microcode determines the optimal power state for cores, clusters, and CCPLEX inputs. In at least one embodiment, the processing core may support a simplified power state input sequence in software, wherein the work is offloaded to the microcode.

[0238] In at least one embodiment, one or more GPUs 1308 may include integrated GPUs (or "iGPUs" herein). In at least one embodiment, one or more GPUs 1308 may be programmable and efficient for parallel workloads. In at least one embodiment, one or more GPUs 1308 may use an enhanced tensor instruction set. In at least one embodiment, one or more GPUs 1308 may include one or more streaming microprocessors, wherein each streaming microprocessor may include a Level 1 ("L1") cache (e.g., an L1 cache with at least 96KB of storage capacity), and two or more streaming microprocessors may share an L2 cache (e.g., an L2 cache with 512KB of storage capacity). In at least one embodiment, one or more GPUs 1308 may include at least eight streaming microprocessors. In at least one embodiment, one or more GPUs 1308 may use a computation application programming interface (API). In at least one embodiment, one or more GPUs 1308 may use one or more parallel computing platforms and / or programming models (e.g., NVIDIA's CUDA model).

[0239] In at least one embodiment, one or more GPU 1308s may be power-optimized for optimal performance in automotive and embedded use cases. For example, in at least one embodiment, one or more GPU 1308s may be fabricated on FinFET (“FinFET”) circuitry. In at least one embodiment, each streaming microprocessor may include multiple mixed-precision processing cores divided into multiple blocks. For example, but not limited to, 64 PF32 cores and 32 PF64 cores may be divided into four processing blocks. In at least one embodiment, each processing block may be allocated 16 FP32 cores, 8 FP64 cores, 16 INT32 cores, two mixed-precision NVIDIA Tensor cores for deep learning matrix arithmetic, a level-zero (“L0”) instruction cache, a thread bundle scheduler, a dispatch unit, and / or a 64KB register file. In at least one embodiment, the streaming microprocessor may include independent parallel integer and floating-point data paths to provide efficient execution of workloads that mix computation and addressing operations. In at least one embodiment, the streaming microprocessor may include independent thread scheduling capabilities to enable finer-grained synchronization and collaboration between parallel threads. In at least one embodiment, the streaming microprocessor may include a combined L1 data cache and shared memory unit to improve performance while simplifying programming.

[0240] In at least one embodiment, one or more GPUs 1308 may include high-bandwidth memory (“HBM”) and / or a 16GB HBM2 memory subsystem to provide a peak storage bandwidth of approximately 900GB / s in some examples. In at least one embodiment, in addition to or instead of HBM memory, synchronous graphics random access memory (“SGRAM”) may be used, such as graphics double data rate type five synchronous random access memory (“GDDR5”).

[0241] In at least one embodiment, one or more GPUs 1308 may include unified memory technology. In at least one embodiment, address translation service (“ATS”) support may be used to allow one or more GPUs 1308 to directly access the page tables of one or more CPUs 1306. In at least one embodiment, when a memory management unit (“MMU”) of one or more GPUs 1308 experiences a miss, an address translation request may be sent to one or more CPUs 1306. In response, in at least one embodiment, two CPUs of one or more CPUs 1306 may look up the virtual-physical mapping of the address in their page tables and transfer the translation back to one or more GPUs 1308. In at least one embodiment, unified memory technology may allow a single unified virtual address space to be used for the memory of both one or more CPUs 1306 and one or more GPUs 1308, thereby simplifying the programming of one or more GPUs 1308 and the porting of applications to one or more GPUs 1308.

[0242] In at least one embodiment, one or more GPUs 1308 may include any number of access counters that can track the frequency with which one or more GPUs 1308 access the memory of other processors. In at least one embodiment, one or more access counters can help ensure that memory pages are moved to the physical memory of the processor that accesses the pages most frequently, thereby improving the efficiency of shared memory ranges between processors.

[0243] In at least one embodiment, one or more SoCs 1304 may include any number of caches 1312, including those described herein. For example, in at least one embodiment, one or more caches 1312 may include a Level 3 (“L3”) cache available for one or more CPUs 1306 and one or more GPUs 1308 (e.g., connected to CPUs 1306 and GPUs 1308). In at least one embodiment, one or more caches 1312 may include a write-back cache that can, for example, track the state of a line using a cache coherence protocol (e.g., MEI, MESI, MSI, etc.). In at least one embodiment, although a smaller cache size may be used, according to an embodiment, the L3 cache may include 4 MB of memory or more.

[0244] In at least one embodiment, one or more SoCs 1304 may include one or more accelerators 1314 (e.g., hardware accelerators, software accelerators, or combinations thereof). In at least one embodiment, one or more SoCs 1304 may include a hardware acceleration cluster, which may include optimized hardware accelerators and / or large on-chip memory. In at least one embodiment, large on-chip memory (e.g., 4MB of SRAM) enables the hardware acceleration cluster to accelerate neural networks and other computations. In at least one embodiment, the hardware acceleration cluster may be used to supplement one or more GPUs 1308 and offload some tasks from one or more GPUs 1308 (e.g., freeing up more cycles from one or more GPUs 1308 to perform other tasks). In at least one embodiment, one or more accelerators 1314 may be used for a target workload (e.g., perceptual, convolutional neural network (“CNN”), recurrent neural network (“RNN”), etc.) that is sufficiently stable to withstand acceleration testing. In at least one embodiment, the CNN may include region-based or region convolutional neural networks (“RCNN”) and fast RCNN (e.g., for object detection) or other types of CNNs.

[0245] In at least one embodiment, one or more accelerators 1314 (e.g., a hardware acceleration cluster) may include one or more deep learning accelerators (“DLAs”). In at least one embodiment, one or more DLAs may include, but are not limited to, one or more Tensor Processing Units (“TPUs”), which may be configured to provide an additional 10 trillion operations per second for deep learning applications and inference. In at least one embodiment, a TPU may be an accelerator configured and optimized for performing image processing functions (e.g., for CNNs, RCNNs, etc.). In at least one embodiment, one or more DLAs may be further optimized for specific sets of neural network types and floating-point operations and inference. In at least one embodiment, one or more DLAs are designed to provide higher performance per millimeter than typical general-purpose GPUs and typically significantly outperform CPUs. In at least one embodiment, one or more TPUs may perform several functions, including single-instance convolution functions supporting, for example, INT8, INT16, and FP16 data types for features and weights, as well as post-processor functions. In at least one embodiment, one or more DLAs can execute neural networks, particularly CNNs, quickly and efficiently on processed or unprocessed data for any of the various functions, including, but not limited to: CNNs for object recognition and detection using data from camera sensors; CNNs for distance estimation using data from camera sensors; CNNs for emergency vehicle detection, recognition, and identification using data from microphones; CNNs for face recognition and vehicle owner recognition using data from camera sensors; and / or CNNs for safety and / or safety-related events.

[0246] In at least one embodiment, the DLA can perform any function of one or more GPUs 1308, and by using inference accelerators, for example, the designer can target one or more DLAs or one or more GPUs 1308 for any function. For example, in at least one embodiment, the designer can concentrate the CNN processing and floating-point operations on one or more DLAs, leaving other functions to one or more GPUs 1308 and / or one or more accelerators 1314.

[0247] In at least one embodiment, one or more accelerators 1314 may include programmable vision accelerators (“PVAs”), which may alternatively be referred to herein as computer vision accelerators. In at least one embodiment, one or more PVAs may be designed and configured to accelerate computer vision algorithms for advanced driver assistance systems (“ADAS”) 1338, autonomous driving, augmented reality (“AR”) applications, and / or virtual reality (“VR”) applications. In at least one embodiment, one or more PVAs may strike a balance between performance and flexibility. For example, in at least one embodiment, each of one or more PVAs may include, for example, but not limited to, any number of reduced instruction set computer (“RISC”) cores, direct memory access (“DMA”), and / or any number of vector processors.

[0248] In at least one embodiment, the RISC core can interact with an image sensor (e.g., the image sensor of any camera described herein), an image signal processor, etc. In at least one embodiment, each RISC core may include any number of memories. In at least one embodiment, the RISC core may use any of a variety of protocols, depending on the embodiment. In at least one embodiment, the RISC core may execute a real-time operating system (“RTOS”). In at least one embodiment, the RISC core may be implemented using one or more integrated circuit devices, application-specific integrated circuits (“ASICs”), and / or storage devices. For example, in at least one embodiment, the RISC core may include an instruction cache and / or tightly coupled RAM.

[0249] In at least one embodiment, DMA enables components of the PVA to access system memory independently of one or more CPUs 1306. In at least one embodiment, DMA can support any number of features for providing optimization to the PVA, including but not limited to, support for multidimensional addressing and / or circular addressing. In at least one embodiment, DMA can support up to six or more addressing dimensions, which may include, but are not limited to, block width, block height, block depth, horizontal block step, vertical block step, and / or depth step.

[0250] In at least one embodiment, the vector processor may be a programmable processor designed to efficiently and flexibly execute programming for computer vision algorithms and provide signal processing capabilities. In at least one embodiment, the PVA may include a PVA core and two vector processing subsystem partitions. In at least one embodiment, the PVA core may include a processor subsystem, a DMA engine (e.g., two DMA engines), and / or other peripherals. In at least one embodiment, the vector processing subsystem may serve as the main processing engine of the PVA and may include a vector processing unit (“VPU”), an instruction cache, and / or a vector memory (e.g., “VMEM”). In at least one embodiment, the VPU core may include a digital signal processor, such as a Single Instruction Multiple Data (“SIMD”) or Very Long Instruction Word (“VLIW”) digital signal processor. In at least one embodiment, the combination of SIMD and VLIW can improve throughput and speed.

[0251] In at least one embodiment, each vector processor may include an instruction cache and may be coupled to dedicated memory. As a result, in at least one embodiment, each vector processor may be configured to execute independently of other vector processors. In at least one embodiment, the vector processors included in a particular PVA may be configured to employ data parallelism. For example, in at least one embodiment, multiple vector processors included in a single PVA may execute general-purpose computer vision algorithms, except on different regions of an image. In at least one embodiment, vector processors included in a particular PVA may execute different computer vision algorithms simultaneously on a single image, or even execute different algorithms on a sequence of images or portions of images. In at least one embodiment, among others, any number of PVAs may be included in the hardware-accelerated cluster, and any number of vector processors may be included in each PVA. In at least one embodiment, the PVA may include additional error-correcting code (“ECC”) memory to enhance overall system security.

[0252] In at least one embodiment, one or more accelerators 1314 may include an on-chip computer vision network and static random access memory (“SRAM”) for providing high-bandwidth, low-latency SRAM to one or more accelerators 1314. In at least one embodiment, the on-chip memory may include at least 4 MB of SRAM, comprising, for example, but not limited to, eight field-configurable memory blocks accessible to both the PVA and DLA. In at least one embodiment, each pair of memory blocks may include an advanced peripheral bus (“APB”) interface, configuration circuitry, a controller, and a multiplexer. In at least one embodiment, any type of memory may be used. In at least one embodiment, the PVA and DLA may access the memory via a backbone providing high-speed access to the memory for both the PVA and DLA. In at least one embodiment, the backbone may include an on-chip computer vision network that interconnects the PVA and DLA to the memory (e.g., using an APB).

[0253] In at least one embodiment, the on-chip computer vision network may include an interface that determines that both the PVA and DLA provide ready and valid signals before transmitting any control signals / addresses / data. In at least one embodiment, the interface may provide separate phases and separate channels for transmitting control signals / addresses / data, as well as bursty communication for continuous data transmission. In at least one embodiment, although other standards and protocols may be used, the interface may conform to the International Organization for Standardization (“ISO”) 26262 or the International Electrotechnical Commission (“IEC”) 61508 standard.

[0254] In at least one embodiment, one or more SoCs 1304 may include a real-time eye-tracking hardware accelerator. In at least one embodiment, the real-time eye-tracking hardware accelerator may be used to quickly and efficiently determine the location and extent of an object (e.g., within a world model) to generate real-time visualization simulations for RADAR signal interpretation, for sound propagation synthesis and / or analysis, for SONAR system simulation, for general wave propagation simulation, for comparison with LIDAR data for localization and / or other functions, and / or for other purposes.

[0255] In at least one embodiment, one or more accelerators 1314 have broad applications for autonomous driving. In at least one embodiment, PVA can be used in critical processing stages in ADAS and autonomous vehicles. In at least one embodiment, the capabilities of PVA with low power consumption and low latency are well-matched to algorithmic domains requiring predictable processing. In other words, PVA performs well in semi-intensive or intensive conventional computations, even on small datasets that may require predictable runtimes with low latency and low power consumption. In at least one embodiment, such as in vehicle 1300, PVA may be designed to run classical computer vision algorithms, as they are efficient in object detection and integer mathematical operations.

[0256] For example, according to at least one embodiment of the technology, PVA is used to perform computer stereo vision. In at least one embodiment, a semi-global matching-based algorithm may be used in some examples, although this is not intended to be limiting. In at least one embodiment, applications for Level 3-5 autonomous driving use dynamic estimation / stereo matching during operation (e.g., structure recovery from motion, pedestrian recognition, lane detection, etc.). In at least one embodiment, PVA can perform computer stereo vision functions on input from two monocular cameras.

[0257] In at least one embodiment, the PVA can be used to perform intensive optical flow. For example, in at least one embodiment, the PVA can process raw RADAR data (e.g., using 4D Fast Fourier Transform) to provide processed RADAR data. In at least one embodiment, the PVA is used for time-of-flight depth processing, for example, by processing raw time-of-flight data to provide processed time-of-flight data.

[0258] In at least one embodiment, the DLA can be used to run any type of network to enhance control and driving safety, including, but not limited to, neural networks whose output is used for a confidence score for each object detection. In at least one embodiment, the confidence score can be represented or interpreted as a probability, or as providing a relative “weight” for each detection relative to other detections. In at least one embodiment, the confidence score measurement enables the system to make further decisions about which detections should be considered true positives rather than false positives. In at least one embodiment, the system can set a threshold for the confidence score and only consider detections exceeding the threshold as true positives. In embodiments using an Automatic Emergency Braking (“AEB”) system, false positives would cause the vehicle to automatically perform emergency braking, which is obviously undesirable. In at least one embodiment, a highly confident detection can be considered a trigger for AEB. In at least one embodiment, the DLA can run a neural network for regressing the confidence score value. In at least one embodiment, the neural network may take at least a subset of parameters as its input, such as bounding box size, obtained ground plane estimate (e.g., from another subsystem), and outputs of one or more IMU sensors 1366 related to the vehicle 1300 orientation, distance, and 3D position estimate of the object obtained from the neural network and / or other sensors (e.g., one or more LiDAR sensors 1364 or one or more RADAR sensors 1360).

[0259] In at least one embodiment, one or more SoCs 1304 may include one or more data storage units 1316 (e.g., memory). In at least one embodiment, one or more data storage units 1316 may be on-chip memory of one or more SoCs 1304, which may store neural networks to be executed on one or more GPUs 1308 and / or DLAs. In at least one embodiment, one or more data storage units 1316 may have a sufficiently large capacity to store multiple instances of the neural network for redundancy and security. In at least one embodiment, one or more data storage units 1316 may include L2 or L3 caches.

[0260] In at least one embodiment, one or more SoCs 1304 may include any number of processors 1310 (e.g., embedded processors). In at least one embodiment, one or more processors 1310 may include a startup and power management processor, which may be a dedicated processor and subsystem for handling startup power and management functions, as well as associated security implementations. In at least one embodiment, the startup and power management processor may be part of a startup sequence of one or more SoCs 1304 and may provide runtime power management services. In at least one embodiment, the startup power and management processor may provide clock and voltage programming, assist system low-power state transitions, thermal and temperature sensor management of one or more SoCs 1304s, and / or power state management of one or more SoCs 1304s. In at least one embodiment, each temperature sensor may be implemented with its output frequency proportional to temperature, and one or more SoCs 1304s may use the ring oscillator to detect the temperature of one or more CPUs 1306s, one or more GPUs 1308s, and / or one or more accelerators 1314s. In at least one embodiment, if it is determined that the temperature exceeds a threshold, the startup and power management processor may enter a temperature fault routine and place one or more SoCs 1304s into a lower power state and / or place the vehicle 1300 into a driver's safe stopping pattern (e.g., bring the vehicle 1300 to a safe stop).

[0261] In at least one embodiment, one or more processors 1310 may further include a set of embedded processors that can serve as an audio processing engine. The audio processing engine may be an audio subsystem capable of providing full hardware support for multi-channel audio through multiple interfaces and a wide and flexible range of audio I / O interfaces. In at least one embodiment, the audio processing engine is a dedicated processor core with a digital signal processor having dedicated RAM.

[0262] In at least one embodiment, one or more processors 1310 may further include an always-on processor engine that can provide the necessary hardware features to support low-power sensor management and wake-up use cases. In at least one embodiment, the processor on the always-on processor engine may include, but is not limited to, a processor core, tightly coupled RAM, peripheral support devices (e.g., timers and interrupt controllers), various I / O controller peripherals, and routing logic.

[0263] In at least one embodiment, one or more processors 1310 may further include a secure clustering engine, which includes, but is not limited to, a dedicated processor subsystem for handling security management of automotive applications. In at least one embodiment, the secure clustering engine may include, but is not limited to, two or more processor cores, tightly coupled RAM, supporting peripherals (e.g., timers, interrupt controllers, etc.) and / or routing logic. In secure mode, in at least one embodiment, the two or more cores may operate in lockstep mode and may be used as a single core with comparison logic for detecting any differences between their operations. In at least one embodiment, one or more processors 1310 may further include a real-time camera engine, which may include, but is not limited to, a dedicated processor subsystem for handling real-time camera management. In at least one embodiment, one or more processors 1310 may further include a high dynamic range signal processor, which may include, but is not limited to, an image signal processor, which is a hardware engine as part of the camera processing pipeline.

[0264] In at least one embodiment, one or more processors 1310 may include a video image synthesizer, which may be a processing block (e.g., implemented on a microprocessor) that implements video post-processing functions required by the video playback application to produce the final video for the player window. In at least one embodiment, the video image synthesizer may perform lens distortion correction on one or more wide-angle cameras 1370, one or more surround cameras 1374, and / or one or more cabin monitoring camera sensors. In at least one embodiment, preferably, the cabin monitoring camera sensors are monitored by a neural network running on another instance of SoC 1304, the neural network being configured to recognize cabin events and respond accordingly. In at least one embodiment, the cabin system may perform, but is not limited to, lip reading to activate cellular service and make phone calls, instruct emails, change the vehicle's destination, activate or change the vehicle's infotainment system and settings, or provide voice-activated web browsing. In at least one embodiment, certain functions are available to the driver when the vehicle is operating in autonomous mode, and are otherwise disabled.

[0265] In at least one embodiment, the video image synthesizer may include enhanced temporal denoising for simultaneous spatial and temporal denoising. For example, in at least one embodiment, when motion occurs in the video, denoising appropriately weights spatial information, thereby reducing the weight of information provided by adjacent frames. In at least one embodiment, when the image or a portion of the image does not contain motion, temporal denoising performed by the video image synthesizer may use information from previous images to reduce noise in the current image.

[0266] In at least one embodiment, the video image compositor can also be configured to perform stereoscopic correction on the input stereo lens frames. In at least one embodiment, when using an operating system desktop, the video image compositor can also be used for user interface compositing and does not require one or more GPUs 1308 to continuously render new surfaces. In at least one embodiment, when one or more GPUs 1308 are powered and actively performing 3D rendering, the video image compositor can be used to offload one or more GPUs 1308 to improve performance and responsiveness.

[0267] In at least one embodiment, one or more SoCs of SoC 1304 may further include a Mobile Industrial Processor Interface (“MIPI”) camera serial interface, a high-speed interface, and / or a video input block that can be used for receiving video and input from a camera and associated pixel input functions. In at least one embodiment, one or more SoCs of SoC 1304 may further include an input / output controller that can be software controlled and can be used to receive I / O signals not assigned to a specific role.

[0268] In at least one embodiment, one or more SoCs of SoC 1304 may further include extensive peripheral interfaces to enable communication with peripheral devices, audio encoders / decoders (“codecs”), power management and / or other devices. In at least one embodiment, one or more SoCs of SoC 1304 may be used to process data from (e.g., connected via gigabit multimedia serial links and Ethernet channels) cameras, sensors (e.g., one or more LiDAR sensors 1364, one or more RADAR sensors 1360, etc., which may be connected via Ethernet channels), data from bus 1302 (e.g., vehicle 1300 speed, steering wheel position, etc.), data from one or more GNSS sensors 1358 (e.g., connected via Ethernet bus or CAN bus), etc. In at least one embodiment, one or more SoCs of SoC 1304 may further include a dedicated high-performance mass storage controller, which may include its own DMA engine and may be used to free one or more CPUs 1306 from routine data management tasks.

[0269] In at least one embodiment, one or more SoCs 1304 can be an end-to-end platform with a flexible architecture spanning automation levels 3-5, providing a comprehensive functional safety architecture that leverages and effectively utilizes computer vision and ADAS technologies to achieve diversity and redundancy. This provides a platform offering a flexible and reliable driving software stack as well as deep learning tools. In at least one embodiment, one or more SoCs 1304 can be faster, more reliable, and even more energy and space efficient than conventional systems. For example, in at least one embodiment, one or more accelerators 1314, when combined with one or more CPUs 1306, one or more GPUs 1308, and one or more data storage 1316, can provide a fast and efficient platform for Level 3-5 autonomous vehicles.

[0270] In at least one embodiment, the computer vision algorithm can be executed on a CPU, which can be configured using a high-level programming language (e.g., C) to execute multiple processing algorithms on a variety of visual data. However, in at least one embodiment, the CPU typically cannot meet the performance requirements of many computer vision applications, such as performance requirements related to execution time and power consumption. In at least one embodiment, many CPUs cannot execute complex object detection algorithms in real time, which are used in automotive ADAS applications and practical Level 3-5 autonomous vehicles.

[0271] The embodiments described herein allow multiple neural networks to be executed simultaneously and / or sequentially, and allow the results to be combined to achieve Level 3-5 autonomous driving capabilities. For example, in at least one embodiment, a CNN executed on a DLA or discrete GPU (e.g., one or more GPUs 1320) may include text and word recognition, thereby allowing a supercomputer to read and understand traffic signs, including signs for which the neural network has not yet been specifically trained. In at least one embodiment, the DLA may also include a neural network capable of recognizing, interpreting, and providing semantic understanding of symbols, and passing this semantic understanding to a path planning module running on a CPU Complex.

[0272] In at least one embodiment, for drives of levels 3, 4, or 5, multiple neural networks can run simultaneously. For example, in at least one embodiment, a warning sign consisting of a light bulb accompanied by the warning sign “Caution: flashing lights indicate icy conditions” can be interpreted independently or jointly by multiple neural networks. In at least one embodiment, the warning sign itself can be recognized as a traffic sign by a first deployed neural network (e.g., a trained neural network), and the text “flashing lights indicate icy conditions” can be interpreted by a second deployed neural network, which informs the vehicle’s path planning software (preferably executed on the CPU Complex) that icing conditions exist when flashing lights are detected. In at least one embodiment, flashing lights can be identified by operating a third deployed neural network across multiple frames, informing the vehicle’s path planning software of the presence (or absence) of flashing lights. In at least one embodiment, all three neural networks can run simultaneously, for example within the DLA and / or on one or more GPUs 1308.

[0273] In at least one embodiment, the CNN for facial recognition and vehicle owner identification can use data from camera sensors to identify the presence of an authorized driver and / or the owner of vehicle 1300. In at least one embodiment, a normally open sensor processor engine can be used to unlock the vehicle when the owner approaches the driver's door and turns on the lights, and, in security mode, can be used to disable the vehicle when the owner leaves it. In this way, one or more SoCs 1304 provide protection against theft and / or carjacking.

[0274] In at least one embodiment, the CNN for emergency vehicle detection and identification can use data from microphone 1396 to detect and identify emergency vehicle sirens. In at least one embodiment, one or more SoCs 1304 use the CNN to classify environmental and urban sounds, as well as visual data. In at least one embodiment, the CNN running on DLA is trained to identify the relative approach speed of emergency vehicles (e.g., by using the Doppler effect). In at least one embodiment, the CNN can also be trained to identify emergency vehicles in the area where the vehicle is operating, as identified by one or more GNSS sensors 1358. In at least one embodiment, when operating in Europe, the CNN will seek to detect European sirens, while in North America, the CNN will seek to identify only North American sirens. In at least one embodiment, once an emergency vehicle is detected, a control program can be used, with the assistance of one or more ultrasonic sensors 1362, to execute emergency vehicle safety routines, slow the vehicle, pull the vehicle to the side of the road, stop, and / or leave the vehicle idle until the emergency vehicle passes.

[0275] In at least one embodiment, vehicle 1300 may include one or more CPUs 1318 (e.g., one or more discrete CPUs or one or more dCPUs) that may be coupled to one or more SoCs 1304 via high-speed interconnects (e.g., PCIe). In at least one embodiment, one or more CPUs 1318 may include x86 processors. For example, one or more CPUs 1318 may be used to perform any of the various functions, such as arbitrating the results of potential inconsistencies between ADAS sensors and one or more SoCs 1304, and / or monitoring the status and health of one or more monitoring controllers 1336 and / or on-chip information systems (“information SoCs”) 1330.

[0276] In at least one embodiment, vehicle 1300 may include one or more GPUs 1320 (e.g., one or more discrete GPUs or one or more dGPUs) coupled to one or more SoCs 1304 via high-speed interconnects (e.g., NVIDIA's NVLINK channels). In at least one embodiment, one or more GPUs 1320 may provide additional artificial intelligence capabilities, such as by executing redundant and / or different neural networks, and may be used to train and / or update the neural networks based at least in part on inputs from sensors of vehicle 1300 (e.g., sensor data).

[0277] In at least one embodiment, vehicle 1300 may further include a network interface 1324, which may include, but is not limited to, one or more wireless antennas 1326 (e.g., one or more wireless antennas for different communication protocols, such as cellular antennas, Bluetooth antennas, etc.). In at least one embodiment, network interface 1324 may be used to enable wireless connectivity with other vehicles and / or computing devices (e.g., passenger client devices) via Internet cloud services (e.g., using servers and / or other network devices). In at least one embodiment, for communication with other vehicles, a direct link and / or an indirect link (e.g., via a network and the Internet) may be established between vehicle 130 and another vehicle. In at least one embodiment, a vehicle-to-vehicle communication link may be used to provide a direct link. In at least one embodiment, the vehicle-to-vehicle communication link may provide vehicle 1300 with information about vehicles near vehicle 1300 (e.g., vehicles in front, to the side, and / or behind vehicle 1300). In at least one embodiment, the foregoing functionality may be part of a cooperative adaptive cruise control function of vehicle 1300.

[0278] In at least one embodiment, network interface 1324 may include a System-on-Chip (SoC) that provides modulation and demodulation functions and enables one or more controllers 1336 to communicate over a wireless network. In at least one embodiment, network interface 1324 may include a radio frequency (RF) front-end for up-conversion from baseband to RF and down-conversion from RF to baseband. In at least one embodiment, frequency conversion may be performed in any technically feasible manner. For example, frequency conversion may be performed using known processes and / or using a superheterodyne process. In at least one embodiment, the RF front-end functionality may be provided by a separate chip. In at least one embodiment, the network interface may include wireless functions for communication via LTE, WCDMA, UMTS, GSM, CDMA2000, Bluetooth, Bluetooth LE, Wi-Fi, Z-Wave, ZigBee, LoRaWAN, and / or other wireless protocols.

[0279] In at least one embodiment, the vehicle 1300 may further include one or more data storage units 1328, which may include, but are not limited to, off-chip (e.g., one or more SoC 1304) storage. In at least one embodiment, the one or more data storage units 1328 may include, but are not limited to, one or more storage elements, including RAM, SRAM, dynamic random access memory (“DRAM”), video random access memory (“VRAM”), flash memory, hard disk and / or other components and / or devices capable of storing at least one bit of data.

[0280] In at least one embodiment, the vehicle 1300 may further include one or more GNSS sensors 1358 (e.g., GPS and / or auxiliary GPS sensors) to assist in map creation, perception, occupancy raster generation, and / or path planning functions. In at least one embodiment, any number of GNSS sensors 1358 may be used, including, for example, but not limited to, GPS sensors connected to a serial interface (e.g., RS-232) bridge using a USB connector with Ethernet.

[0281] In at least one embodiment, vehicle 1300 may further include one or more RADAR sensors 1360. In at least one embodiment, one or more RADAR sensors 1360 may be used by vehicle 1300 for remote vehicle detection, even in dark and / or inclement weather conditions. In at least one embodiment, the RADAR functional safety level may be ASIL B. In at least one embodiment, one or more RADAR sensors 1360 may use a CAN bus and / or bus 1302 (e.g., to transmit data generated by one or more RADAR sensors 1360) for control and access to object tracking data, and in some examples may access an Ethernet channel to access raw data. In at least one embodiment, a wide variety of RADAR sensor types may be used. For example, but not limited to, one or more of the RADAR sensors 1360 may be suitable for front, rear, and side RADAR use. In at least one embodiment, one or more RADAR sensors 1360 are pulse Doppler RADAR sensors.

[0282] In at least one embodiment, one or more RADAR sensors 1360 may include different configurations, such as long-range with a narrow field of view, short-range with a wide field of view, short-range side coverage, etc. In at least one embodiment, the long-range RADAR can be used for adaptive cruise control functions. In at least one embodiment, the long-range RADAR system can provide a wide field of view achieved through two or more independent scans (e.g., within a 250m range). In at least one embodiment, one or more RADAR sensors 1360 can help distinguish between stationary and moving objects and can be used by the ADAS system 1338 for emergency braking assistance and forward collision warning. In at least one embodiment, one or more sensors 1360 included in the long-range RADAR system may include, but are not limited to, a monostatic multimode RADAR with multiple (e.g., six or more) fixed RADAR antennas and high-speed CAN and FlexRay interfaces. In at least one embodiment, having six antennas, with the four central antennas, can create a focused beammap designed to record the surrounding environment of the vehicle 1300 at a high speed while minimizing traffic interference from adjacent lanes. In at least one embodiment, the other two antennas can expand the field of view, thereby enabling rapid detection of vehicles 1300 entering or leaving the lane.

[0283] In at least one embodiment, as an example, a mid-range RADAR system may include, for example, a range of up to 160m (front) or 80m (rear), and a field of view of up to 42 degrees (front) or 150 degrees (rear). In at least one embodiment, a short-range RADAR system may include, but is not limited to, any number of RADAR sensors 1360 designed to be mounted at both ends of the rear bumper. When mounted at both ends of the rear bumper, in at least one embodiment, the RADAR sensor system may generate two beams that continuously monitor the rearward direction of the vehicle and nearby blind spots. In at least one embodiment, the short-range RADAR system may be used in ADAS system 1338 for blind spot detection and / or lane change assistance.

[0284] In at least one embodiment, the vehicle 1300 may further include one or more ultrasonic sensors 1362. In at least one embodiment, one or more ultrasonic sensors 1362, which may be positioned at the front, rear, and / or sides of the vehicle 1300, may be used for parking assistance and / or creating and updating occupancy detectors. In at least one embodiment, a wide variety of ultrasonic sensors 1362 may be used, and different ultrasonic sensors 1362 may be used for different detection ranges (e.g., 2.5m, 4m). In at least one embodiment, the ultrasonic sensors 1362 may operate at the ASIL B functional safety level.

[0285] In at least one embodiment, vehicle 1300 may include one or more LiDAR sensors 1364. In at least one embodiment, one or more LiDAR sensors 1364 may be used for object and pedestrian detection, emergency braking, collision avoidance, and / or other functions. In at least one embodiment, one or more LiDAR sensors 1364 may operate at functional safety level ASIL B. In at least one embodiment, vehicle 1300 may include multiple (e.g., two, four, six, etc.) LiDAR sensors 1364 that can use Ethernet channels (e.g., providing data to a Gigabit Ethernet switch).

[0286] In at least one embodiment, one or more LiDAR sensors 1364 may be able to provide a list of objects and their distances for a 360-degree field of view. In at least one embodiment, one or more commercially available LiDAR sensors 1364 may, for example, have an advertising range of approximately 100m, an accuracy of 2cm-3cm, and support a 100Mbps Ethernet connection. In at least one embodiment, one or more non-protruding LiDAR sensors may be used. In such an embodiment, one or more LiDAR sensors 1364 may include small devices that can be embedded in the front, rear, side, and / or corner locations of vehicle 1300. In at least one embodiment, one or more LiDAR sensors 1364, in such an embodiment, can provide a horizontal field of view of up to 120 degrees and a vertical field of view of 35 degrees, even for objects with low reflectivity, and have a range of 200m. In at least one embodiment, one or more forward-facing LiDAR sensors 1364 may be configured for a horizontal field of view between 45 degrees and 135 degrees.

[0287] In at least one embodiment, LIDAR technology (such as 3D flash LIDAR) may also be used. In at least one embodiment, 3D flash LIDAR uses a laser flash as a transmission source to illuminate approximately 200m around vehicle 1300. In at least one embodiment, the flash LIDAR unit includes, but is not limited to, a receiver that records the laser pulse propagation time and reflected light on each pixel, which in turn corresponds to the range from vehicle 1300 to the object. In at least one embodiment, flash LIDAR can allow the generation of highly accurate and distortion-free images of the surrounding environment using each laser flash. In at least one embodiment, four flash LIDAR sensors may be deployed, one on each side of vehicle 1300. In at least one embodiment, the 3D flash LIDAR system includes, but is not limited to, a solid-state 3D line-of-sight array LIDAR camera with no moving parts other than a fan (e.g., a non-scanning LIDAR device). In at least one embodiment, the flash LIDAR device can use a 5-nanosecond Class I (eye-safe) laser pulse per frame and can capture reflected laser light as a 3D ranging point cloud and co-registered intensity data.

[0288] In at least one embodiment, vehicle 1300 may further include one or more IMU sensors 1366. In at least one embodiment, one or more IMU sensors 1366 may be located at the center of the rear axle of vehicle 1300. In at least one embodiment, one or more IMU sensors 1366 may include, for example, but not limited to, one or more accelerometers, one or more magnetometers, one or more gyroscopes, a magnetic compass, multiple magnetic compasses, and / or other sensor types. In at least one embodiment, for example in a six-axis application, one or more IMU sensors 1366 may include, but are not limited to, accelerometers and gyroscopes. In at least one embodiment, for example in a nine-axis application, one or more IMU sensors 1366 may include, but are not limited to, accelerometers, gyroscopes, and magnetometers.

[0289] In at least one embodiment, one or more IMU sensors 1366 may be implemented as a miniature, high-performance GPS-assisted inertial navigation system (“GPS / INS”) combining a microelectromechanical system (“MEMS”) inertial sensor, a high-sensitivity GPS receiver, and an advanced Kalman filtering algorithm to provide position, velocity, and attitude estimations; in at least one embodiment, one or more IMU sensors 1366 may enable vehicle 1300 to estimate heading without input from a magnetic sensor obtained by directly observing and correlating velocity changes from GPS to one or more IMU sensors 1366. In at least one embodiment, one or more IMU sensors 1366 and one or more GNSS sensors 1358 may be combined in a single integrated unit.

[0290] In at least one embodiment, vehicle 1300 may include one or more microphones 1396 placed inside and / or around vehicle 1300. In at least one embodiment, in addition, one or more microphones 1396 may be used for emergency vehicle detection and identification.

[0291] In at least one embodiment, vehicle 1300 may further include any number of camera types, including one or more stereo cameras 1368, one or more wide-angle cameras 1370, one or more infrared cameras 1372, one or more surround cameras 1374, one or more long-range cameras 1398, one or more mid-range cameras 1376, and / or other camera types. In at least one embodiment, the cameras can be used to capture image data around the entire perimeter of vehicle 1300. In at least one embodiment, the type of camera used depends on vehicle 1300. In at least one embodiment, any combination of camera types can be used to provide the necessary coverage around vehicle 1300. In at least one embodiment, the number of cameras deployed may vary depending on the embodiment. For example, in at least one embodiment, vehicle 1300 may include six cameras, seven cameras, ten cameras, twelve cameras, or other numbers of cameras. In at least one embodiment, the cameras may be, by way of example but not limited to, supporting gigabit multimedia serial link (“GMSL”) and / or gigabit Ethernet communication. In at least one embodiment, previously referenced herein Figure 13A and Figure 13B Each camera can be described in more detail.

[0292] In at least one embodiment, the vehicle 1300 may further include one or more vibration sensors 1342. In at least one embodiment, the one or more vibration sensors 1342 may measure vibrations of components of the vehicle 1300 (e.g., axles). For example, in at least one embodiment, changes in vibration may indicate changes in road surface conditions. In at least one embodiment, when two or more vibration sensors 1342 are used, differences between vibrations may be used to determine road surface friction or slippage (e.g., when there is a vibration difference between a power drive axle and a free-rotating axle).

[0293] In at least one embodiment, vehicle 1300 may include ADAS system 1338. In at least one embodiment, ADAS system 1338 may include, but is not limited to, SoC. In at least one embodiment, ADAS system 1338 may include, but is not limited to, any number of autonomous / adaptive / automatic cruise control (“ACC”) systems, cooperative adaptive cruise control (“CACC”) systems, forward collision warning (“FCW”) systems, automatic emergency braking (“AEB”) systems, lane departure warning (“LDW”) systems, lane keeping assist (“LKA”) systems, blind spot warning (“BSW”) systems, rear cross traffic warning (“RCTW”) systems, collision warning (“CW”) systems, lane centering (“LC”) systems, and / or other systems, features, and / or functions, and combinations thereof.

[0294] In at least one embodiment, the ACC system may use one or more RADAR sensors 1360, one or more LIDAR sensors 1364, and / or any number of cameras. In at least one embodiment, the ACC system may include a longitudinal ACC system and / or a lateral ACC system. In at least one embodiment, the longitudinal ACC system monitors and controls the distance to another vehicle adjacent to vehicle 1300 and automatically adjusts the speed of vehicle 1300 to maintain a safe distance from the vehicle ahead. In at least one embodiment, the lateral ACC system performs distance holding and suggests that vehicle 1300 change lanes if necessary. In at least one embodiment, lateral ACC is associated with other ADAS applications, such as LC and CW.

[0295] In at least one embodiment, the CACC system uses information from other vehicles, which may be received from other vehicles via network interface 1324 and / or one or more wireless antennas 1326 via a wireless link or indirectly via a network connection (e.g., via the Internet). In at least one embodiment, the direct link may be provided by a vehicle-to-vehicle (“V2V”) communication link, while the indirect link may be provided by an infrastructure-to-vehicle (“I2V”) communication link. Typically, V2V communication provides information about the vehicle immediately preceding it (e.g., a vehicle immediately in front of vehicle 1300 and in the same lane as it), while I2V communication provides information about traffic further ahead. In at least one embodiment, the CACC system may include one or both of the I2V and V2V information sources. In at least one embodiment, given information about vehicles preceding vehicle 1300, the CACC system can be more reliable and has the potential to improve traffic flow smoothness and reduce road congestion.

[0296] In at least one embodiment, the FCW system is designed to warn the driver of danger so that the driver can take corrective action. In at least one embodiment, the FCW system uses a forward-facing camera and / or one or more RADAR sensors 1360, coupled to a dedicated processor, DSP, FPGA, and / or ASIC, electrically coupled to components providing driver feedback, such as a display, speaker, and / or vibration. In at least one embodiment, the FCW system can provide warnings, for example, in the form of audible, visual warnings, vibrations, and / or rapid braking pulses.

[0297] In at least one embodiment, the AEB system detects an impending forward collision with another vehicle or other object and can automatically apply brakes if the driver does not take corrective action within a specified time or distance parameter. In at least one embodiment, the AEB system may use one or more forward-facing cameras and / or one or more RADAR sensors 1360 coupled to a dedicated processor, DSP, FPGA, and / or ASIC. In at least one embodiment, when the AEB system detects a hazard, it typically first warns the driver to take corrective action to avoid a collision, and if the driver does not take corrective action, the AEB system may automatically apply brakes to attempt to prevent or at least mitigate the effects of the predicted collision. In at least one embodiment, the AEB system may include techniques such as dynamic braking to support and / or brakes for impending collisions.

[0298] In at least one embodiment, when vehicle 1300 crosses lane markings, the LDW system provides visual, auditory, and / or tactile warnings, such as steering wheel or seat vibrations, to alert the driver. In at least one embodiment, the LDW system is inactive when the driver indicates intentional lane departure, such as by activating turn signals. In at least one embodiment, the LDW system may use a front-facing camera coupled to a dedicated processor, DSP, FPGA, and / or ASIC, which is electrically coupled to provide driver feedback such as a display, speaker, and / or vibration components. In at least one embodiment, the LKA system is a variant of the LDW system. In at least one embodiment, if vehicle 1300 begins to leave the lane, the LKA system provides steering input or braking to correct vehicle 1300.

[0299] In at least one embodiment, the BSW system detects and warns the driver of a vehicle in the blind spot. In at least one embodiment, the BSW system can provide visual, auditory, and / or tactile alerts to indicate that merging or changing lanes is unsafe. In at least one embodiment, the BSW system can provide additional warnings when the driver uses the turn signal. In at least one embodiment, the BSW system can use one or more rear-facing cameras and / or one or more RADAR sensors 1360 coupled to a dedicated processor, DSP, FPGA, and / or ASIC, electrically coupled to driver feedback, such as a display, speaker, and / or vibration assembly.

[0300] In at least one embodiment, the RCTW system can provide visual, auditory, and / or tactile notifications when an object is detected outside the range of the rear camera while the vehicle 1300 is reversing. In at least one embodiment, the RCTW system includes an AEB system to ensure the applied vehicle brakes to avoid a collision. In at least one embodiment, the RCTW system may use one or more rear-facing RADAR sensors 1360 coupled to a dedicated processor, DSP, FPGA, and / or ASIC, which are electrically coupled to provide driver feedback such as displays, speakers, and / or vibration components.

[0301] In at least one embodiment, conventional ADAS systems may be prone to generating false alarms, which can be annoying and distracting to the driver, but are generally not catastrophic because conventional ADAS systems warn the driver and allow the driver to determine whether a safe situation truly exists and take appropriate action. In at least one embodiment, in the event of conflicting results, the vehicle 1300 itself decides whether to follow the result of the main computer or the auxiliary computer (e.g., the first or second controller of controller 1336). For example, in at least one embodiment, ADAS system 1338 may be a backup and / or auxiliary computer for providing perception information to a backup computer rationality module. In at least one embodiment, the backup computer rationality monitor may run redundant software on hardware components to detect faults in perception and dynamic driving tasks. In at least one embodiment, the output from ADAS system 1338 may be provided to a monitoring MCU. In at least one embodiment, if the output from the main computer and the output from the auxiliary computer conflict, the monitoring MCU decides how to reconcile the conflict to ensure safe operation.

[0302] In at least one embodiment, the master computer may be configured to provide a confidence score to the supervisory MCU to indicate the master computer's confidence in the selected result. In at least one embodiment, if the confidence score exceeds a threshold, the supervisory MCU may follow the master computer's instructions regardless of whether the auxiliary computer provides conflicting or inconsistent results. In at least one embodiment, if the confidence score does not meet the threshold, and if the master computer and the auxiliary computer indicate different results (e.g., conflicting), the supervisory MCU may arbitrate between the computers to determine the appropriate result.

[0303] In at least one embodiment, the supervisory MCU may be configured to run a neural network trained and configured to determine, at least in part, the conditions under which the auxiliary computer provides a false alarm based on outputs from a host computer and an auxiliary computer. In at least one embodiment, the neural network in the supervisory MCU may learn when the outputs of the auxiliary computer can be trusted and when they cannot. For example, in at least one embodiment, when the auxiliary computer is a RADAR-based FCW system, the neural network in the supervisory MCU may learn when the FCW system recognizes a metallic object that is not actually dangerous, such as a drain grating or manhole cover that would trigger an alarm. In at least one embodiment, when the auxiliary computer is a camera-based LDW system, the neural network in the supervisory MCU may learn to override the LDW when a cyclist or pedestrian is present and lane departure is actually the safest operation. In at least one embodiment, the supervisory MCU may include at least one of a DLA or GPU suitable for running a neural network with associated memory. In at least one embodiment, the supervisory MCU may include and / or be included as a component of one or more SoC 1304s.

[0304] In at least one embodiment, the ADAS system 1338 may include an auxiliary computer that performs ADAS functions using conventional computer vision rules. In at least one embodiment, the auxiliary computer may use classic computer vision rules (if-then), and the presence of a neural network in the supervisory MCU can improve reliability, security, and performance. For example, in at least one embodiment, diverse implementations and intentional non-identity make the entire system more fault-tolerant, especially for failures caused by software (or software-hardware interface) functionality. For example, in at least one embodiment, if a software vulnerability or bug exists in the software running on the host computer, and different software code running on the auxiliary computer provides consistent overall results, the supervisory MCU can more confidently assume that the overall result is correct and that the vulnerability in the software or hardware on the host computer will not lead to a significant error.

[0305] In at least one embodiment, the output of the ADAS system 1338 can be input to the perception module and / or the dynamic driving task module of the host computer. For example, in at least one embodiment, if the ADAS system 1338 indicates a forward collision warning due to an object directly ahead, the perception block can use this information when identifying the object. In at least one embodiment, as described herein, the assistance computer can have its own neural network trained to reduce the risk of false alarms.

[0306] In at least one embodiment, vehicle 1300 may further include an infotainment SoC 1330 (e.g., an in-vehicle infotainment system (IVI)). Although shown and described as an SoC, in at least one embodiment, the infotainment system SoC 1330 may not be an SoC and may include, but is not limited to, two or more discrete components. In at least one embodiment, the infotainment SoC 1330 may include, but is not limited to, a combination of hardware and software that can be used to provide audio (e.g., music, personal digital assistant, navigation instructions, news, radio, etc.), video (e.g., television, movies, streaming media, etc.), telephone (e.g., hands-free calling), network connectivity (e.g., LTE, WiFi, etc.) and / or information services (e.g., navigation system, rear parking assist, radio data system, vehicle-related information such as fuel level, total coverage distance, brake fuel level, fuel level, door opening / closing, air filter information, etc.) to vehicle 1300. For example, the infotainment SoC 1330 may include a radio, disk player, navigation system, video player, USB and Bluetooth connectivity, automobile, in-vehicle entertainment system, WiFi, steering wheel audio controls, hands-free voice control, head-up display (“HUD”), HMI display 1334, telematics device, control panel (e.g., for controlling and / or interacting with various components, features and / or systems) and / or other components. In at least one embodiment, the infotainment SoC 1330 may further be used to provide information (e.g., visual and / or auditory) to a user of vehicle 1300, such as information from ADAS system 1338, autonomous driving information (such as planned vehicle maneuvers), trajectory, surrounding environment information (e.g., intersection information, vehicle information, road information, etc.) and / or other information.

[0307] In at least one embodiment, the infotainment SoC 1330 may include any number and type of GPU functionality. In at least one embodiment, the infotainment SoC 1330 may communicate with other devices, systems, and / or components of the vehicle 1300 via bus 1302. In at least one embodiment, the infotainment SoC 1330 may be coupled to a monitoring MCU, enabling the GPU of the infotainment system to perform some autonomous driving functions in the event of a failure of the main controller 1336 (e.g., the main computer and / or backup computer of the vehicle 1300). In at least one embodiment, the infotainment SoC 1330 may cause the vehicle 1300 to enter a driver-to-safe-stop mode, as described herein.

[0308] In at least one embodiment, vehicle 1300 may further include instrument panel 1332 (e.g., digital instrument panel, electronic instrument panel, digital instrument control panel, etc.). In at least one embodiment, instrument panel 1332 may include, but is not limited to, controllers and / or supercomputers (e.g., discrete controllers or supercomputers). In at least one embodiment, instrument panel 1332 may include, but is not limited to, any number and combination of a set of instruments, such as speedometer, fuel level, oil pressure, tachometer, odometer, turn indicator, shift position indicator, one or more seatbelt warning lights, one or more parking brake warning lights, one or more engine malfunction lights, auxiliary restraint system (e.g., airbag) information, lighting controls, safety system controls, navigation information, etc. In some examples, information may be displayed and / or shared between infotainment SoC 1330 and instrument panel 1332. In at least one embodiment, instrument panel 1332 may be included as part of infotainment SoC 1330, or vice versa.

[0309] Inference and / or training logic 1015 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 10A and / or Figure 10B Details regarding the inference and / or training logic 1015 are provided. In at least one embodiment, the inference and / or training logic 1015 can be implemented in the system. Figure 13C The inference and / or training logic 1015 is used to infer or predict operations based at least in part on weight parameters calculated using neural network training operations, neural network functions and / or architecture, or neural network use cases described herein. In various embodiments, the inference and / or training logic 1015 utilizes target image data generated by offline image signal processing 240, as described above. Figure 2 As stated above. Furthermore, the above is combined with... Figure 2 The data collection 202 described is performed by vehicle 1300 in various embodiments.

[0310] Figure 13DIt is based on at least one embodiment in a cloud-based server and Figure 13A A diagram of a system for communication between autonomous vehicles 1300. In at least one embodiment, the system may include, but is not limited to, one or more servers 1378, one or more networks 1390, and any number and type of vehicles, including vehicle 1300. In at least one embodiment, one or more servers 1378 may include, but is not limited to, multiple GPUs 1384(A)-1384(H) (collectively referred to herein as GPU 1384), PCIe switches 1382(A)-1382(D) (collectively referred to herein as PCIe switch 1382), and / or CPUs 1380(A)-1380(B) (collectively referred to herein as CPU 1380). GPU 1384, CPU 1380, and PCIe switch 1382 may be interconnected with high-speed cables, such as, but not limited to, NVLink interface 1388 developed by NVIDIA and / or PCIe connection 1386. In at least one embodiment, the GPU 1384 is connected via NVLink and / or NVSwitchSoC, and the GPU 1384 and PCIe switch 1382 are connected via PCIe interconnect. Although eight GPUs 1384, two CPUs 1380, and four PCIe switches 1382 are shown, this is not intended to be limiting. In at least one embodiment, each of one or more servers 1378 may include, but is not limited to, any combination of any number of GPUs 1384, CPUs 1380, and / or PCIe switches 1382. For example, in at least one embodiment, one or more servers 1378 may each include eight, sixteen, thirty-two, and / or more GPUs 1384.

[0311] In at least one embodiment, one or more servers 1378 may receive image data representing images from vehicles via one or more networks 1390, the images showing unexpected or changed road conditions, such as recently commenced roadworks. In at least one embodiment, one or more servers 1378 may transmit updated neural network 1392 and / or map information 1394, including but not limited to information about traffic and road conditions, to vehicles via one or more networks 1390. In at least one embodiment, updates to map information 1394 may include, but are not limited to, updates to HD map 1322, such as information about construction sites, potholes, sidewalks, floods, and / or other obstacles. In at least one embodiment, neural network 1392 and / or map information 1394 may be generated from new training and / or experience represented by data received from any number of vehicles in the environment, and / or at least based on training performed in a data center (e.g., using one or more servers 1378 and / or other servers).

[0312] In at least one embodiment, one or more servers 1378 may be used to train a machine learning model (e.g., a neural network) at least in part based on training data. In at least one embodiment, the training data may be generated by the vehicle, and / or may be generated in a simulation (e.g., using a game engine). In at least one embodiment, any amount of training data is labeled (e.g., where the associated neural network benefits from supervised learning) and / or undergoes other preprocessing. In at least one embodiment, no amount of training data is labeled and / or preprocessed (e.g., where the associated neural network does not require supervised learning). In at least one embodiment, once the machine learning model is trained, the machine learning model may be used by the vehicle (e.g., transmitted to the vehicle via one or more networks 1390), and / or the machine learning model may be used by one or more servers 1378 to remotely monitor the vehicle.

[0313] In at least one embodiment, one or more servers 1378 may receive data from the vehicle and apply the data to state-of-the-art real-time neural networks for real-time intelligent inference. In at least one embodiment, one or more servers 1378 may include a deep learning supercomputer and / or a dedicated AI computer powered by one or more GPUs 1384, such as the DGX and DGX Station machines developed by NVIDIA. However, in at least one embodiment, one or more servers 1378 may include a deep learning infrastructure in a data center using CPU power.

[0314] In at least one embodiment, the deep learning infrastructure of one or more servers 1378 may be capable of fast, real-time inference and may use this capability to assess and verify the health of the processor, software, and / or associated hardware in vehicle 1300. For example, in at least one embodiment, the deep learning infrastructure may receive periodic updates from vehicle 1300, such as image sequences and / or objects located by vehicle 1300 in the image sequence (e.g., via computer vision and / or other machine learning object classification techniques). In at least one embodiment, the deep learning infrastructure may run its own neural network to identify objects and compare them with objects identified by vehicle 1300, and if the results do not match and the deep learning infrastructure determines that the AI ​​in vehicle 1300 is malfunctioning, one or more servers 1378 may signal to vehicle 1300 to instruct the fail-safe computer of vehicle 1300 to take control, notify passengers, and complete a safe stopping operation.

[0315] In at least one embodiment, one or more servers 1378 may include one or more GPUs 1384 and one or more programmable inference accelerators (e.g., NVIDIA's TensorRT 3 devices). In at least one embodiment, the combination of GPU-driven servers and inference acceleration enables real-time response. In at least one embodiment, for example, where performance is less critical, servers driven by CPUs, FPGAs, and other processors may be used for inference. In at least one embodiment, training logic 1015 is used to execute one or more embodiments. This document incorporates... Figure 10A and / or Figure 10B Provide details about training logic 1015.

[0316] Computer System

[0317] Figure 14 This is a block diagram illustrating an exemplary computer system according to at least one embodiment. The exemplary computer system may be a system of interconnected devices and components, a system-on-a-chip (SOC), or some combination thereof formed with a processor, which may include an execution unit to execute instructions. In at least one embodiment, according to this disclosure, such as the embodiments described herein, computer system 1400 may include, but is not limited to, components such as processor 1402, whose execution unit includes logic to execute algorithms for process data. In at least one embodiment, computer system 1400 may include a processor, such as those available from Intel Corporation of Santa Clara, California. Processor family, Xeon TM , XScale TM and / or StrongARM TM , Core TM or Nervana TM A microprocessor may be used, although other systems (including PCs, engineering workstations, set-top boxes, etc.) with other microprocessors may also be used. In at least one embodiment, computer system 1400 may execute a version of the Windows operating system available from Microsoft Corporation of Redmond, Washington, although other operating systems (such as UNIX and Linux), embedded software, and / or graphical user interfaces may also be used.

[0318] The embodiments can be used in other devices, such as handheld devices and embedded applications. Some examples of handheld devices include cellular phones, Internet Protocol (IP) devices, digital cameras, personal digital assistants (“PDAs”), and handheld PCs. In at least one embodiment, the embedded application may include a microcontroller, a digital signal processor (“DSP”), a system-on-a-chip (SoC), a network computer (“NetPC”), a set-top box, a network hub, a wide area network (“WAN”) switch, or any other system that can execute one or more instructions according to at least one embodiment.

[0319] In at least one embodiment, the computer system 1400 may include, but is not limited to, a processor 1402, which may include, but is not limited to, one or more execution units 1408, to perform machine learning model training and / or inference according to the techniques described herein. In at least one embodiment, the computer system 1400 is a single-processor desktop or server system, but in another embodiment, the computer system 1400 may be a multiprocessor system. In at least one embodiment, the processor 1402 may include, but is not limited to, a Complex Instruction Set Computer (“CISC”) microprocessor, a Reduced Instruction Set Computing (“RISC”) microprocessor, a Very Long Instruction Word (“VLIW”) microprocessor, a processor implementing instruction set combination, or any other processor device, such as a digital signal processor. In at least one embodiment, the processor 1402 may be coupled to a processor bus 1410, which can transmit data signals between the processor 1402 and other components in the computer system 1400.

[0320] In at least one embodiment, processor 1402 may include, but is not limited to, a Level 1 (“L1”) internal cache memory (“cache”) 1404. In at least one embodiment, processor 1402 may have a single internal cache or multiple levels of internal cache. In at least one embodiment, the cache memory may reside external to processor 1402. Depending on specific implementation and requirements, other embodiments may also include a combination of internal and external caches. In at least one embodiment, register file 1406 may store different types of data in various registers, including but not limited to integer registers, floating-point registers, status registers, and instruction pointer registers.

[0321] In at least one embodiment, an execution unit 1408, including but not limited to logic for performing integer and floating-point operations, is also located within processor 1402. In at least one embodiment, processor 1402 may further include a microcode (“ucode”) read-only memory (“ROM”) for storing microcode of certain macro instructions. In at least one embodiment, execution unit 1408 may include logic for processing a packaged instruction set 1409. In at least one embodiment, by including the packaged instruction set 1409 in the instruction set of a general-purpose processor, along with the associated circuitry for executing the instructions, the packaged data in processor 1402 can be used to perform operations used by numerous multimedia applications. In at least one or more embodiments, the execution of numerous multimedia applications can be accelerated and performed more efficiently by using the full width of the processor's data bus to perform operations on the packaged data, which may eliminate the need to transfer smaller data units on the processor's data bus to perform one or more operations on one data element at a time.

[0322] In at least one embodiment, execution unit 1408 may also be used in a microcontroller, embedded processor, graphics device, DSP, and other types of logic circuitry. In at least one embodiment, computer system 1400 may include, but is not limited to, memory 1420. In at least one embodiment, memory 1420 may be a dynamic random access memory (“DRAM”) device, a static random access memory (“SRAM”) device, a flash memory device, or another storage device. In at least one embodiment, memory 1420 may store instructions 1419 and / or data 1421 represented by data signals that can be executed by processor 1402.

[0323] In at least one embodiment, the system logic chip may be coupled to processor bus 1410 and memory 1420. In at least one embodiment, the system logic chip may include, but is not limited to, a memory controller hub (“MCH”) 1416, and processor 1402 may communicate with MCH 1416 via processor bus 1410. In at least one embodiment, MCH 1416 may provide a high-bandwidth memory path 1418 to memory 1420 for instruction and data storage, as well as for storage of graphics commands, data, and textures. In at least one embodiment, MCH 1416 may initiate data signals between processor 1402, memory 1420, and other components in computer system 1400, and bridge data signals between processor bus 1410, memory 1420, and system I / O interface 1422. In at least one embodiment, the system logic chip may provide a graphics port for coupling to a graphics controller. In at least one embodiment, MCH 1416 may be coupled to memory 1420 via high-bandwidth memory path 1418, and graphics / video card 1412 may be coupled to MCH 1416 via Accelerated Graphics Port (“AGP”) interconnect 1414.

[0324] In at least one embodiment, the computer system 1400 may use the system I / O interface 1422 as a proprietary hub interface bus to couple the MCH 1416 to the I / O controller hub (“ICH”) 1430. In at least one embodiment, the ICH 1430 may provide direct connectivity to certain I / O devices via a local I / O bus. In at least one embodiment, the local I / O bus may include, but is not limited to, a high-speed I / O bus for connecting peripheral devices to the memory 1420, chipset, and processor 1402. Examples may include, but are not limited to, an audio controller 1429, a firmware hub (“Flash BIOS”) 1428, a wireless transceiver 1426, a data storage 1424, a conventional I / O controller 1423 including a user input and keyboard interface 1425, a serial expansion port 1427 (e.g., a Universal Serial Bus (USB) port), and a network controller 1434. In at least one embodiment, the data storage 1424 may include a hard disk drive, a floppy disk drive, a CD-ROM device, a flash memory device, or other mass storage device.

[0325] In at least one embodiment, Figure 14 A system including interconnected hardware devices or "chips" is shown, while in other embodiments, Figure 14 The SoC can be shown. In at least one embodiment, Figure 14The devices shown can be interconnected with proprietary interconnects, standardized interconnects (e.g., PCIe), or some combination thereof. In at least one embodiment, one or more components of the computer system 1400 are interconnected using a Compute Fast Link (CXL) interconnect.

[0326] The inference and / or training logic 1015 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 10A and / or Figure 10B Details regarding the inference and / or training logic 1015 are provided. In at least one embodiment, the inference and / or training logic 1015 can... Figure 14 Used in systems for reasoning or predicting operations based at least in part on weight parameters calculated using neural network training operations, neural network functions and / or architectures or neural network use cases described herein.

[0327] Figure 15 This is a block diagram illustrating an electronic device 1500 for utilizing a processor 1510 according to at least one embodiment. In at least one embodiment, the electronic device 1500 may be, for example, but not limited to, a laptop computer, tower server, rack server, blade server, laptop computer, desktop computer, tablet computer, mobile device, telephone, embedded computer, or any other suitable electronic device.

[0328] In at least one embodiment, the electronic device 1500 may include, but is not limited to, a processor 1510 communicatively coupled to any suitable number or type of components, peripherals, modules, or devices. In at least one embodiment, the processor 1510 is coupled using a bus or interface, such as I... 2 C-bus, System Management Bus (“SMBus”), Low Pin Count (LPC) bus, Serial Peripheral Interface (“SPI”), High Definition Audio (“HDA”) bus, Serial Advanced Technology Accessory (“SATA”) bus, Universal Serial Bus (“USB”) (versions 1, 2, 3, etc.), or Universal Asynchronous Receiver / Transmitter (“UART”) bus. In at least one embodiment, Figure 15 The system shown includes interconnected hardware devices or "chips," while in other embodiments, Figure 15 An exemplary SoC can be shown. In at least one embodiment, Figure 15 The device shown can be interconnected with proprietary interconnects, standardized interconnects (e.g., PCIe), or some combination thereof. In at least one embodiment, Figure 15 One or more components are interconnected using Computational Fast Link (CXL) interconnects.

[0329] In at least one embodiment, Figure 15It may include a display 1524, a touch screen 1525, a touchpad 1530, a near field communication unit (“NFC”) 1545, a sensor hub 1540, a thermal sensor 1546, a fast chipset (“EC”) 1535, a trusted platform module (“TPM”) 1538, a BIOS / firmware / flash (“BIOS, FW Flash”) 1522, a DSP 1560, a drive 1520 (e.g., a solid-state drive (“SSD”) or a hard disk drive (“HDD”)), a wireless local area network unit (“WLAN”) 1550, a Bluetooth unit 1552, a wireless wide area network unit (“WWAN”) 1556, a global positioning system (GPS) unit 1555, a camera (“USB 3.0 camera”) 1554 (e.g., a USB 3.0 camera), and / or a low-power double data rate (“LPDDR”) memory unit (“LPDDR3”) 1515 implemented in, for example, the LPDDR3 standard. These components can each be implemented in any suitable way.

[0330] In at least one embodiment, other components may be communicatively coupled to processor 1510 via the components described herein. In at least one embodiment, accelerometer 1541, ambient light sensor (“ALS”) 1542, compass 1543, and gyroscope 1544 may be communicatively coupled to sensor hub 1540. In at least one embodiment, thermal sensor 1539, fan 1537, keyboard 1536, and touchpad 1530 may be communicatively coupled to EC 1535. In at least one embodiment, speaker 1563, earphone 1564, and microphone (“mic”) 1565 may be communicatively coupled to audio unit (“audio codec and Class D amplifier”) 1562, which in turn may be communicatively coupled to DSP 1560. In at least one embodiment, audio unit 1562 may include, for example, but not limited to, audio encoder / decoder (“codec”) and Class D amplifier. In at least one embodiment, SIM card (“SIM”) 1557 may be communicatively coupled to WWAN unit 1556. In at least one embodiment, components such as WLAN unit 1550, Bluetooth unit 1552, and WWAN unit 1556 can be implemented as next-generation form factor (NGFF).

[0331] Inference and / or training logic 1015 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 10A and / or Figure 10B Details regarding the inference and / or training logic 1015 are provided. In at least one embodiment, the inference and / or training logic 1015 can be implemented in the system. Figure 15The inference and / or training logic 1015 is used to infer or predict operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein. In various embodiments, the inference and / or training logic 1015 utilizes target image data generated by offline image signal processing 240, as described above in conjunction with... Figure 2 As stated above. Furthermore, the above is combined with... Figure 2 The data collection 202 described is performed by vehicle 1300 in various embodiments.

[0332] Figure 16 A computer system 1600 according to at least one embodiment is shown. In at least one embodiment, the computer system 1600 is configured to implement various processes and methods described throughout this disclosure.

[0333] In at least one embodiment, the computer system 1600 includes, but is not limited to, at least one central processing unit (“CPU”) 1602 connected to a communication bus 1610 implemented using any suitable protocol, such as PCI (“Peripheral Interconnect”), Peripheral Component Interconnect Express (“PCI-Express”), AGP (“Accelerated Graphics Port”), HyperTransport, or any other bus or point-to-point communication protocol. In at least one embodiment, the computer system 1600 includes, but is not limited to, main memory 1604 and control logic (e.g., implemented in hardware, software, or a combination thereof), and data may be stored in main memory 1604 in the form of random access memory (“RAM”). In at least one embodiment, a network interface subsystem (“Network Interface”) 1622 provides an interface to other computing devices and networks for receiving data using the computer system 1600 and transferring data to other systems.

[0334] In at least one embodiment, the computer system 1600 includes, but is not limited to, an input device 1608, a parallel processing system 1612, and a display device 1606, which may be implemented using conventional cathode ray tube (“CRT”), liquid crystal display (“LCD”), light-emitting diode (“LED”) display, plasma display, or other suitable display technologies. In at least one embodiment, user input is received from the input device 1608 (such as a keyboard, mouse, touchpad, microphone, etc.). In at least one embodiment, each of the modules described herein may reside on a single semiconductor platform to form the processing system.

[0335] Inference and / or training logic 1015 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 10A and / or Figure 10BDetails regarding the inference and / or training logic 1015 are provided. In at least one embodiment, the inference and / or training logic 1015 can be implemented in the system. Figure 16 The inference and / or training logic 1015 is used to perform inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architecture, or neural network use cases described herein. In various embodiments, the inference and / or training logic 1015 utilizes target image data generated by offline image signal processing 240, as described above in conjunction with... Figure 2 As stated above. Furthermore, the above is combined with... Figure 2 The data collection 202 described is performed by vehicle 1300 in various embodiments.

[0336] Figure 17 A computer system 1700 according to at least one embodiment is illustrated. In at least one embodiment, the computer system 1700 includes, but is not limited to, a computer 1710 and a USB flash drive 1720. In at least one embodiment, the computer 1710 may include, but is not limited to, any number and type of processors (not shown) and memory (not shown). In at least one embodiment, the computer 1710 includes, but is not limited to, a server, a cloud instance, a laptop computer, and a desktop computer.

[0337] In at least one embodiment, the USB flash drive 1720 includes, but is not limited to, a processing unit 1730, a USB interface 1740, and USB interface logic 1750. In at least one embodiment, the processing unit 1730 can be any instruction execution system, apparatus, or device capable of executing instructions. In at least one embodiment, the processing unit 1730 can include, but is not limited to, any number and type of processing cores (not shown). In at least one embodiment, the processing unit 1730 includes an application-specific integrated circuit (“ASIC”) optimized to perform any number and type of operations associated with machine learning. For example, in at least one embodiment, the processing unit 1730 is a tensor processing unit (“TPC”) optimized to perform machine learning inference operations. In at least one embodiment, the processing unit 1730 is a vision processing unit (“VPU”) optimized to perform machine vision and machine learning inference operations.

[0338] In at least one embodiment, the USB interface 1740 can be any type of USB connector or USB receptacle. For example, in at least one embodiment, the USB interface 1740 is a USB 3.0 Type-C receptacle for data and power. In at least one embodiment, the USB interface 1740 is a USB 3.0 Type-A connector. In at least one embodiment, the USB interface logic 1750 may include any amount and type of logic enabling the processing unit 1730 to connect to a device (e.g., computer 1710) via the USB interface 1740.

[0339] Inference and / or training logic 1015 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 10A and / or Figure 10B Details regarding the inference and / or training logic 1015 are provided. In at least one embodiment, the inference and / or training logic 1015 can be implemented in the system. Figure 17 In use, at least in part, the operation is based on weight parameters, neural network functions and / or architectures computed using neural network training operations, or neural network use cases described herein to infer or predict operations.

[0340] Figure 18A An exemplary architecture is illustrated in which multiple GPUs 1810(1)-1810(N) are communicatively coupled to multiple multi-core processors 1805(1)-1805(M) via high-speed links 1840(1)-1840(N) (e.g., bus / point-to-point interconnect, etc.). In at least one embodiment, the high-speed links 1840(1)-1840(N) support communication throughput of 4GB / s, 30GB / s, 80GB / s, or higher. In at least one embodiment, various interconnect protocols may be used, including but not limited to PCIe 4.0 or 5.0 and NVLink 2.0. In the various figures, “N” and “M” represent positive integers, the values ​​of which may vary from figure to figure.

[0341] Furthermore, in at least one embodiment, two or more GPUs 1810 are interconnected via high-speed links 1829(1)-1829(2), which can be implemented using a protocol / link similar to or different from that used for high-speed links 1840(1)-1840(N). Similarly, two or more multi-core processors 1805 can be connected via high-speed link 1828, which can be a symmetric multiprocessor (SMP) bus operating at speeds of 20GB / s, 30GB / s, 120GB / s, or higher. Alternatively, similar protocols / links (e.g., via a common interconnect structure) can be used. Figure 18A This shows all communication between the various system components.

[0342] In at least one embodiment, each multi-core processor 1805 is communicatively coupled to processor memories 1801(1)-1801(M) via memory interconnects 1826(1)-1826(M), and each GPU 1810(1)-1810(N) is communicatively coupled to GPU memories 1820(1)-1820(N) via GPU memory interconnects 1850(1)-1850(N). In at least one embodiment, memory interconnects 1826 and 1850 may utilize similar or different memory access technologies. By way of example and not limitation, processor memories 1801(1)-1801(M) and GPU memories 1820 may be volatile memories, such as dynamic random access memory (DRAM) (including stacked DRAM), graphics DDR SDRAM (GDDR) (e.g., GDDR5, GDDR6), or high bandwidth memory (HBM), and / or may be non-volatile memories, such as 3D XPoint or Nano-RAM. In at least one embodiment, some portions of the processor memory 1801 may be volatile memory, while other portions may be non-volatile memory (e.g., using a two-level memory (2LM) hierarchy).

[0343] As described herein, although various multi-core processors 1805 and GPUs 1810 can be physically coupled to specific memories 1801 and 1820 respectively, and / or can implement a unified memory architecture, in which the virtual system address space (also known as the “effective address” space) is distributed among the various physical memories. For example, processor memories 1801(1)-1801(M) can each contain 64GB of system memory address space, and GPU memories 1820(1)-1820(N) can each contain 32GB of system memory address space, resulting in a total addressable memory size of 256GB when M=2 and N=4. N and M may also be other values.

[0344] Figure 18B Additional details are shown regarding the interconnection between a multi-core processor 1807 and a graphics acceleration module 1846 according to an exemplary embodiment. In at least one embodiment, the graphics acceleration module 1846 may include one or more GPU chips integrated on a line card coupled to the processor 1807 via a high-speed link 1840 (e.g., PCIe bus, NVLink, etc.). In at least one embodiment, the graphics acceleration module 1846 may optionally be integrated on a package or chip having the processor 1807.

[0345] In at least one embodiment, the processor 1807 includes a plurality of cores 1860A-1860D, each core having a translation back cover buffer (“TLB”) 1861A-1861D and one or more caches 1862A-1862D. In at least one embodiment, the cores 1860A-1860D may include various other components (not shown) for executing instructions and processing data. In at least one embodiment, the caches 1862A-1862D may include level 1 (L1) and level 2 (L2) caches. Furthermore, one or more shared caches 1856 may be included in the caches 1862A-1862D and shared by the respective groups of cores 1860A-1860D. For example, one embodiment of the processor 1807 includes 24 cores, each core having its own L1 cache, twelve shared L2 caches, and twelve shared L3 caches. In this embodiment, two adjacent cores share one or more L2 and L3 caches. In at least one embodiment, the processor 1807 and the graphics acceleration module 1846 are connected to a system memory 1814, which may include... Figure 18A The processor memory in the memory is 1801(1)-1801(M).

[0346] In at least one embodiment, consistency of data and instructions stored in the various caches 1862A-1862D, the shared cache 1856, and the system memory 1814 is maintained via inter-core communication through the consistency bus 1864. In at least one embodiment, for example, each cache may have associated cache consistency logic / circuit to communicate via the consistency bus 1864 in response to the detection of a read or write to a particular cache line. In at least one embodiment, a cache snooping protocol is implemented via the consistency bus 1864 to snoop on cache accesses.

[0347] In at least one embodiment, proxy circuitry 1825 communicatively couples graphics acceleration module 1846 to coherence bus 1864, thereby allowing graphics acceleration module 1846 to participate in cache coherence protocols as a peer of cores 1860A-1860D. Specifically, in at least one embodiment, interface 1835 provides connectivity to proxy circuitry 1825 via high-speed link 1840, and interface 1837 connects graphics acceleration module 1846 to high-speed link 1840.

[0348] In at least one embodiment, the accelerator integrated circuit 1836 provides cache management, memory access, context management, and interrupt management services for a plurality of graphics processing engines 1831(1)-1831(N) of the graphics acceleration module. In at least one embodiment, the graphics processing engines 1831(1)-1831(N) may each include a separate graphics processing unit (GPU). In at least one embodiment, the graphics processing engines 1831(1)-1831(N) may optionally include different types of graphics processing engines within the GPU, such as graphics execution units, media processing engines (e.g., video encoders / decoders), samplers, and blit engines. In at least one embodiment, the graphics acceleration module 1846 may be a GPU having a plurality of graphics processing engines 1831(1)-1831(N), or the graphics processing engines 1831(1)-1831(N) may be individual GPUs integrated on a general-purpose package, line card, or chip.

[0349] In at least one embodiment, the accelerator integrated circuit 1836 includes a memory management unit (MMU) 1839 for performing various memory management functions, such as virtual-to-physical memory translation (also known as effective-to-real memory translation), and a memory access protocol for accessing system memory 1814. In at least one embodiment, the MMU 1839 may also include a translation back buffer (“TLB”) (not shown) for caching virtual / effective-to-physical / real address translations. In at least one embodiment, cache 1838 may store commands and data for efficient access by graphics processing engines 1831(1)-1831(N). In at least one embodiment, a fetch unit 1844 may be used to keep data stored in cache 1838 and graphics memory 1833(1)-1833(M) consistent with core caches 1862A-1862D, shared cache 1856, and system memory 1814. As previously mentioned, this task can be accomplished via proxy circuitry 1825 representing cache 1838 and graphics memory 1833(1)-1833(M) (e.g., sending updates related to modifications / accesses to cache lines on processor caches 1862A-1862D and shared cache 1856 to cache 1838 and receiving updates from cache 1838).

[0350] In at least one embodiment, a set of registers 1845 stores context data of threads executed by graphics processing engines 1831(1)-1831(N), and context management circuitry 1848 manages the thread context. For example, context management circuitry 1848 can perform save and restore operations to save and restore the context of individual threads during context switching (e.g., saving the first thread and storing the second thread so that the second thread can be executed by the graphics processing engine). For example, during context switching, context management circuitry 1848 can store the current register value in a designated area of ​​memory (e.g., identified by a context pointer). The register value can then be restored when returning to the context. In at least one embodiment, interrupt management circuitry 1847 receives and processes interrupts received from system devices.

[0351] In at least one embodiment, MMU 1839 translates virtual / effective addresses from graphics processing engine 1831 into real / physical addresses in system memory 1814. In at least one embodiment, accelerator integrated circuit 1836 supports multiple (e.g., 4, 8, 16) graphics acceleration modules 1846 and / or other accelerator devices. In at least one embodiment, graphics acceleration module 1846 may be dedicated to a single application executing on processor 1807, or may be shared among multiple applications. In at least one embodiment, a virtualized graphics execution environment is presented, wherein resources of graphics processing engines 1831(1)-1831(N) are shared with multiple applications or virtual machines (VMs). In at least one embodiment, resources may be subdivided into “slices” based on processing requirements and priorities associated with VMs and / or applications, which are allocated to different VMs and / or applications.

[0352] In at least one embodiment, the accelerator integrated circuit 1836 acts as a bridge to the system of the graphics acceleration module 1846 and provides address translation and system memory caching services. Additionally, in at least one embodiment, the accelerator integrated circuit 1836 can provide virtualization facilities for the host processor to manage the virtualization, interrupt, and memory management of the graphics processing engines 1831(1)-1831(N).

[0353] In at least one embodiment, since the hardware resources of the graphics processing engines 1831(1)-1831(N) are explicitly mapped to the real address space seen by the host processor 1807, any host processor can directly address these resources using valid address values. In at least one embodiment, a function of the accelerator integrated circuit 1836 is to physically separate the graphics processing engines 1831(1)-1831(N) so that they appear as independent units to the system.

[0354] In at least one embodiment, one or more graphics memories 1833(1)-1833(M) are coupled to each graphics processing engine 1831(1)-1831(N), and N = M. In at least one embodiment, the graphics memories 1833(1)-1833(M) store instructions and data processed by each graphics processing engine 1831(1)-1831(N). In at least one embodiment, the graphics memories 1833(1)-1833(M) may be volatile memory, such as DRAM (including stacked DRAM), GDDR memory (e.g., GDDR5, GDDR6), or HBM, and / or may be non-volatile memory, such as 3DXPoint or Nano-RAM.

[0355] In at least one embodiment, to reduce data traffic on the high-speed link 1840, a biasing technique can be used to ensure that the data stored in the graphics memory 1833(1)-1833(M) is the data most frequently used by the graphics processing engine 1831(1)-1831(N), and preferably data that the cores 1860A-1860D do not use (or at least do not use frequently). Similarly, in at least one embodiment, the biasing mechanism attempts to keep the data needed by the cores (and preferably not the graphics processing engine 1831(-1)-1831(N)) in the caches 1862A-1862D, the shared cache 1856, and the system memory 1814.

[0356] Figure 18C Another exemplary embodiment is shown, in which the accelerator integrated circuit 1836 is integrated within the processor 1807. In this embodiment, the graphics processing engines 1831(1)-1831(N) communicate directly with the accelerator integrated circuit 1836 via a high-speed link 1840 through interfaces 1837 and 1835 (which may also be any form of bus or interface protocol). In at least one embodiment, the accelerator integrated circuit 1836 can perform operations related to... Figure 18B The described operation is similar. However, due to its close proximity to the coherence bus 1864 and caches 1862A-1862D, and shared cache 1856, it may have higher throughput. In at least one embodiment, the accelerator integrated circuit supports different programming models, including a dedicated process programming model (without graphics acceleration module virtualization) and a shared programming model (with virtualization), which may include a programming model controlled by the accelerator integrated circuit 1836 and a programming model controlled by the graphics acceleration module 1846.

[0357] In at least one embodiment, graphics processing engines 1831(1)-1831(N) are dedicated to a single application or process under a single operating system. In at least one embodiment, a single application can funnel requests from other applications to graphics processing engines 1831(1)-1831(N), thereby providing virtualization within a VM / partition.

[0358] In at least one embodiment, graphics processing engines 1831(1)-1831(N) can be shared by multiple VM / application partitions. In at least one embodiment, the shared model can use a hypervisor to virtualize graphics processing engines 1831(1)-1831(N) to allow each operating system to access them. In at least one embodiment, for a single-partition system without a hypervisor, the operating system owns graphics processing engines 1831(1)-1831(N). In at least one embodiment, the operating system can virtualize graphics processing engines 1831(1)-1831(N) to provide access to each process or application.

[0359] In at least one embodiment, the graphics acceleration module 1846 or the individual graphics processing engine 1831(1)-1831(N) uses a process handle to select a process element. In at least one embodiment, the process element is stored in system memory 1814 and can be addressed using the effective address to real address translation techniques described herein. In at least one embodiment, the process handle may be an implementation-specific value provided to the host process when registering its context with the graphics processing engine 1831(1)-1831(N) (i.e., invoking system software to add the process element to the process element linked list). In at least one embodiment, the lower 16 bits of the process handle may be the offset of the process element in the process element linked list.

[0360] Figure 18DAn exemplary accelerator integration slice 1890 is illustrated. In at least one embodiment, a "slice" includes a designated portion of the processing resources of an accelerator integrated circuit 1836. In at least one embodiment, the application is an effective address space 1882 in system memory 1814, which stores process element 1883. In at least one embodiment, process element 1883 is stored in response to a GPU call 1881 from an application 1880 executing on processor 1807. In at least one embodiment, process element 1883 contains the process state of the corresponding application 1880. In one embodiment, a job descriptor (WD) 1884 contained in process element 1883 may be a single job requested by the application, or it may contain a pointer to a job queue. In at least one embodiment, WD 1884 is a pointer to a job request queue in the effective address space 1882 of the application.

[0361] In at least one embodiment, the graphics acceleration module 1846 and / or the various graphics processing engines 1831(1)-1831(N) may be shared by all processes or a subset of processes in the system. In at least one embodiment, infrastructure may be included for setting process states and sending WD 1884 to the graphics acceleration module 1846 to begin operations in a virtualized environment.

[0362] In at least one embodiment, the dedicated process programming model is implementation-specific. In at least one embodiment, in this model, a single process owns either the graphics acceleration module 1846 or an individual graphics processing engine 1831. In at least one embodiment, when the graphics acceleration module 1846 is owned by a single process, the hypervisor initializes the accelerator integrated circuit for the owned partition, and when the graphics acceleration module 1846 is assigned, the operating system initializes the accelerator integrated circuit 1836 for the owned process.

[0363] In at least one embodiment, during operation, the WD acquisition unit 1891 in the accelerator integration slice 1890 acquires the next WD 1884, which includes instructions for work to be performed by one or more graphics processing engines of the graphics acceleration module 1846. In at least one embodiment, data from the WD 1884 may be stored in register 1845 and used by the MMU 1839, interrupt management circuitry 1847, and / or context management circuitry 1848, as shown. For example, one embodiment of the MMU 1839 includes segment / page roaming circuitry for accessing segment / page tables 1886 within the OS virtual address space 1885. In at least one embodiment, the interrupt management circuitry 1847 may process an interrupt event 1892 received from the graphics acceleration module 1846. In at least one embodiment, when performing graphics operations, a valid address 1893 generated by the graphics processing engines 1831(1)-1831(N) is translated into a real address by the MMU 1839.

[0364] In at least one embodiment, register 1845 is copied for each graphics processing engine 1831(1)-1831(N) and / or graphics acceleration module 1846, and said register 1845 may be initialized by a hypervisor or operating system. In at least one embodiment, each of these copied registers may be included in accelerator integration slice 1890. Exemplary registers that may be initialized by a hypervisor are shown in Table 1.

[0365]

[0366] Table 2 shows exemplary registers that can be initialized by the operating system.

[0367]

[0368] In at least one embodiment, each WD 1884 is specific to a particular graphics acceleration module 1846 and / or graphics processing engine 1831(1)-1831(N). In at least one embodiment, it contains all the information required for the graphics processing engine 1831(1)-1831(N) to complete its work, or it may be a pointer to a memory location where the application has set up a command queue for the work to be completed.

[0369] Figure 18E Additional details of an exemplary embodiment of the shared model are shown. This embodiment includes a hypervisor real address space 1898, in which a list of process elements 1899 is stored. In at least one embodiment, the hypervisor real address space 1898 can be accessed via a hypervisor 1896, which virtualizes the graphics acceleration module engine for operating system 1895.

[0370] In at least one embodiment, the shared programming model allows all processes or subsets of processes from all partitions or subsets of partitions in the system to use the graphics acceleration module 1846. In at least one embodiment, there are two programming models in which the graphics acceleration module 1846 is shared by multiple processes and partitions, namely, time-slice sharing and graphics-oriented sharing.

[0371] In at least one embodiment, in this model, the hypervisor 1896 owns the graphics acceleration module 1846 and makes its functionality available to all operating systems 1895. In at least one embodiment, for the graphics acceleration module 1846 to support virtualization through the hypervisor 1896, the graphics acceleration module 1846 may comply with certain requirements, such as (1) the job requests of the application must be autonomous (i.e., no state needs to be maintained between jobs), or the graphics acceleration module 1846 must provide a context saving and recovery mechanism, (2) the graphics acceleration module 1846 guarantees that the job requests of the application are completed within a specified amount of time, including any conversion errors, or the graphics acceleration module 1846 provides the ability to preempt job processing, and (3) when operating in a directed shared programming model, fairness between the processes of the graphics acceleration module 1846 must be ensured.

[0372] In at least one embodiment, application 1880 needs to make operating system 1895 system calls using the graphics acceleration module type, working descriptor (WD), permission mask register (AMR) value, and context save / restore region pointer (CSRP). In at least one embodiment, the graphics acceleration module type describes the target acceleration function for the system call. In at least one embodiment, the graphics acceleration module type can be a system-specific value. In at least one embodiment, the WD is specifically formatted for graphics acceleration module 1846 and can take the form of graphics acceleration module 1846 commands, valid address pointers to user-defined structures, valid address pointers to command queues, or any other data structure describing the work to be performed by graphics acceleration module 1846.

[0373] In at least one embodiment, the AMR value is the AMR state for the current process. In at least one embodiment, the value passed to the operating system is similar to that of the application that sets the AMR. In at least one embodiment, if the implementation of the accelerator integrated circuit 1836 (not shown) and the graphics acceleration module 1846 does not support the User Rights Mask Overwrite Register (UAMOR), the operating system may apply the current UAMOR value to the AMR value before passing the AMR in the hypervisor call. In at least one embodiment, the hypervisor 1896 may selectively apply the current Rights Mask Overwrite Register (AMOR) value before placing the AMR into the process element 1883. In at least one embodiment, CSRP is one of the registers 1845 containing the effective address of a region in the effective address space 1882 of the application for the graphics acceleration module 1846 to save and restore the context state. In at least one embodiment, this pointer is optional if it is not necessary to save state between jobs or when a job is preempted. In at least one embodiment, the context save / restore region may be fixed system memory.

[0374] Upon receiving a system call, operating system 1895 can verify that application 1880 has been registered and granted permission to use graphics acceleration module 1846. Then, in at least one embodiment, operating system 1895 uses the information shown in Table 3 to invoke hypervisor 1896.

[0375]

[0376] In at least one embodiment, upon receiving a hypervisor call, hypervisor 1896 verifies that operating system 1895 has been registered and granted permission to use graphics acceleration module 1846. Then, in at least one embodiment, hypervisor 1896 adds process element 1883 to a linked list of process elements of the corresponding graphics acceleration module 1846 type. In at least one embodiment, the process element may include the information shown in Table 4.

[0377]

[0378]

[0379] In at least one embodiment, the hypervisor initializes multiple accelerator integration slice 1890 registers 1845.

[0380] like Figure 18FAs shown, in at least one embodiment, a unified memory is used, which is addressable via a common virtual memory address space for accessing physical processor memories 1801(1)-1801(N) and GPU memories 1820(1)-1820(N). In this implementation, operations performed on GPUs 1810(1)-1810(N) utilize the same virtual / effective memory address space to access processor memories 1801(1)-1801(M) and vice versa, thereby simplifying programmability. In at least one embodiment, a first portion of the virtual / effective address space is allocated to processor memory 1801(1), a second portion to second processor memory 1801(N), a third portion to GPU memory 1820(1), and so on. In at least one embodiment, the entire virtual / effective memory space (sometimes referred to as the effective address space) is thus distributed across each of processor memory 1801 and GPU memory 1820, thereby allowing any processor or GPU to access that memory using a virtual address mapped to any physical memory.

[0381] In at least one embodiment, the bias / coherence management circuitry 1894A-1894E within one or more MMUs 1894A-1894E ensures cache coherence between the caches of one or more host processors (e.g., 1805) and the GPU 1810, and implements biasing techniques to indicate the physical memory in which certain types of data should be stored. In at least one embodiment, although in Figure 18F Several instances of bias / coherence management circuits 1894A-1894E are shown, but bias / coherence circuits can be implemented within the MMU of one or more host processors 1805 and / or within the accelerator integrated circuit 1836.

[0382] One embodiment allows GPU memory 1820 to be mapped as part of system memory and accessed using shared virtual memory (SVM) technology without suffering the performance drawbacks associated with full system cache coherence. In at least one embodiment, the ability to access GPU memory 1820 as system memory without the heavy overhead of cache coherence provides a favorable operating environment for GPU offloading. In at least one embodiment, this arrangement allows the host processor 1805 to software-set operands and access computation results without the overhead of conventional I / ODMA data copying. In at least one embodiment, such conventional copying includes driver calls, interrupts, and memory-mapped I / O (MMIO) accesses, all of which are less efficient than simple memory accesses. In at least one embodiment, the ability to access GPU memory 1820 without cache coherence overhead can be critical to the execution time of offloaded computations. In at least one embodiment, for example, in cases with high streaming write memory traffic, cache coherence overhead can significantly reduce the effective write bandwidth seen by GPU 1810. In at least one embodiment, the efficiency of operand setting, the efficiency of result access, and the efficiency of GPU computation can play a role in determining the effectiveness of GPU offloading.

[0383] In at least one embodiment, the selection of GPU bias and host processor bias is driven by a bias tracker data structure. In at least one embodiment, for example, a bias table can be used, which may be a page-granular structure (e.g., controlled at the memory page level) comprising one or two bits of memory pages attached to each GPU. In at least one embodiment, with or without a bias cache (e.g., for caching frequently / recently used entries in the bias table) in GPU 1810, the bias table can be implemented across one or more stolen memory ranges of GPU memory 1820. Alternatively, in at least one embodiment, the entire bias table can be maintained within the GPU.

[0384] In at least one embodiment, prior to actual access to GPU memory, an access to the bias table entry associated with each access to GPU-attached memory 1820 is performed, resulting in the following operations: In at least one embodiment, a local request from GPU 1810 to find its page in the GPU bias is forwarded directly to the corresponding GPU memory 1820. In at least one embodiment, a local request from the GPU to find its page in the host bias is forwarded to processor 1805 (e.g., via the high-speed link described herein). In at least one embodiment, a request from processor 1805 to find the requested page in the host processor bias completes a request similar to a normal memory read. Alternatively, a request for a page pointing to the GPU bias can be forwarded to GPU 1810. In at least one embodiment, if the GPU is not currently using the page, the GPU may subsequently migrate the page to the host processor bias. In at least one embodiment, the page bias state can be changed through a software-based mechanism, a hardware-assisted software mechanism, or, in limited cases, a purely hardware-based mechanism.

[0385] In at least one embodiment, a mechanism for changing the bias state employs an API call (e.g., OpenCL), which subsequently invokes the GPU's device driver. The device driver then sends a message (or enqueues a command descriptor) to the GPU, instructing the GPU to change the bias state and, in some migration, performs a cache refresh operation on the host. In at least one embodiment, the cache refresh operation is used for migration from the host processor 1805 bias to the GPU bias, but not for the reverse migration.

[0386] In at least one embodiment, cache coherence is maintained by temporarily rendering GPU bias pages that the host processor 1805 cannot cache. In at least one embodiment, to access these pages, the processor 1805 may request access from the GPU 1810, which may or may not immediately grant access. Therefore, in at least one embodiment, to reduce communication between the processor 1805 and the GPU 1810, it is beneficial to ensure that the GPU bias pages are pages needed by the GPU, not those needed by the host processor 1805, and vice versa.

[0387] One or more training logic 1015s are used to execute one or more implementations. This document can be combined with... Figure 10A and / or Figure 10B Provide details about one or more training logics 1015.

[0388] Figure 19Exemplary integrated circuits and associated graphics processors according to various embodiments described herein are illustrated, which may be manufactured using one or more IP cores. In addition to the illustrations, at least one embodiment may include other logic and circuitry, including additional graphics processors / cores, peripheral interface controllers, or general-purpose processor cores.

[0389] Figure 19 This is a block diagram illustrating an exemplary system on a chip integrated circuit 1900 that can be fabricated using one or more IP cores according to at least one embodiment. In at least one embodiment, the integrated circuit 1900 includes one or more application processors 1905 (e.g., CPUs), at least one graphics processor 1910, and may additionally include an image processor 1915 and / or a video processor 1920, any of which may be a modular IP core. In at least one embodiment, the integrated circuit 1900 includes peripheral or bus logic, which includes a USB controller 1925, a UART controller 1930, an SPI / SDIO controller 1935, and an I... 2 2S / I 2 2C controller 1940. In at least one embodiment, integrated circuit 1900 may include display device 1945 coupled to one or more of High Definition Multimedia Interface (HDMI) controller 1950 and Mobile Industrial Processor Interface (MIPI) display interface 1955. In at least one embodiment, storage may be provided by flash memory subsystem 1960, including flash memory and flash memory controller. In at least one embodiment, a memory interface may be provided via memory controller 1965 for accessing SDRAM or SRAM memory devices. In at least one embodiment, some integrated circuits also include embedded security engine 1970.

[0390] Inference and / or training logic 1015 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 10A and / or Figure 10B Details regarding inference and / or training logic 1015 are provided. In at least one embodiment, inference and / or training logic 1015 may be used in integrated circuit 1900 to infer or predict operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architecture, or neural network use cases described herein. In various embodiments, inference and / or training logic 1015 utilizes target image data generated by offline image signal processing 240, as described above in conjunction with... Figure 2 As stated above. Furthermore, the above is combined with... Figure 2 The data collection 202 described is performed by vehicle 1300 in various embodiments.

[0391] Figures 20A-20BExemplary integrated circuits and associated graphics processors according to various embodiments described herein are illustrated, which may be manufactured using one or more IP cores. In addition to the illustrations, at least one embodiment may include other logic and circuitry, including additional graphics processors / cores, peripheral interface controllers, or general-purpose processor cores.

[0392] Figures 20A-20B This is a block diagram illustrating an exemplary graphics processor used within a SoC according to embodiments described herein. Figure 20A An exemplary graphics processor 2010 of a system-on-a-chip according to at least one embodiment is shown, which can be manufactured using one or more IP cores. Figure 20B Further exemplary graphics processor 2040 of a system-on-a-chip according to at least one embodiment is shown, which can be manufactured using one or more IP cores. In at least one embodiment, Figure 20A The graphics processor 2010 is a low-power graphics processor core. In at least one embodiment, Figure 20B The graphics processor 2040 is a higher-performance graphics processor core. In at least one embodiment, each graphics processor 2010, 2040 may be... Figure 19 A variant of the 1910 graphics processor.

[0393] In at least one embodiment, the graphics processor 2010 includes a vertex processor 2005 and one or more fragment processors 2015A-2015N (e.g., 2015A, 2015B, 2015C, 2015D to 2015N-1 and 2015N). In at least one embodiment, the graphics processor 2010 may execute different shader programs via separate logic, such that the vertex processor 2005 is optimized to perform operations for the vertex shader program, while one or more fragment processors 2015A-2015N perform fragment (e.g., pixel) shading operations for fragments or pixels or shader programs. In at least one embodiment, the vertex processor 2005 performs the vertex processing stage of the 3D graphics pipeline and generates primitive and vertex data. In at least one embodiment, one or more fragment processors 2015A-2015N use the primitive and vertex data generated by the vertex processor 2005 to generate framebuffers for display on a display device. In at least one embodiment, one or more fragment processors 2015A-2015N are optimized to execute fragment shader programs as provided in the OpenGL API, which can be used to perform operations similar to those of pixel shader programs provided in the Direct 3D API.

[0394] In at least one embodiment, the graphics processor 2010 additionally includes one or more memory management units (MMUs) 2020A-2020B, one or more caches 2025A-2025B, and one or more circuit interconnects 2030A-2030B. In at least one embodiment, the one or more MMUs 2020A-2020B provide a virtual-to-physical address mapping for the graphics processor 2010, including for the vertex processor 2005 and / or fragment processors 2015A-2015N, which can reference vertex or image / texture data stored in memory, in addition to vertex or image / texture data stored in the one or more caches 2025A-2025B. In at least one embodiment, the one or more MMUs 2020A-2020B can be synchronized with other MMUs within the system, including with… Figure 19 One or more application processors 1905, graphics processors 1915, and / or video processors 1920 are associated with one or more MMUs, enabling each processor 1905-1920 to participate in a shared or unified virtual memory system. In at least one embodiment, one or more circuit interconnects 2030A-2030B enable the graphics processor 2010 to connect to other IP cores within the SoC via the SoC's internal bus or via a direct connection.

[0395] In at least one embodiment, the graphics processor 2040 includes one or more shader cores 2055A-2055N (e.g., 2055A, 2055B, 2055C, 2055D, 2055E, 2055F to 2055N-1 and 2055N), such as Figure 20B As shown, it provides a unified shader core architecture, where a single core or type or core can execute all types of programmable shader code, including shader program code for implementing vertex shaders, fragment shaders, and / or compute shaders. In at least one embodiment, the number of shader cores can vary. In at least one embodiment, ...

Claims

1. An image processing method, comprising: Stored sensor data representing a set of scenes captured by the image sensor is obtained using the exposure settings corresponding to the first dynamic range; A set of control points is automatically determined based at least in part on a first image of the sensor data. The set of control points includes a first control point, a second control point, and a third control point. The second control point includes a second hue value between a first hue value of the first control point and a third hue value of the third control point. The gain value is determined at least in part based on at least two selected control points from the set of control points; A curve is calculated using the gain value and the tone mapping function of the image signal processor (ISP), the curve passing through at least the first, second, and third control points, wherein the gain value is used to determine the slope of the curve at the second control point; as well as The ISP applies the curve to at least one different second image of the sensor data to obtain a set of images having one or more pixels in a second dynamic range different from the first dynamic range.

2. The method of claim 1, wherein the capture of the sensor data is decoupled from the ISP.

3. The method of claim 1, wherein the at least two selected control points include the second control point.

4. The method of claim 1, wherein the sensor data includes data generated by the image sensor before being converted into an image format.

5. The method of claim 1, wherein the set of images comprises low dynamic range (SDR) images.

6. The method of claim 1, wherein the sensor data is captured by a camera device mounted on at least one of the following: vehicle; Robot; or Drones.

7. The method of claim 1, wherein the sensor data is captured by a camera device including the image sensor.

8. The method of claim 1, wherein the sensor data is stored in permanent storage.

9. The method of claim 1, further comprising: The model is trained at least in part based on the set of images.

10. The method of claim 9, wherein the model is a neural network.

11. The method of claim 9, further comprising: Obtain the results of the inference operation of the model; as well as The ISP is modified at least in part based on the results.

12. The method of claim 11, wherein modifying the ISP further comprises modifying a set of parameters of the tone mapping function included in the ISP.

13. The method of claim 1, further comprising: The ISP is modified at least in part based on the set of images.

14. The method of claim 1, further comprising: The set of images is fed into a neural network to perform object detection.

15. The method of claim 1, further comprising: The ISP applies a set of image processing algorithms to the different second images, the set of image processing algorithms comprising models executed by one or more arithmetic logic units (ALUs) incorporated into the autonomous vehicle.

16. A processor, comprising: One or more processing units are configured to obtain stored sensor data representing a set of scenes captured by an image sensor using exposure settings corresponding to a first dynamic range; A set of control points is automatically determined, at least in part, based on a first image of the sensor data. This set of control points includes a first control point, a second control point, and a third control point. The second control point includes a second hue value between a first hue value of the first control point and a third hue value of the third control point. A gain value is determined, at least in part, based on at least two selected control points of the set of control points. A curve is calculated using the gain value and a tone mapping function of an image signal processor (ISP). This curve passes through at least the first, second, and third control points, wherein the gain value is used to determine the slope of the curve at the second control point. The ISP then applies the curve to at least one different second image of the sensor data to obtain a set of images within a second dynamic range different from the first dynamic range.

17. The processor of claim 16, wherein the one or more processing units are further configured to train a neural network based at least in part on the set of images.

18. The processor of claim 17, wherein the one or more processing units are further configured to: The results of obtaining the neural network; and At least one parameter of the tone mapping algorithm included in the ISP is adjusted based at least in part on the result, wherein the tone mapping algorithm is used to calculate the curve using the gain value and the tone mapping function.

19. The processor of claim 16, wherein the one or more processing units are further configured to modify at least one parameter of a tone mapping algorithm based at least in part on one of the set of images, wherein the tone mapping algorithm is used to calculate the curve using the gain value and the tone mapping function.

20. The processor of claim 16, wherein the sensor data further includes grating ratio data.

21. The processor of claim 16, wherein the sensor is mounted on the vehicle.

22. The processor of claim 16, wherein the image sensor is incorporated into a camera device mounted on an autonomous vehicle.

23. The processor of claim 16, wherein the ISP is implemented by a computing device in a data center.

24. The processor of claim 16, wherein the ISP is implemented by a graphics processing unit (GPU) acceleration system.

25. The processor of claim 16, wherein the exposure calibration is not modified during the capture of the set of scenes by the image sensor.

26. A non-transitory machine-readable medium having a set of instructions stored thereon, which, when executed by one or more processors, causes the one or more processors to at least: Stored sensor data representing a set of scenes captured by a sensor is obtained using exposure calibration, the sensor data including a first dynamic range associated with the exposure calibration; A set of control points is automatically determined, at least in part, based on a first image of the sensor data. This set of control points includes a first control point, a second control point, and a third control point. The second control point includes a second hue value between a first hue value of the first control point and a third hue value of the third control point. A gain value is determined, at least in part, based on at least two selected control points from the set of control points. A curve is calculated using the gain value and a tone mapping function, the curve passing through at least the first, second, and third control points, wherein the gain value is used to determine the slope of the curve at the second control point. as well as As a result of applying the curve to at least one different second image of the sensor data by the image signal processor (ISP), multiple images are obtained that will be used in the application, the multiple images including one or more pixels in a second dynamic range different from the first dynamic range.

Images