Display panel and display device

Abstract

Embodiments of the present invention provide a display panel and a display device. The display panel includes a display area and a non-display area. The display panel includes a drive circuit and drive signal lines. The drive circuit is located in the non-display area and includes multiple cascaded shift registers. The drive signal lines are used to provide signals to the drive circuit. The drive signal lines include at least one first signal line, and the first signal line is located in the display area. The present invention can reduce the border width of the non-display area.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] With the increasing application of display technology in smart wearables and other portable electronic devices, the design of electronic products is increasingly focused on a smooth user experience and a sensory experience. For example, wide viewing angles, high resolution, narrow bezels, and high screen-to-body ratios have become selling points for various electronic products. Driver circuits and signal lines are located within the display panel's border area, resulting in a wide bezel and limiting its narrowing. Therefore, narrowing the bezel has become a key research issue for major manufacturers. Summary of the Invention

[0003] Embodiments of the present invention provide a display panel and a display device to solve the technical problem of narrowing the frame.

[0004] In a first aspect, an embodiment of the present invention provides a display panel, comprising a display area and a non-display area; the display panel comprises a driving circuit and a driving signal line, wherein the driving circuit is located in the non-display area, the driving circuit comprises a plurality of cascaded shift registers, and the driving signal line is used to provide signals to the driving circuit;

[0005] in,

[0006] The driving signal line includes at least one first signal line, and the first signal line is located in the display area.

[0007] In a second aspect, an embodiment of the present invention further provides another display panel, the display panel including a display area and a non-display area; the display panel including a driving circuit located in the non-display area and a pixel circuit located in the display area;

[0008] The plurality of pixel circuits are arranged in a first direction into pixel circuit rows, the pixel circuit rows including a first pixel circuit row and a second pixel circuit row; in the first direction, the first pixel circuit row and the second pixel circuit row are offset at one end close to the non-display area;

[0009] The driving circuit includes a plurality of cascaded shift registers; the shift registers include a fifth shift register and a sixth shift register; wherein,

[0010] In the first direction, the fifth shift register is adjacent to the first pixel circuit row, the sixth shift register is adjacent to the second pixel circuit row, and the fifth shift register and the sixth shift register are staggered at one end close to the display area.

[0011] In a third aspect, an embodiment of the present invention further provides a display device, comprising any display panel provided by an embodiment of the present invention.

[0012] The display panel and display device provided by the embodiments of the present invention have the following beneficial effects: at least part of the driving signal lines that are originally required to be arranged in the non-display area are arranged in the display area, which can save space in the non-display area and narrow the width of the non-display area. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following is a brief introduction to the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without paying any creative labor.

[0014] Figure 1 A partial schematic diagram of a display panel in the prior art;

[0015] Figure 2 A schematic diagram of a shift register arrangement in the prior art;

[0016] Figure 3 A schematic diagram of a display panel provided by an embodiment of the present invention;

[0017] Figure 4 for Figure 3 An enlarged schematic diagram of the middle area Q1;

[0018] Figure 5 A schematic diagram of a shift register structure provided by an embodiment of the present invention;

[0019] Figure 6 A schematic diagram of another shift register structure provided by an embodiment of the present invention;

[0020] Figure 7 for Figure 3 An enlarged schematic diagram of the position Q2 in the middle area;

[0021] Figure 8 A partial schematic diagram of another display panel provided by an embodiment of the present invention;

[0022] Figure 9 A partial schematic diagram of another display panel provided by an embodiment of the present invention;

[0023] Figure 10 A partial schematic diagram of another display panel provided by an embodiment of the present invention;

[0024] Figure 11 A partial schematic diagram of another display panel provided by an embodiment of the present invention;

[0025] Figure 12A partial schematic diagram of another display panel provided by an embodiment of the present invention;

[0026] Figure 13 A partial schematic diagram of another display panel provided by an embodiment of the present invention;

[0027] Figure 14 A partial schematic diagram of another display panel provided by an embodiment of the present invention;

[0028] Figure 15 A partial schematic diagram of another display panel provided by an embodiment of the present invention;

[0029] Figure 16 A partial schematic diagram of another display panel provided by an embodiment of the present invention;

[0030] Figure 17 A partial schematic diagram of another display panel provided by an embodiment of the present invention;

[0031] Figure 18 A partial schematic diagram of another display panel provided by an embodiment of the present invention;

[0032] Figure 19 A pixel circuit diagram of a display panel provided by an embodiment of the present invention;

[0033] Figure 20 A schematic diagram of another display panel film structure provided by an embodiment of the present invention;

[0034] Figure 21 A partial schematic diagram of another display panel provided by an embodiment of the present invention;

[0035] Figure 22 A partial schematic diagram of another display panel provided by an embodiment of the present invention;

[0036] Figure 23 A partial schematic diagram of another display panel provided by an embodiment of the present invention;

[0037] Figure 24 A partial schematic diagram of another display panel provided by an embodiment of the present invention;

[0038] Figure 25 A partial schematic diagram of another display panel provided by an embodiment of the present invention;

[0039] Figure 26 A partial schematic diagram of another display panel provided by an embodiment of the present invention;

[0040] Figure 27 A partial schematic diagram of another display panel provided by an embodiment of the present invention;

[0041] Figure 28A partial schematic diagram of another display panel provided by an embodiment of the present invention;

[0042] Figure 29 A partial schematic diagram of another display panel provided by an embodiment of the present invention;

[0043] Figure 30 A schematic diagram of a display device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0044] To make the objectives, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.

[0045] The terms used in the embodiments of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The singular forms "a", "an", "the" and "the" used in the embodiments of the present invention and the appended claims are also intended to include plural forms unless the context clearly indicates otherwise.

[0046] Figure 1 FIG. 1 is a partial schematic diagram of a display panel in the prior art. Figure 1 As shown, a cascaded shift register 01 and a plurality of driving signal lines 02 ( Figure 1 The output end of the shift register 01 is connected to the gate line 03 in the display area AA. The display area AA is provided with a pixel circuit ( Figure 1 (not shown) a gate line 03 is coupled to a plurality of pixel circuits. The shift register 01 and the driving signal line 02 provided in the non-display area NA will occupy a large space, thus affecting the narrowing of the non-display area NA.

[0047] In addition, if Figure 1As shown in the figure, the display area AA has an irregular corner G, and the non-display area NA includes a corner non-display area NAG adjacent to the irregular corner G, and a straight-edge non-display area NA1 connected to the corner non-display area NAG. To ensure that the shift register 01 and the drive signal line 02 in the corner non-display area NAG are connected, and to ensure that the shift register 01 and the drive signal line 02 occupy a small space in the corner non-display area NAG, the shift register 01 in the corner non-display area NAG needs to be tilted. That is, the shift register 01 is arranged along the outline of the irregular corner G, and the drive signal line 02 extends along the outer edge of the arranged shift register 01.

[0048] Figure 2 The diagram below shows the arrangement of the shift register in the prior art. Figure 2 As shown, and continue to refer to Figure 1 :

[0049] Figure (1) shows two shift registers 01 aligned in the vertical direction and four drive signal lines 02. The drive signal lines 02 are made of the same film layer, so the four drive signal lines 02 are arranged in sequence. The shift register 01 includes multiple transistors, and the connecting line segments 04 connect the corresponding transistors to the drive signal lines 02. In the physical structure of the display panel, the arrangement of each transistor is fixed, and the connecting line segment 04 is connected to a fixed position in the shift register 01, so the arrangement of multiple connecting line segments 04 is fixed, which requires that the drive signal line 02 located on one side of the shift register 01 has a certain positional relationship with the shift register 01.

[0050] As shown in (2), when the two shift registers 01 are staggered in the longitudinal direction, in order to meet the connection between the drive signal line 02 and the connecting line segment 04, the drive signal line 02 needs to be set as a broken line. As shown in the position of area Q1′, the drive signal line 02 includes a first transition line segment 051. In order to ensure that the first transition line segments 051 in area Q1′ are insulated from each other, it is necessary to increase the longitudinal distance between the two shift registers 01. Comparing (1) and (2), the longitudinal distance between the two shift registers 01 increases from L0 to L1. In the case of limited longitudinal space in the non-display area NA, the longitudinal distance between the two adjacent shift registers 01 becomes larger, resulting in a reduction in the number of shift registers 01 arranged in the longitudinal direction. For the corner non-display area NAG, the number of shift registers 01 that can be set cannot meet the design requirements. Furthermore, when the offset distance Δ1 between the two shift registers 01 is fixed, the more the number of driving signal lines 02 in the region Q1 ′ is, the larger the distance L1 between the two shift registers 01 in the longitudinal direction is.

[0051] Figure (3) is another prior art design. The difference from Figure (2) is that the shape of the transition line segment in region Q2′ in Figure (3) is different. However, since the drive signal line 02 itself has a certain width and there is a certain spacing between adjacent drive signal lines 02, the wiring design of Figure (3) will also increase the longitudinal distance between two adjacent shift registers 01. Comparing (1) and (3), the longitudinal distance between the two shift registers 01 increases from L0 to L2.

[0052] Since there are certain problems with the designs of Figures (2) and (3), the prior art adopts the design of Figure (4), which tilts the shift register 01 in the corner non-display area NAG, and the minimum distance between two adjacent shift registers 01 meets L0. For example, the drive signal line 02 at the position of area Q3′ includes a second transition line segment 052. Comparing (2) and (4), after the shift register 01 is tilted, the spacing between adjacent second transition line segments 052 is greater than the spacing between adjacent first transition line segments 051, which can ensure that the drive signal lines 02 in area Q3′ are insulated from each other and can meet the connection between the connecting line segment 04 and the drive signal line 02. In addition, the shift registers 01 can be arranged closely.

[0053] Figure 1 Adopted Figure 2 In the design (4), the shift register 01 in the corner non-display area NAG is tilted. This arrangement causes misalignment between the shift register 01 in the corner non-display area NAG and its corresponding pixel circuit row. Therefore, when connecting the shift register 01 and its corresponding gate line 03, an oblique pull line 06 is required. The oblique pull line 06 increases the width of the corner non-display area NAG, making the width of the corner non-display area NAG larger than the width of the straight-edge non-display area NA1. This results in inconsistency in the width of the non-display area NA at the corner position and the straight-edge position of the display area AA, affecting the visual effect.

[0054] In order to solve the problems existing in the prior art, an embodiment of the present invention provides a display panel, which designs the area where at least part of the driving signal lines in the display panel are located or the film layer where at least part of the driving signal lines are located, so as to save wiring space in the non-display area and narrow the width of the non-display area.

[0055] In some embodiments, at least part of the driving signal lines are disposed in the display area to save space in the non-display area.

[0056] In one embodiment, Figure 3 A schematic diagram of a display panel provided by an embodiment of the present invention is shown. Figure 4 for Figure 3 An enlarged schematic diagram of the position Q1 in the middle area. Figure 3As shown, the display panel includes a display area AA and a non-display area NA; the non-display area NA surrounds the display area AA. The display area AA has an irregular corner G, which is an unconventional right-angle corner. Figure 3 The non-display area NA further includes a corner non-display area NAG and a straight-edge non-display area NA1 . The corner non-display area NAG is adjacent to the irregular corner G, and the straight-edge non-display area NA1 is connected to the corner non-display area NAG.

[0057] Figure 4 A schematic diagram of the straight edge non-display area NA1 is shown, as shown in FIG. Figure 4 As shown, the display panel includes a driving circuit 10 and a driving signal line 20 . The driving circuit 10 is located in the non-display area NA and includes a plurality of cascaded shift registers 11 . The driving signal line 20 is used to provide signals to the driving circuit 10 . Figure 4 The shift register 11 is only shown in a block diagram. The shift register 11 is any circuit structure that can realize the signal shifting function. The driving signal line 20 corresponding to the shift register 11 in the straight edge non-display area NA1 includes at least one first signal line 21. The first signal line 21 is located in the display area AA. Figure 4 As shown, the display area AA includes pixel circuits 30 and gate lines 40. The gate lines 40 extend along a first direction x. The pixel circuits 30 are arranged in a pixel circuit row in the first direction x. A plurality of pixel circuits 30 arranged in the first direction x are coupled to the gate lines 40. The gate lines 40 are coupled to the output end of the shift register 11.

[0058] Figure 4 In this embodiment, the straight-edge non-display area NA1 extends along a second direction y, which intersects the first direction x. Within the straight-edge non-display area NA1, the shift registers 11 are arranged along the second direction y. The drive signal lines 20 that drive the shift registers 11 extend along the second direction y, and the drive signal lines 20 occupy a certain space within the straight-edge non-display area NA1. In this embodiment of the present invention, the drive signal lines 20 include a first signal line 21, which is located in the display area AA. Replacing at least a portion of the drive signal lines 20 that would otherwise be located in the straight-edge non-display area NA1 in the display area AA can save wiring space within the straight-edge non-display area NA1 and narrow the width of the straight-edge non-display area NA1.

[0059] Figure 4 The region Q1 shown in FIG. 1 is located at the left side frame of the display panel. Optionally, the right side frame of the display panel adopts the same design as that of region Q1. When the drive circuit 10 is disposed in the non-display area NA on both the left and right sides of the display area AA, the same design as that of region Q1 can be adopted at both the left and right sides of the display area AA.

[0060] Figure 5 A schematic diagram of a shift register structure provided by an embodiment of the present invention is shown in FIG. Figure 5 As shown, the shift register 11 includes eight transistors, M1 to M8, and also includes a first capacitor C1 and a second capacitor C2, as well as a first node N1 and a second node N2. The control electrode of the first transistor M1 is coupled to the first node N1, the first electrode of the first transistor M1 is coupled to the first clock signal line CK1, and the second electrode of the first transistor M1 is coupled to the output terminal OUT of the shift register. The control electrode of the second transistor M2 is coupled to the second node N2, the first electrode of the second transistor M2 is coupled to the first power signal line VGH, and the second electrode of the second transistor M2 is coupled to the output terminal OUT of the shift register. Furthermore, the control electrode of the third transistor M3, the control electrode of the fourth transistor M4, and one electrode of the eighth transistor M8 are connected to the second clock signal line CK2, and the first electrode of the third transistor M3 is coupled to the input terminal IN of the shift register. The first electrode of the fourth transistor M4 and the control electrode of the fifth transistor M5 are coupled to the second power signal line VGL. The control electrode of the sixth transistor M6 is coupled to the first clock signal line CK1. In the display panel, shift registers are cascaded, with the input terminal IN of the first-stage shift register connected to the start signal line, and the input terminal IN of the m-th-stage shift register connected to the output terminal OUT of the m-1-th-stage shift register, where m is an integer greater than or equal to 2. The drive signal lines 20 for driving the shift registers include a start signal line, a first clock signal line CK1, a second clock signal line CK2, a first power signal line VGH, and a second power signal line VGL.

[0061] In another embodiment, Figure 6 Another structural diagram of a shift register provided by an embodiment of the present invention is shown in FIG. Figure 6As shown, the shift register includes eleven transistors, M1 to M11, and further includes a first capacitor C1, a second capacitor C2, a third capacitor C3, a fourth capacitor C4, and a first node N1 and a second node N2. The control electrode of the first transistor M1 is coupled to the first node N1, the first electrode of the first transistor M1 is coupled to the second power signal line VGL, the control electrode of the second transistor M2 is coupled to the second node N2, the first electrode of the second transistor M2 is coupled to the first power signal line VGH, and the second electrode of the first transistor M1 and the second electrode of the second transistor M2 are both coupled to the output terminal OUT of the shift register. The control electrode of the sixth transistor M6, the control electrode of the tenth transistor M10, the first electrode of the ninth transistor M9, and one plate of the first capacitor C1 are all connected to the first clock signal line CK1. The control electrode of the third transistor M3, the control electrode of the fourth transistor M4, the control electrode of the fifth transistor M5, and the first electrode of the eighth transistor M8 are all coupled to the second clock signal line CK2. The first electrode of the third transistor M3 and the first electrode of the fifth transistor M5 are coupled to the input terminal IN of the shift register, and the first electrode of the fourth transistor M4 is coupled to the second power signal line VGL. In the display panel, the shift registers are cascaded, with the input terminal IN of the first-stage shift register connected to the start signal line, and the input terminal IN of the m-th stage shift register is connected to the output terminal OUT of the m-1-th stage shift register. In this embodiment, the drive signal lines 20 for driving the shift register include the start signal line, the first clock signal line CK1, the second clock signal line CK2, the first power signal line VGH, and the second power signal line VGL.

[0062] Figure 5 and Figure 6 In the figure, only the structure of the shift register is given as an example to illustrate the driving signal line 20 in the embodiment of the present invention. In the embodiment of the present invention, the driving signal line includes at least a start signal line, a clock signal line, and a power signal line. The start signal line is electrically connected to the first-stage shift register 11 in the driving circuit 10, and the start signal line provides a start signal for the driving circuit 10. The clock signal line includes a first clock signal line CK1 and a second clock signal line CK2, and the clock signal line provides a periodic pulse signal. The power signal line includes a first power signal line and a second power signal line, and the first power signal line and the second power signal line both provide constant voltage signals, and the voltage value of the voltage signal provided by the first power signal line is greater than the voltage value of the voltage signal provided by the second power signal line. Optionally, the first power signal line VGH is a positive power signal line, and the second power signal line VGL is a negative power signal line.

[0063] Figure 4In the illustrated embodiment, a first signal line 21 among the drive signal lines 20 is located in the display area AA, wherein the first signal line 21 includes any one of a start signal line, a clock signal line, and a power signal line. In some embodiments, the first signal line 21 includes a clock signal line, and two clock signal lines among the drive signal lines 20 are located in the display area AA. In other embodiments, the first signal line 21 includes a power signal line, and two power signal lines among the drive signal lines 20 are located in the display area AA. In other embodiments, the start signal line, the clock signal line, and the power signal line among the drive signal lines 20 are all located in the display area AA.

[0064] Figure 7 for Figure 3 An enlarged schematic diagram of the Q2 position in the middle area, Figure 7 A schematic diagram of the corner non-display area NAG is shown, as shown in FIG. Figure 7 As shown, a shift register 11 is disposed within the corner non-display area NAG. The drive signal lines 20 corresponding to the shift register 11 within the corner non-display area NAG include at least one first signal line 21. The first signal line 21 is located in the display area AA. By disposing at least some of the drive signal lines 20 that would otherwise be disposed in the corner non-display area NAG within the display area AA, space can be saved in the corner non-display area NAG, the width of the corner non-display area NAG can be narrowed, and the width difference between the straight-edge non-display area NA1 and the corner non-display area NAG can be reduced.

[0065] In the display area AA, the pixel circuits 30 are arranged into pixel circuit rows in the first direction x, and the pixel circuits 30 are arranged into pixel circuit columns in the second direction y. Figure 7 In the embodiment, portions of the plurality of first signal lines 21 extending in the second direction y within the display area AA are shown to overlap with one pixel circuit column. In other embodiments, portions of the plurality of first signal lines 21 extending in the second direction y overlap with two pixel circuit columns. In still other embodiments, portions of the plurality of first signal lines 21 extending in the second direction y each overlap with one pixel circuit column.

[0066] Figure 7 The region Q2 shown in FIG. 1 is located at the lower left corner of the display panel. Optionally, the lower left corner of the display panel adopts the same design as that of region Q2. When the driving circuit 10 is provided at both the left and right corners of the display area AA, the same design as that of region Q2 can be adopted at both the left and right corners of the display area AA.

[0067] In some embodiments, the display panel includes a first connection line, and at least one shift register 11 is coupled to a first signal line 21 via the first connection line, wherein the first connection line extends from the non-display area NA to the display area AA. The first connection line is used to provide an electrical signal transmitted by the first signal line 21 to the corresponding shift register 11 to drive the shift register 11. When the first signal line 21 includes a start signal line, the first-stage shift register in the driving circuit 10 is coupled to the first signal line 21 via the first connection line. When the first signal line 21 includes a clock signal line and / or a power signal line, the shift register 11 in the driving circuit 10 is directly or indirectly coupled to the first signal line 21 via the first connection line.

[0068] In one embodiment, Figure 8 A partial schematic diagram of another display panel provided by an embodiment of the present invention, Figure 8 The diagram shows a portion of the display area AA and a non-display area NA adjacent to the display area AA. Figure 8 As shown, in the second direction y, the display area AA has two irregular corners G, the corner non-display area NAG is adjacent to the irregular corner G, and a straight-edge non-display area NA1 is provided between the two corner non-display areas NAG. Shift registers 11 are provided in both the corner non-display area NAG and the straight-edge non-display area NA1. The first signal line 21 is located in the display area AA, and the first signal line 21 includes a start signal line STV. The first-stage shift register 11_1 of the cascaded multiple shift registers 11 is located in a corner non-display area NAG, wherein the first-stage shift register 11_1 is connected to the first signal line 21 via a first connecting line 31. It can be seen that the first connecting line 31 extends from the non-display area NA to the display area AA. The display area AA includes a plurality of gate lines ( Figure 8 (not shown), the routing direction of the first signal line 21 is the second direction y. The first signal line 21 can be any one of a straight line, a broken line, and a curve. Figure 8 The first signal line 21 is merely illustrated as a straight line and is not intended to limit the present invention.

[0069] In another embodiment, Figure 9 Another partial schematic diagram of a display panel provided by an embodiment of the present invention. Taking the corner position of the display panel as an example, Figure 9 As shown, at least part of the shift register 11 in the corner non-display area NAG is coupled to the first signal line 21 through the first connection line 31. The first connection line 31 extends from the non-display area NA to the display area AA. To illustrate the connection relationship between the first connection line 31 and the first signal line 21, Figure 9The gate lines extending along the first direction x in the display area AA are not shown. In the embodiment of the present invention, at least part of the drive signal lines 20 that are originally required to be arranged in the corner non-display area NAG are arranged in the display area AA, and the electrical connection between the shift register 11 and the drive signal lines 20 (i.e., the first signal lines 21) in the display area AA is achieved through the first connecting lines 31. The design of the embodiment of the present invention reduces the number of drive signal lines 20 arranged in the corner non-display area NAG. Figure 1 and Figure 2 When a portion of the driving signal line 20 is retained in the corner non-display area NAG, the second direction y (relative to the Figure 2 When the shift registers 11 that are staggered in the longitudinal direction (as mentioned in the preceding text) are all placed upright, the design of the embodiment of the present invention can reduce the spacing distance between two adjacent shift registers 11 in the second direction y compared to the prior art. When the drive signal lines 20 originally set in the corner non-display area NAG are all set in the display area AA, and the shift registers 11 in the corner non-display area NAG are placed upright, the spacing distance between two adjacent shift registers 11 in the corner non-display area NAG in the second direction y can be made substantially the same as the spacing distance between two adjacent shift registers 11 in the straight-edge non-display area NA1 in the second direction y. With the design of the embodiment of the present invention, in the corner non-display area NAG, it is no longer necessary to tilt the shift register 11 for electrical connection between the shift register 11 and the drive signal line 20, which is conducive to placing the shift register 11 upright, and can reduce the spacing distance between adjacent upright shift registers 11 in the second direction y, which is conducive to aligning the shift register 11 with the corresponding pixel circuit row. In the embodiment of the present invention, it is also not necessary to set the shift register 11 when connecting it to the selection line in the display area AA. Figure 1 The diagonal pull lines 06 shown save space within the corner non-display area NAG, reducing the distance between the shift register 11 and the display area AA within the corner non-display area NAG, thereby reducing the border width of the corner non-display area NAG. This reduces the difference in width between the corner non-display area NAG and the straight-edge non-display area NA1, improving the visual quality of the display.

[0070] Figure 9 In this embodiment, four first signal lines 21 are provided within the display area AA, and one drive signal line 20 is provided within the corner non-display area NAG. The drive signal line 20 within the corner non-display area NAG is the starting signal line. The first signal lines 21 within the display area AA include two clock signal lines and two power signal lines. In other words, the shift register 11 within the corner non-display area NAG is connected to the clock signal lines and power signal lines within the display area AA via first connection lines 31.

[0071] In another embodiment, Figure 10 A partial schematic diagram of another display panel provided by an embodiment of the present invention, such as Figure 10 As shown, at the corner of the display panel, five first signal lines 21 are disposed in the display area AA at the location of the irregular corner G. In other words, the drive signal lines 20 that would otherwise be disposed in the corner non-display area NAG are all disposed in the display area AA, and electrical connections are established between the shift register 11 and the corresponding first signal lines 21 via first connecting lines 31. Not disposing drive signal lines 20 in the corner non-display area NAG saves wiring space in the corner non-display area NAG. Furthermore, this embodiment reduces the distance between the shift register 11 in the corner non-display area NAG and the display area AA, thereby reducing the border width of the corner non-display area NAG and thereby minimizing the difference in width between the corner non-display area NAG and the straight-edge non-display area NA1.

[0072] In addition, if Figure 10 As shown, the first signal line 21 includes a starting signal line STV, which is the first signal line 21 that is farthest from the irregular corner G. When the first connecting line 31 extends from the position where it is connected to the first signal line 21 to the corner non-display area NAG, it will not overlap with the starting signal line STV, that is, the number of signal lines overlapping with the first connecting line 31 is reduced, thereby reducing the coupling capacitance generated by the overlapping signal lines.

[0073] In some embodiments, the driving signal lines 20 include a start signal line, a clock signal line, and a power signal line. The first signal lines 21 in the display area AA include at least one power signal line. The shift register 11 in the corner non-display area NAG is connected to the power signal lines in the display area AA via first connection lines 31.

[0074] In other embodiments, the first signal line 21 in the display area AA includes at least one clock signal line, and the shift register 11 in the corner non-display area NAG is connected to the clock signal line in the display area AA via a first connection line 31. This is not illustrated in the figure.

[0075] In one embodiment, Figure 11 A partial schematic diagram of another display panel provided by an embodiment of the present invention is shown in FIG. Figure 11As shown, the corner non-display area NAG is connected to the straight-edge non-display area NA1 extending in the second direction y; the shift register 11 includes a first shift register 11a and a second shift register 11b, the first shift register 11a is located in the straight-edge non-display area NA1, and the second shift register 11b is located in the corner non-display area NAG; the first shift register 11a and the second shift register 11b are named according to their positions in the non-display area. In fact, multiple shift registers 11 in the driving circuit 10 are arranged in sequence and cascaded in the non-display area NA. That is, the first shift register 11a and the second shift register 11b are cascaded at the junction of the straight-edge non-display area NA1 and the corner non-display area NAG. The shift register 11 includes multiple transistors; the shift register 11 can be the above-mentioned Figure 5 or Figure 6 The schematic structure, or the shift register 11 is other circuit structures capable of realizing the signal shifting function.

[0076] In the embodiment of the present invention, the channels of the transistors with the same functions in the first shift register 11a and the second shift register 11b extend in the same direction, so that the arrangement of the transistors in the first shift register 11a and the second shift register 11b is the same. Therefore, the second shift register 11b is positioned upright relative to the first shift register 11a. In the corner non-display area NAG, the second shift register 11b is not arranged tilted to accommodate the irregular corner G. Such an arrangement can align the second shift register 11b with the corresponding pixel circuit row, and the connection between the second shift register 11b and the corresponding gate line is more convenient, and there is no need to set such a configuration in the corner non-display area NAG. Figure 1 The oblique lines in the corner non-display area NAG are drawn, thereby saving wiring space in the corner non-display area NAG and narrowing the border of the corner non-display area NAG.

[0077] In some embodiments, as Figure 11 As shown, the first shift register 11a and the second shift register 11b are both shown in block diagrams. It can be seen that the outer contours of the first shift register 11a and the second shift register 11b are the same. The edge of the shift register 11 is understood to be the outer contour edge of the graphic shape shared by multiple transistors in the shift register 11. Among them, on the side close to the display area AA, the extension direction of the edge of the first shift register 11a is the same as the extension direction of the edge of the second shift register 11b. Figure 11As shown in the figure, the edges of the shift registers 11 in the two regions near the display area AA are extended along the second direction y. Therefore, the edge of the second shift register 11b near the display area AA is not configured to adapt to the shape of the irregular corner G, that is, the second shift register 11b does not need to be tilted relative to the first shift register 11a. This configuration can align the second shift register 11b with the corresponding pixel circuit row, and the connection between the second shift register 11b and the corresponding gate line is more convenient, without the need to set the corner non-display area NAG as shown in the figure. Figure 1 The oblique lines in the corner non-display area NAG are drawn, thereby saving wiring space in the corner non-display area NAG and narrowing the border of the corner non-display area NAG.

[0078] In some embodiments, Figure 12 A partial schematic diagram of another display panel provided by an embodiment of the present invention, Figure 12 In order to clearly illustrate the position and connection relationship of each structure, Figure 12 Only two first signal lines 21 located in the display area AA are shown. Figure 12 As shown, multiple pixel circuits 30 are arranged in a pixel circuit row 30H in a first direction x; multiple pixel circuits 30 in a pixel circuit row 30H are coupled to the same gate line 40. The output end of the shift register 11 is coupled to the gate line 40. In the first direction x, the shift register 11 and the pixel circuit row 30H in the corner non-display area NAG are aligned. Figure 12 In the figure, the second shift register 11b is provided in the corner non-display area NAG, and the second shift register 11b is aligned with the pixel circuit row 30H. Then, the misalignment distance between the second shift register 11b and the gate line 40 to be coupled thereto in the first direction x is small or substantially non-misaligned. Figure 12 As shown in the middle area Q3, the connection lead from the output end of the second shift register 11b extends from the corner non-display area NAG to the display area AA and is connected to the gate line 40 in the display area AA. Figure 1 The oblique wiring in the corner non-display area NAG can save wiring space and reduce the width of the corner non-display area NAG.

[0079] in addition, Figure 12 As shown in the middle area Q3, the connection lead extending from the output end of the second shift register 11b is a straight line. The connection lead at this position may also be a broken line or a curve.

[0080] like Figure 12As shown, the shift register 11 includes a first shift register 11a, and the first shift register 11a is located in the straight-edge non-display area NA1. In the first direction x, the distance between the first shift register 11a and the pixel circuit row 30H is a first distance d1, and the distance between the second shift register 11b and the pixel circuit row 30H is a second distance d2, and the first distance d1 and the second distance d2 are equal. Among them, the distance between the shift register 11 and the pixel circuit row 30H in the first direction x is understood to be: the distance between the edge of the shift register 11 and the edge of the first pixel circuit in the pixel circuit row 30H in the first direction x. As Figure 12 As shown, within the straight-edge non-display area NA1, the first shift registers 11a are arranged along the second direction y, with adjacent first shift registers 11a substantially aligned in the second direction y. The distances between each first shift register 11a and the pixel circuit rows 30H are substantially equal. At the corners of the display panel, at least some adjacent pixel circuit rows 30H arranged within the display area AA are staggered to form a special-shaped corner G in the display area AA. Setting d1 = d2 can reduce the border width of the corner non-display area NAG, minimizing the difference between the border width of the corner non-display area NAG and the border width of the straight-edge non-display area NA1, thereby improving the visual quality of the display.

[0081] In the embodiment of the present invention, at least part of the driving signal lines 20 that were originally required to be arranged in the corner non-display area NAG are arranged in the display area AA, and the connection between the driving signal lines 20 located in the display area AA and the second shift register 11b is realized through the first connecting line 31. This arrangement can align the second shift register 11b and the pixel circuit row 30H, reduce the distance between the second shift register 11b and the pixel circuit row 30H, and thus achieve d1=d2.

[0082] In some embodiments, as Figure 12As shown, the drive signal lines 20 also include a second signal line 22 located in the non-display area NA. The second signal line 22 and the first signal line 21 are coupled via a lead 50; the lead 50 extends from the non-display area NA to the display area AA. The second signal line 22 extends within the straight-edge non-display area NA1 and terminates at the boundary between the straight-edge non-display area NA1 and the corner non-display area NAG. The first shift register 11a within the straight-edge non-display area NA1 is correspondingly coupled to the second signal line 22. In this embodiment, at least a portion of the drive signal lines 20, which would otherwise be located within the corner non-display area NAG, is located within the display area AA. Connections between the drive signal lines 20 located in the display area AA and the second shift register 11b are established via first connecting lines 31. The first shift register 11a no longer needs to be tilted within the corner non-display area NAG to ensure electrical connection between the first shift register 11a and the drive signal lines 20, facilitating alignment of the first shift register 11a with the corresponding pixel circuit row. Furthermore, when the first shift register 11a is connected to the gate line 40 in the display area AA, it is not necessary to set Figure 1 The diagonal pull lines 06 shown save space within the corner non-display area NAG, reducing the distance between the shift register 11 within the corner non-display area NAG and the display area AA, thereby reducing the border width of the corner non-display area NAG. This reduces the difference in width between the corner non-display area NAG and the straight-edge non-display area NA1, improving the visual quality of the display. Furthermore, a second signal line 22 is provided within the straight-edge non-display area NA1. The second signal line 22 is coupled to the first signal line 21, providing a drive signal to the first shift register 11a within the straight-edge non-display area NA1 via the second signal line 22. This maintains the existing wiring pattern of the drive signal lines 20 within the straight-edge non-display area NA1. Optionally, a lead 50 is located between two adjacent shift register stages 11 to prevent overlap and signal coupling between the lead 50 and the shift register 11.

[0083] In one embodiment, Figure 13 A partial schematic diagram of another display panel provided by an embodiment of the present invention, Figure 13 In the figure, two first signal lines 21 are provided in the display area AA for illustration. Figure 13 As shown, the corner non-display area NAG includes a driving signal line segment 20d extending along the second direction y, and the driving signal line segment 20d is coupled to the first signal line 21 via a first connecting line 31. In the corner non-display area NAG, at least two shift registers 11 adjacent to and aligned with each other in the second direction y are both coupled to the driving signal line segment 20d. Figure 13The figure shows the n-th shift register 11_n, the n+1-th shift register 11_n+1, and the n+2-th shift register 11_n+2, which are cascaded in sequence. n is a positive integer. The n-th shift register 11_n and the n+1-th shift register 11_n+1 are aligned with each other in the second direction y, and the n+1-th shift register 11_n+1 and the n+2-th shift register 11_n+2 are staggered in the second direction y. The staggered arrangement of two adjacent shift registers 11 in the second direction y means that the same edges of the two shift registers 11 arranged along the second direction y have a staggered spacing in the first direction x. Figure 13 As shown, the edges of the n+1th stage shift register 11_n+1 and the n+2th stage shift register 11_n+2, away from the display area AA, are offset by a distance Δ in the first direction x. In this embodiment, the extension direction of the drive signal line segment 20d is arranged in the same direction as the arrangement direction of the adjacent and aligned shift registers 11. Utilizing the drive signal line segment 20d to connect to the first signal line 21 in the display area AA can reduce the number of first connecting lines 31, the number of wiring lines within the display area AA, and the number of vias connecting the first connecting line 31 to the first signal line 21.

[0084] Furthermore, the driving signal line segment 20d is only arranged on one side of the aligned and adjacent shift registers 11, and has no influence on the arrangement of the two shift registers 11 that are staggered in the second direction y. Figure 13 The n+1th-level shift register 11_n+1 and the n+2th-level shift register 11_n+2 are shown in the figure. The n+2th-level shift register 11_n+2 is connected to the first signal line 21 through the first connecting line 31. The n+2th-level shift register 11_n+2 does not need to be tilted relative to the n+1th-level shift register 11_n+1. The n+2th-level shift register 11_n+2 can be aligned with the pixel circuit row. When the n+2th-level shift register 11_n+2 is connected to the selection line, there is no need to set an oblique pull line, thereby reducing the wiring space of the corner non-display area NAG.

[0085] by Figure 5 Taking the illustrated shift register as an example, the shift register includes an output module 111 and a switch module 112. The output module 111 of the shift register includes an output terminal OUT, which is coupled to a gate line. In the display panel, the output module 111 is located on the side of the switch module 112 that is closer to the display area AA, or the output module 111 is located on the side of the switch module 112 that is farther from the display area AA. The position of the drive signal line segment 20d can be designed based on the relative positions of the output module 111 and the switch module 112.

[0086] In one embodiment, if Figure 13As shown, the drive signal line segment 20d is located on the side of the shift register 11 away from the display area AA, which can reduce the distance between the shift register 11 and the display area AA. This can also reduce the distance between the output terminal OUT of the shift register 11 and the display area AA, thereby reducing the length of the connecting lead between the output terminal OUT of the shift register 11 and the gate line in the display area AA. In addition, the output module 111 of the shift register 11 can be further arranged to be located on the side of the switch module 112 closer to the display area AA. Compared with the output module 111, the switch module 112 is closer to the drive signal line segment 20d. This arrangement facilitates the connection between the shift register 11 and the drive signal line segment 20d. Moreover, the output terminal OUT of the shift register 11 is close to the display area AA, which can further reduce the length of the connecting lead between the output terminal OUT of the shift register 11 and the gate line 40 in the display area AA. Moreover, the connecting lead between the two does not need to overlap with the drive signal line segment 20d, which can reduce the parasitic capacitance on the connecting lead.

[0087] In another embodiment, Figure 14 A partial schematic diagram of another display panel provided by an embodiment of the present invention, such as Figure 14 As shown, the drive signal line segment 20d is located on the side of the shift register 11 close to the display area AA, which can shorten the length of the first connection line 31 connecting the drive signal line segment 20d and the first signal line 31. The first connection line 31 does not need to overlap with the n-th stage shift register 11_n, which can reduce the voltage drop, and can also reduce the parasitic capacitance generated by the overlap and reduce signal interference. Furthermore, the output module 111 in the shift register 11 is set to be located on the side of the switch module 112 away from the display area AA. Compared with the output module 111, the switch module 112 is closer to the drive signal line segment 20d, which facilitates the connection between the shift register 11 and the drive signal line segment 20d. Moreover, in this embodiment, the output module 111 in the shift register 11 is located on the side of the switch module 112 away from the display area AA, which can reduce the influence of the operating temperature of the display area AA on the transistors in the output module 111, and avoid the threshold voltage of the transistors in the output module 111 from shifting.

[0088] In another embodiment, Figure 15 A partial schematic diagram of another display panel provided by an embodiment of the present invention, Figure 15 The position of the straight-edge non-display area NA1 of the display panel is shown. Figure 15As shown, the shift register 11 includes a first shift register 11a, which is located in the straight-edge non-display area NA1. At least a portion of the first shift register 11a in the straight-edge non-display area NA1 is coupled to the first signal line 21 via a first connecting line 31. At least a portion of the drive signal lines 20 that originally needed to be set in the straight-edge non-display area NA1 is set in the display area AA, and the first connecting line 31 is used to achieve electrical connection between the first shift register 11a and the drive signal lines 20 in the display area AA. This can save space in the straight-edge non-display area NA1 and narrow the width of the straight-edge non-display area NA1. In this embodiment, the first signal line 21 is at least one clock signal line and / or at least one power signal line among the drive signal lines 20.

[0089] In another embodiment, Figure 16 A partial schematic diagram of another display panel provided by an embodiment of the present invention, such as Figure 16 As shown, the drive signal line 20 includes a first signal line 21 located in the display area AA. At least a portion of the first shift register 11a in the straight-edge non-display area NA1 is coupled to the first signal line 21 via a first connection line 31. At least a portion of the second shift register 11b in the corner non-display area NAG is coupled to the first signal line 21 via a first connection line 31. The first signal line 21 extends within the display area AA adjacent to the corner non-display area NAG and also extends into the display area AA adjacent to the straight-edge non-display area NA1. This embodiment can reduce the width of both the straight-edge non-display area NA1 and the corner non-display area NAG.

[0090] In another embodiment, Figure 17 A partial schematic diagram of another display panel provided by an embodiment of the present invention, such as Figure 17 As shown, the shift register 11 includes a third shift register 11c and a fourth shift register 11d. The third shift register 11c is coupled to the first signal line 21 via a first connection line 31. The corner non-display area NAG includes a second connection line 32, and the fourth shift register 11d is coupled to the first connection line 31 via the second connection line 32. The fourth shift register 11d does not require a first connection line 31, which reduces the number of first connection lines 31, the number of wiring lines within the display area AA, and the number of vias connecting the first connection line 31 to the first signal line 21.

[0091] like Figure 17 As shown, in the second direction y, the third shift register 11c and the fourth shift register 11d are aligned, and the second direction y is the arrangement direction of the third shift register 11c and the fourth shift register 11d, so that the length of the second connecting line 32 is relatively short. Optionally, the third shift register 11c and the fourth shift register 11d are adjacent.

[0092] Figure 17 In this embodiment, the corner non-display area NAG includes a third shift register 11c and a fourth shift register 11d. In another embodiment, the straight-edge non-display area NA1 includes a third shift register 11c and a fourth shift register 11d, with the third shift register 11c coupled to the first signal line 21 via a first connection line 31. The straight-edge non-display area NA1 includes a second connection line 32, and the fourth shift register 11d is coupled to the first connection line 31 via the second connection line 32. The third shift register 11c and the fourth shift register 11d are aligned in the second direction y. This is not further illustrated in the figures.

[0093] In another embodiment, Figure 18 A partial schematic diagram of another display panel provided by an embodiment of the present invention, such as Figure 18 As shown, the corner non-display area NAG includes a third shift register 11c and a fourth shift register 11d. In the second direction y, the third shift register 11c and the fourth shift register 11d are staggered. The second direction y is the arrangement direction of the third shift register 11c and the fourth shift register 11d.

[0094] In another embodiment, the straight-edge non-display area NA1 includes a third shift register 11c, and the corner non-display area NAG includes a fourth shift register 11d. In the second direction y, the third shift register 11c and the fourth shift register 11d are staggered. The third shift register 11c is coupled to the first signal line 21 via a first connection line 31, and the fourth shift register 11d is coupled to the first connection line 31 via a second connection line 32. This is not further illustrated in the figures.

[0095] In one embodiment, Figure 19 A pixel circuit diagram of a display panel provided by an embodiment of the present invention. Figure 19 As shown, the pixel circuit includes a drive transistor Tm, a gate reset transistor T1, an electrode reset transistor T2, a data write transistor T3, a threshold compensation transistor T4, a first emission control transistor T5, a second emission control transistor T6, and a storage capacitor Cst. The display panel is provided with scan lines (a first scan line Sc1 and a second scan line Sc2), a reset signal line Ref, a positive power supply voltage signal line Pvdd, a negative power supply voltage signal line Pvee, an emission control line E, and a data line Vdata. The first electrode of the light-emitting device P is electrically connected to the pixel circuit, and the second electrode of the light-emitting device P is electrically connected to the negative power supply voltage signal line Pvee.

[0096] Figure 19The data write transistor T3 and the threshold compensation transistor T4 are both connected to the first scan line Sc1. In another embodiment, the data write transistor T3 and the threshold compensation transistor T4 are connected to different scan lines. Optionally, the data write transistor T3 is a silicon transistor, and the threshold compensation transistor T4 is a metal oxide transistor. The data write transistor T3 is a p-type transistor, and the threshold compensation transistor T4 is an n-type transistor.

[0097] In another embodiment, the gate reset transistor T1 and the electrode reset transistor T2 are connected to different scan lines. Optionally, the gate reset transistor T1 is a silicon transistor, and the gate reset transistor T1 is an n-type transistor.

[0098] Figure 19 A 7T1C pixel circuit is used as an example. 7T1C refers to 7 transistors and 1 capacitor. In the embodiment of the present invention, the pixel circuit is aTbC, where a and b are positive integers. The pixel circuit can also be a 2T1C, 8T1C, or 8T2C pixel circuit.

[0099] Figure 20 A schematic diagram of another display panel film structure provided by an embodiment of the present invention is shown in FIG. Figure 20 As shown, the display panel includes a substrate 010 and a semiconductor layer 011 , a first metal layer 012 , a capacitor metal layer 013 , a second metal layer 014 , a third metal layer 015 and a fourth metal layer 016 located on one side of the substrate 010 . Figure 20 Only one transistor in each of the shift register 11 and the pixel circuit 30 is shown, wherein the active layer of the transistor is located in the semiconductor layer 011, and the gate of the transistor is located in the first metal layer 012. The pixel circuit 30 includes a storage capacitor CST, wherein the first plate of the storage capacitor CST is located in the capacitor metal layer 012, and the second plate of the storage capacitor CST is located in the first metal layer 012. Optionally, the first metal layer 012 and the capacitor metal layer 013 are made of the same material, and the second metal layer 014, the third metal layer 015, and the fourth metal layer 016 are made of the same material.

[0100] In one embodiment, the first scan line Sc1, the second scan line Sc2 and the light emitting control line E are located in the first metal layer 012, the reset signal line Ref is located in the capacitor metal layer 013, the positive power supply voltage signal line Pvdd is located in the second metal layer 014, and the data line Vdata is located in the third metal layer 015.

[0101] Depend on Figure 19 It can be seen that the first plate of the storage capacitor Cst is electrically connected to the positive power supply voltage signal line Pvdd. Figure 20The diagram shows the positive power supply voltage signal line Pvdd located in the second metal layer 014 and the functional power supply line Pvdd` located in the third metal layer 015. The functional power supply line Pvdd` is connected in parallel with the positive power supply voltage signal line Pvdd. The functional power supply line Pvdd` is used to reduce the voltage drop of the transmitted positive power supply voltage signal and improve the uniformity of the entire surface.

[0102] In an embodiment of the present invention, the first signal line 21 and the first connecting line 31 are located in different film layers, wherein the first signal line 21 is located in the fourth metal layer 016, and the first connecting line 31 is located in the third metal layer 015. The first connecting line 31 and the first signal line 21 are electrically connected in the display area AA through a via penetrating the insulating layer.

[0103] In the embodiment of the present invention, the second connection line 32 is located in the fourth metal layer 016, the second connection line 32 and the first signal line 21 are located in the same film layer, and the second connection line 32 and the first connection line 31 are located in different layers. Figure 17 or Figure 18 As shown, the first connection line 31 and the second connection line 32 may intersect in the non-display area NA. Placing the two in different film layers can avoid cross-circuiting.

[0104] In another embodiment, Figure 21 A partial schematic diagram of another display panel provided by an embodiment of the present invention, such as Figure 21 As shown, the display area AA has an irregular corner G, and the non-display area NA includes a corner non-display area NAG and a straight-edge non-display area NA1. The corner non-display area NAG is adjacent to the irregular corner G, and the straight-edge non-display area NA1 is connected to the corner non-display area NAG. The first shift register 11a is located in the straight-edge non-display area NA1, and the second shift register 11b is located in the corner non-display area NAG. The driving signal line 20 includes a third signal line 23, and the third signal line 23 extends within the corner non-display area NAG and extends from the corner non-display area NAG to the straight-edge non-display area NA1. In this embodiment, the third signal line 23 in the driving signal line 20 is still wired within the non-display area NA. Optionally, the third signal line 23 is the starting signal line STV. In the driving circuit, only the input end of the first-stage shift register needs to be electrically connected to the third signal line 23. Figure 21 Taking the case where the middle corner non-display area NAG is located at the lower frame of the display panel as an example, the second shift register 11b does not need to be electrically connected to the third signal line 23. The third signal line 23 can be wired along the outer edge of each second shift register 11b, and the second shift register 11b can be upright relative to the first shift register 11a so that the second shift register 11b and the pixel circuit row 30H are aligned.

[0105] In some embodiments, as Figure 9As shown, at least a portion of the first signal line 21 is a zigzag line. At the irregular corner G of the display area AA, some adjacent pixel circuit rows 30H are staggered in the second direction y to form a step-like edge. By configuring at least a portion of the first signal line 21 as a zigzag line, the line shape of the first signal line 21 can be designed to match the step-like edge of the display area AA within the display area AA, concentrating the first signal line 21 at the edge of the display area AA and reducing the space occupied by the first signal line 21 in the display area AA. Furthermore, the distance between the first signal line 21 and the shift register 11 in the first direction x can be reduced, thereby reducing the length of the first connecting line 31 and thereby reducing the voltage drop across the signal line.

[0106] like Figure 9 As shown, the first signal line 21 includes a first line segment 21-1 extending along a first direction x and a second line segment 21-2 extending along a second direction y, the first direction x and the second direction y intersecting each other. The first line segment 21-1 and the second line segment 21-2 are connected to form the first signal line 21 in a stepped shape.

[0107] In some embodiments, as Figure 8 As shown, the first signal line 21 in the display area AA is a straight line.

[0108] In some embodiments, Figure 22 A schematic diagram of another display panel provided by an embodiment of the present invention, Figure 22 The corner position of the display panel is used for schematic illustration, such as Figure 22 As shown, the pixel circuit 30 includes a virtual pixel circuit 30x; the virtual pixel circuit 30x is not used to drive the light-emitting device to emit light. The virtual pixel circuit 30x is located at the edge of the pixel circuit row. The embodiment of the present invention does not limit the number of virtual pixel circuits 30x included in the pixel circuit row. Figure 22 In the figure, only two dummy pixel circuits 30x are provided at one end of a pixel circuit row. In a direction perpendicular to the plane of the substrate, the first signal line 21 overlaps with the dummy pixel circuit 30x. This prevents the first signal line 21 from overlapping with the pixel circuit 30 for driving the light-emitting device and causing interference to the signal of the pixel circuit 30.

[0109] In some embodiments, the display panel includes fixed-potential signal lines, and at least a portion of the first signal line 21 overlaps with the fixed-potential signal line in a direction perpendicular to the plane of the substrate. This arrangement can reduce coupling caused by the overlap between the first signal line 21 and the signal line, thereby reducing the impact of the coupling on the signal transmitted on the first signal line 21.

[0110] In one embodiment, Figure 23 A schematic diagram of another display panel provided by an embodiment of the present invention, Figure 23The circuit diagram at a local position of the display panel is shown, showing that two pixel circuit rows are offset by one pixel circuit 30 at the edge position. Figure 23 The pixel circuit structure can be combined with Figure 19 Understand. Figure 23 As shown, the display panel includes a reset signal line Ref extending in a first direction x and a positive power supply voltage signal line Pvdd extending in a second direction y. The fixed potential signal lines include the reset signal line Ref and the positive power supply voltage signal line Pvdd. Specifically, the reset signal line Ref and the positive power supply voltage signal line Pvdd each transmit a fixed potential signal. The pixel circuit 30 is coupled to the positive power supply voltage signal line Pvdd and the reset signal line Ref, respectively. The second direction y intersects the first direction x. The pixel circuit 30 includes a storage capacitor Cst. The first plate of the storage capacitor Cst is coupled to the positive power supply voltage signal line Pvdd. The first plates of adjacent pixel circuits 30 in the first direction x are interconnected to form an auxiliary power supply voltage line 60. The auxiliary power supply voltage line 60 is connected in parallel with the positive power supply voltage signal line Pvdd to reduce the voltage drop during transmission of the positive power supply voltage signal and improve overall in-plane uniformity. The first signal line 21 includes a first line segment 21-1 extending in the first direction x. Figure 23 This is a schematic diagram of a top view of a display panel. It can be understood that the top view direction is parallel to the direction perpendicular to the plane where the substrate is located. Figure 23 As shown, in a direction perpendicular to the substrate plane, the first line segment 21-1 at least partially overlaps the auxiliary power voltage line 60. This arrangement can reduce the coupling caused by the overlap between the first signal line 21 and the signal line, and reduce the impact of the coupling on the signal transmitted on the first signal line 21.

[0111] In another embodiment, in a direction perpendicular to the plane of the substrate, the first line segment 21 - 1 at least partially overlaps with the reset signal line Ref, which is not illustrated in the figure here.

[0112] like Figure 23 As shown, the first signal line 21 includes a second line segment 21-2 extending in the second direction y. In a direction perpendicular to the substrate plane, the second line segment 21-2 at least partially overlaps with the positive power supply voltage signal line Pvdd. This arrangement can reduce coupling caused by the overlap between the first signal line 21 and the signal line, thereby reducing the impact of the coupling on the signal transmitted on the first signal line 21.

[0113] In some embodiments, Figure 24 A schematic diagram of another display panel provided by an embodiment of the present invention, Figure 24 The corner area of ​​the display panel is used as a schematic illustration. Figure 24 As shown, the display panel further includes a dummy signal line 70 , and the dummy signal line 70 and the first signal line 21 are located in different areas of the display area AA. Figure 24Only the dummy signal lines 70 extending along the second direction y are illustrated. Optionally, the display panel further includes dummy signal lines 70 extending along the first direction x. Because the first signal lines 21 are located in the display area AA, they may reflect ambient light, resulting in differences in reflectivity at different locations in the display area and affecting the display effect. The dummy signal lines 70 can balance the differences in metal line pattern density at different locations in the display area AA, reducing the differences in reflectivity at different locations in the display area AA and improving the display effect.

[0114] In one embodiment, the dummy signal line 70 and the first signal line 21 are located in the same film layer. Thus, the dummy signal line 70 and the first signal line 21 can be manufactured in the same process, which simplifies the process.

[0115] In the embodiment of the present invention, the dummy signal line 70 transmits a fixed potential signal, which can prevent the dummy signal line 70 from floating and reduce signal interference.

[0116] In one embodiment, the dummy signal line 70 is coupled to the positive power supply voltage signal line Pvdd, and the dummy signal line 70 transmits a positive power supply voltage signal.

[0117] In another embodiment, the dummy signal line 70 is coupled to the reset signal line Ref, and the dummy signal line 70 transmits a reset signal.

[0118] In another embodiment, the dummy signal line 70 is coupled to the negative power supply voltage signal line Pvee, and the dummy signal line 70 transmits a negative power supply voltage signal.

[0119] In the embodiment of the present invention, the driving circuit includes a scanning driving circuit and a light-emitting driving circuit. The scanning driving circuit includes a scanning shift register, and the light-emitting driving circuit includes a light-emitting shift register. Figure 19 As can be understood from the pixel circuit diagram provided, the first scan line Sc1 and the second scan line Sc2 are electrically connected to the scan shift register, and the light-emission control line E is electrically connected to the light-emission shift register. In other words, the gate line 40 mentioned in the above-mentioned related embodiments includes the first scan line Sc1, the second scan line Sc2, and the light-emission control line E.

[0120] Figure 25 A schematic diagram of another display panel provided by an embodiment of the present invention, Figure 25 The corner position of the display panel is still used for illustration, and the situation at the straight edge position of the display panel can be understood by reference. Figure 25As shown, in the corner non-display area NAG, the scanning shift register 11S and the light-emitting shift register 11E are located on the same side of the display area AA in the first direction x; the driving signal lines 20 coupled to the scanning shift register 11S include at least one first signal line 21, and the driving signal lines 20 coupled to the light-emitting shift register 11E include at least one first signal line 21. The scanning shift register 11S is coupled to the first signal line 21 through the first connecting line 31, and the light-emitting shift register 11E is coupled to the first signal line 21 through the first connecting line 31. Such a setting can make the light-emitting shift register 11E and the scanning shift register 11S, both shift registers, aligned with the pixel circuit row, so there is no need to set the following when the two shift registers are connected to the corresponding selection lines in the display area AA. Figure 1 The oblique wires 06 shown save space in the corner non-display area NAG, reduce the distance between the shift register 11 and the display area AA in the corner non-display area NAG, and reduce the border width of the corner non-display area NAG.

[0121] Figure 25 In the figure, the scanning shift register 11S is located on the side of the light emitting shift register 11E close to the display area AA. In another embodiment, the scanning shift register 11S is located on the side of the light emitting shift register 11E away from the display area AA.

[0122] In another embodiment, the scanning shift register 11S and the light emitting shift register 11E are located on the same side of the display area AA in the first direction x, and the driving signal lines coupled to one of the scanning shift register 11S and the light emitting shift register 11E include the first signal line 21 .

[0123] Figure 25 The figure shows that a scanning shift register 11S and a light-emitting shift register 11E are provided at the corner positions. In other embodiments, the scanning shift register 11S and the light-emitting shift register 11E are provided on both sides of the display area AA, for example, the scanning shift register 11S is provided on the left side of the display area AA and the light-emitting shift register 11E is provided on the right side. Then, the scanning shift register 11S is provided at the corner position of the lower left corner of the display panel, and the light-emitting shift register 11E is provided at the corner position of the lower right corner. In addition, the drive signal lines 20 coupled to the scanning shift register 11S include at least one first signal line 21, and the drive signal lines 20 coupled to the light-emitting shift register 11E include at least one first signal line 21. This is not illustrated in the figure here.

[0124] In another embodiment, Figure 26 A schematic diagram of another display panel provided by an embodiment of the present invention, Figure 26The corner position of the display panel is still used for illustration, and the situation at the straight edge position of the display panel can be understood by reference. Figure 26 As shown, the first signal line 21 includes a common signal line 21g, and at least part of the scanning shift register 11S and at least part of the light emitting shift register 11E are connected to the same common signal line 21g. The driving signal line 20 includes a power signal line, as described above. Figure 5 or Figure 6 The illustrated power signal lines include a first power signal line VGH and a second power signal line VGL. The common signal line 21g includes at least one of the first power signal line VGH and the second power signal line VGL. In this embodiment, the common signal line 21g is provided within the display area AA. The common signal line 21g simultaneously drives the scanning shift register 11S and the light-emitting shift register 11E, thereby reducing the number of first signal lines 21 provided within the display area AA and reducing the space occupied by the first signal lines 21 in the display area AA.

[0125] In some embodiments, common signal line 21g is the widest line among the drive signal lines 20. Because common signal line 21g drives both the scanning shift register 11S and the light-emitting shift register 11E, the load on common signal line 21g is relatively large. In this embodiment, by widening the width of common signal line 21g, the resistance of common signal line 21g can be reduced, thereby reducing the voltage drop across common signal line 21g and ensuring the driving performance of common signal line 21g for the shift register.

[0126] Based on the same inventive concept, an embodiment of the present invention also provides another display panel, Figure 27 A partial schematic diagram of another display panel provided by an embodiment of the present invention, such as Figure 27 As shown, the display panel includes a display area AA and a non-display area NA; the display panel includes a driving circuit 10 located in the non-display area NA and pixel circuits 30 located in the display area AA; a plurality of pixel circuits 30 are arranged in pixel circuit rows in a first direction x, and the pixel circuit rows include a first pixel circuit row 30H-1 and a second pixel circuit row 30H-2; in a second direction y, the first pixel circuit row 30H-1 and the second pixel circuit row 30H-2 are offset at one end near the non-display area NA, and the second direction y intersects the first direction x; the driving circuit 10 includes a plurality of cascaded shift registers 11, and the shift registers 11 are coupled to corresponding gate lines 40 in the display area AA. The shift registers 11 include a fifth shift register 11e and a sixth shift register 11f; wherein, in the first direction x, the fifth shift register 11e is adjacent to the first pixel circuit row 30H-1, and the sixth shift register 11f is adjacent to the second pixel circuit row 30H-2. In the second direction y, the fifth shift register 11e and the sixth shift register 11f are offset at one end close to the display area AA.

[0127] In this embodiment, for pixel circuit rows 30H that are staggered in the second direction y, the shift registers 11 adjacent to them are also staggered in the second direction y. By staggering the shift registers 11 based on the staggered arrangement of the pixel circuit rows 30H, the distance difference between the shift register 11 and the adjacent pixel circuit rows 30H at various locations can be minimized. In particular, when the display area AA has an irregular corner G, the pixel circuit rows 30H are staggered in the second direction y at the irregular corner G, forming a step-like edge. By staggering the shift registers 11 according to the design of this embodiment of the present invention, the spacing between the shift register 11 and the pixel circuit rows 30H within the corner non-display area NAG can be reduced, thereby narrowing the border width of the corner non-display area NAG.

[0128] In some embodiments, as Figure 27 As shown, in the first direction x, the fifth shift register 11e is spaced a third distance d3 from the first pixel circuit row 30H-1, and the sixth shift register 11f is spaced a fourth distance d4 from the second pixel circuit row 30H-2, where d3 = d4. The distance between the shift register 11 and the pixel circuit row 30H in the first direction x is understood to be the distance in the first direction x between the edge of the shift register 11 and the edge of the first pixel circuit in the pixel circuit row 30H. Setting d3 = d4 means that for pixel circuit rows 30H that are misaligned in the second direction y, the distances between the pixel circuit rows 30H and their adjacent shift registers 11 are equal. In particular, at the irregular corner G of the display area AA, the pixel circuit rows 30H are staggered in the second direction y, forming a step-like edge. The design of this embodiment of the present invention can equalize the distances between each shift register 11 and the pixel circuit row 30H within the corner non-display area NAG, thereby reducing the border width of the corner non-display area NAG.

[0129] Figure 27 In the embodiment, the shift register 11 includes a fifth shift register 11e and a sixth shift register 11f. In some of the above embodiments, the shift register 11 includes a first shift register 11a and a second shift register 11b. In other embodiments, the shift register 11 includes a third shift register 11c and a fourth shift register 11d. In each embodiment, the naming of "first" and "second", "third" and "fourth", "fifth" and "sixth" is only for illustrating the specific technical solutions in the embodiments of the present invention. In the absence of conflict, the technical features in the above embodiments can be combined. And in the absence of conflict, the naming of the shift registers in different embodiments can be simply replaced, for example, Figure 27The fifth shift register 11e and the sixth shift register 11f in the embodiment may be named the first shift register 11a and the second shift register 11b, or the fifth shift register 11e and the sixth shift register 11f may be named the third shift register 11c and the fourth shift register 11d.

[0130] In some embodiments, Figure 28 A partial schematic diagram of another display panel provided by an embodiment of the present invention, such as Figure 28 As shown, the non-display area NA includes a corner non-display area NAG and a straight-edge non-display area NA1; the fifth shift register 11e is located in the straight-edge non-display area NA1, and the sixth shift register 11f is located in the corner non-display area NAG; the shift register 11 includes a plurality of transistors; the shift register 11 can be the above Figure 5 or Figure 6 The schematic structure, or the shift register 11 is another circuit structure capable of realizing the signal shifting function. In the embodiment of the present invention, the channel extension direction of the transistors with the same function in the fifth shift register 11e and the sixth shift register 11f is the same, which can realize the same arrangement of the transistors in the fifth shift register 11e and the sixth shift register 11f, and the sixth shift register 11f is upright relative to the fifth shift register 11e. Such a setting can align the fifth shift register 11e with the corresponding pixel circuit row 30H, and the connection between the fifth shift register 11e and the corresponding gate line 40 is more convenient, and there is no need to set such a gate line in the corner non-display area NAG. Figure 1 The oblique lines in the corner non-display area NAG are drawn, thereby saving wiring space in the corner non-display area NAG and narrowing the border of the corner non-display area NAG.

[0131] like Figure 28As shown, the fifth shift register 11e and the sixth shift register 11f are both illustrated in block diagrams. It can be seen that the outer contour shapes of the fifth shift register 11e and the sixth shift register 11f are the same. The edge of the shift register 11 is understood to be the outer contour edge of the graphic shape jointly occupied by multiple transistors in the shift register 11. The fifth shift register 11e is located in the straight-edge non-display area NA1, and the sixth shift register 11f is located in the corner non-display area NAG; on the side close to the display area AA, the extension direction of the edge of the fifth shift register 11e is the same as the extension direction of the edge of the sixth shift register 11f. Then the edge of the sixth shift register 11f close to the display area AA is not set to adapt to the shape of the irregular corner G, that is, the sixth shift register 11f does not need to be tilted relative to the fifth shift register 11e. Such a setting can align the sixth shift register 11f with the corresponding pixel circuit row, and the connection between the sixth shift register 11f and the corresponding gate line 40 is more convenient, and there is no need to set such a setting in the corner non-display area NAG. Figure 1 The oblique lines in the corner non-display area NAG are drawn, thereby saving wiring space in the corner non-display area NAG and narrowing the border of the corner non-display area NAG.

[0132] When the display panel has an irregular corner G, at least some of the adjacent shift registers in the multi-stage shift registers arranged in the corner non-display area NAG adjacent to the irregular corner G will be staggered. Figure 2 As can be seen from the description of the prior art, in the prior art, the drive signal lines are made of the same film layer, and multiple drive signal lines are arranged in the same film layer. However, in order to ensure the connection between the shift register and the drive signal lines, the shift register and the pixel circuit rows in the display area are misaligned and cannot be aligned. To solve the problems of the prior art, an embodiment of the present invention proposes a display panel in which at least part of the drive signal lines are arranged in a different layer, and some line segments are arranged to overlap with the shift register, thereby saving wiring space for the drive signal lines and allowing the shift register in the corner non-display area to be upright and aligned with the pixel circuit rows.

[0133] In some embodiments, Figure 29 A partial schematic diagram of another display panel provided by an embodiment of the present invention, such as Figure 29 As shown, the fifth shift register 11e and the sixth shift register 11f are adjacent to each other in the second direction y. The display panel further includes a driving signal line 20. The driving signal line 20 includes a start signal line, a clock signal line, and a power signal line. Figure 29 Only two driving signal lines 20 are shown. The driving signal lines 20 are located in the non-display area NA. The driving signal lines 20 include a fourth signal line 24 and a fifth signal line 25. The fourth signal line 24 and the fifth signal line 25 are located in different film layers.

[0134] The fourth signal line 24 is located on one side of the shift register 11 in the first direction x. The fourth signal line includes a first sub-signal line 24a and a second sub-signal line 24b. The first sub-signal line 24a is located on one side of the fifth shift register 11e, and the second sub-signal line 24b is located on one side of the sixth shift register 11f. One end of the fifth signal line 25 is connected to the first sub-signal line 24a, and the other end of the fifth signal line 25 is connected to the second sub-signal line 24b. The display panel includes a substrate. In a direction perpendicular to the plane of the substrate, the fifth signal line 25 at least partially overlaps with the fifth shift register 11e. Figure 29 The fifth signal line 25 is illustrated as a broken line, and the embodiment of the present invention does not limit the line shape of the fifth signal line 25.

[0135] In the display panel, the driving signal lines 20 have a certain width, and adjacent driving signal lines 20 need to be spaced a certain distance apart. In order to ensure the consistent performance of each shift register, the transistors in each shift register are set to the same size, that is, the space occupied by each shift register is fixed. On this basis, since the fifth shift register 11e and the sixth shift register 11f are misaligned in the second direction y, if the driving signal line 20 is set on one side of the shift register 11 according to the design method of the prior art, as shown in FIG. Figure 2 As described in (2) and (3), in order to arrange multiple drive signal lines 20 and connect the shift register 11 with the corresponding drive signal lines 20, arranging multiple drive signal lines 20 made of the same film layer will occupy a larger space, making the spacing between adjacent shift registers 11 in the second direction y larger, resulting in the shift register 11 and the corresponding pixel circuit row 30H being unable to be aligned.

[0136] By adopting the design of the embodiment of the present invention, the fifth signal line 25 overlaps the shift register 11, so that the area occupied by the driving signal line 20 at the position where the shift register 11 is staggered can be reduced. Moreover, the extension direction of the driving signal line 20 on one side of the shift register 11 is the same as the arrangement direction of the shift register 11 (i.e., the second direction y), so that the shift register 11 in the corner non-display area NAG can be placed upright, and the shift register 11 in the corner non-display area NAG and the corresponding pixel circuit row 30H can be easily aligned. There is no need to set the following arrangement in the corner non-display area NAG: Figure 1 The oblique lines in the corner non-display area NAG are drawn, thereby saving wiring space in the corner non-display area NAG and narrowing the border of the corner non-display area NAG.

[0137] Combined with the above Figure 20 To understand from the embodiments, in some embodiments, the fourth signal line 24 is located in the second metal layer 014 , and the fifth signal line 25 is located in the third metal layer 015 or the fourth metal layer 016 .

[0138] In some embodiments, Figure 29 The solution of the embodiment is the same as above Figure 7 The solutions of the embodiments are combined to achieve narrowing of the border of the corner non-display area NAG.

[0139] like Figure 5 As shown, the shift register 11 includes an output module 111 and a switch module 112. The output module 111 of the shift register includes an output terminal OUT, wherein the output terminal OUT is coupled to the gate line 40. In the embodiment of the present invention, the output module 111 is located on the side of the switch module 112 close to the display area AA, and the fourth signal line 24 is located on the side of the shift register 11 away from the display area AA. This can reduce the length of the connecting lead between the output terminal OUT of the shift register 11 and the gate line 40 in the display area AA, and the connecting lead between the two does not need to overlap with the drive signal line 20, which can reduce the parasitic capacitance on the connecting lead.

[0140] It should be noted that the figures related to the above-described embodiments of the present invention merely illustrate the positional and connection relationships between the various device structures in the display panel. The adjacent shift registers 11 shown in the figures are spaced a certain distance apart in the second direction y for the sole purpose of clarifying the technical solutions of the embodiments of the present invention. In actual products, the shift registers are closely arranged, with the spacing between adjacent shift registers being only the minimum process spacing (the minimum spacing required to ensure mutual insulation between metal lines).

[0141] Based on the same inventive concept, an embodiment of the present invention further provides a display device, Figure 30 A schematic diagram of a display device provided by an embodiment of the present invention, such as Figure 30 As shown, the display device includes a display panel 100 provided by any embodiment of the present invention. The structure of the display panel has been described in the above embodiments and will not be repeated here. The display device provided by the embodiment of the present invention can be, for example, an electronic device such as a mobile phone, a computer, a television, a tablet, or a smart wearable device.

[0142] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

[0143] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A display panel, characterized in that: The display panel includes a display area and a non-display area; the display panel includes a driving circuit and a driving signal line, the driving circuit is located in the non-display area, the driving circuit includes a plurality of cascaded shift registers, and the driving signal line is used to provide signals to the driving circuit; wherein, The driving signal line includes at least one first signal line, and the first signal line is located in the display area; The display panel includes a first connecting line, at least one stage of the shift register is coupled to the first signal line via the first connecting line, and the first connecting line extends along a first direction; The display area has an irregular corner, the non-display area includes a corner non-display area adjacent to the irregular corner, and part of the shift register is located in the corner non-display area; at least part of the line segment of the first signal line is located in the display area adjacent to the corner non-display area in the first direction, and at least part of the shift register in the corner non-display area is coupled to the first signal line through the first connecting line; The non-display area further includes a straight-edge non-display area connected to the corner non-display area, and part of the shift register is located in the straight-edge non-display area; The driving signal line further includes a second signal line located in the non-display area, the second signal line being coupled to the first signal line; The second signal line extends in the straight-edge non-display area, and the second signal line terminates at a junction of the straight-edge non-display area and the corner non-display area.

2. The display panel according to claim 1, wherein: The non-display area further includes a straight-edge non-display area connected to the corner non-display area; The shift register includes a first shift register and a second shift register, the first shift register is located in the straight edge non-display area, and the second shift register is located in the corner non-display area; the shift register includes a plurality of transistors; Channels of transistors with the same function in the first shift register and the second shift register extend in the same direction.

3. The display panel according to claim 1, wherein: The non-display area further includes a straight-edge non-display area connected to the corner non-display area; The shift register includes a first shift register and a second shift register, the first shift register is located in the straight edge non-display area, and the second shift register is located in the corner non-display area; On a side close to the display area, an extension direction of an edge of the first shift register is the same as an extension direction of an edge of the second shift register.

4. The display panel according to claim 1, wherein: A plurality of pixel circuits are arranged into pixel circuit rows in the first direction; In the first direction, the shift register and the pixel circuit rows are aligned in the corner non-display area.

5. The display panel according to claim 1, wherein: The non-display area further includes a straight-edge non-display area connected to the corner non-display area; The shift register includes a first shift register and a second shift register, the first shift register is located in the straight edge non-display area, and the second shift register is located in the corner non-display area; A plurality of pixel circuits are arranged into pixel circuit rows in the first direction; In the first direction, a distance between the first shift register and the pixel circuit row is equal to a distance between the second shift register and the pixel circuit row.

6. The display panel according to claim 1, wherein: The corner non-display area includes a driving signal line segment extending along the second direction, and the driving signal line segment is coupled to the first signal line through the first connecting line; In the corner non-display area: at least two shift registers adjacent to each other in the second direction and aligned with each other are both coupled to the driving signal line segment.

7. The display panel according to claim 6, wherein: The driving signal line segment is located at a side of the shift register away from the display area, or the driving signal line segment is located at a side of the shift register close to the display area.

8. The display panel according to claim 1, wherein: At least a portion of the shift register in the straight-edge non-display area is coupled to the first signal line through the first connecting line.

9. The display panel according to claim 1, wherein: The shift register includes a third shift register and a fourth shift register, and the third shift register is coupled to the first signal line through the first connecting line; The non-display area includes a second connection line, and the fourth shift register is coupled to the first connection line through the second connection line.

10. The display panel according to claim 9, wherein: In a second direction, the third shift register and the fourth shift register are aligned, and the second direction is an arrangement direction of the third shift register and the fourth shift register.

11. The display panel according to claim 9, wherein In a second direction, the third shift register and the fourth shift register are staggered, and the second direction is an arrangement direction of the third shift register and the fourth shift register.

12. The display panel according to claim 9, wherein: The second connecting line and the first signal line are located in the same film layer.

13. The display panel according to claim 1, wherein In the driving circuit, only the first-stage shift register is coupled to the first signal line.

14. The display panel according to claim 1, wherein The driving signal line includes a third signal line, and the third signal line extends in the corner non-display area and extends from the corner non-display area to the straight-side non-display area.

15. The display panel according to claim 1, wherein At least a portion of the first signal line is a broken line.

16. The display panel according to claim 15, wherein: The first signal line includes a first line segment extending along the first direction and a second line segment extending along a second direction, and the first direction and the second direction intersect each other.

17. The display panel according to claim 1, wherein: The display panel includes a pixel circuit located in the display area, and the pixel circuit includes a virtual pixel circuit; The display panel includes a substrate, and the first signal line overlaps with the dummy pixel circuit in a direction perpendicular to a plane of the substrate.

18. The display panel according to claim 1, wherein The display panel includes a fixed potential signal line, In a direction perpendicular to the plane of the substrate, at least a portion of the first signal line overlaps with the fixed potential signal line.

19. The display panel according to claim 18, wherein: The display panel includes a reset signal line extending in the first direction and a power supply voltage signal line extending in a second direction, the pixel circuit is coupled to the power supply voltage signal line and the reset signal line respectively, and the second direction intersects the first direction; The pixel circuit includes a storage capacitor, a first plate of the storage capacitor is coupled to the power supply voltage signal line, and the first plates in the adjacent pixel circuits in the first direction are connected to each other to form an auxiliary power supply voltage line; The first signal line includes a first line segment extending in the first direction; The display panel includes a substrate; in a direction perpendicular to a plane of the substrate, the first line segment at least partially overlaps with the auxiliary power voltage line, or the first line segment at least partially overlaps with the reset signal line.

20. The display panel according to claim 18, wherein The display panel includes a power supply voltage signal line extending in a second direction, and the pixel circuit is coupled to the power supply voltage signal line; The first signal line includes a second line segment extending in the second direction; The display panel includes a substrate; in a direction perpendicular to a plane of the substrate, the second line segment at least partially overlaps with the power supply voltage signal line.

21. The display panel according to claim 1, wherein The display panel further includes a dummy signal line, and the dummy signal line and the first signal line are located in different areas of the display area.

22. The display panel according to claim 21, wherein: The dummy signal line transmits a fixed potential signal.

23. The display panel according to claim 1, wherein The driving circuit includes a scanning driving circuit and a light-emitting driving circuit, wherein the scanning driving circuit includes a scanning shift register and the light-emitting driving circuit includes a light-emitting shift register. The scanning shift register and the light emitting shift register are located on the same side of the display area in the first direction; The driving signal lines to which at least one of the scanning shift register and the light-emitting shift register is coupled include the first signal line.

24. The display panel according to claim 23, wherein: The first signal line comprises a common signal line, and at least part of the scanning shift register and at least part of the light emitting shift register are connected to the same common signal line; The driving signal line includes a power signal line, and the power signal line includes a first power signal line and a second power signal line; the common signal line includes at least one of the first power signal line and the second power signal line.

25. The display panel according to claim 24, wherein: The common signal line is a line with the widest line width among the driving signal lines.

26. A display panel, characterized in that: The display panel includes a display area and a non-display area; the display panel includes a driving circuit located in the non-display area and a pixel circuit located in the display area; The plurality of pixel circuits are arranged in a first direction into pixel circuit rows, the pixel circuit rows including a first pixel circuit row and a second pixel circuit row; in a second direction, the first pixel circuit row and the second pixel circuit row are offset at one end close to the non-display area, and the second direction intersects the first direction; The driving circuit includes a plurality of cascaded shift registers; the shift registers include a fifth shift register and a sixth shift register; wherein, In the first direction, the fifth shift register is adjacent to the first pixel circuit row, and the sixth shift register is adjacent to the second pixel circuit row; in the second direction, the fifth shift register and the sixth shift register are staggered at one end close to the display area; The fifth shift register and the sixth shift register are adjacent to each other in the second direction; The display panel further includes a driving signal line, and the driving signal line is located in the non-display area; The driving signal line includes a fourth signal line and a fifth signal line, and the fourth signal line and the fifth signal line are located in different film layers; The fourth signal line is located on a side of the shift register away from the display area in the first direction; the fourth signal line includes a first sub-signal line and a second sub-signal line, the first sub-signal line is located on a side of the fifth shift register, and the second sub-signal line is located on a side of the sixth shift register; One end of the fifth signal line is connected to the first sub-signal line, and the other end of the fifth signal line is connected to the second sub-signal line; The display panel includes a substrate, and in a direction perpendicular to a plane of the substrate, the fifth signal line at least partially overlaps with the fifth shift register.

27. The display panel according to claim 26, wherein: The non-display area includes a corner non-display area and a straight-edge non-display area; The fifth shift register is located in the straight-edge non-display area, and the sixth shift register is located in the corner non-display area; the shift register includes a plurality of transistors; Channels of transistors with the same function in the fifth shift register and the sixth shift register extend in the same direction.

28. The display panel according to claim 26, wherein: The non-display area includes a corner non-display area and a straight-edge non-display area; The fifth shift register is located in the straight-edge non-display area, and the sixth shift register is located in the corner non-display area; On a side close to the display area, an extension direction of an edge of the fifth shift register is the same as an extension direction of an edge of the sixth shift register.

29. The display panel according to claim 26, wherein: The fourth signal line is located at a side of the shift register away from the display area.

30. The display panel according to claim 26, wherein: In the first direction, a distance between the fifth shift register and the first pixel circuit row is equal to a distance between the sixth shift register and the second pixel circuit row.

31. A display device, characterized in that: A display panel comprising any one of claims 1 to 30.

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