SRAM word line voltage generation circuit and regulation circuit

Abstract

The present invention provides an SRAM word line voltage regulation circuit, comprising: a first n-input NAND gate, whose input receives a row decoding signal from a word line decoding circuit; a first PMOS transistor, whose source is connected to a power supply voltage, and whose output signal from the first n-input NAND gate passes through two stages of inverters and is then input into the gate of the first PMOS transistor; a second n-input NAND gate, whose input receives the row decoding signal; a NOR gate, whose input receives the output signal of the second n-input NAND gate and a read / write control signal; and a second PMOS transistor, whose source and drain are short-circuited and connected to the drain of the first PMOS transistor, and which outputs the regulation signal from the word line decoding circuit. The output signal from the NOR gate passes through a single stage of inverters and is then input into the gate of the second PMOS transistor. The present invention can control the SRAM word line voltage without requiring an external control signal, reducing the circuit's control difficulty. Furthermore, by using the second PMOS transistor for charging, capacitors can be eliminated, thereby reducing occupied area.

Description

Technical Field

[0001] The present invention relates to the field of circuit technology, and in particular to an SRAM word line voltage generating circuit and a regulating circuit. Background Art

[0002] As process nodes and supply voltages continue to decrease, device threshold voltages also decrease, leading to a continuous decline in the robustness of SRAM memory cells. This degrades the read and write capabilities of the memory cells during operation. During read operations, read corruption of half-selected cells frequently occurs, resulting in erroneous data reads. During write operations, write performance deteriorates, making it very easy for SRAM to write erroneous data.

[0003] Word line undervoltage (WLUD) technology is often used in read assist circuits, and word line overvoltage (WLOD) technology is often used in write assist circuits.

[0004] However, the auxiliary circuit of the prior art SRAM memory cell requires an external control signal and has strict requirements on the timing of the input signal, thereby increasing the difficulty of circuit control. In addition, the capacitors used in the auxiliary circuit of the SRAM memory cell occupy a large area. Summary of the Invention

[0005] The object of the present invention is to provide an SRAM word line voltage generating circuit and regulating circuit, which do not require an external control signal, thereby reducing the difficulty of circuit control. At the same time, capacitors can be omitted, thereby reducing the area occupied by the regulating circuit.

[0006] In order to achieve the above object, the present invention provides a circuit for regulating an SRAM word line voltage, comprising:

[0007] A first n-input NAND gate, whose input terminal receives a row decoding signal from a word line decoding circuit;

[0008] A first PMOS transistor, whose source is connected to a power supply voltage, and an output signal of the first n-input NAND gate is input to a gate of the first PMOS transistor after passing through two stages of inverters;

[0009] a second n-input NAND gate, whose input receives the row decoding signal, wherein n is a positive integer;

[0010] A NOR gate, whose input terminal is connected to the output signal of the second n-input NAND gate and the read / write control signal;

[0011] The second PMOS tube has its source and drain short-circuited and connected to the drain of the first PMOS tube, and outputs the adjustment signal of the word line decoding circuit. The output signal of the NOR gate is input to the gate of the second PMOS tube after passing through a first-stage inverter.

[0012] Optionally, in the SRAM word line voltage regulation circuit, the output signal of the first n-input NAND gate is input into the gate of the first PMOS tube after passing through the first inverter and the second inverter, the output signal of the first n-input NAND gate is input into the output end of the first inverter, the output signal of the first inverter is input into the input end of the second inverter, and the output signal of the second inverter is input into the gate of the first PMOS tube.

[0013] Optionally, in the SRAM word line voltage regulation circuit, the output signal of the NOR gate is input into the gate of the second PMOS tube after passing through the third inverter, the output signal of the NOR gate is input into the input end of the third inverter, and the output signal of the third inverter is output to the gate of the second PMOS tube.

[0014] Optionally, in the SRAM word line voltage regulation circuit, the first n-input NAND gate and the second n-input NAND gate each include n input terminals, and each input terminal is connected to a row decoding signal.

[0015] Optionally, in the SRAM word line voltage regulating circuit, each input terminal receives a different row decoding signal.

[0016] Optionally, in the SRAM word line voltage regulation circuit, when the read-write control signal is at a low level, the initial values ​​of all the row decoding signals are at a high level, the gate of the first PMOS tube is at a low level, the gate of the first PMOS tube is turned on, and the power supply voltage charges the second PMOS tube through the gate of the first PMOS tube.

[0017] Optionally, in the SRAM word line voltage regulation circuit, when the read-write control signal is at a high level, the initial value of the row decoding signal is a high level, the gate of the first PMOS tube is at a low level, the first PMOS tube is turned on, and the power supply voltage charges the second PMOS tube through the first PMOS tube, so that the regulation signal of the word line decoding circuit reaches the power supply voltage.

[0018] The present invention also provides an SRAM word line voltage generating circuit, comprising:

[0019] An SRAM memory cell for generating a word line voltage;

[0020] The word line selection circuit controls the voltage of the word line voltage together with the adjustment signal of the word line decoding circuit.

[0021] Optionally, in the SRAM word line voltage generating circuit, the SRAM storage unit is a 6T SRAM memory.

[0022] Optionally, in the SRAM word line voltage generating circuit, the 6T SRAM memory includes two PMOS transistors and four NMOS transistors.

[0023] In the SRAM word line voltage generation and regulation circuit provided by the present invention, a row decoding signal and a read / write control signal are used to control the charging of a second PMOS transistor by a first PMOS transistor, thereby making the regulation signal of the word line decoding circuit equal to the power supply voltage, thereby controlling the SRAM word line voltage. The present invention can control the SRAM word line voltage without requiring any signals other than the row decoding signal and the read / write control signal, reducing the circuit's control difficulty. Furthermore, using the second PMOS transistor for charging eliminates the need for capacitors, thereby reducing the area occupied by the regulation circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 Schematic diagram of an SRAM word line voltage regulation circuit according to an embodiment of the present invention;

[0025] Figure 2 is a schematic diagram of an SRAM word line voltage generating circuit according to an embodiment of the present invention;

[0026] Figure 3 is a schematic diagram of an SRAM memory cell according to an embodiment of the invention;

[0027] Figure 4 1 is a timing diagram of the read and write operations of the SRAM memory cell according to an embodiment of the invention;

[0028] 110 - first n-input NAND gate, 120 - second n-input NAND gate, 130 - NOR gate, 140 - first inverter, 150 - second inverter, 160 - third inverter, 170 - word line selection circuit, 180 - SRAM memory cell, MP1 - first PMOS transistor, MP2 - second PMOS transistor, P3 - third PMOS transistor, P4 - fourth PMOS transistor, N1 - first NMOS transistor, N2 - second NMOS transistor, N3 - third NMOS transistor, N4 - fourth NMOS transistor. DETAILED DESCRIPTION

[0029] The following is a more detailed description of the specific embodiments of the present invention with reference to schematic diagrams. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are greatly simplified and not to exact scale, and are only used for the purpose of conveniently and clearly illustrating the embodiments of the present invention.

[0030] Hereinafter, the terms "first," "second," and the like are used to distinguish between similar elements and are not necessarily used to describe a particular order or chronological sequence. It is to be understood that these terms used in this manner are interchangeable where appropriate. Similarly, if a method described herein comprises a series of steps, the order in which the steps are presented herein is not necessarily the only order in which the steps may be performed, and some of the steps described may be omitted and / or other steps not described herein may be added to the method.

[0031] Please refer to Figure 1 The present invention provides a SRAM word line voltage regulating circuit, comprising:

[0032] A first n-input NAND gate 110, whose input terminal receives a row decoding signal from a word line decoding circuit;

[0033] The first PMOS transistor MP1 has a source connected to the power supply voltage VDD, and the output signal of the first n-input NAND gate 110 is input to the gate of the first PMOS transistor MP1 after passing through two stages of inverters;

[0034] A second n-input NAND gate 120 , whose input terminal receives the row decoding signal, wherein n is a positive integer;

[0035] NOR gate 130, input terminal of which is connected to the output signal of the second n-input NAND gate 120 and the read / write control signal;

[0036] The second PMOS transistor MP2 has its source and drain short-circuited and connected to the drain of the first PMOS transistor MP1, and outputs the adjustment signal VG of the word line decoding circuit. The output signal of the NOR gate 130 is input to the gate of the second PMOS transistor MP2 after passing through a first-stage inverter.

[0037] Preferably, the output signal of the first n-input NAND gate 110 is input to the gate of the first PMOS transistor MP1 after passing through the first inverter 140 and the second inverter 150. The output signal of the first n-input NAND gate 110 is input to the output end of the first inverter 140. The output signal of the first inverter 140 is input to the input end of the second inverter 150. The output signal of the second inverter 150 is input to the gate of the first PMOS transistor MP1. <0> - Y <n>) is generated by the row decoding circuit, the read / write signal WE is generated by the read / write circuit, the row decoding signal (Y <0> - Y <n>) and the read / write signal WE are already present in the read / write circuit of the SRAM storage unit, and therefore, no additional provision is required. <0> -Y <n>) and the use of the read / write signal WE, therefore, the row decoding circuit and the read / write circuit are not limited here. When the read / write signal WE is low, it indicates that the memory cell is read, and when the read / write signal WE is high, it indicates that the memory cell is written.

[0038] Preferably, the output signal of the NOR gate 130 is input to the gate of the second PMOS transistor MP2 after passing through the third inverter 160, the output signal of the NOR gate 130 is input to the input end of the third inverter 160, and the output signal of the third inverter 160 is output to the gate of the second PMOS transistor MP2.

[0039] Preferably, the first n-input NAND gate 110 and the second n-input NAND gate 120 each include n input terminals, each input terminal is connected to a row decoding signal, and the row decoding signal connected to each input terminal is different.

[0040] In the embodiment of the present invention, when the read / write control signal WE is at a low level, all row decoding signals (Y <0> - Y <n>) are both at a high level, the gate of the first PMOS transistor MP1 is at a low level, the gate of the first PMOS transistor MP1 is turned on, and the power supply voltage charges the second PMOS transistor MP2 through the gate of the first PMOS transistor MP1. When the read / write control signal WE is at a high level, the row decoding signal (Y <0> - Y <n>) are both at a high level, the gate of the first PMOS transistor MP1 is at a low level, the first PMOS transistor MP1 is turned on, and the power supply voltage charges the second PMOS transistor MP2 through the first PMOS transistor MP1, so that the adjustment signal VG of the word line decoding circuit reaches the power supply voltage VDD.

[0041] Please refer to Figure 2 The present invention further provides an SRAM word line voltage generating circuit, comprising:

[0042] SRAM memory cell 180, for generating a word line voltage;

[0043] The word line selection circuit 170 receives the row decoding signal and performs a read or write operation on the SRAM memory cell according to the adjustment signal of the word line decoding circuit.

[0044] The word line selection circuit 170 includes an inverter. There are n word line selection circuits, and each word line selection circuit 170 receives a row decoding signal (Y <0> - Y <n>For example, each word line selection circuit 170 receives a different row decoding signal, and there are as many word line selection circuits 170 as there are row decoding signals. Each word line selection circuit 170 includes an inverter.

[0045] Please refer to the preferred Figure 3 The SRAM storage unit 180 is a 6T SRAM memory. Each of the SRAM storage units 180 is a 6T SRAM memory. The 6T SRAM memory includes two PMOS transistors and four NMOS transistors. The four NMOS transistors are a first NMOS transistor N1, a second NMOS transistor N2, a third NMOS transistor N3, and a fourth NMOS transistor N4; the two PMOS transistors are a third PMOS transistor P3 and a fourth PMOS transistor P4. The source of the first NMOS transistor N1 is grounded, the drain of the first NMOS transistor N1 is connected to the drain of the third PMOS transistor P3, the source of the third PMOS transistor P3 is connected to a power supply voltage, and the gate of the third PMOS transistor P3 is connected to the gate of the first NMOS transistor N1, and is also connected to the drain of the fourth PMOS transistor P4 and the drain of the second NMOS transistor N2. The source of the second NMOS transistor N2 is grounded, the drain of the second NMOS transistor N2 is connected to the drain of the fourth PMOS transistor P4, the source of the fourth PMOS transistor P4 is connected to the power supply voltage, the gate of the fourth PMOS transistor P4 is connected to the gate of the second NMOS transistor N2, and is also connected to the drain of the third PMOS transistor P3 and the drain of the first NMOS transistor N1. The gate of the third NMOS transistor N3 is connected to the word line, the drain of the third NMOS transistor N3 is connected to the bit line, the source of the third NMOS transistor N3 is connected to the drain of the third PMOS transistor P3, and is also connected to the drain of the first NMOS transistor N1. The gate of the fourth NMOS transistor N4 is connected to the word line, the source of the fourth NMOS transistor N4 is connected to the inverted bit line, and the drain of the fourth NMOS transistor N4 is connected to the drain of the fourth PMOS transistor P4 and is also connected to the drain of the second NMOS transistor N2, with the connection point being the storage point QB. The gates of the third NMOS transistor N3 and the fourth NMOS transistor N4 are both connected to the word line signal WL. The read and write operations of the word line signal WL can control the read and write of the SRAM storage unit. The read and write operations of the SRAM storage unit can be assisted by adjusting the voltage (WLUD, WLOD) of the word line signal WL.

[0046] Please refer to Figure 4 , the read / write control signal (WE) controls the working state of the SRAM storage unit, and can also control the voltage value V(VG) of the adjustment signal VG of the word line decoding circuit. The adjustment signal VG supplies power to the inverter in the word line decoding circuit and controls the word line decoding voltage value. Therefore, there are two working modes: word line undervoltage (WLUD) read assist mode and word line overvoltage (WLOD) write assist mode. In the word line overvoltage (WLOD) write assist working mode, during the write assist circuit working cycle, that is, the write cycle, the read / write control signal (WE) is low, and the row decoding signal (Y <0> - Y <n>) voltage V(Y <n>) are all at a high level, so the gate of the first PMOS transistor MP1 is at a low level, the first PMOS transistor MP1 is turned on, and the power supply voltage VDD charges the second PMOS transistor MP2 connected to the drain of the first PMOS transistor MP1 (the source and drain of the second PMOS transistor MP2 are short-circuited, equivalent to a capacitor) through the first PMOS transistor MP1, so that it reaches the power supply voltage. <0> - Y <n>) and the read / write control signal (WE) act together on the gate of the second PMOS transistor MP2. At this time, the gate of the second PMOS transistor MP2 is at a low level. Next, wait for the arrival of the decoding signal. When the row decoding signal Y <0> When the gate of the first PMOS tube MP1 is at a low level, the gate of the first PMOS tube MP1 is at a low level when the decoding signal Y <0> The gate of the second PMOS transistor MP2 is also at the decoding signal Y after a slight transmission delay. <0> , which is equivalent to the voltage of the lower plate of the capacitor being suddenly raised. Due to the capacitive coupling effect, the upper plate of the capacitor outputs the adjustment signal VG which is higher than the power supply voltage VDD. The adjustment signal VG is connected to the inverter in the word line selection circuit 170, and supplies power to the word line selection circuit 170 instead of the power supply voltage VDD, so that the output voltage V(WLn) of the word line selection circuit 170 is higher than the power supply voltage VDD. At this time, the output voltage is used for the write operation of the SRAM storage unit 180. In the word line undervoltage (WLUD) read assist working mode, the read assist circuit working cycle, that is, the read cycle, the read and write control signal (WE) is high, and the row decoding signal (Y <0> - Y <n>) are all at a high level, so the gate of the first PMOS transistor MP1 is at a low level, the first PMOS transistor MP1 is turned on, and the power supply voltage VDD charges the second PMOS transistor MP2 connected to the drain of the first PMOS transistor MP1 (the source and drain of the second PMOS transistor MP2 are short-circuited, which is equivalent to a capacitor) through the first PMOS transistor MP1, so that the voltage of the adjustment signal VG reaches the power supply voltage VDD. <0> - Y <n>) and the read / write control signal (WE) act together on the gate of the second PMOS transistor MP2. At this time, the gate of the second PMOS transistor MP2 is at a high level. Then, when the decoded signal arrives, if the row decoding signal Y <0> At this time, the gate of the first PMOS tube MP1 is at the decoding signal Y <0> The gate of the second PMOS tube MP2 is turned high under the action of the decoding signal Y. <0> , which is equivalent to the lower plate voltage of the capacitor always maintaining a high level. When the upper plate output voltage of the capacitor supplies power to the word line selection circuit 170, due to the loss of charge, the adjustment signal VG will gradually decrease and be lower than the power supply voltage VDD. At this time, the adjustment signal VG is used for the write operation of the SRAM circuit. The read-write auxiliary circuit of the present invention uses fewer MOS transistors, and the source and drain of the second PMOS tube MP2 are short-circuited to replace the capacitor. It has strong compatibility with silicon MOS process and adopts the strategy of MOS transistor voltage reduction and capacitor coupling. The circuit can be used in combination with the word line selection circuit 170 in the SRAM circuit to achieve the purpose of lowering and raising the word line signal voltage value relative to the power supply voltage, generating two voltage values ​​of word line undervoltage (WLUD) and word line overvoltage (WLOD), thereby realizing read-assist and write-assist operations on the SRAM storage unit. And the use of this circuit does not require control signals other than the row decoding signal and the read-write signal. The auxiliary circuit read-write control signal WE is derived from the read-write control signal WE of the SRAM circuit. The row decoding signal (Y <0> - Y <n>) is derived from the output of the SRAM row decoding circuit. Therefore, the SRAM word line voltage regulation circuit does not require any changes to the original control signal and control timing, and is adaptive to the original SRAM circuit. During the read cycle, the regulation signal VG output by the auxiliary circuit is combined with the word line selection circuit to lower the voltage value of the word line signal, and the data is read from the SRAM memory cell. This can improve the static noise margin (SNM), avoid interference with the data stored in the SRAM memory cell, and enhance the read capability of the SRAM memory cell. During the write cycle, the regulation signal VG output by the auxiliary circuit using a capacitive coupling strategy is combined with the word line selection circuit to raise the voltage value of the word line signal, and write data to the SRAM memory cell. This improves the write noise margin (WSNM), improves the stability of the written data of the SRAM memory cell, avoids erroneous write operations on the SRAM stored data, and can enhance the write capability of the SRAM memory cell. The read / write assist circuit (SRAM wordline voltage regulation circuit) of the present invention improves the static noise margin (SNM) and write static noise margin (WSNM) of SRAM memory cells, enhancing the read / write capability of SRAM memory cells at low voltages, improving the read / write stability of SRAM memory cells, and ensuring the accuracy of read / write data. It also ensures that the timing control of read / write operations in the circuit is consistent with that of the original SRAM circuit, and the assist circuit is well adapted to the control logic of the original SRAM circuit.

[0047] In summary, in the SRAM word line voltage generation and regulation circuit provided in the embodiments of the present invention, the charging of the second PMOS transistor by the first PMOS transistor is controlled by a row decoding signal and a read / write control signal, thereby making the regulation signal of the word line decoding circuit equal to the power supply voltage, thereby controlling the SRAM word line voltage. This invention can control the SRAM word line voltage without requiring an external control signal, reducing the circuit's control difficulty. Furthermore, by using the second PMOS transistor for charging, capacitors can be eliminated, thereby reducing the area occupied by the regulation circuit.

[0048] The above description is merely a preferred embodiment of the present invention and does not limit the present invention in any way. Any person skilled in the art who, without departing from the scope of the present invention, makes any equivalent substitution, modification, or other changes to the technical solution and technical content disclosed in the present invention shall be deemed to be within the scope of the present invention and still fall within the scope of protection of the present invention.< / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n>

Claims

1. A circuit for regulating an SRAM word line voltage, characterized in that: include: A first n-input NAND gate, whose input terminal receives a row decoding signal from a word line decoding circuit; A first PMOS transistor, whose source is connected to a power supply voltage, and an output signal of the first n-input NAND gate is input to a gate of the first PMOS transistor after passing through two stages of inverters; a second n-input NAND gate, whose input receives the row decoding signal, wherein n is a positive integer; A NOR gate, whose input terminal is connected to the output signal of the second n-input NAND gate and the read / write control signal; The second PMOS tube has its source and drain short-circuited and connected to the drain of the first PMOS tube, and outputs the adjustment signal of the word line decoding circuit. The output signal of the NOR gate is input to the gate of the second PMOS tube after passing through a first-stage inverter.

2. The regulating circuit according to claim 1, wherein: The output signal of the first n-input NAND gate is input into the gate of the first PMOS transistor after passing through the first inverter and the second inverter. The output signal of the first n-input NAND gate is input into the output end of the first inverter. The output signal of the first inverter is input into the input end of the second inverter. The output signal of the second inverter is input into the gate of the first PMOS transistor.

3. The regulating circuit according to claim 1, wherein: The output signal of the NOR gate is input to the gate of the second PMOS tube after passing through the third inverter, the output signal of the NOR gate is input to the input end of the third inverter, and the output signal of the third inverter is output to the gate of the second PMOS tube.

4. The regulating circuit according to claim 1, wherein: The first n-input NAND gate and the second n-input NAND gate each include n input terminals, and each input terminal is connected to a row decoding signal.

5. The regulating circuit according to claim 4, wherein: The row decoding signals input to each input terminal are different.

6. The regulating circuit according to claim 1, wherein: When the read / write control signal is at a low level, the initial values ​​of all the row decoding signals are at a high level, the gate of the first PMOS tube is at a low level, the gate of the first PMOS tube is turned on, and the power supply voltage charges the second PMOS tube through the gate of the first PMOS tube.

7. The regulating circuit according to claim 1, wherein: When the read / write control signal is at a high level, the initial value of the row decoding signal is all at a high level, the gate of the first PMOS transistor is at a low level, the first PMOS transistor is turned on, and the power supply voltage charges the second PMOS transistor through the first PMOS transistor, so that the adjustment signal of the word line decoding circuit reaches the power supply voltage.

8. An SRAM word line voltage generating circuit, characterized in that: include: An SRAM memory cell for generating a word line voltage; A word line selection circuit controls the voltage of the word line voltage together with the adjustment signal of the word line decoding circuit generated by the adjustment circuit according to any one of claims 1 to 7.

9. The SRAM word line voltage generating circuit according to claim 8, wherein: The SRAM storage unit is a 6TSRAM memory.

10. The SRAM word line voltage generating circuit according to claim 9, wherein: The 6T SRAM memory includes two PMOS transistors and four NMOS transistors.

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