The present invention provides an SRAM word line
voltage regulation circuit, comprising: a first n-input
NAND gate, whose input receives a row decoding
signal from a word line decoding circuit; a first PMOS
transistor, whose source is connected to a
power supply voltage, and whose output
signal from the first n-input
NAND gate passes through two stages of inverters and is then input into the gate of the first PMOS
transistor; a second n-input
NAND gate, whose input receives the row decoding
signal; a
NOR gate, whose input receives the output signal of the second n-input NAND gate and a read / write
control signal; and a second PMOS
transistor, whose source and drain are short-circuited and connected to the drain of the first PMOS transistor, and which outputs the regulation signal from the word line decoding circuit. The output signal from the
NOR gate passes through a
single stage of inverters and is then input into the gate of the second PMOS transistor. The present invention can control the SRAM word line
voltage without requiring an external
control signal, reducing the circuit's control difficulty. Furthermore, by using the second PMOS transistor for charging, capacitors can be eliminated, thereby reducing occupied area.