A high-frequency schottky diode and a preparation method thereof

Abstract

The application is suitable for the technical field of semiconductor device manufacturing, and provides a high-frequency Schottky diode and a preparation method thereof. The preparation method comprises the following steps: preparing a lightly doped semiconductor layer on a heavily doped semiconductor layer; preparing a conductive layer on the lightly doped semiconductor layer, wherein the width of the conductive layer is smaller than that of the lightly doped semiconductor layer; preparing a passivation layer with a preset shape on the upper surface of the lightly doped semiconductor layer and the conductive layer, wherein the passivation layer does not cover the middle region of the conductive layer; performing wet etching on the conductive layer to form a guard ring and expose part of the lightly doped semiconductor layer; preparing a first electrode on the exposed part of the lightly doped semiconductor layer, and forming an air cavity between the first electrode, the passivation layer, the guard ring and the lightly doped semiconductor layer; and forming a second electrode on the lower surface of the heavily doped semiconductor layer. The method can easily realize a Schottky diode with small parasitic capacitance and high breakdown voltage, improve the working frequency and the withstand power, and effectively improve the yield and consistency of the diode device.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of semiconductor device manufacturing, and particularly relates to a high-frequency Schottky diode and a preparation method thereof. BACKGROUND

[0002] The Schottky diode is a kind of low-power and super-speed semiconductor device. The most prominent feature is that the reverse recovery time is extremely short, and the forward conduction voltage drop is only about 0.4 V. It is mostly used as a high-frequency, low-voltage and large-current rectifier diode, a freewheeling diode and a protection diode, and is also used as a rectifier diode and a small-signal detection diode in microwave communication circuits. It is commonly used in communication power supplies, frequency converters and the like.

[0003] With the increase of the working frequency of frequency multipliers and mixers and the like, the anode diameter of the Schottky diode needs to be reduced to below 1 micrometer to reduce the junction capacitance and improve the cutoff frequency, as shown in FIG. 1. Figure 1 However, the traditional Schottky diode is affected by the edge effect, resulting in breakdown. SUMMARY

[0004] To overcome the problems in the related art, the application embodiments provide a high-frequency Schottky diode and a preparation method thereof, which can easily realize a small parasitic capacitance of the Schottky diode, a high breakdown voltage, an improved working frequency and a high withstand power, and effectively improve the yield and consistency of the diode device.

[0005] The application is implemented by the following technical solutions:

[0006] In a first aspect, the application embodiments provide a preparation method of a high-frequency Schottky diode, comprising:

[0007] preparing a lightly doped semiconductor layer on a heavily doped semiconductor layer, wherein a first preset doping concentration of the lightly doped semiconductor layer is lower than a second preset doping concentration of the heavily doped semiconductor layer;

[0008] preparing a conductive layer on the lightly doped semiconductor layer, wherein the width of the conductive layer is smaller than the width of the lightly doped semiconductor layer;

[0009] preparing a passivation layer with a preset shape on the upper surface of the lightly doped semiconductor layer and the upper surface of the conductive layer, wherein the passivation layer does not cover the middle region of the conductive layer;

[0010] wet etching the conductive layer to form a protection ring and expose part of the lightly doped semiconductor layer;

[0011] preparing a first electrode on the exposed part of the lightly doped semiconductor layer, wherein an air cavity is formed between the first electrode, the passivation layer, the protection ring and the lightly doped semiconductor layer;

[0012] a second electrode is formed on the lower surface of the heavily doped semiconductor layer.

[0013] In a possible implementation manner of the first aspect, the preparing the passivation layer with the preset shape on the upper surface of the lightly doped semiconductor layer and the upper surface of the conductive layer comprises:

[0014] The passivation layer is prepared on the upper surface of the lightly doped semiconductor layer and the upper surface of the conductive layer, and the passivation layer covers the conductive layer;

[0015] A medium mask layer with a preset pattern is prepared on the outer side of the upper surface of the passivation layer, and the medium mask layer does not cover the middle region of the passivation layer

[0016] The passivation layer is etched to form the passivation layer with the preset shape.

[0017] In a possible implementation manner of the first aspect, after the first electrode is prepared, the medium mask layer is removed.

[0018] In a possible implementation manner of the first aspect, the wet etching of the conductive layer to form the guard ring comprises:

[0019] The conductive layer is wet etched by using an etching liquid with a preset temperature and a preset concentration to remove part of a target region of the conductive layer, so as to form the guard ring; in the projection of the conductive layer in the thickness direction, the opening region of the passivation layer is located in the target region, and the opening region corresponds to the middle region of the conductive layer.

[0020] In a possible implementation manner of the first aspect, the width of the guard ring is smaller than the width of the passivation layer with the preset shape.

[0021] The first lateral distance between the inner side of the guard ring and the first electrode is smaller than the second lateral distance between the inner side of the passivation layer with the preset shape and the first electrode.

[0022] In a possible implementation manner of the first aspect, the material of the conductive layer is metal or polysilicon.

[0023] In a possible implementation manner of the first aspect, the thickness of the conductive layer ranges from 1 nanometer to 1 micrometer.

[0024] In a possible implementation manner of the first aspect, the diameter of the first electrode ranges from 10 nanometers to 10 micrometers.

[0025] In a possible implementation manner of the first aspect, the lightly doped semiconductor with the first preset doping concentration is used to form an anode Schottky contact.

[0026] The heavily doped semiconductor with the second preset doping concentration is used to form a cathode ohmic contact.

[0027] In a second aspect, the embodiments of the present application provide a high-frequency Schottky diode, comprising:

[0028] a heavily doped semiconductor layer;

[0029] a lightly doped semiconductor layer formed on an upper surface of the heavily doped semiconductor layer, a first preset doping concentration of the lightly doped semiconductor layer being lower than a second preset doping concentration of the heavily doped semiconductor layer;

[0030] a guard ring formed on an upper surface of the lightly doped semiconductor layer, and a preset distance being provided between an outer edge of the guard ring and an outer edge of the lightly doped semiconductor layer;

[0031] a passivation layer formed on a portion of the lightly doped semiconductor layer close to an edge and on the guard ring, and an inner edge of the passivation layer exceeding an inner edge of the guard ring;

[0032] a first electrode formed on an exposed portion of the lightly doped semiconductor layer, the first electrode being located in the guard ring and not in contact with the guard ring, the first electrode, the passivation layer, the guard ring and the lightly doped semiconductor layer enclosing an air cavity;

[0033] a second electrode formed on a lower surface of the heavily doped semiconductor layer.

[0034] It can be understood that the beneficial effects of the above-mentioned second aspect can be referred to the related description in the above-mentioned first aspect, which will not be repeated here.

[0035] Compared with the prior art, the embodiments of the present application have the following beneficial effects:

[0036] In the embodiments of the present application, by preparing the passivation layer, the guard ring and the first electrode, the self-alignment of the guard ring, the air cavity and the first electrode is realized, and a Schottky diode with small parasitic capacitance and high breakdown voltage can be easily realized, thereby improving the working frequency and the withstand power, and effectively improving the yield and consistency of the diode device.

[0037] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit the present specification. BRIEF DESCRIPTION OF DRAWINGS

[0038] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the embodiments or prior art description will be briefly introduced. Obviously, the drawings in the following description only constitute some embodiments of the present application, and for those skilled in the art, other drawings can also be obtained without creative labor.

[0039] Figure 1 is a schematic diagram of a conventional Schottky diode structure provided by an embodiment of the present application;

[0040] Figure 2 is a schematic flow chart of a preparation method of a high-frequency Schottky diode provided by an embodiment of the present application;

[0041] Figure 3 is an initial effect diagram of a heavily doped semiconductor layer and a lightly doped semiconductor layer provided by an embodiment of the present application;

[0042] Figure 4 is an effect diagram of front sputtering of a conductive layer provided by an embodiment of the present application;

[0043] Figure 5 is an effect diagram of deposition of a passivation layer on a conductive layer provided by an embodiment of the present application;

[0044] Figure 6 is an effect diagram of formation of a protection ring by wet etching provided by an embodiment of the present application;

[0045] Figure 7 is an effect diagram of formation of an air cavity by sputtering method provided by an embodiment of the present application;

[0046] Figure 8 is an effect diagram of preparation of a second electrode provided by an embodiment of the present application;

[0047] Figure 9 is Figure 8 a cross-sectional view of a medium-high frequency Schottky diode at A-A. DETAILED DESCRIPTION

[0048] In the following description, for the purpose of explanation and not limitation, specific details are set forth, such as particular system configurations, techniques, etc., in order to provide a thorough understanding of the embodiments of the present application. However, it will be apparent to those skilled in the art that the present application can be practiced in other embodiments that depart from these specific details. In other instances, detailed descriptions of well-known systems, devices, circuits, and methods are omitted so as not to obscure the description of the present application with unnecessary detail.

[0049] It should be understood that the term "includes" when used in the specification and the appended claims herein is used to indicate the presence of features, integers, steps, operations, elements, and / or components but does not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0050] It should also be understood that the term "and / or" when used in the specification and the appended claims herein is intended to mean one or more of the associated listed items and includes all possible combinations of the associated listed items.

[0051] As used in the specification and the appended claims herein, the term "if' can be interpreted as meaning "when" or "once" or "in response to a determination" or "in response to a detection" depending on the context. Similarly, the phrase "if determined" or "if detected [the described condition or event]" can be interpreted to mean "once determined" or "in response to a determination" or "once detected [the described condition or event]" or "in response to a detection [the described condition or event]" depending on the context.

[0052] In addition, in the description of the application and the appended claims herein, the terms "first", "second", "third", etc. are used only to distinguish descriptions, and cannot be understood as indicating or implying relative importance.

[0053] Reference in the specification to "one embodiment" or "some embodiments" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the application. The appearances of the phrases "in one embodiment", "in some embodiments", "in other embodiments", "in additional embodiments", etc. in various places in the specification are not necessarily all referring to the same embodiment, although they can. The terms "comprising", "including", "having" and their variants are meant to be construed as "including but not limited to", unless otherwise specifically noted.

[0054] The present application adopts a guard ring structure to weaken the electric field peak and suppress the "edge effect" faced by traditional Schottky diodes, which are affected by the "edge effect" and cause breakdown.

[0055] In addition, for a Schottky diode device with a sub-micron diameter anode, the alignment between the anode and the guard ring is difficult to achieve, and the presence of the passivation layer increases the parasitic capacitance between the anode and the guard ring, affecting the cutoff frequency. The present application uses an air cavity to reduce the parasitic capacitance and improve the operating frequency.

[0056] The application will be further described in detail below in conjunction with the accompanying drawings and specific embodiments.

[0057] Figure 2 This is a schematic flowchart illustrating a method for fabricating a high-frequency Schottky diode according to an embodiment of this application, with reference to... Figure 2 The fabrication method of this high-frequency Schottky diode is described in detail below:

[0058] In step 101, a lightly doped semiconductor layer is prepared on the heavily doped semiconductor layer.

[0059] like Figure 3 As shown, a lightly doped semiconductor layer 202 is fabricated on a heavily doped semiconductor layer 201. The first preset doping concentration of the lightly doped semiconductor layer 202 is lower than the second preset doping concentration of the heavily doped semiconductor layer 201.

[0060] In one embodiment, a lightly doped semiconductor 202 with a first preset doping concentration is used to form an anode Schottky contact; and a heavily doped semiconductor 201 with a second preset doping concentration is used to form a cathode ohmic contact.

[0061] For example, the heavily doped semiconductor 201 and the lightly doped semiconductor 202 can be bulk doped semiconductors such as Si, Ge, GeSi, GaAs, InP, GaN, AlN, InN, SiC, ZnO, Ga2O3 or diamond. The lightly doped semiconductor has a lower concentration to facilitate the formation of an anode Schottky contact, while the heavily doped semiconductor has a higher concentration to facilitate the formation of a cathode ohmic contact.

[0062] In step 102, a conductive layer is prepared on the lightly doped semiconductor layer.

[0063] like Figure 4 As shown, a conductive layer 203 is fabricated on a lightly doped semiconductor layer 202. The width of the conductive layer 203 is smaller than the width of the lightly doped semiconductor layer 202.

[0064] In one embodiment, the conductive layer 203 is made of metal or polycrystalline silicon.

[0065] In one embodiment, the thickness of the conductive layer 203 sputtered on the front side ranges from 1 nanometer to 1 micrometer.

[0066] In step 103, a passivation layer of a predetermined shape is prepared on the upper surface of the lightly doped semiconductor layer and the upper surface of the conductive layer, wherein the passivation layer does not cover the central region of the conductive layer.

[0067] In one embodiment, step 103 may include:

[0068] A passivation layer 204 is prepared on the upper surface of the lightly doped semiconductor layer 202 and the upper surface of the conductive layer 203. The passivation layer 204 covers the conductive layer 203. Figure 5As shown in (a) of FIG. 2, a medium mask layer 205 is prepared on the outer side of the surface of the passivation layer 204. The medium mask layer 205 does not cover the middle region of the passivation layer 204, as shown in (b) of FIG. 2. Figure 5 As shown in (c) of FIG. 2, the passivation layer 204 is etched to form a passivation layer 204 of a preset shape, exposing the middle region of the conductive layer 203. Figure 5

[0069] For example, the passivation layer 204 can be made of a medium material commonly used in semiconductor processes, such as SiN, SiO2, AlN, HfO, NiO, etc.

[0070] For example, an anode hole is etched in the passivation layer 204 (i.e., an opening region in the middle of the passivation layer 204), as shown in (a) of FIG. 3. The anode hole diameter is in the range of 10 nanometers to 10 micrometers, which is the size of the first electrode (anode). The passivation layer 204 can be etched by ICP dry etching, and the photoresist is retained after the passivation layer 204 is etched. Figure 5

[0071] In step 104, the conductive layer is wet etched to form a protection ring and expose part of the lightly doped semiconductor layer.

[0072] In some embodiments, step 104 can include wet etching the conductive layer 203 by using a corrosion liquid of a preset temperature and a preset concentration to remove part of the target region of the conductive layer 203, thereby forming the protection ring 2031. In the projection of the conductive layer 203 in the thickness direction, the opening region of the passivation layer 204 is located in the target region of the conductive layer 203, and the opening region corresponds to the middle region of the conductive layer 203, as shown in (a) of FIG. 4. Figure 6

[0073] For example, the etching process is implemented by using a wet slow etching method, and the corrosion liquid of the preset temperature and the preset concentration is selected as a low-temperature and low-concentration corrosion liquid. The specific temperature and concentration can be selected according to actual conditions.

[0074] For example, by using a lateral etching method of a preset depth, the target region of the conductive layer 203 is larger than the opening region of the passivation layer 204 in the projection of the conductive layer 203 in the thickness direction.

[0075] In step 105, the first electrode is prepared on the exposed part of the lightly doped semiconductor layer, and an air cavity 207 is formed between the first electrode, the passivation layer, the protection ring, and the lightly doped semiconductor layer.

[0076] In one embodiment, after the first electrode 206 is prepared, the medium mask layer 205 is removed, as shown in (a) and (b) of FIG. 5. Figure 7 In one embodiment, the first electrode 206 is an anode.​​​

[0077] In an embodiment, the width of the protection ring 2031 is less than the width of the passivation layer 204 of the preset shape. The first lateral distance between the inner side of the protection ring 2031 and the first electrode 206 is less than the second lateral distance between the inner side of the passivation layer 204 of the preset shape and the first electrode 206.

[0078] For example, the conductive layer 203 under the passivation layer 204 near the anode hole is removed due to lateral etching to form the air cavity 207. The etching of the passivation layer 204, the preparation of the protection ring 2031, and the sputtering of the first electrode 206 are performed by the photolithography of step 103, and the self-alignment of the protection ring 2031, the air cavity 207, and the first electrode 206 is achieved. At the same time, the air cavity 207 reduces the parasitic capacitance of the anode by using the low dielectric constant of air, and also reduces the leakage current due to the reduction of the contact between the anode and the dielectric. Therefore, the air cavity 207 reduces the parasitic capacitance and the leakage current at the same time.

[0079] In an embodiment, the diameter of the first electrode 206 ranges from 10 nanometers to 10 micrometers.

[0080] In step 106, the second electrode is formed on the lower surface of the heavily doped semiconductor layer.

[0081] As shown in Figure 8 , the second electrode 208 is formed on the lower surface of the heavily doped semiconductor layer 201. The second electrode 208 is a cathode and is formed on the back surface of the material to form a longitudinal structure.

[0082] The preparation method of the high-frequency Schottky diode can improve the breakdown voltage and withstand power of the Schottky diode by using the protection ring structure. The protection ring is prepared by wet etching, and the self-alignment of the first electrode (anode), the protection ring, and the air cavity is achieved, which effectively improves the yield and consistency of the diode device. There is an air cavity between the first electrode (anode) and the protection ring, which is beneficial to reduce the parasitic capacitance and leakage current, and can improve the working frequency of the Schottky diode.

[0083] The embodiment of the present application also provides a high-frequency Schottky diode, which is described with reference to Figure 8 and Figure 9 The gallium oxide diode device includes a heavily doped semiconductor layer 201, a lightly doped semiconductor layer 202, a protection ring 2031, a passivation layer 204, a first electrode 206, and a second electrode 208.

[0084] The lightly doped semiconductor layer 202 is formed on the upper surface of the heavily doped semiconductor layer 201, and the first preset doping concentration of the lightly doped semiconductor layer 202 is lower than the second preset doping concentration of the heavily doped semiconductor layer 201. The guard ring 2031 is formed on the upper surface of the lightly doped semiconductor layer 202, and a preset distance is provided between the outer edge of the guard ring 2031 and the outer edge of the lightly doped semiconductor layer 202. The passivation layer 204 is formed on the edge-adjacent portion of the lightly doped semiconductor layer 202 and the guard ring 2031, and the inner edge of the passivation layer 204 exceeds the inner edge of the guard ring 2031. The first electrode 206 is formed on the exposed portion of the lightly doped semiconductor layer 202, the first electrode 206 is located in the guard ring 2031 and does not contact the guard ring 2031, and the first electrode 206, the passivation layer 204, the guard ring 2031 and the lightly doped semiconductor layer 202 form the air cavity 207. The second electrode 208 is formed on the lower surface of the heavily doped semiconductor layer 201.

[0085] It should be understood that the size of the serial number of each step in the above-mentioned embodiments does not mean the order of execution, and the execution order of each process should be determined according to its function and inherent logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0086] The above-described embodiments are only used to illustrate the technical solutions of the present application, but not limit it; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement for part of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application, and should be included in the protection scope of the present application.

Claims

1. A method for fabricating a high-frequency Schottky diode, characterized in that, include: Fabricating a lightly doped semiconductor layer on a heavily doped semiconductor layer; The first preset doping concentration of the lightly doped semiconductor layer is lower than the second preset doping concentration of the heavily doped semiconductor layer; A conductive layer is formed on the lightly doped semiconductor layer, wherein the width of the conductive layer is smaller than the width of the lightly doped semiconductor layer; A passivation layer of a predetermined shape is prepared on the upper surface of the lightly doped semiconductor layer and the upper surface of the conductive layer, wherein the passivation layer does not cover the central region of the conductive layer; The conductive layer is subjected to wet etching to form a protective ring, exposing a portion of the lightly doped semiconductor layer. The step of wet etching the conductive layer to form a protective ring includes: wet etching the conductive layer with a pre-set temperature and pre-set concentration of etching solution to remove a portion of the target area of ​​the conductive layer and form the protective ring; wherein, on the projection of the conductive layer in the thickness direction, the opening area of ​​the passivation layer is located in the target area, and the opening area corresponds to the middle area of ​​the conductive layer. A first electrode is fabricated at the exposed portion of the lightly doped semiconductor layer, and an air cavity is formed between the first electrode, the passivation layer, the protective ring, and the lightly doped semiconductor layer. A second electrode is formed on the lower surface of the heavily doped semiconductor layer.

2. The method for fabricating a high-frequency Schottky diode as described in claim 1, characterized in that, The step of preparing a passivation layer of a predetermined shape on the upper surface of the lightly doped semiconductor layer and the upper surface of the conductive layer includes: A passivation layer is prepared on the upper surface of the lightly doped semiconductor layer and the upper surface of the conductive layer, and the passivation layer covers the conductive layer; A dielectric mask layer with a preset pattern is prepared on the outer side of the upper surface of the passivation layer, wherein the dielectric mask layer does not cover the central region of the passivation layer; The passivation layer is etched to form the passivation layer of the preset shape.

3. The method for fabricating a high-frequency Schottky diode as described in claim 2, characterized in that, After the first electrode is fabricated, the dielectric mask layer is removed.

4. The method for fabricating a high-frequency Schottky diode as described in claim 1, characterized in that, The width of the protective ring is smaller than the width of the passivation layer of the preset shape; The first lateral distance between the inner side of the protective ring and the first electrode is less than the second lateral distance between the inner side of the passivation layer of the preset shape and the first electrode.

5. The method for fabricating a high-frequency Schottky diode as described in claim 1, characterized in that, The conductive layer is made of metal or polycrystalline silicon.

6. The method for fabricating a high-frequency Schottky diode as described in claim 1, characterized in that, The thickness of the conductive layer ranges from 1 nanometer to 1 micrometer.

7. The method for fabricating a high-frequency Schottky diode as described in claim 1, characterized in that, The diameter of the first electrode ranges from 10 nanometers to 10 micrometers.

8. The method for fabricating a high-frequency Schottky diode as described in claim 1, characterized in that, The lightly doped semiconductor having the first preset doping concentration is used to form an anode Schottky contact; The heavily doped semiconductor having the second preset doping concentration is used to form a cathode ohmic contact.

9. A high-frequency Schottky diode, characterized in that, The high-frequency Schottky diode is prepared by a method for preparing a high-frequency Schottky diode as described in any one of claims 1-8, comprising: Heavily doped semiconductor layer; A lightly doped semiconductor layer is formed on the upper surface of the heavily doped semiconductor layer, wherein the first preset doping concentration of the lightly doped semiconductor layer is lower than the second preset concentration of the heavily doped semiconductor layer; A protective ring is formed on the upper surface of the lightly doped semiconductor layer, and there is a predetermined distance between the outer edge of the protective ring and the outer edge of the lightly doped semiconductor layer; A passivation layer is formed on the portion of the lightly doped semiconductor layer near the edge and on the guard ring, with the inner edge of the passivation layer extending beyond the inner edge of the guard ring; A first electrode is formed on the exposed portion of the lightly doped semiconductor layer. The first electrode is located in the protective ring and does not contact the protective ring. The first electrode, the passivation layer, the protective ring, and the lightly doped semiconductor layer form an air cavity. The second electrode is formed on the lower surface of the heavily doped semiconductor layer.

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