Method of manufacturing a semiconductor device having a vertical structure and semiconductor device

Abstract

The application discloses a method for preparing a semiconductor device with a vertical structure and the semiconductor device. The method comprises: performing H-containing ion implantation on one side of a first substrate; forming a conductive layer on at least one of the first substrate and the surface of a second substrate; performing bonding at the conductive layer to form a first bonding body; performing a first annealing process on the first bonding body to make the first bonding body peel off, so as to form a second bonding body with the second substrate; forming a first epitaxial layer on the side of the second bonding body with the first substrate; forming a gate and a first electrode on the side of the first epitaxial layer away from the first substrate; and forming a second electrode on the side of the second bonding body with the second substrate. The method has at least one of the following advantages: the electrode end (such as a collector end or a drain end) with low resistance can be obtained relatively simply, the device processing process has better compatibility, the first substrate can be reused, and the production cost is relatively low.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor technology and semiconductor manufacturing, and in particular, the present application relates to a method for preparing a semiconductor device with a vertical structure and a semiconductor device. BACKGROUND

[0002] With the development of semiconductor technology in recent years, semiconductor devices based on semiconductor substrates such as silicon (Si) material and silicon carbide (SiC) have also developed rapidly. For example, the excellent properties of SiC can make semiconductor devices based on SiC wafers have smaller size, lower loss, higher frequency and better high-temperature resistance. However, the preparation of semiconductor devices based on high-quality SiC substrate materials is still difficult at present: the defect density of SiC crystals prepared by current industry is high, and the yield is low. Especially for large-size SiC crystals, the larger the size, the narrower the process window, the lower the yield, the more difficult to control the defect density, and the higher the preparation cost. The high defect density and high cost of the substrate material result in low yield of SiC devices, the device reliability is significantly affected by defects, and the device cost is high.

[0003] Therefore, the current SiC device preparation method still needs to be improved. SUMMARY

[0004] The present application is based on the discovery and understanding of the inventors of the following facts and problems:

[0005] In order to reduce the production cost of semiconductor devices based on the above-mentioned materials, the present application uses high-quality SiC substrates repeatedly for power devices (SBD, PiN diode, vertical MOSFET, BJT, JFET, IGBT, etc.) with vertical structure to reduce the cost of devices, and combines bonding and ion cutting technology to realize the preparation of low-cost vertical power devices. Specifically, the wafer bonding process is used to bond a semiconductor single crystal wafer (such as a SiC wafer) with high crystal quality and a semiconductor wafer with poor crystal quality but extremely low resistivity, and then the ion implantation and stripping technology is used to strip the bonding body in the high-quality wafer layer, realizing the transfer of the thin layer of high-quality crystal in the vertical power device. This method can obtain a collector or drain with low resistance structure more simply, and the high-quality SiC semiconductor wafer and other materials can be used again, not only saving the cost of high-quality wafers, but also avoiding the process difficulty of forming a low-resistance collector by ion implantation and high-temperature activation on the back surface in the vertical structure power device, and the process compatibility is good, so the production cost and process difficulty of preparing the vertical semiconductor device can be significantly reduced.

[0006] In one aspect of the present application, a method for preparing a semiconductor device with vertical structure is provided. The method comprises: performing H-containing ion implantation on one side of a first substrate, the first substrate being formed of non-silicon crystal material; forming a conductive layer on at least one of the surfaces of the first substrate and a second substrate, the second substrate having a resistivity of no more than 0.2 Ωcm; bonding the first substrate and the second substrate at the conductive layer to form a first bonded body; performing first annealing treatment on the first bonded body to cause the first bonded body to be peeled off at the depth of the H-containing ion implantation, so as to form a second bonded body with the second substrate; performing polishing treatment on the side surface of the second bonded body with the first substrate; forming a first epitaxial layer on the side surface of the second bonded body with the first substrate, the first epitaxial layer being lattice-matched with the first substrate; forming a gate and a first electrode on the side of the first epitaxial layer away from the first substrate; and forming a second electrode on the side of the second bonded body with the second substrate. The method has at least one of the following advantages: the low-resistance electrode terminal (such as the collector terminal or the drain terminal) can be obtained relatively easily, the device processing technology has good compatibility, the first substrate can be reused, and the production cost is relatively low.

[0007] According to an embodiment of the present application, the conductive layer satisfies at least one of the following conditions: the conductive layer is an amorphous layer, preferably the conductive layer comprises silicon carbide; and the conductive layer comprises metal silicide. In this way, the difficulty of bonding the first substrate and the second substrate can be reduced, so that the first bonded body can be obtained easily.

[0008] According to an embodiment of the present application, the first substrate is SiC single crystal material, and the SiC single crystal material satisfies the condition that the basal plane dislocation density is no more than 1500 / cm 2 . In this way, a high-quality crystal thin layer structure can be provided for the semiconductor device, so as to guarantee the crystal quality of the electrical function area of the device, thereby guaranteeing that the device performance is not affected by defects.

[0009] According to an embodiment of the present application, the second substrate is SiC material, and the crystal quality of the SiC material of the first substrate is better than that of the SiC material of the second substrate. In this way, by using the second substrate with low quality, on the one hand, the cost of preparing the semiconductor device by using the method can be further reduced; on the other hand, since the crystal quality does not need to be considered, the second substrate can be doped more heavily (heavy doping generally causes the crystal quality to deteriorate), so as to reduce the resistivity of the second substrate, and further reduce the series resistance of the semiconductor device in the on state, and improve the device performance.

[0010] According to an embodiment of the present application, the conductive layer is formed on the first substrate, and the H-containing ion implantation is performed on a side surface of the first substrate on which the conductive layer is formed, or the H-containing ion implantation is performed on the side surface of the first substrate after the conductive layer is formed on the side surface of the first substrate. Thus, the conductive layer can be easily obtained.

[0011] According to an embodiment of the present application, the conductive layer comprises silicon carbide, and the conductive layer is obtained by one or both of magnetron sputtering and ion implantation; or the conductive layer comprises metal silicide, and the H-containing ion implantation is performed on the first substrate having the conductive layer after the conductive layer is formed. The silicon carbide formed by magnetron sputtering or ion implantation is easy to be amorphized, and the amorphous silicon carbide or metal silicide can reduce the bonding difficulty of the first substrate and the second substrate. Thus, the conductive layer which can significantly reduce the bonding difficulty of the first substrate and the second substrate can be easily obtained.

[0012] According to an embodiment of the present application, when the conductive layer comprises metal silicide, forming the conductive layer further comprises forming a metal conductive sub-layer on a surface of the metal silicide. The metal conductive sub-layer is easy to realize high-strength bonding, and thus the bonding strength based on the conductive layer can be further improved.

[0013] According to an embodiment of the present application, the second substrate on a side of the second bonding body is thinned before the second electrode is formed. Thus, the series resistance of the device in the on state can be reduced, and the performance of the semiconductor device is further improved.

[0014] According to an embodiment of the present application, before the H-containing ion implantation is performed, the method further comprises epitaxially forming a second epitaxial layer on the surface of the first substrate, the H-containing ion implantation is performed on the second epitaxial layer, the second epitaxial layer serves as an ion implantation layer of the semiconductor device, and the peeling is completed in the second epitaxial layer. Thus, the defects on the surface and the subsurface of the first bonding body can be further reduced, the crystal quality is improved, and the performance of the semiconductor device is further improved.

[0015] According to an embodiment of the present application, after the first epitaxial layer is formed and before the gate is formed, the method further comprises etching a local region of the first epitaxial layer to form a trench, and forming a gate stack structure in the trench. Thus, the trench gate structure can be easily obtained, and the area of the semiconductor device is reduced, and the power density of the device is improved.

[0016] According to an embodiment of the present application, the first epitaxial layer is formed by metal organic chemical vapor deposition. Thus, the crystal quality of the first epitaxial layer made of SiC or the like can be further improved.

[0017] According to an embodiment of the present application, the semiconductor device is an IGBT device, the first epitaxial layer and the first substrate are both n-type conductive, the second substrate is p-type conductive, the first electrode is an emitter, and the second electrode is a collector. Thus, an IGBT device based on SiC or the like can be easily obtained.

[0018] According to an embodiment of the present application, the semiconductor device is a MOSFET device, the second substrate, the first substrate and the first epitaxial layer are all n-type conductive, the first electrode is a source, and the second electrode is a drain. Thus, a MOSFET device based on SiC or the like can be easily obtained.

[0019] According to an embodiment of the present application, after forming the first epitaxial layer and before forming the first electrode, the method further comprises: performing ion implantation on a local region of the surface of the first epitaxial layer to form a well region having p-type conductivity. Thus, a well region of the device can be easily formed for both IGBT and MOSFET structures.

[0020] In yet another aspect of the present application, a semiconductor device is provided. The semiconductor device is formed by the method described above. Thus, the semiconductor device has at least one of the following advantages: low production cost, low process difficulty, and good process compatibility.

[0021] According to an embodiment of the present application, the semiconductor device is an IGBT or a MOSFET. BRIEF DESCRIPTION OF DRAWINGS

[0022] Figure 1 is a flowchart of a method according to an embodiment of the present application;

[0023] Figure 2 is a flowchart of a method according to another embodiment of the present application;

[0024] Figure 3 is a flowchart of a method according to yet another embodiment of the present application;

[0025] Figure 4 is a structural diagram of an IGBT according to an embodiment of the present application;

[0026] Figure 5 is a structural diagram of an IGBT according to yet another embodiment of the present application;

[0027] Figure 6 is a structural diagram of a MOSFET according to an embodiment of the present application;

[0028] Figure 7 is a structural diagram of a MOSFET according to yet another embodiment of the present application. DETAILED DESCRIPTION

[0029] Embodiments of the present application are described in detail below with reference to the attached drawing figures, wherein the same or like component have the same or similar designations. The embodiments described below are presented by way of example to explain the present application, and are not intended to limit the present application.

[0030] In one aspect of the present application, a method for preparing a semiconductor device with a vertical structure is provided. The method uses a wafer bonding process to bond a semiconductor single crystal wafer (such as a SiC wafer) with high crystal quality and a semiconductor wafer with poor crystal quality but extremely low resistivity, and then uses an ion implantation and stripping technique to strip the bonded body in the high-quality wafer layer, thereby achieving the transfer of a thin layer of high-quality crystal in a vertical power device, and the high-quality SiC semiconductor wafer can be reused, which not only saves the cost of high-quality wafers, but also avoids the process difficulty of forming a low-resistance collector on the back surface of the vertical structure power device by ion implantation and high-temperature activation, and has good process compatibility. Since the device structure is vertical, the substrate of the semiconductor device can be thinned in the back surface process. According to the method of the embodiment of the present application, a conductive layer is introduced as a bonding interface during the preparation process, so the substrate does not need to be completely removed at this time, and the performance of the device will not be affected, and the process precision requirement for the final removal of the substrate can be reduced. Specifically, with reference to Figure 1 , the method can include the following steps:

[0031] S100: Perform H-containing ion implantation on one side of the first substrate

[0032] According to the embodiment of the present application, in this step, H-containing ion implantation is performed on one side of the first substrate, so that stripping is performed at the H-containing ion implantation depth in the subsequent processing steps. According to the embodiment of the present application, the first substrate can be a substrate with good crystal quality, so that the bonding body obtained in the subsequent processing steps can have a surface and a subsurface on one side of the first substrate with high crystal quality, thereby improving the quality of the semiconductor device with a vertical structure prepared based on the surface and the subsurface.

[0033] It should be particularly noted that in the present application, the first and second substrates are only used to distinguish the two substrates forming the bonding body, and cannot be understood as limiting the importance, and when the first and second substrates need to be pretreated before forming the first bonding body, such as cleaning, polishing and the like, the pretreatment process should not be understood as being performed in the order of the first and second substrates.

[0034] For example, in some embodiments of the present application, the first substrate can be a SiC single crystal wafer with good crystal quality, such as the crystal quality of the first substrate is at least better than that of the second substrate. For example, the first substrate with SiC can satisfy the basal plane dislocation (EPD) density of no more than 1500 / cm 2 . Alternatively, at least one of the following conditions is satisfied: the microtubule density satisfies no more than 0.5 / cm 2 , the threading screw dislocation (TSD) density is <1000 / cm 2 , and the threading edge dislocation (TED) density is <8000 / cm 2 . The material of the first substrate is not particularly limited, for example, can be formed of a non-silicon crystal material, for example, can be formed of a semiconductor material such as GaN, SiC, etc. According to some specific embodiments of the present application, the first substrate can be a SiC crystal, such as a single crystal of SiC. The second substrate can also be formed of a low resistivity SiC material. Specifically, when the first substrate is SiC, the second substrate can also be SiC, for example, can be formed of a heavily doped single crystal or polycrystalline SiC. When the first substrate is GaN, the second substrate can be Si or a SiC with poor crystal quality. It should be particularly noted here that the "SiC with poor crystal quality" specifically refers to a substrate formed of a silicon carbide material with a crystal quality slightly lower than that of the first substrate, specifically, a silicon carbide crystal that does not satisfy the aforementioned conditions for the aforementioned crystal quality parameters. For example, according to some specific examples of the present application, the specific conductivity type of the first substrate is not particularly limited, for example, can be a p-type semiconductor or an n-type semiconductor, and a person skilled in the art can select it according to the specific type of the semiconductor device. The second substrate can specifically be a polycrystalline SiC. In this way, on the one hand, the cost can be reduced, and on the other hand, the polycrystalline silicon carbide, whether p-type or n-type doped, can achieve a lower resistivity than single crystal SiC, thereby improving the performance of the SiC-based semiconductor device, which is extremely advantageous for IGBT and MOSFET with vertical structure formed thereon.

[0035] According to embodiments of the present application, the parameters such as the implantation dose and the implantation depth of the H-containing ion implantation in this step are not particularly limited, and similarly, can be selected according to the specific needs of the semiconductor device (i.e. the thickness required by the high-quality crystal thin layer peeled off from the first substrate in the semiconductor device). For example, the implantation dose can be no less than 5*10 15 cm -2 . For example, according to some specific examples of the present application, the H-containing ion implantation in this step can be performed at room temperature or high temperature (≤600 degrees Celsius), with an implantation dose of 1*10 16 ~1*10 17 cm -2 , specifically 5*10 16 cm-2 The implantation energy in this step can be tens of keV to several MeV, and the implantation depth can be tens of nanometers to tens of microns.

[0036] S200: forming a conductive layer on at least one of the first substrate and the second substrate

[0037] According to an embodiment of the present application, in this step, the conductive layer is formed to improve the bonding strength of the first and second substrates, so that the first and second substrates are bonded at the conductive layer in subsequent operations.

[0038] The inventors found that semiconductor devices based on wafer materials with high cost, high hardness or difficult to bond have the problem of difficult to dope the collector or drain on the substrate side, especially for semiconductor devices of non-silicon crystal materials such as SiC, GaN, diamond, AlN, etc. It is difficult to obtain a semiconductor substrate with low resistivity and a low ohmic contact resistance by a simple process. Moreover, this problem is also difficult to be alleviated by the traditional Smartcut technology: taking a silicon carbide-based vertical semiconductor device as an example, silicon-silicon direct bonding is difficult, and silicon carbide and silicon carbide crystal direct bonding is also difficult. Generally, the semiconductor bonding body interface adopts an oxide such as silicon dioxide as the bonding interface, but the silicon dioxide material is not conductive, which will have a certain impact on the subsequent semiconductor structure and performance; at the same time, silicon dioxide softens at 1200°C, which is unacceptable for device processing processes of 1600-1800°C for SiC devices. Therefore, using a conductive layer as the bonding interface layer for the subsequent formation of the bonding body can alleviate the impact of the non-conductive silicon oxide on the performance of the device, and the inventors found that for most hard semiconductor substrates that are difficult to bond, bonding in a mild environment can be achieved through the conductive layer.

[0039] According to some examples of the present application, the conductive layer can be an amorphous layer, for example, specifically including silicon carbide and metal silicide, for example, can be molybdenum silicide, titanium silicide, tantalum silicide, nickel silicide, tungsten silicide, etc. In some examples of the present application, the conductive layer can be formed of silicon carbide. The conductive layer formed of the above-mentioned materials, especially the amorphous layer of the above-mentioned materials, not only makes the bonding of the first and second substrate surfaces easier and improves the bonding strength, for example, the bonding of the two substrates can be achieved at a temperature lower than 600 degrees Celsius, but also does not affect the performance of the final semiconductor device. Taking an IGBT as an example, the resistivity of the conductive layer is very low, which can be used as the field cutoff layer of the device, so that it is not necessary to remove it in subsequent operations. According to some embodiments of the present application, the thickness of the conductive layer can be 1-1000 nm.

[0040] According to some embodiments of the present application, when the conductive layer contains silicon carbide, the conductive layer can be obtained by one or both of magnetron sputtering and ion implantation. Specifically, referring to Figure 2 The ion implantation can be performed first on one side of the first substrate 100, and then the conductive layer 10 can be formed on the surface of the first substrate 100. Alternatively, in some other embodiments, the conductive layer can be formed on both sides of the first and second substrates, such as 10A and 10B shown in FIG. 1C. Figure 3

[0041] According to some embodiments of the present application, when the conductive layer is formed by ion implantation, a high implantation dose can be obtained relatively easily, and the conductive layer can be amorphized relatively easily. According to some embodiments of the present application, when the first substrate is SiC, the ion-implanted elements can include one or more of Si, C, N, P, As, and Sb. Si and C are elements of silicon carbide itself, and do not introduce additional contamination. The elements including N, P, As, and Sb are beneficial to form an n-type semiconductor conductive layer. Preferably, the ion implantation can be plasma source ion implantation or plasma immersion ion implantation, which can obtain a large implantation dose at low cost and with ease, and the implanted surface can be amorphized easily, thereby facilitating the formation of an amorphous conductive layer.

[0042] According to some embodiments of the present application, when the conductive layer contains a metal silicide, the conductive layer can be formed first on one side of the first substrate, and then the ion implantation of H-containing ions on the first substrate can be performed. The metal silicide can be formed directly by deposition, or a metal layer can be formed first, and then annealing treatment can be performed on the metal layer to form the metal silicide. Specifically, a metal layer of Ni or the like can be formed first by a method including but not limited to magnetron sputtering, and then annealing treatment can be performed at a high temperature, such as 1100 degrees Celsius, to form a nickel silicide. Finally, a carbon precipitation layer formed during the annealing treatment can be removed by surface Ar ion back sputtering. In this way, a metal silicide with high bonding strength to the first substrate can be obtained.

[0043] According to some embodiments of the present application, when the conductive layer contains a metal silicide, the conductive layer can be formed first on one side of the first substrate, and then the ion implantation of H-containing ions on the first substrate can be performed. The metal silicide can be formed directly by deposition, or a metal layer can be formed first, and then annealing treatment can be performed on the metal layer to form the metal silicide. Specifically, a metal layer of Ni or the like can be formed first by a method including but not limited to magnetron sputtering, and then annealing treatment can be performed at a high temperature, such as 1100 degrees Celsius, to form a nickel silicide. Finally, a carbon precipitation layer formed during the annealing treatment can be removed by surface Ar ion back sputtering. In this way, a metal silicide with high bonding strength to the first substrate can be obtained.

[0044] ​According to specific examples of the present invention, the specific conductivity type of the second substrate is not particularly limited. For example, it can be a p-type semiconductor or an n-type semiconductor, and those skilled in the art can choose according to the specific type of the semiconductor device. For example, when the semiconductor device with the vertical structure is a MOSFET, the second substrate, the first substrate, and the subsequently formed first epitaxial layer can all be n-type conductive. When the semiconductor device with the vertical structure is an IGBT, the second substrate is p-type conductive, and the first substrate and the first epitaxial layer are n-type.

[0045] It should be noted that, according to some specific examples of the present invention, when the second substrate is p-type SiC, its resistivity is not higher than 0.2 Ωcm, preferably not higher than 0.01 Ωcm; when the second substrate is n-type SiC, its resistivity is not higher than 0.015 Ωcm, preferably not higher than 0.001 Ωcm.

[0046] S300: Bonding is performed at the conductive layer to form a first bond.

[0047] According to an embodiment of the present invention, in this step, the first and second substrates are bonded at the conductive layer to form a first bonded body.

[0048] For details, please refer to Figure 2 as well as Figure 3 The first substrate 100 and the second substrate 200 are bonded at the conductive layer to obtain the first bonded body 1000. The bonding process can be performed at room temperature or below 600 degrees Celsius. For example, the bonding can be performed directly in a vacuum chamber at room temperature, and the vacuum degree of the chamber can be <0.1 Pa.

[0049] According to some embodiments of the present invention, before bonding, the surfaces of the first and second substrates to be bonded may be subjected to surface activation treatment. Specifically, inert gas ion beams or plasma may be used to bombard the bonding surfaces to remove particulate contaminants and oxides from the surfaces, thereby maintaining the cleanliness of the bonding surfaces.

[0050] S400: The first bond is stripped at the H-ion implantation depth to form a second bond having the second substrate.

[0051] According to an embodiment of the present invention, reference Figure 2 as well as Figure 3 In this step, operations including but not limited to a first annealing process can be used to peel off the first bond at the H-ion implantation depth to obtain a second bond 2000 having the second substrate. Figure 2 as well as Figure 3As shown in the figure, the first bonding body 1000 is peeled off at the peeling boundary, and the first bonding body after peeling includes the remaining first substrate 100 and the second bonding body 2000 including the high-quality single-crystal thin film 100 (derived from the first substrate) derived from the first substrate. Thus, the bonding material can be obtained simply without long-time and high-temperature treatment, and is particularly suitable for forming a bonding material of SiC-SiC and the like.

[0052] According to some embodiments of the present application, the temperature of the first annealing treatment is above 600 degrees Celsius, and the specific temperature can be adjusted according to the H-containing ion implantation energy. The treatment at the above temperature can repair the damage in the substrate, and finally a second bonding body of the high-quality single-crystal thin film 100 with a thickness of tens of nanometers to tens of microns and the second substrate 200 with higher quality can be obtained. For example, when the semiconductor device prepared by the method is an n-channel IGBT device, the implantation energy of the H-containing ion implantation in the foregoing step can be 400 keV, the implantation depth can be 2 microns, and the temperature of the first annealing treatment can be 800-1000 degrees Celsius.

[0053] As understood by those skilled in the art, a second annealing treatment (with a temperature lower than the first annealing treatment) can be performed on the first bonding structure before the first annealing treatment, so as to further enhance the bonding degree and improve the interface quality. A third annealing treatment can be performed on the second bonding body after the first annealing treatment, so as to eliminate the damage layer generated in the bonding process. When the temperature of the first annealing treatment is higher than 1000 degrees Celsius, the second annealing treatment can be omitted, and the high-temperature first annealing treatment can repair the damage layer while peeling.

[0054] S500: polishing the surface of the second bonding body with the first substrate side and forming a first epitaxial layer

[0055] According to the embodiments of the present application, the first epitaxial layer is formed in this step. Specifically, the surface on which the first epitaxial layer is to be formed, i.e., the first substrate side of the second bonding body, can be polished first. The first epitaxial layer can be formed by metal organic chemical vapor deposition.

[0056] Reference Figure 2 The first epitaxial layer 110 is formed on the high-quality single-crystal thin film 100. Thus, the first epitaxial layer also has good crystal quality and is suitable for forming a drift region of a semiconductor device.

[0057] As mentioned above, the specific material of the first and second substrates in the present application is not particularly limited. For example, when the first and second substrates are both SiC, the first epitaxial layer formed thereon can also be SiC, and thus an IGBT or MOSFET device with a vertical structure can be obtained. When the method is used to form an IGBT or MOSFET device based on GaN, the first and second substrates can be GaN, and the first epitaxial layer formed thereon can be one of GaN / AlGaN / InAlN / InAlGaN or a multi-layer epitaxial composite structure.

[0058] According to embodiments of the present application, the semiconductor conductivity type of the first epitaxial layer is not particularly limited, and can be selected by those skilled in the art according to the semiconductor type of the substrate and the type of the device to be formed. Specifically, when the semiconductor device to be formed is an IGBT, the first epitaxial layer can have the same semiconductor type as the first substrate and the opposite semiconductor type to the second substrate, i.e., the first substrate and the epitaxial layer can both be n-type, and the second substrate can be p-type. Thus, an n-type doped drift region can be formed. When the semiconductor device to be formed is a MOSFET, the second substrate, the first substrate and the first epitaxial layer can all have the same conductivity type, e.g., all can be n-type.

[0059] According to some embodiments of the present application, the method for forming a semiconductor device can further comprise the following steps before the H-containing ion implantation: Figure 3 Specifically, the method for forming a semiconductor device can further comprise the following steps before the H-containing ion implantation: epitaxially forming a second epitaxial layer 120 on the surface of the first substrate. The second epitaxial layer has a first conductivity type, and the H-containing ion implantation is performed on the second epitaxial layer. The second epitaxial layer serves as an implantation layer of the semiconductor device, and the subsequent separation of the first bonded body 1000 can be performed in the second epitaxial layer 120. Specifically, the high-quality second epitaxial layer 120 in the second bonded body 2000 obtained after the separation of the first bonded body 1000 can serve as an epitaxial seed layer of the first epitaxial layer 110, and the remaining second epitaxial layer 120 on the side of the first substrate 100 can continue to be subjected to the aforementioned ion implantation. According to specific embodiments of the present application, the first substrate is a SiC single crystal, and the second epitaxial layer obtained by epitaxial growth has a better crystal quality than the first substrate, which can further reduce the defect density of the surface layer of the second bonded body. The first epitaxial layer can be further epitaxially obtained on the basis of the second epitaxial layer, which can further improve the crystal quality of the first epitaxial layer. The semiconductor conductivity type of the second epitaxial layer can be consistent with that of the first epitaxial layer, and the second epitaxial layer can serve as part of the drift region of the device.

[0060] As mentioned above, the first epitaxial layer 110 can serve as an electrically functional region of the semiconductor device, and thus the method for forming a semiconductor device can further comprise the following steps after the formation of the first epitaxial layer:

[0061] A local region of the surface of the first epitaxial layer is ion implanted to form a well region. Similar to the first and second substrates and the conductive layer described above, the conductive type of the well region formed can be determined according to the specific type of the semiconductor device. For example, for IGBT and MOSFET devices, a p-type conductive well region can be formed by ion implantation.

[0062] According to embodiments of the present application, the specific process of forming the well region is not particularly limited. For example, for silicon carbide-based devices, a shielding layer can be first formed on the surface of the first epitaxial layer, such as a silicon dioxide / silicon layer, and then a photolithography etching process is performed to form a shielding structure covering part of the surface of the first epitaxial layer, and then ion implantation and high-temperature annealing are performed to form a well region in the partial region. The type and dosage of the ions implanted in this step can be controlled according to the specific requirements of the device, for example, Al ion implantation can be performed to form a p-type well region. Referring to Figure 4 and Figure 5 When the semiconductor device formed is an IGBT, a heavily doped n+ type buffer region can be formed using the high-quality single-crystal thin film 100, and an n-type drift region is formed based on the first epitaxial layer 110, and then the well region 140 is formed by the above-described method of setting a shielding structure and implanting ions. Then, the above-described operation of setting a mask can be repeated to form a source region 130 in the p-type well region 140, which can be n+ type or formed by ion implantation, for example, by implanting nitrogen ions. Then, the etching shielding structure can be removed. According to some embodiments of the present application, the buffer layer and the drift region can both be formed directly in the above-described epitaxial process, and no further ion implantation doping can be performed. The high-quality single-crystal thin film 100 formed by the first substrate can be part of the drift region.

[0063] Similarly, when the semiconductor device formed is a MOSFET, a p-type well region can also be formed by a similar process. Referring to Figure 6 and Figure 7 A heavily doped region 150 can also be provided on the side of the well region 141. The source region 131 of the MOSFET can also be formed inside the well region 141. Among them, the heavily doped region 150 can have a p+ doping, and the source region 131 can be n+ type.

[0064] S600: Forming a gate and a first electrode on one side of the first epitaxial layer, and forming a second electrode on the side of the second substrate of the second bonding body

[0065] According to embodiments of the present application, referring to Figure 2 and Figure 3In this step, the gate 310 and the first electrode 400 can be formed on one side of the first epitaxial layer, and the second electrode 500, i.e. the back electrode, can be formed on the other side of the second substrate of the second bonding body. According to some embodiments of the present application, a gate oxide layer 300 can be formed between the gate 310 and the first epitaxial layer 110, and a dielectric layer 402 can be formed between the gate 310 and the first electrode 400. According to some embodiments of the present application, the gate oxide layer 300 can be formed by high-temperature oxidation of SiC, and the dielectric layer 402 can be formed by deposition using methods including but not limited to PECVD.

[0066] When the semiconductor device is an IGBT device, referring to Figure 4 and Figure 5 , the first electrode 400 is the emitter, and the second electrode 500 is the collector; when the semiconductor device is a MOSFET device, referring to Figure 6 and Figure 7 , the first electrode is the source 401, and the second electrode is the drain 501.

[0067] According to some embodiments of the present application, the gate structure of the semiconductor device is not particularly limited, and can be a planar gate structure or a trench gate structure. When the gate of the semiconductor device is a trench gate structure, a local area of the first epitaxial layer can be etched to form a trench before the gate is formed, and a trench-type gate stack structure can be formed in the trench. Specifically, referring to Figure 5 and Figure 7 , the shielding structure can also be formed by photolithography, and the first epitaxial layer can be etched to form a trench, and then the gate oxide layer 300, the polysilicon gate 310, etc. of the IGBT can be formed, and the dielectric layer 402 can be formed in advance before the emitter 400 of the IGBT device is formed, so as to separate the emitter 400 and the polysilicon gate 310 of the IGBT. Or the gate oxide layer 301, the polysilicon gate 311 of the MOSFET can be formed, and similarly, in order to separate the source 401 and the polysilicon gate 311 of the MOSFET, the method also includes the operation of forming the dielectric layer 402. In other embodiments, the trench gate can also be used as a mask for p-type well region implantation, i.e. the trench of the trench gate can be formed first, and then the well region is implanted to form the aforementioned well region.

[0068] According to some embodiments of the present application, the side of the second substrate of the second bonding body can be thinned before the second electrode is formed. Thus, the device resistance can be further reduced. As described above, the conductive layer formed in the aforementioned step can be used as a field stop layer. Moreover, since the second substrate has very low resistivity, the thickness of the thinning process does not need to be accurately controlled for accurate removal of the second substrate, and thus the production cost of the method can be further reduced. Finally, the back metal is deposited on the side of the second substrate, and annealing is performed to form an ohmic contact, thereby forming the second electrode.

[0069] In some embodiments of the present application, the method can further include high temperature oxidation to form a gate oxide layer, high temperature annealing to activate, etc. In some embodiments, the front side of the device can be passivated before forming the back metal, or other passivation layer structure, etc. When the first and second substrates are large size substrates, a plurality of devices can be formed on one substrate, and a plurality of semiconductor devices can be obtained by dicing.

[0070] In another aspect of the present application, a semiconductor device is provided. The semiconductor device is formed by the method described above, and has all the features and advantages of the method described above, which will not be repeated here. According to embodiments of the present application, the semiconductor device is an IGBT or a MOSFET.

[0071] In the description of the present specification, the description of the terms "one embodiment", "some embodiments", "an example", "a specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present application. In the present specification, the illustrative description of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any appropriate manner in any one or more embodiments or examples. In addition, the person skilled in the art can combine and combine the different embodiments or examples described in the present specification and the features of the different embodiments or examples without contradiction.

[0072] In addition, in the present application, the terms "first", "second" are only for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined with "first", "second" can explicitly or implicitly include at least one of the features.

[0073] Although the embodiments of the present application have been shown and described above, it should be understood that the above-described embodiments are exemplary and cannot be construed as limiting the present application, and those skilled in the art can make changes, modifications, replacements and variations to the above-described embodiments within the scope of the present application.

Claims

1. A method of fabricating a semiconductor device having a vertical structure, characterized by, The semiconductor device comprises: performing H-containing ion implantation on one side of a first substrate, the first substrate being formed of a non-silicon crystal material; forming a conductive layer on at least one of the surfaces of the first substrate and a second substrate, the second substrate having a resistivity of no higher than 0.2 Ω·cm; bonding the first substrate and the second substrate at the conductive layer to form a first bonded body; performing first annealing on the first bonded body to cause the first bonded body to be peeled at a depth of the H-containing ion implantation, thereby forming a second bonded body having the second substrate; polishing the surface of the first substrate on one side of the second bonded body; forming a first epitaxial layer on the surface of the first substrate on one side of the second bonded body, the first epitaxial layer being lattice-matched with the first substrate; forming a gate and a first electrode on a side of the first epitaxial layer away from the first substrate; forming a second electrode on a side of the second bonded body having the second substrate; before the H-containing ion implantation, further comprising epitaxially forming a second epitaxial layer on the surface of the first substrate, the H-containing ion implantation being performed on the second epitaxial layer, the second epitaxial layer serving as an ion implantation layer of the semiconductor device, and the peeling being performed in the second epitaxial layer; The first substrate is a SiC single crystal material, and the SiC single crystal material satisfies a basal plane dislocation density of not higher than 1500 / cm 2 ; the second epitaxial layer is epitaxially grown to have a better crystal quality than the first substrate; the second epitaxial layer has a semiconductor conductivity type consistent with that of the first epitaxial layer, and the second epitaxial layer serves as a part of a device drift region; the second substrate is formed of SiC material, and the SiC material of the first substrate has a better crystal quality than the SiC material of the second substrate.

2. The method of claim 1, wherein, The conductive layer satisfies at least one of the following conditions: the conductive layer is an amorphous layer, and the conductive layer comprises silicon carbide; the conductive layer comprises a metal silicide.

3. The method of claim 1, wherein, The conductive layer is formed on at least one of the following: a surface of the first substrate on which the H-containing ion implantation is performed, or a surface of the first substrate on which the conductive layer is formed, and then the surface is subjected to the H-containing ion implantation.

4. The method of claim 1, wherein, The conductive layer comprises silicon carbide, and the conductive layer is obtained by one or both of magnetron sputtering and ion implantation; or The conductive layer comprises a metal silicide, and the H-containing ion implantation is performed on the first substrate having the conductive layer on one side after the conductive layer is formed.

5. The method of claim 4, wherein, When the conductive layer comprises a metal silicide, forming the conductive layer further comprises forming a metal conductive sub-layer on a surface of the metal silicide.

6. The method of claim 1, wherein, The second bonded body having the second substrate on one side is thinned before the second electrode is formed.

7. The method of claim 1, wherein, After the first epitaxial layer is formed, before the gate is formed, further comprising: etching a local region of the first epitaxial layer to form a trench, and forming a trench-type gate stack structure in the trench.

8. The method of claim 1, wherein, The first epitaxial layer is formed by metal organic chemical vapor deposition.

9. The method of claim 1, wherein, The semiconductor device is an IGBT device, the first epitaxial layer and the first substrate are both n-type conductive, the second substrate is p-type conductive, the first electrode is an emitter, and the second electrode is a collector.

10. The method of claim 1, wherein, The semiconductor device is a MOSFET device, the second substrate, the first substrate and the first epitaxial layer are n-type conductive, the first electrode is a source electrode, and the second electrode is a drain electrode.

11. The method according to claim 9 or 10, characterized in that, Further comprising, after forming the first epitaxial layer and before forming the first electrode: Ion implantation is performed on a local region of the surface of the first epitaxial layer to form a well region with p-type conductivity.

12. A semiconductor device, characterized by comprising: The semiconductor device is formed by the method of any one of claims 1-11.

13. The semiconductor device of claim 12, wherein, The semiconductor device is an IGBT or a MOSFET.

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