Method for forming a gate dielectric layer

Abstract

The present application discloses a method for forming a gate dielectric layer, including: providing a substrate, the substrate including a cell region and a terminal region, a first trench being formed in the substrate of the cell region, a second trench being formed in the substrate of the terminal region, a first dielectric layer being formed on the surfaces of the substrate, the first trench and the second trench, a first shielding gate being formed in the first trench, and a second shielding gate being formed in the second trench; forming a second dielectric layer, the second dielectric layer filling the first trench but not filling the second trench; filling a barrier layer in the second trench; performing etching to remove the first dielectric layer and the second dielectric layer outside the first trench and the second trench; forming sidewalls on both sides of the portion where the barrier layer is higher than the second dielectric layer in the second trench; removing the first dielectric layer and the second dielectric layer at a predetermined depth above the first shielding gate in the first trench without exposing the first shielding gate; removing the remaining barrier layer and sidewalls; and forming a third dielectric layer on the sidewalls of the first trench.

Description

Technical Field

[0001] This application relates to the field of semiconductor integrated circuit manufacturing technology, and particularly to a method for forming a gate dielectric layer. Background Art

[0002] A metal-oxide-semiconductor field-effect transistor (MOSFET, simply referred to as "MOS" in this application) device is an electronic device applied to analog circuits and digital circuits.

[0003] Among them, the trench MOS (trench MOS) device has lower on-resistance and gate-drain charge density, thus having lower on-state and switching losses, and faster switching speed. It is usually used as a power device (also known as "electronic power device") and is widely applied in fields such as consumer electronics, new energy vehicles, servers, and control devices. Generally, on a wafer integrated with trench MOS devices, the surface electric field of the device can be reduced by setting a termination structure.

[0004] Reference Figure 1 , which shows a cross-sectional schematic diagram of a trench MOS device provided in the related art. Exemplarily, as Figure 1 shown, the substrate 110 includes a cell region 101 and a termination region 102. The cell region 101 is used to integrate MOS devices, and the termination region 102 is used to integrate a termination structure. A doped region 111 is formed on the substrate 110. A first shielding gate structure is formed in the doped region 111 of the cell region 101 and the substrate 110. The first shielding gate structure includes a first gate dielectric layer 121 and a polysilicon gate of the MOS device from the inside to the outside. The polysilicon gate includes a first shielding gate 131 and a first gate electrode 132 located above the first shielding gate 131. The first shielding gate 131 and the first gate electrode 132 are isolated by the first gate dielectric layer 121. Heavily doped regions 1121 and 1122 are formed in the doped regions 111 on both sides of the first shielding gate structure; a second shielding gate structure is formed in the doped region 111 of the termination region 102 and the substrate 110. The second shielding gate structure includes a second gate dielectric layer 122 and a polysilicon gate of the termination structure from the inside to the outside. The polysilicon gate includes a second shielding gate 133 and a second gate electrode 134 located above the second shielding gate 133. The second shielding gate 133 and the second gate electrode 134 are isolated by the second gate dielectric layer 122. Since the sidewall regions of the first gate dielectric layer 121 and the second gate dielectric layer 122 are formed simultaneously, the sidewall region of the second gate dielectric layer 122 is thinner and is prone to breakdown in the Figure 1 region indicated by the dashed ellipse.

[0005] In view of this, in the related art, a manufacturing method of a trench MOS device is provided. After the polysilicon layer is etched back, a dielectric layer is continuously filled and the cell region and the terminal region are simultaneously etched back, and then selective oxidation of the barrier layer is formed, so as to form a relatively thick gate dielectric layer on the sidewalls of the terminal structure.

[0006] Reference Figures 2 to 5 , which shows a schematic diagram of the formation of a trench MOS device provided in the related art: As Figure 2 shown, a first trench 1011 and a second trench 1012 are formed in the substrate 110. The first trench 1011 is used to form a first shielding gate structure, and the second trench 1012 is used to form a second shielding gate structure. A first dielectric layer 1201 is formed on the surface of the substrate 110 and the trenches (the first trench 1011 and the second trench 1012). After depositing a polysilicon layer and etching in sequence, the remaining polysilicon layer in the first trench 1011 forms a first shielding gate 131, and the remaining polysilicon layer in the second trench 1012 forms a second shielding gate 133; As Figure 3 shown, a second dielectric layer 1202 is filled in the trenches 1011 and 1022, and the dielectric layer outside the trenches is removed; As Figure 4 shown, a barrier layer 140 is formed on the substrate 110. A photoresist ( Figure 4 not shown in the figure) is covered on the barrier layer 140, exposing the regions above the first trench 1011 and the second trench 1012. Among them, the first trench 1011 is a repeating unit in which a plurality of trenches of the same size are connected in parallel, and the regions above need to be exposed simultaneously. Therefore, the width W1 of the exposed region above the first trench 1011 is greater than the width W2 of the exposed region above the second trench 1012. Etching is performed to remove the dielectric layer above the first shielding gate 131 in the first trench 1011, and to remove the dielectric layer in the middle region above the second shielding gate 133 in the second trench 1012. The remaining dielectric layer in the second trench 1012 forms the second gate dielectric layer 122 of the terminal structure; As Figure 5 shown, subsequently, a third dielectric layer is formed on the sidewalls above the first shielding gate 131. The third dielectric layer and the remaining first dielectric layer 1201 form the first gate dielectric layer 121 of the MOS device. A first gate 132 is formed above the first shielding gate 131, a second gate 134 is formed above the second shielding gate 133, a doped region 111 is formed in the substrate 110, and heavily doped regions 1121 and 1122 are formed in the doped regions 111 on both sides of the first shielding gate structure.

[0007] As described above, although the thickness of the sidewall gate dielectric layer of the terminal structure has been increased in the related art, different-sized windows need to be opened above the first trench and the second trench during its manufacturing process. As the size of the second trench 1012 continuously decreases, the exposed area above the second trench is greatly affected by the lithography process overlay error, resulting in a low yield. Summary of the Invention

[0008] The present application provides a method for forming a gate dielectric layer, which can solve the problem of low yield caused by the large influence of the overlay error in the manufacturing method of the gate dielectric layer of the trench-type MOS device provided in the related art. The method includes:

[0009] Providing a substrate, which, when viewed from above, includes a cell region and a terminal region. The cell region is used to integrate MOS devices, and the terminal region is used to integrate a terminal structure. A first trench is formed in the substrate of the cell region, and a second trench is formed in the substrate of the terminal region. A first dielectric layer is formed on the surfaces of the substrate, the first trench, and the second trench. A first shielding gate is formed in the first trench, and a second shielding gate is formed in the second trench. The top of the first shielding gate is lower than the opening of the first trench, and the top of the second shielding gate is lower than the opening of the second trench;

[0010] Forming a second dielectric layer, which fills the first trench but does not fill the second trench. The second dielectric layer is a conformal dielectric layer;

[0011] Filling a blocking layer in the second trench;

[0012] Performing etching to remove the first dielectric layer and the second dielectric layer outside the first trench and the second trench. After etching, the blocking layer is higher than the second dielectric layer in the second trench;

[0013] Forming sidewalls on both sides of the part where the blocking layer is higher than the second dielectric layer in the second trench;

[0014] Removing the first dielectric layer and the second dielectric layer at a predetermined depth above the first shielding gate in the first trench without exposing the first shielding gate;

[0015] Removing the remaining blocking layer and sidewalls;

[0016] Forming a third dielectric layer on the sidewalls of the first trench. The remaining first dielectric layer, second dielectric layer, and the third dielectric layer in the first trench constitute the gate dielectric layer of the MOS device, and the first dielectric layer and the second dielectric layer in the second trench form the gate dielectric layer of the terminal structure.

[0017] In some embodiments, the etching selectivity ratios of the barrier layer, the first dielectric layer, and the second dielectric layer are different;

[0018] The etching to remove the first dielectric layer and the second dielectric layer outside the first trench and the second trench includes:

[0019] Removing the first dielectric layer and the second dielectric layer outside the first trench and the second trench by wet etching.

[0020] In some embodiments, the first dielectric layer and the second dielectric layer include oxide layers.

[0021] In some embodiments, the filling of the barrier layer in the second trench includes:

[0022] Forming a barrier layer on the second dielectric layer;

[0023] Etching and removing the barrier layer outside the second trench.

[0024] In some embodiments, after forming the third dielectric layer on the sidewall of the first trench, the method further includes:

[0025] Forming a first gate above the first shielding gate and a second gate above the second shielding gate;

[0026] Forming a doped region in the substrate;

[0027] Forming heavily doped regions in the doped regions on both sides of the first shielding gate and the first gate.

[0028] In some embodiments, the impurity types doped in the doped region and the heavily doped region are different.

[0029] In some embodiments, the substrate is an epitaxial layer formed on a silicon substrate.

[0030] The technical solution of the present application has at least the following advantages:

[0031] During the manufacturing process of the trench-type MOS device, after forming the shielding gates of the MOS device and the shielding gate of the terminal structure, a dielectric layer is formed to fill the trench of the MOS device, thickening the sidewall of the trench of the terminal structure. By forming a barrier layer and sidewalls on both sides of the barrier layer to protect the dielectric layer on the sidewall of the trench of the terminal structure, and then removing the dielectric layer in the trench of the MOS device to form a thinner sidewall dielectric layer. Since it is not necessary to use photomasks with different window sizes for etching, the influence of overlay error is small and the yield is high. Description of the Drawings

[0032] To more clearly illustrate the specific embodiments of the present application or the technical solutions in the prior art, the following will briefly introduce the drawings required for the description of the specific embodiments or the prior art. Obviously, the drawings in the following description are some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0033] Figure 1 is a cross-sectional schematic diagram of a trench MOS device provided in the related art;

[0034] Figures 2 to 5 is a formation schematic diagram of a trench MOS device provided in the related art;

[0035] Figure 6 is a flowchart of a method for forming a gate dielectric layer provided in an exemplary embodiment of the present application;

[0036] Figures 7 to 14 is a formation schematic diagram of a trench MOS device provided in an exemplary embodiment of the present application. Specific Embodiments

[0037] The following will clearly and completely describe the technical solutions in the present application with reference to the drawings. Obviously, the described embodiments are some embodiments of the present application, rather than all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts fall within the protection scope of the present application.

[0038] In the description of the present application, it should be noted that the orientation or positional relationship indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the present application. In addition, the terms "first", "second", and "third" are only used for descriptive purposes and cannot be construed as indicating or implying relative importance.

[0039] In the description of the present application, it should be noted that unless otherwise clearly specified and defined, the terms "install", "connect", and "couple" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, an electrical connection; it can be directly connected, or indirectly connected through an intermediate medium, and can also be the internal communication of two components. It can be a wireless connection or a wired connection. For those of ordinary skill in the art, the specific meanings of the above terms in the present application can be understood according to specific circumstances.

[0040] In addition, the technical features involved in different embodiments of the present application described below can be combined with each other as long as they do not conflict with each other.

[0041] Referring to Figure 6 , which shows a flowchart of a method for forming a gate dielectric layer provided by an exemplary embodiment of the present application. This method can be applied to the manufacturing process of trench MOS devices, such as Figure 6 shown, the method includes:

[0042] Step S1: Provide a substrate, which includes a cell region and a terminal region. A first trench is formed in the substrate of the cell region, and a second trench is formed in the substrate of the terminal region. A first dielectric layer is formed on the surfaces of the substrate, the first trench, and the second trench. A first shielding gate is formed in the first trench, and a second shielding gate is formed in the second trench.

[0043] Referring to Figure 7 , which shows a cross-sectional schematic diagram after the formation of the first shielding gate and the second shielding gate. Exemplarily, as Figure 7 shown, from a top view, the substrate 310 includes a cell region 301 and a terminal region 302. The cell region 301 is used to integrate MOS devices, and the terminal region 302 is used to integrate terminal structures. A first trench 3011 is formed in the substrate 310 of the cell region 301, and a second trench 3012 is formed in the substrate 310 of the terminal region 302. The width of the second trench 3012 is greater than the width of the first trench 3011. A first dielectric layer 3201 is formed on the surfaces of the substrate 310, the first trench 3011, and the second trench 3012. A first shielding gate 331 is formed in the first trench 3011, and a second shielding gate 333 is formed in the second trench 3012. The top of the first shielding gate 331 is lower than the opening of the first trench 3011, and the top of the second shielding gate 333 is lower than the opening of the second trench 3012.

[0044] Among them, the substrate 310 can be an epitaxial layer formed on a silicon substrate (not shown in the figure). The first dielectric layer 3201 can be an oxide layer (for example, a silicon dioxide (SiO 2 ) layer). After the first trench 3011 and the second trench 3012 are etched in the substrate 310, the first dielectric layer 3201 can be formed on the surfaces of the substrate 310, the first trench 3011, and the second trench 3012 through a thermal oxidation process. After depositing a polysilicon layer, the polysilicon layer outside the first trench 3011 and the second trench 3012 and the polysilicon layer at a predetermined depth inside the first trench 3011 and the second trench 3012 are removed by etching. The remaining polysilicon layer in the first trench 3011 forms the first shielding gate 331, and the remaining polysilicon layer in the second trench 3012 forms the second shielding gate 333.

[0045] Step S2: Form a second dielectric layer. The second dielectric layer fills the first trench but does not fill the second trench. The second dielectric layer is a conformal dielectric layer.

[0046] Reference Figure 8 , which shows a cross-sectional schematic diagram of forming the second dielectric layer. Exemplarily, as Figure 8 shown, the second dielectric layer 3202 and the first dielectric layer 3201 are made of the same material, both can be oxide layers, and the second dielectric layer 3202 can be formed by depositing silicon dioxide or locally oxidizing the sidewall silicon material through chemical vapor deposition (CVD) process to achieve the denseness and conformality of the second dielectric layer 3202. The second dielectric layer 3202 fills the first trench 3011 but does not fill the second trench 3012. The second dielectric layer 3202 formed on the sidewalls of the second trench 3012 can be used as the sidewall gate dielectric layer of its gate later, and its thickness is relatively thick, thereby reducing the breakdown probability.

[0047] Step S3: Fill a barrier layer in the second trench.

[0048] Reference Figure 9 , which shows a cross-sectional schematic diagram of filling the barrier layer in the second trench. Exemplarily, as Figure 9 shown, Step S3 includes but is not limited to: forming a barrier layer 341 on the second dielectric layer 3202; etching and removing the barrier layer 341 outside the second trench 3012, and retaining the barrier layer 341 filled in the second trench 3012. Among them, the etching selectivity of the barrier layer 341 is different from that of the first dielectric layer 3201, the second dielectric layer 3202, and the subsequent formed third dielectric layer 3203. It can be a nitride layer (for example, a silicon nitride (SiN) layer), and the barrier layer 341 can be formed by depositing silicon nitride through CVD process.

[0049] Step S4: Perform etching to remove the first dielectric layer and the second dielectric layer outside the first trench and the second trench. After etching, the barrier layer is higher than the second dielectric layer in the second trench.

[0050] Reference Figure 10 , which shows a cross-sectional schematic diagram after removing the first dielectric layer and the second dielectric layer outside the first trench and the second trench. Exemplarily, as Figure 10 shown, the first dielectric layer 3201 and the second dielectric layer 3202 outside the first trench 3011 and the second trench 3012 can be removed by wet etching. After etching, the barrier layer 341 is higher than the second dielectric layer 3202 in the second trench 3012.

[0051] Step S5: Form sidewalls on both sides of the part where the barrier layer is higher than the second dielectric layer in the second trench.

[0052] Reference Figure 11 , which shows a cross-sectional schematic diagram of forming spacers on both sides of the barrier layer. Exemplarily, as Figure 11 shown, the material of the spacer 342 is the same as that of the barrier layer 341. After depositing a silicon nitride layer by CVD process, the redundant silicon nitride layer can be etched away to form spacers 342 on both sides of the part where the barrier layer 341 is higher than the second dielectric layer 3202 in the second trench 3012.

[0053] Step S6, removing the first dielectric layer and the second dielectric layer with a predetermined depth above the first shielding gate in the first trench without exposing the first shielding gate.

[0054] Reference Figure 12 , which shows a cross-sectional schematic diagram of removing the first dielectric layer and the second dielectric layer with a predetermined depth above the first shielding gate in the first trench. Exemplarily, as Figure 12 shown, the first dielectric layer 3201 and the second dielectric layer 3202 with a predetermined depth above the first shielding gate 331 in the first trench 3011 can be removed by wet etching process. Due to the protection of the spacer 331, the reaction solution in the wet etching will not etch the second dielectric layer 3202 in the second trench 3012. After etching, the remaining second dielectric layer 3202 in the first trench 3011 can be used as an isolation layer between the first shielding gate 331 and the subsequently formed first gate 332.

[0055] Step S7, removing the remaining barrier layer and spacers.

[0056] Reference Figure 13 , which shows a cross-sectional schematic diagram after removing the remaining barrier layer and spacers. Exemplarily, as Figure 13 shown, the remaining barrier layer and spacers can be removed by wet etching process.

[0057] Step S8, forming a third dielectric layer on the sidewalls of the first trench. The remaining first dielectric layer, second dielectric layer and third dielectric layer in the first trench constitute the gate dielectric layer of the MOS device, and the first dielectric layer and the second dielectric layer in the second trench form the gate dielectric layer of the terminal structure.

[0058] Optionally, after step S8, it further includes: forming a first gate 332 above the first shielding gate 331, and forming a second gate 334 above the second shielding gate 333; forming a doped region 311 in the substrate 310; forming heavily doped regions 3121, 3122 in the doped regions 311 on both sides of the first shielding gate 331 and the first gate 332.

[0059] Reference Figure 14 , which shows a cross-sectional schematic diagram after forming the MOS device and the terminal structure. Exemplarily, as Figure 14As shown in the figure, the third dielectric layer 3203 can be formed by a CVD process. The third dielectric layer 3203 in other regions except the first trench 3011 is removed by etching. The remaining first dielectric layer 3201, second dielectric layer 3202, and third dielectric layer 3203 in the first trench 3011 constitute the gate dielectric layer of the MOS device. The thickness of the third dielectric layer 3203 above the first shielding gate 331 in the first trench 3011 is less than the thickness of the second dielectric layer 3202 above the second shielding gate 333 in the second trench 3012. After the polysilicon layer is formed, the polysilicon layer outside the first trench 3011 and the second trench 3012 can be removed by etching. The polysilicon layer in the remaining first trench 3011 forms the first gate 332, and the polysilicon layer in the remaining second trench 3012 forms the second gate 334. A doped region (which can be used as the well region of the MOS device) 311 can be formed in the substrate 310 by ion implantation. Ion implantation can be performed through a photolithography process to form heavily doped regions 3121 and 3122 in the doped region 311 on both sides of the first gate 332. Among them, the heavily doped region 3121 can be used as the source electrode of the MOS device, and the heavily doped region 3122 can be used as the drain electrode of the MOS device.

[0060] Among them, the impurity concentration of the heavily doped regions 3121 and 3122 is greater than that of the doped region 311, and the types of impurities doped in the doped region 311 and the heavily doped regions 3121 and 3122 are different. For example, if the impurity doped in the doped region 311 is an N (negative) type impurity, then the impurities doped in the heavily doped regions 3121 and 3122 are P (positive) type impurities; if the impurity doped in the doped region 311 is a P type impurity, then the impurities doped in the heavily doped regions 3121 and 3122 are N type impurities.

[0061] In summary, in the embodiments of the present application, during the manufacturing process of the trench-type MOS device, after forming the shielding gate of the MOS device and the shielding gate of the terminal structure, a dielectric layer is formed to fill the trench of the MOS device, the trench sidewall of the terminal structure is thickened, and the dielectric layer on the trench sidewall of the terminal structure is protected by forming a barrier layer and sidewalls on both sides of the barrier layer. Then, the dielectric layer in the trench of the MOS device is removed to form a thinner sidewall dielectric layer. Since it is not necessary to use photomasks with different window sizes for etching, the influence of overlay error is small and the yield is high.

[0062] Obviously, the above embodiments are only examples clearly described and not limitations on the implementation manners. For those of ordinary skill in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to enumerate all implementation manners here. The obvious changes or modifications derived therefrom are still within the protection scope of the present invention.

Claims

1. A method for forming a gate dielectric layer, characterized in that, the method is applied to the manufacturing process of a trench MOS device, and the method includes: providing a substrate, which, when viewed from a top-down perspective, includes a cell region and a terminal region. The cell region is used to integrate MOS devices, and the terminal region is used to integrate terminal structures. A first trench is formed in the substrate of the cell region, and a second trench is formed in the substrate of the terminal region. The width of the second trench is greater than the width of the first trench. A first dielectric layer is formed on the surfaces of the substrate, the first trench, and the second trench. A first shielding gate is formed in the first trench, and a second shielding gate is formed in the second trench. The top of the first shielding gate is lower than the opening of the first trench, and the top of the second shielding gate is lower than the opening of the second trench; forming a second dielectric layer, which fills the first trench but does not fill the second trench, and the second dielectric layer is a conformal dielectric layer; filling a blocking layer in the second trench; performing etching to remove the first dielectric layer and the second dielectric layer outside the first trench and the second trench. After etching, the blocking layer is higher than the second dielectric layer in the second trench; forming sidewalls on both sides of the part where the blocking layer is higher than the second dielectric layer in the second trench; removing the first dielectric layer and the second dielectric layer with a predetermined depth above the first shielding gate in the first trench without exposing the first shielding gate; removing the remaining blocking layer and sidewalls; forming a third dielectric layer on the sidewalls of the first trench. The remaining first dielectric layer, second dielectric layer, and the third dielectric layer in the first trench constitute the gate dielectric layer of the MOS device, and the first dielectric layer and the second dielectric layer in the second trench form the gate dielectric layer of the terminal structure.

2. The method according to claim 1, characterized in that, the etching selectivity ratios of the blocking layer and the first dielectric layer and the second dielectric layer are different; the performing etching to remove the first dielectric layer and the second dielectric layer outside the first trench and the second trench includes: removing the first dielectric layer and the second dielectric layer outside the first trench and the second trench by wet etching.

3. The method according to claim 2, characterized in that, the first dielectric layer and the second dielectric layer include an oxide layer.

4. The method according to claim 3, characterized in that, the filling a blocking layer in the second trench includes: forming a blocking layer on the second dielectric layer; etching to remove the blocking layer outside the second trench.

5. The method according to any one of claims 1 to 4, characterized in that, after forming the third dielectric layer on the sidewalls of the first trench, it further includes: forming a first gate above the first shielding gate and a second gate above the second shielding gate; forming a doped region in the substrate; forming a heavily doped region in the doped regions on both sides of the first shielding gate and the first gate.

6. The method according to claim 5, characterized in that, the impurity types doped in the doped region and the heavily doped region are different.

7. The method according to claim 6, It is characterized in that the substrate is an epitaxial layer formed on a silicon substrate.

Images