Electronic packaging and manufacturing method thereof

Abstract

An electronic package and its manufacturing method include embedding an electronic component having a conductive layer on its outer surface into a coating layer, wherein the active surface of the electronic component has at least one electrode pad, and the interior of the electronic component is provided with at least one wire electrically connected to the electrode pad, so that the conductive layer is electrically connected to the wire, so that the electrode pad, the wire and the conductive layer serve as a power transmission structure, and the power transmission structure serves as a current path to reduce DC resistance and improve the impedance problem caused by the current supply.

Description

Technical Field

[0001] The present invention relates to a semiconductor packaging process, and in particular to an electronic package capable of supplying power and a manufacturing method thereof. Background Art

[0002] To ensure the continued miniaturization and multifunctionality of electronic products and communications equipment, semiconductor packaging must evolve towards miniaturization to facilitate multi-pin connections, high-speed operation, and high functionality. For example, in advanced process packaging, commonly used packaging types include 2.5D packaging processes and fan-out (Fan-Out) wiring with embedded bridge (Embedded Bridge) components (FO-EB). FO-EB offers advantages over 2.5D packaging processes, such as low cost and a wider range of material suppliers.

[0003] Figure 1 FIG1 is a cross-sectional schematic diagram of a conventional FO-EB semiconductor package 1. The semiconductor package 1 comprises a first semiconductor chip 11 and a plurality of conductive pillars 13 disposed on a substrate structure 10 having a circuit layer 101. The semiconductor chip 11 and the conductive pillars 13 are then encapsulated with a cladding layer 15. A wiring structure 16 electrically connecting the first semiconductor chip 11 and the conductive pillars 13 is then formed on the cladding layer 15. A plurality of second semiconductor chips 14 electrically connected to the wiring structure 16 are then disposed on the wiring structure 16. The second semiconductor chips 14 are then encapsulated with an encapsulation layer 18. The circuit layer 101 and the wiring structure 16 utilize fan-out redistribution layer (RDL) specifications. The first semiconductor chip 11 serves as a bridging element embedded in the cladding layer 15 to electrically bridge two adjacent second semiconductor chips 14.

[0004] In the conventional semiconductor package 1, the substrate structure 10 is mounted on a circuit board 1a via a plurality of solder balls 12, and the conductive pillars 13 are electrically connected to the circuit layer 101, so that a portion of the conductive pillars 13 cooperate with the circuit layer 101 and the wiring structure 16 as a power transmission structure, so that the circuit board 1a can provide the power required by the second semiconductor chip 14 away from the circuit board 1a through the circuit layer 101 and the conductive pillars 13.

[0005] However, in the conventional semiconductor package 1, for the electronic components above the wiring structure 16, the closer they are to the center of the first semiconductor chip 11, the greater the DC resistance generated, resulting in poor power supply capability, that is, the power transmission path is too long, resulting in increased impedance (such as Figure 2FAs shown in the impedance curve L2), some electronic components above the wiring structure 16 often experience power shortages or even power failures. For example, the power supply contact 17 of the second semiconductor chip 14 on the right side above the wiring structure 16 is located above the contact 110 at the center of the first semiconductor chip 11, and the power supply end of the circuit board 1a transmits power through the wiring layer 101 to the Figure 1 The right conductive pillar 13 transmits power to the power contact 17 via the wiring structure 16 , so the power transmission path is extremely long, resulting in excessive impedance, making the right second semiconductor chip 14 above the wiring structure 16 prone to power failure.

[0006] Therefore, how to overcome the above-mentioned problems of the prior art has become a topic that needs to be solved urgently. Summary of the Invention

[0007] In view of the above-mentioned defects in the prior art, the present invention provides an electronic package and a manufacturing method thereof, which can reduce DC resistance and improve the impedance problem generated by current supply.

[0008] The electronic package of the present invention includes: a coating layer; a first electronic component embedded in the coating layer, wherein the first electronic component has an active surface and an inactive surface relative to each other and side surfaces adjacent to the active surface and the inactive surface, the active surface has at least one electrode pad, and the interior of the first electronic component is provided with at least one wire electrically connected to the electrode pad; and a conductive layer formed on the surface of the first electronic component and embedded in the coating layer and electrically connected to the wire, wherein the conductive layer is not formed on the electrode pad.

[0009] The present invention also provides a method for manufacturing an electronic package, comprising: providing a first electronic component having a conductive layer on its surface, wherein the first electronic component has an active surface and an inactive surface relative to each other and side surfaces adjacent to the active surface and the inactive surface, the active surface has at least one electrode pad, and at least one wire electrically connected to the electrode pad is configured inside the first electronic component so that the conductive layer is electrically connected to the wire, and the conductive layer is not formed on the electrode pad; and embedding the first electronic component together with the conductive layer in a covering layer.

[0010] In the aforementioned electronic package and its manufacturing method, the electrode pad is located in the middle of the active surface.

[0011] In the aforementioned electronic package and its manufacturing method, the conductive wire is exposed on the side surface and / or the inactive surface of the first electronic component to contact the conductive layer.

[0012] In the aforementioned electronic package and its manufacturing method, the conductive layer is formed on the inactive surface and / or the side surface of the first electronic component.

[0013] The aforementioned electronic package and method for manufacturing the same further include forming a wiring structure on the coating layer, wherein the wiring structure is electrically connected to the electrode pad. For example, the wiring structure has a first surface and a second surface opposite each other, such that the coating layer and the first electronic component are disposed on the first surface, and at least one second electronic component electrically connected to the wiring structure is disposed on the second surface. Furthermore, a plurality of the second electronic components are disposed on the second surface of the wiring structure, such that the first electronic component electrically bridges two of the plurality of the second electronic components.

[0014] The aforementioned electronic package and its manufacturing method further include embedding a conductive pillar in the coating layer, for example, further including forming a plurality of conductive elements on the coating layer, wherein the plurality of conductive elements electrically connect the conductive layer and the conductive pillar.

[0015] The aforementioned electronic package and its manufacturing method further include forming a plurality of conductive elements on the coating layer, and the plurality of conductive elements are electrically connected to the conductive layer.

[0016] In the aforementioned electronic package and its manufacturing method, a plurality of mutually separated and unconnected conductive wires are disposed inside the first electronic component, and a plurality of mutually separated and unconnected conductive layers are formed on the first electronic component so that the plurality of conductive wires are electrically connected to different conductive layers respectively.

[0017] As can be seen from the above, in the electronic package and its manufacturing method of the present invention, the conductive layer is mainly formed on the first electronic component and electrically connected to the wire, so that the electrode pad, wire and conductive layer serve as a power transmission structure. Therefore, compared with the prior art, in addition to the conductive column as the current path, the electronic package of the present invention has other current paths composed of the electrode pad, wire and conductive layer to reduce the DC resistance of the electronic package, thereby improving the impedance problem caused by the current supply. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 Schematic cross-sectional view of a conventional semiconductor package.

[0019] Figure 1-1 for Figure 1 FIG. 1 is a partial top view of a first semiconductor chip.

[0020] Figures 2A to 2E FIG. 1 is a cross-sectional view of a method for manufacturing an electronic package according to a first embodiment of the present invention.

[0021] Figure 2E-1 for Figure 2E A cross-sectional schematic diagram of another embodiment of the present invention.

[0022] Figure 2F FIG. 4 is a schematic diagram of the impedance distribution curves of the electronic package of the present invention and the conventional semiconductor package.

[0023] Figure 2F-1 for Figure 2E A partial top view of a first electronic component is shown.

[0024] Figures 3A to 3D It is a cross-sectional schematic diagram of a method for manufacturing an electronic module of an electronic package of the present invention.

[0025] Figure 4A and Figure 4B FIG. 1 is a schematic cross-sectional view of a second embodiment of an electronic package according to the present invention.

[0026] Description of Reference Numerals

[0027] 1:Semiconductor package

[0028] 1a: Circuit board

[0029] 10: Substrate structure

[0030] 101: Circuit layer

[0031] 11: First semiconductor chip

[0032] 110,210a,300a: Contact

[0033] 12: Solder balls

[0034] 13,23: conductive column

[0035] 14: Second semiconductor chip

[0036] 15,25: coating

[0037] 16,26 wiring structure

[0038] 17: Power contact

[0039] 18,28: Encapsulation layer

[0040] 2,4: Electronic packaging

[0041] 20: Bearing structure

[0042] 20a: First side

[0043] 20b: Second side

[0044] 200: first dielectric layer

[0045] 201: First circuit layer

[0046] 21,30: First Electronic Component

[0047] 21a, 30a: Action surface

[0048] 21b, 30b: non-active surface

[0049] 21c, 30c: side

[0050] 210,300:Electrode pads

[0051] 211,301,410,411,412: Wire

[0052] 212: Conductor

[0053] 213: Insulation protective film

[0054] 22,32,42: conductive layer

[0055] 22a, 42a: first conductive layer

[0056] 22b, 42b: second conductive layer

[0057] 24,44: Second electronic component

[0058] 26a: first surface

[0059] 26b: Second surface

[0060] 260: second dielectric layer

[0061] 261: Second circuit layer

[0062] 27: Conductive bump

[0063] 29: Conductive element

[0064] 3: Electronic module

[0065] 40a: first connecting portion

[0066] 40b: Second connecting portion

[0067] 5: Wafer

[0068] 7: Electronic devices

[0069] 70,71: Power supply end

[0070] 8,9: bearing parts

[0071] 90:Plate body

[0072] 91: Binding layer

[0073] L, S: cutting path. DETAILED DESCRIPTION

[0074] The following describes the embodiments of the present invention through specific embodiments. Those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification.

[0075] It should be noted that the structures, proportions, sizes, etc. illustrated in the drawings of this specification are only used to match the contents disclosed in the specification for the understanding and reading of those skilled in the art, and are not used to limit the conditions under which the present invention can be implemented. Therefore, they have no substantial technical significance. Any structural modification, change in proportional relationship, or adjustment in size should still fall within the scope of the technical content disclosed by the present invention without affecting the efficacy and purpose that can be achieved by the present invention. At the same time, terms such as "on", "first", "second" and "one" quoted in this specification are only for the convenience of description and are not used to limit the scope of the implementation of the present invention. Changes or adjustments in their relative relationships should also be regarded as the scope of the implementation of the present invention without substantially changing the technical content.

[0076] Figures 2A to 2E FIG1 is a cross-sectional view of a first embodiment of the electronic package 2 of the present invention. In this embodiment, the electronic package 2 is manufactured using a FO-EB method.

[0077] like Figure 2A As shown, a first electronic component 21 having a conductive layer 22 on one surface is provided. The first electronic component 21 is then placed on a supporting structure 20 that is bonded to a carrier 9. The supporting structure 20 has a first side 20a and a second side 20b that are opposite each other, such that the first electronic component 21 is placed on the first side 20a of the supporting structure 20. A plurality of conductive pillars 23 (e.g., made of copper metal or solder) are disposed on the first side 20a of the supporting structure 20. Alternatively, in one embodiment, the first electronic component 21 having the conductive layer 22 may be first placed on the first side 20a of the supporting structure 20 and then bonded to the carrier 9.

[0078] In this embodiment, the carrier structure 20 is, for example, a package substrate with a core layer and a circuit structure, a package substrate with a coreless circuit structure, a through-silicon interposer (TSI) with conductive through-silicon vias (TSVs), or other board types. The carrier structure 20 includes at least one first dielectric layer 200 and at least one first circuit layer 201 bonded to the first dielectric layer 200, such as at least one fan-out redistribution layer (RDL). For example, the first circuit layer 201 is formed of copper, and the first dielectric layer 200 is formed of a dielectric material such as poly(p-oxadiazole) (PBO), polyimide (PI), or prepreg (PP). It should be understood that the carrier structure 20 may also be other substrates for supporting chips, such as a lead frame, wafer, or other board with metal routing, and is not limited to the above.

[0079] Furthermore, the second side 20b of the supporting structure 20 is connected to the supporting member 9 via a plurality of conductive elements 29, such as solder balls or other metal bumps (e.g., copper pillars). For example, the supporting member 9 includes a plate 90 made of, but not limited to, a semiconductor material, a dielectric material, a ceramic material, glass, or a metal material. The size of the supporting member 9 can be selected as a wafer-type substrate or a general panel-type substrate as required. A bonding layer 91, such as a release film or adhesive, can be formed on the plate 90 by coating or laminating. The supporting structure 20 is pressed onto the bonding layer 91, and the conductive elements 29 are embedded in the bonding layer 91.

[0080] Furthermore, the first electronic component 21 is an active component, a passive component, or a combination thereof, wherein the active component is, for example, a semiconductor chip, and the passive component is, for example, a resistor, a capacitor, and an inductor. In this embodiment, the first electronic component 21 is a semiconductor chip having an active surface 21a and an inactive surface 21b opposite to each other, and a side surface 21c adjacent to the active surface 21a and the inactive surface 21b. The first electronic component 21 is disposed on the first side 20a of the supporting structure 20 with its inactive surface 21b, and the active surface 21a has at least one electrode pad 210 (which serves as a power pin port and can be arranged in the middle of the active surface 21a) and a plurality of contacts 210a (which serve as signal pin ports and can be arranged at any position of the active surface 21a, such as the periphery or the middle). The first electronic component 21 has at least one wire 211 electrically connected to the electrode pad 210 and a plurality of integrated circuits (not shown) electrically connected to the contacts 210a disposed inside the first electronic component 21, and the wire 211 is exposed on the side surface 21c of the first electronic component 21 (such as Figure 2A As shown) or the non-active surface 21b (as shown Figure 2E-1 For example, a conductor 212 in the form of a column, needle, or other bump is formed on the electrode pad 210 and the contacts 210a, and an insulating protective film 213 is formed on the active surface 21a so that the conductor 212 is exposed outside the insulating protective film 213.

[0081] In addition, the conductive layer 22 is formed on the inactive surface 21b and the side surface 21c of the first electronic component 21, so that the first electronic component 21 is arranged on the first side 20a of the supporting structure 20 through the conductive layer 22, and the conductive layer 22 is electrically connected to the first circuit layer 201, so that the conductive layer 22 and the conductive wire 211 serve as a power transmission structure. For example, the material forming the conductive layer 22 is copper, and its plating thickness is about 5 microns (um). It should be understood that if the conductive wire 411 is exposed on the inactive surface 21b of the first electronic component 21, then the conductive layer 42 can be formed only on the inactive surface 21b of the first electronic component 21 (such as Figure 2E-1 shown).

[0082] like Figure 2B As shown, a coating layer 25 is formed on the first side 20a of the supporting structure 20, so that the coating layer 25 covers the first electronic component 21, the conductive layer 22, and the conductive pillars 23. Then, a wiring structure 26 is formed on the coating layer 25, so that the wiring structure 26 electrically connects the conductive pillars 23 and the conductors 212.

[0083] In this embodiment, the coating layer 25 is formed of an insulating material such as polyimide (PI), dry film, epoxy, or a molding compound, but is not limited to these materials. For example, the coating layer 25 can be formed on the first side 20a of the supporting structure 20 by lamination or molding.

[0084] Furthermore, a flattening process can be performed as needed to level the top surface of the cladding layer 25 with the end surfaces of the conductive pillars 23, the surface of the insulating protective film 213, and the top surface of the conductors 212, so that the end surfaces of the conductive pillars 23, the surface of the insulating protective film 213, and the top surface of the conductors 212 are exposed outside the cladding layer 25. For example, the flattening process can be performed by polishing to remove portions of the conductive pillars 23, the insulating protective film 213, the conductors 212, and the cladding layer 25.

[0085] Furthermore, the wiring structure 26 has a first surface 26 a and a second surface 26 b opposite to each other, so that the wiring structure 26 is combined with the cladding layer 25 through the first surface 26 a , and the first electronic component 21 and the conductive pillars 23 are disposed on the first surface 26 a .

[0086] Furthermore, the wiring structure 26 includes at least one second dielectric layer 260 and a plurality of second wiring layers 261 (e.g., RDLs) disposed on the second dielectric layer 260. The second wiring layer 261 of the wiring structure 26 is electrically connected to the conductive pillars 23 and electrically connected to the electrode pads 210 and the contacts 210a via the conductors 212. For example, the second wiring layer 261 is formed of copper, and the second dielectric layer 260 is formed of a dielectric material such as poly(p-oxadiazole) (PBO), polyimide (PI), or prepreg (PP).

[0087] like Figure 2C As shown, a plurality of second electronic components 24 are disposed on the second surface 26 b of the wiring structure 26 , and then a packaging layer 28 is used to cover the second electronic components 24 .

[0088] In this embodiment, the second electronic component 24 is an active component, a passive component, or a combination thereof. The active component is, for example, a semiconductor chip, while the passive component is, for example, a resistor, capacitor, or inductor. For example, the second electronic component 24 is electrically connected to the second wiring layer 261 of the wiring structure 26 via a plurality of conductive bumps 27 such as solder bumps, copper bumps, or other conductive bumps in a flip-chip manner, so that the first electronic component 21 becomes a bridging element embedded in the cladding layer 25, thereby electrically bridging two adjacent second electronic components 24 via the electrode pads 210. However, there are many ways to connect the second electronic component 24 to the wiring structure 26, such as wire bonding, and the method is not limited to the above.

[0089] Furthermore, the encapsulation layer 28 can simultaneously cover the second electronic component 24 and the conductive bumps 27. Alternatively, an underfill (not shown) can be first formed between the second electronic component 24 and the second surface 26b of the wiring structure 26 to cover the conductive bumps 27, and then the encapsulation layer 28 can be formed to cover the underfill and the second electronic component 24.

[0090] Furthermore, the encapsulation layer 28 is an insulating material, such as polyimide (PI), dry film, or an encapsulant or molding compound such as epoxy. It can be formed on the wiring structure 26 by lamination or molding. It should be understood that the material forming the encapsulation layer 28 may be the same as or different from the material of the covering layer 25.

[0091] In addition, the packaging layer 28 can cover the back of the second electronic element 24 (not shown) or expose the back of the second electronic element 24 (such as Figure 2C shown).

[0092] like Figure 2D As shown, the carrier 9 and the bonding layer 91 thereon are removed to expose the plurality of conductive elements 29 .

[0093] like Figure 2E As shown, along Figure 2D The cutting path S shown is used for performing a singulation process to obtain a plurality of electronic packages 2 , so that each of the electronic packages 2 can be placed on an electronic device 7 such as a circuit board via its conductive element 29 in a subsequent process.

[0094] In this embodiment, a portion of the conductive element 29 (eg Figure 2EThe left conductive element 29 shown in FIG. 2 corresponds to the power supply terminals 70 and 71 of the electronic device 7. For example, a portion of the power supply terminals 70 is electrically connected to the conductive layer 22, while another portion of the power supply terminals 71 is electrically connected to the conductive pillar 23. It should be understood that the other conductive elements 29 (such as Figure 2E The right conductive element 29 shown corresponds to a signal contact (not shown) of the electronic device 7 .

[0095] Therefore, the electronic package 2 of the present invention mainly utilizes the first electronic component 21 to have an electrode pad 210, a conductive wire 211, 411, and a conductive layer 22, 42, so that the electrode pad 210, the conductive wire 211, 411, and the conductive layer 22, 42 serve as a power transmission structure. Therefore, compared to the prior art, in addition to the conductive column 23 serving as a current path, the electronic package 2 of the present invention also has another current path composed of the electrode pad 210, the conductive wire 211, 411, and the conductive layer 22, 42, so as to reduce the DC resistance of the electronic package 2, thereby improving the impedance problem generated by the current supply.

[0096] For example, in the conventional distribution of the contacts 110 of the first semiconductor chip 11, Figure 1-1 As shown, the contact 110 near the middle (as shown Figure 2F The horizontal axis number is 24), and the DC resistance it produces is extremely large (such as Figure 2F The impedance curve L2 shows an impedance value of 38.62 milliohms). In contrast, in the distribution of the pin ports of the first electronic component 21 of the present invention, as shown in FIG. Figure 2F-1 As shown, the electrode pad 210 near the middle (as shown Figure 2F The horizontal axis number is 24), and the DC resistance generated becomes smaller (such as Figure 2F The impedance value shown in the impedance curve L1 is 17.73 milliohms), where Figure 2F The vertical axis represents the inductor internal impedance (DCR) generated by the internal operating voltage (VDD) of the device, and the horizontal axis represents the distribution of the pin ports on the active surface of the chip (number 1 is the peripheral pin port, such as contact 110, 210a, and number 24 is the middle pin port, such as contact 110 or electrode pad 210).

[0097] Therefore, by Figure 2F It can be seen that the electronic package 2 of the present invention can significantly reduce the DC resistance of the FO-EB type package (such as Figure 2FThe impedance curve L1 of the electronic package 2 shown is much lower than the impedance curve L2 of the conventional semiconductor package 1. That is, the surface of the first electronic component 21 is plated with a conductive layer 22, 42 with a thickness of about 5 microns, which can improve the DCR by 54%, thereby effectively solving the power supply problem of the FO-EB electronic package 2.

[0098] Furthermore, since the electrode pad 210 , conductive wires 211 , 411 and conductive layers 22 , 42 can serve as current paths, the conductive pillar 23 can be omitted (or only conductive pillars with other functions other than power supply functions can be manufactured) according to power requirements.

[0099] In addition, there are many processes related to FO-EB, and they are not limited to the above. For example, the conductive column 23 and the first electronic component 21 with the conductive layer 22, 42 can be placed on the carrier 9, and then Figures 2B to 2D After the manufacturing process, the carrier 9 is removed, and the carrier structure 20 and the conductive element 29 are formed. Alternatively, the carrier structure 20 can be omitted and the conductive element 29 electrically connecting the conductive pillar 23 and the conductive layer 22, 42 can be directly formed. Therefore, the electronic package 2 of the present invention can be equipped with or omit the carrier structure 20 as required.

[0100] Figures 3A to 3D It is a cross-sectional schematic diagram of a method for manufacturing the electronic module 3 (ie, the first electronic component 21 equipped with the conductive layer 22 ) of the electronic package 2 of the present invention.

[0101] like Figures 3A to 3B As shown, a wafer 5 is singulated to obtain a plurality of first electronic components 30. Then, the plurality of first electronic components 30 are arranged on a full-size carrier 8 at intervals.

[0102] In this embodiment, the first electronic component 30 has an active surface 30a and an inactive surface 30b opposite each other. The active surface 30a has a plurality of electrode pads 300 and a plurality of contacts 300a. A plurality of conductive lines 301 electrically connected to the electrode pads 300 are disposed within the first electronic component 30. The first electronic component 30 is bonded to the carrier 8 via the active surface 30a. For example, conductive bodies 212 are formed on the electrode pads 300 and the contacts 300a. An insulating protective film 213 is formed on the active surface 30a of the wafer 5 to cover the conductive bodies 212. This allows the wafer 5 to be bonded to the carrier 8 via the insulating protective film 213.

[0103] Furthermore, after singulating the wafer 5 , the conductive wires 301 will be exposed on the side surface 30 c of the first electronic component 30 . It should be understood that the conductive wires 301 may also be exposed on the inactive surface 30 b of the first electronic component 30 .

[0104] like Figure 3CAs shown, a conductive layer 32 is formed on the inactive surface 30 b and the side surface 30 c of the first electronic component 30 , so that the conductive layer 32 covers the first electronic component 30 .

[0105] In this embodiment, the conductive layer 32 is coated on all or part of the inactive surface 30 b and / or all or part of the side surface 30 c of the first electronic component 30 by electroplating, deposition or other methods.

[0106] Furthermore, the conductive layer 32 contacts the conductive wire 301 to electrically connect the electrode pad 300 via the conductive wire 301, and the conductive layer 32 is not electrically connected to the contact points 300a. For example, the conductive layer 32 and the conductive wire 301 serve as a power transmission structure.

[0107] like Figure 3D As shown, along Figure 3C The cutting path L shown is used for performing a singulation process, and then removing the carrier 8 to obtain a plurality of electronic modules 3 , wherein the conductive layer 32 is not formed on the active surface 30 a of the first electronic component 30 .

[0108] In this embodiment, the electronic module 3 is applied to Figure 2E In the electronic package 2 shown, part of the conductive pillars 23 will serve as one of the power transmission paths, and the first electronic component 30 has another power transmission path (i.e., the conductive layer 32, the wire 301 and the electrode pads 300). Therefore, the first electronic component 30 can serve as a bridge chip between at least two second electronic components 24 to provide the power required by the second electronic components 24.

[0109] Figure 4A and Figure 4B 2 is a cross-sectional view of a second embodiment of the electronic package 4 of the present invention. The difference between this embodiment and the first embodiment is that the electronic package 4 is equipped with multiple power transmission structures, so the similarities will not be repeated below.

[0110] like Figure 4A As shown, the electronic component 21 has two sets of power transmission structures, which include two separate and unconnected wires 211, 410, so that the two wires 211, 410 are respectively electrically connected to different second electronic components 24, and the two wires 211, 410 are respectively electrically connected to the first conductive layer 22a and the second conductive layer 22b, wherein the first conductive layer 22a and the second conductive layer 22b are formed on the side surface 21c and the inactive surface 21b of the first electronic component 21 and are separated and unconnected.

[0111] In this embodiment, the first wiring layer 201 has a first connecting portion 40a and a second connecting portion 40b to electrically connect the first conductive layer 22a and the second conductive layer 22b, respectively. For example, the first and second connecting portions 40a, 40b can be pad-shaped, column-shaped, or other suitable forms without particular limitation.

[0112] Furthermore, in two power transmission structures, such as Figure 4B As shown, one of the wires 411 (which is electrically connected to the first conductive layer 42a) can be electrically connected to different second electronic components 24, 44, while the other wire 412 (which is electrically connected to the second conductive layer 42b) is electrically connected to a single second electronic component 44, so that the same second electronic component 44 can be provided with the required power by two sets of power transmission structures (i.e., the two wires 411, 412), wherein the first conductive layer 42a and the second conductive layer 42b are formed on the inactive surface 21b of the first electronic component 21, and the first connecting portion 40a is electrically connected to the first conductive layer 42a, and the second connecting portion 40b is electrically connected to the second conductive layer 42b.

[0113] The present invention further provides an electronic package 2 , comprising: a coating layer 25 , a first electronic component 21 embedded in the coating layer 25 , and at least one conductive layer 22 , 42 formed on the first electronic component 21 .

[0114] The first electronic component 21 has an active surface 21a and an inactive surface 21b opposite to each other and a side surface 21c adjacent to the active surface 21a and the inactive surface 21b. The active surface 21a has at least one electrode pad 210, and at least one wire 211, 411 electrically connected to the electrode pad 210 is disposed inside the first electronic component 21.

[0115] The conductive layers 22 , 42 are embedded in the cladding layer 25 and electrically connected to the conductive wires 211 , 411 , wherein the conductive layers 22 , 42 are not formed on the electrode pad 210 .

[0116] In one embodiment, the electrode pad 210 is located in the middle of the active surface 21 a.

[0117] In one embodiment, the conductive lines 211 , 411 are exposed on the side surface 21 c and / or the inactive surface 21 b of the first electronic component 21 to contact the conductive layers 22 , 42 .

[0118] In one embodiment, the conductive layers 22 , 42 are formed on the inactive surface 21 b and / or the side surface 21 c of the first electronic component 21 .

[0119] In one embodiment, the electronic package 2 further includes a wiring structure 26 formed on the encapsulation layer 25 and electrically connected to the electrode pads 210. For example, the wiring structure 26 has a first surface 26a and a second surface 26b opposite each other, such that the encapsulation layer 25 and the first electronic component 21 are disposed on the first surface 26a, and at least one second electronic component 24, 44 electrically connected to the wiring structure 26 is disposed on the second surface 26b. Furthermore, a plurality of the second electronic components 24, 44 are disposed on the second surface 26b of the wiring structure 26, such that the first electronic component 21 electrically bridges two of the plurality of second electronic components 24, 44.

[0120] In one embodiment, the electronic package 2 further includes a conductive pillar 23 embedded in the cladding layer 25 and a conductive element 29 formed on the cladding layer 25 and electrically connecting the conductive layer 22 and the conductive pillar 23 .

[0121] In one embodiment, the electronic package 2 further includes a conductive element 29 formed on the coating layer 25 and electrically connected to the conductive layer 22 .

[0122] In one embodiment, a plurality of mutually separated and unconnected conductive lines 211, 410, 411, 412 are disposed inside the first electronic component 21, and a plurality of mutually separated and unconnected first conductive layers 22a, 42a and second conductive layers 22b, 42b are formed on the first electronic component 21, so that the plurality of conductive lines 211, 410, 411, 412 are electrically connected to the first conductive layers 22a, 42a and the second conductive layers 22b, 42b, respectively.

[0123] In summary, the electronic package and its manufacturing method of the present invention form electrode pads, wires and a conductive layer on the first electronic component, so that the electrode pads, wires and conductive layer serve as a power transmission structure. In addition to the conductive column serving as a current path, the electronic package of the present invention also has another current path composed of the electrode pads, wires and conductive layer, thereby reducing the DC resistance of the electronic package and improving the impedance problem generated by the current supply.

[0124] The above embodiments are intended only to illustrate the principles and effects of the present invention and are not intended to limit the present invention. Any skilled artisan may modify the above embodiments without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be as set forth in the appended claims.

Claims

1. An electronic package, characterized in that: include: cladding; a first electronic component embedded in the coating layer, wherein the first electronic component has an active surface and an inactive surface opposite to each other, and side surfaces adjacent to the active and inactive surfaces, the active surface having at least one electrode pad, and at least one conductive wire electrically connected to the electrode pad disposed within the first electronic component, wherein the conductive wire is exposed on the side surface and / or the inactive surface of the first electronic component; and At least one conductive layer is formed on the first electronic component and embedded in the cladding layer and contacts the conductive wire, wherein the conductive layer is not formed on the electrode pad.

2. The electronic package according to claim 1, wherein The electrode pad is located in the middle of the active surface.

3. The electronic package according to claim 1, wherein: The conductive layer is formed on the inactive surface and / or the side surface of the first electronic component.

4. The electronic package according to claim 1, wherein: The electronic package also includes a wiring structure formed on the covering layer and electrically connected to the electrode pad.

5. The electronic package according to claim 4, wherein: The wiring structure has a first surface and a second surface opposite to each other, so that the covering layer and the first electronic element are arranged on the first surface, and at least one second electronic element electrically connected to the wiring structure is arranged on the second surface.

6. The electronic package according to claim 5, wherein: A plurality of second electronic components are disposed on the second surface of the wiring structure so that the first electronic component electrically bridges two of the plurality of second electronic components.

7. The electronic package according to claim 1, wherein: The electronic package also includes a conductive column embedded in the covering layer.

8. The electronic package according to claim 7, wherein: The electronic package also includes a plurality of conductive elements formed on the cladding layer and electrically connecting the conductive layer and the conductive pillar.

9. The electronic package according to claim 1, wherein: The electronic package also includes a plurality of conductive elements formed on the covering layer and electrically connected to the conductive layer.

10. The electronic package according to claim 1, wherein: A plurality of mutually separated and unconnected conducting wires are disposed inside the first electronic component, and a plurality of mutually separated and unconnected conducting layers are formed on the first electronic component so that the plurality of conducting wires are electrically connected to different conducting layers respectively.

11. A method for manufacturing an electronic package, characterized in that: include: Providing a first electronic component having at least one conductive layer on a surface thereof, wherein the first electronic component has an active surface and an inactive surface opposite to each other, and side surfaces adjacent to the active and inactive surfaces, the active surface having at least one electrode pad, and at least one conductive wire electrically connected to the electrode pad disposed within the first electronic component, wherein the conductive wire is exposed on the side surface and / or the inactive surface of the first electronic component so that the conductive layer contacts the conductive wire, and the conductive layer is not formed on the electrode pad; and The first electronic component and the conductive layer are embedded in the cladding layer.

12. The method for manufacturing an electronic package according to claim 11, wherein: The electrode pad is located in the middle of the active surface.

13. The method for manufacturing an electronic package according to claim 11, wherein: The conductive layer is formed on the inactive surface and / or the side surface of the first electronic component.

14. The method for manufacturing an electronic package according to claim 11, wherein: The manufacturing method further comprises forming a wiring structure on the cladding layer, and the wiring structure is electrically connected to the electrode pad.

15. The method for manufacturing an electronic package according to claim 14, wherein: The wiring structure has a first surface and a second surface opposite to each other, so that the covering layer and the first electronic element are arranged on the first surface, and at least one second electronic element electrically connected to the wiring structure is arranged on the second surface.

16. The method for manufacturing an electronic package according to claim 15, wherein: A plurality of second electronic components are disposed on the second surface of the wiring structure so that the first electronic component electrically bridges two of the plurality of second electronic components.

17. The method for manufacturing an electronic package according to claim 11, wherein: The manufacturing method further comprises embedding a conductive column in the cladding layer.

18. The method for manufacturing an electronic package according to claim 17, wherein: The manufacturing method further includes forming a plurality of conductive elements on the cladding layer, and the plurality of conductive elements are electrically connected to the conductive layer and the conductive column.

19. The method for manufacturing an electronic package according to claim 11, wherein: The manufacturing method further includes forming a plurality of conductive elements on the cladding layer, and the plurality of conductive elements are electrically connected to the conductive layer.

20. The method for manufacturing an electronic package according to claim 11, wherein: A plurality of mutually separated and unconnected conducting wires are disposed inside the first electronic component, and a plurality of mutually separated and unconnected conducting layers are formed on the first electronic component so that the plurality of conducting wires are electrically connected to different conducting layers respectively.

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