Latch-free lateral IGBT device, manufacturing method and device

Abstract

The present invention provides a latch-free lateral IGBT device, a manufacturing method and a device, comprising a drift region formed above a substrate, a body region formed above the substrate, a first well region formed in the drift region, a collector region formed in the first well region, an emitter region formed in the body region, a first body contact formed in the body region, a first gate located between the collector region and the emitter region, a second well region formed above the substrate, a drain region formed in the second well region, wherein the drain region and the emitter region are electrically connected to each other, a source region formed in the second well region, wherein the source region and the first body contact are electrically connected to each other, and a second gate located between the drain region and the source region, wherein the second gate and the first gate are electrically connected to each other.

Description

Technical Field

[0001] The present invention relates to a lateral insulated gate bipolar transistor (IGBT) device, a method of manufacturing and a device, and in a particular embodiment, to a latch-free lateral IGBT device. Background Art

[0002] With the development of semiconductor technology, IGBT devices have been widely used in high current applications. IGBT devices are switching devices with high input impedance and large bipolar current carrying capacity. IGBT devices combine the characteristics of metal oxide semiconductor field effect transistors (MOSFET) and bipolar junction transistors (BJT), respectively obtaining high input impedance and low saturation voltage capacity. The MOSFET part of the IGBT device provides high input impedance. The BJT part of the IGBT device provides large bipolar current carrying capacity. IGBT devices are capable of handling large collector-emitter currents with low gate drive losses.

[0003] An IGBT device can be constructed with a simplified equivalent circuit having a MOSFET, a PNP transistor, and an NPN transistor. The collector of the PNP transistor is connected to the base of the NPN transistor. The collector of the NPN transistor is connected to the base of the PNP transistor. The drain of the MOSFET is coupled to the collector of the NPN transistor. The source of the MOSFET is connected to the emitter of the NPN transistor. An IGBT device has three terminals, namely, a collector (C), an emitter (E), and a gate (G). The collector terminal of the IGBT device is connected to the emitter of the PNP transistor. The gate terminal of the IGBT device is connected to the gate of the MOSFET. The emitter terminal of the IGBT device is connected to the emitter of the NPN transistor. A resistor representing the body region resistance is connected between the base and emitter of the NPN transistor. A resistor representing the drift region resistance is connected between the drain of the MOSFET and the collector of the NPN transistor.

[0004] In operation, the gate terminal is used to control the on / off of the IGBT device. When a control voltage is applied to the gate terminal and the control voltage is greater than the turn-on threshold of the IGBT device, a current path is established between the collector terminal and the emitter terminal of the IGBT device. On the other hand, when the control voltage applied to the gate terminal is less than the threshold of the IGBT device, the IGBT device is turned off accordingly.

[0005] The NPN transistor of the IGBT device is a parasitic transistor. The NPN transistor and PNP transistor of the IGBT device can form a thyristor. If the NPN transistor is accidentally turned on, latch-up may occur. Once the IGBT device is in the latched state, the gate terminal no longer has any control over the current flowing through the IGBT device, and the IGBT device cannot be turned off by the gate terminal. After latch-up occurs, excessive power consumption may damage the IGBT device. Latch-up is a very undesirable working state. It is hoped that there is a simple and reliable circuit to avoid latch-up. Summary of the invention

[0006] These and other problems are generally solved or circumvented, and technical advantages are generally achieved, by providing preferred embodiments of the present disclosure of latch-up-free lateral IGBT devices.

[0007] According to one embodiment, a device includes a substrate having a first conductivity, a drift region having a second conductivity formed above the substrate, a body region having the first conductivity formed above the substrate, a first well region having the second conductivity formed in the drift region, a collector region having the first conductivity formed in the first well region, an emitter region having the second conductivity formed in the body region, a first body contact having the first conductivity formed in the body region, a first gate located between the collector region and the emitter region, a second well region having the first conductivity formed above the substrate, a drain region having the second conductivity formed in the second well region, wherein the drain region and the emitter region are electrically connected to each other, a source region having the second conductivity formed in the second well region, wherein the source region and the first body contact are electrically connected to each other, and a second gate located between the drain region and the source region, wherein the second gate and the first gate are electrically connected to each other.

[0008] According to another embodiment, a method includes forming a drift region having a second conductivity over a substrate having a first conductivity, forming a body region having the first conductivity type in the drift region, forming a first well region having the second conductivity within the drift region, a body region having the first conductivity and a second well region having the first conductivity, forming a collector region having the first conductivity in the well region, forming an emitter region having the second conductivity in the body region, forming a drain region having the second conductivity and a source region having the second conductivity in the second well region, wherein the drain region and the emitter region are electrically connected to each other, forming a first gate between the collector region and the emitter region, and forming a second gate between the drain region and the source region, wherein the second gate and the first gate are electrically connected to each other.

[0009] According to yet another embodiment, a device includes a first collector region, a gate region, and a second collector region formed over a drift layer, wherein the gate region is oriented from the first collector region to the second collector region, a plurality of emitter / drain regions and a plurality of source / body regions are formed over the drift layer in an alternating manner, wherein the first collector region and the emitter region having the plurality of emitter / drain regions form an upper IGBT cell, the second collector region and the emitter region having the plurality of emitter / drain regions form a lower IGBT cell, and the drain region having the plurality of emitter / drain regions and the source region having the plurality of source / body regions form an NMOS transistor, wherein the drain region and the emitter region are electrically connected to each other.

[0010] The foregoing has been a fairly extensive overview of the features and technical advantages of the present disclosure so that the detailed description disclosed below may be better understood. Additional features and advantages of the present disclosure will be described below, which form the subject matter of the claims of the present disclosure. It will be appreciated by those skilled in the art that the disclosed concepts and specific embodiments may be easily used as a basis for modifying or designing other structures or processes for achieving the same purpose of the present disclosure. It will also be appreciated by those skilled in the art that such equivalent structures do not depart from the spirit and scope of the present disclosure as set forth in the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] For a more complete understanding of the present invention and its advantages, reference is now made to the following description in conjunction with the accompanying drawings, in which:

[0012] Figure 1 shows a simplified cross-sectional view of a latch-free IGBT device according to various embodiments of the present disclosure;

[0013] Figure 2 The various embodiments of the present disclosure are shown Figure 1 The equivalent circuit diagram of the latch-free IGBT device shown in;

[0014] Figure 3 The various embodiments of the present disclosure are shown Figure 1 A simplified top view of a first embodiment of a layout of a latch-free IGBT device shown in;

[0015] Figure 4 The various embodiments of the present disclosure are shown Figure 1 a simplified top view of a second embodiment of a layout of a latch-free IGBT device shown in; and

[0016] Figure 5 The method for forming the Figure 1 Flowchart of a method for a latch-free IGBT device shown in FIG.

[0017] Corresponding numerals and symbols in the different figures generally refer to corresponding parts unless otherwise indicated.The figures are drawn to clearly illustrate the relevant aspects of the various embodiments and are not necessarily drawn to scale. DETAILED DESCRIPTION

[0018] The making and use of the currently preferred embodiments are discussed in detail below. However, it should be understood that the present disclosure provides many applicable inventive concepts that can be embodied in various specific contexts. The specific embodiments discussed are only used to illustrate the specific ways to make and use the present invention and do not limit the scope of the present invention.

[0019] The present disclosure will be described with respect to embodiments in a specific context, namely a latch-free lateral IGBT device. However, embodiments of the present disclosure may also be applied to various IGBT devices (e.g., vertical IGBT devices). In the following, various embodiments will be described in detail with reference to the accompanying drawings.

[0020] Figure 1 A simplified cross-sectional view of a latch-free IGBT device according to various embodiments of the present disclosure is shown. The latch-free IGBT device 100 includes a substrate 102, a first layer 104, a drift layer 106 formed above the first layer 104, a body region 113, a first well 111, and a second well 112. The latch-free IGBT device 100 also includes a collector region 116 formed in the first well 111, an emitter region formed in the body region 113, a first body contact 118 formed in the body region 113, a first gate dielectric layer 134, a first gate 124, a first shallow trench isolation (STI) region 132, and a second STI region 136. The latch-free IGBT device 100 also includes a drain region 156 formed in the second well 112, a source region 154 formed in the second well 112, a second body contact 158 ​​formed in the second well 112, a second gate dielectric layer 164, and a second gate 162.

[0021] In some embodiments, the substrate 102, the body region 113, the first body contact 118, the collector region 116, the second well 112, and the second body contact 158 ​​have a first conductivity type. The drift layer 106, the first well 111, the emitter region 114, the drain region 156, and the source region 154 have a second conductivity type. In some embodiments, the first conductivity type is p-type and the second conductivity type is n-type. The latch-free IGBT device 100 is an n-channel IGBT device. Alternatively, the first conductivity type is n-type and the second conductivity type is p-type. The latch-free IGBT device 100 is a p-channel IGBT device.

[0022] The substrate 102 may be formed of a suitable semiconductor material such as silicon, silicon germanium, silicon carbide, etc. Depending on different applications and design requirements, the substrate 102 may be n-type or p-type. In some embodiments, the substrate 102 is a p-type substrate. Appropriate p-type dopants such as boron are doped into the substrate 102. Alternatively, the substrate 102 is an n-type substrate. Appropriate n-type dopants such as phosphorus are doped into the substrate 102.

[0023] In some embodiments, the first layer 104 may be a p-type epitaxial layer. The p-type epitaxial layer is grown on the substrate 102. The epitaxial growth of the epitaxial layer may be achieved using any suitable semiconductor manufacturing process such as chemical vapor deposition (CVD). In alternative embodiments, the first layer 104 may include an epitaxial layer and a buried layer. In some embodiments, both the epitaxial layer and the buried layer are n-type layers. The n-type buried layer is formed between the substrate 102 and the n-type epitaxial layer. The n-type buried layer is deposited on the substrate 102 for isolation purposes. For example, the n-type buried layer is used to prevent current from flowing into the substrate 102, thereby avoiding leakage current in the latch-free IGBT device 100. The n-type epitaxial layer is grown above the substrate 102. The epitaxial growth of the epitaxial layer may be achieved using any suitable semiconductor manufacturing process such as CVD. In some embodiments, the doping density of the n-type epitaxial layer ranges from about 10 14 / cm 3 to about 10 16 / cm 3 .

[0024] The drift layer 106 is an n-type layer formed on the first layer 104. In some embodiments, the drift layer 106 may be doped with an n-type dopant such as phosphorus at a doping density of about 10 15 / cm 3 to about 10 17 / cm 3 It should be noted that other n-type dopants such as arsenic, antimony, etc. may be used instead.

[0025] The body region 113 is a p-type body region. The p-type body region 113 may be formed by implanting a p-type doping material such as boron. Alternatively, the p-type body region 113 may be formed by a diffusion process. In some embodiments, a p-type material such as boron may be implanted into about 10 16 / cm 3 to about 10 18 / cm 3 It should be noted that Figure 1 As shown, there is a gap between the body region 113 and the drift layer 106. The first layer 104 occupies the gap between the body region 113 and the drift layer 106.

[0026] The first well 111 is an n-type region. The first well 111 may be formed by implanting an n-type doping material such as phosphorus. Alternatively, the first well 111 may be formed by a diffusion process. In some embodiments, an n-type material such as phosphorus may be implanted into about 10 16 / cm 3 to about 10 18 / cm 3 of doping density.

[0027] The second well 112 is a p-type region. The second well 112 may be formed by implanting a p-type doping material such as boron. Alternatively, the second well 112 may be formed by a diffusion process. In some embodiments, a p-type material such as boron may be implanted into about 10 16 / cm 3 to about 10 18 / cm 3 of doping density.

[0028] The collector region 116 is a P+ region formed in the first well 111. The collector region 116 can be formed by 19 / cm 3 to 10 20 / cm 3 It is formed by implanting a p-type dopant such as boron at a concentration between 10 and 20 nm.

[0029] like Figure 1 As shown, the collector region 116 is formed between the first STI region 132 and the second STI region 136. The STI region (e.g., the first STI region 132) may be formed by etching the semiconductor device to form a trench and filling the trench with a dielectric material. According to one embodiment, the isolation region may be filled with a dielectric material such as an oxide material. The STI region is used to increase the breakdown voltage of the latch-free IGBT device 100. It should be noted that although Figure 1 STI regions 132 and 136 are shown as separate isolation regions, but STI regions 132 and 136 may be parts of one continuous isolation region.

[0030] The emitter region 114 is an N+ region formed in the body region 113. The emitter region 114 may be formed by 19 / cm 3 To about 10 20 / cm 3 It is formed by implanting n-type dopants such as phosphorus and arsenic at a concentration between 10 and 200 nm.

[0031] The first body contact 118 is a P+ region formed in the body region 113. The first body contact 118 can be formed by 19 / cm 3 To about 10 20 / cm 3The first body contact 118 is formed by injecting a p-type dopant such as boron at a concentration between 1 and 2. In operation, holes are injected from the collector region 116 to the first body contact 118 through two paths. The first path is formed by the collector region 116, the first well 111, the drift layer 106, the first layer 104, the body region 113, and the first body contact 118. The second path is formed by the collector region 116, the first well 111, the first layer 104, the body region 113, and the first body contact 118.

[0032] The drain region 156 is an N+ region formed in the second well 112. The drain region 156 may be formed by 19 / cm 3 To about 10 20 / cm 3 It is formed by implanting n-type dopants such as phosphorus and arsenic at concentrations between the two.

[0033] The source region 154 is an N+ region formed in the second well 112. The source region 154 may be formed by 19 / cm 3 To about 10 20 / cm 3 It is formed by implanting n-type dopants such as phosphorus and arsenic at a concentration between 10 and 200 nm.

[0034] The second body contact 158 ​​is a P+ region formed in the second well 112. Figure 1 As shown, the second body contact 158 ​​is formed adjacent to the source region 154. The second body contact 158 ​​can be formed by 19 / cm 3 To about 10 20 / cm 3 The second body contact 158 ​​may contact the p-type body (eg, the second well 112). To eliminate the body effect, the second body contact 158 ​​may be directly connected to the source region 154 through a source contact (not shown).

[0035] The first gate dielectric layer 134 and the second gate dielectric layer 164 may be two parts of the same dielectric layer. Figure 1 As shown, a first gate dielectric layer 134 is formed over the drift layer 106. The first gate dielectric layer 134 is partially located on top of the body region 113, partially located on top of the drift layer 106, and partially located on top of the first STI region 132. A second gate dielectric layer 164 is formed over the second well 112. The second gate dielectric layer 164 is formed between the source region 154 and the drain region 156.

[0036] The first gate 124 is formed on the first gate dielectric layer 134. The second gate 162 is formed on the second gate dielectric layer 164. The first gate 124 and the second gate 162 may be two parts of the same gate layer formed of polysilicon, polysilicon germanium, nickel silicide or other metal or metal alloy materials.

[0037] In some embodiments, the collector region 116, the emitter region 114, the first body contact 118, and the first gate 124 form a lateral IGBT device. The drain region 156, the source region 154, and the second gate 162 form a MOSFET device. Figure 1 As shown, the drain region 156 and the emitter region 114 are electrically connected to each other. The source region 154 and the first body contact 118 are electrically connected to each other. The second gate 162 and the first gate 124 are electrically connected to each other. Figure 1 The configuration of the lateral IGBT device and the MOSFET device shown helps prevent the lateral IGBT from entering a latched operating state. In some embodiments, the lateral IGBT device is prevented from entering a latched operating state by selecting a channel width ratio of the MOSFET device to the lateral IGBT device. The detailed operating principles of the lateral IGBT device and the MOSFET device will be described in detail in conjunction with Figure 2 Detailed description.

[0038] It should be noted that although Figure 1 The embodiment shown in the figure depicts a device having a p-type collector region 116, an n-type well 111, an n-type drift layer 106, a p-type body region 113, a p-type body contact 118, and an n-type emitter region 114. This conductivity arrangement is configured to produce an n-type conductive channel. It should be noted that this conductive arrangement is only an example. In other embodiments, the polarity described can be reversed so that the latch-free IGBT device 100 can have a p-type conductive channel.

[0039] It should also be noted that, to aid understanding and clarity, Figure 1 The MOSFET and IGBT shown in the figure are not combined into a single device so that the electrical connections can be better illustrated. In the actual layout of the latch-free IGBT device, the MOSFET and IGBT are combined into one device, as shown below Figure 3-4 shown.

[0040] Figure 2 The various embodiments of the present disclosure are shown Figure 1 The equivalent circuit diagram of the latch-free IGBT device is shown in FIG. Figure 1The equivalent circuit 200 of the latch-free IGBT device 100 shown in FIG. 1 includes a bipolar PNP transistor Q1, a bipolar NPN transistor Q2, a first NMOS transistor Q3, and a second NMOS transistor Q4. The bipolar NPN transistor Q2 is a parasitic transistor. The second NMOS transistor Q4 is used to prevent the lateral IGBT device from entering a latched working state. Return to reference Figure 1 , the second NMOS transistor Q4 is formed by the drain region 156 , the source region 154 and the second gate 162 .

[0041] like Figure 2 As shown, the base of the bipolar PNP transistor Q1 is connected to the collector of the bipolar NPN transistor Q2. The base of the bipolar NPN transistor Q2 is connected to the collector of the bipolar PNP transistor Q1. The drain of the first NMOS transistor Q3 is connected to the collector of the bipolar NPN transistor through the drift region. The source of the first NMOS transistor Q3 is connected to the drain of the second NMOS transistor Q4, and is further connected to the emitter of the bipolar NPN transistor Q2. The gate of the first NMOS transistor Q3 is connected to the gate of the second NMOS transistor Q4.

[0042] Figure 2 The IGBT device shown has four terminals C, B, E and G. The collector (C) of the IGBT device is the emitter of the bipolar PNP transistor Q1. The emitter (E) of the IGBT device is the emitter of the bipolar NPN transistor Q2. The body (B) of the IGBT device is connected to the base of the bipolar NPN transistor Q2. The gate (G) of the IGBT device is connected to the gate of the first NMOS transistor Q3.

[0043] like Figure 2 As shown, when the base of the bipolar NPN transistor Q2 is grounded, there may be a resistor (not shown) coupled between the base of the bipolar NPN transistor Q2 and ground. The resistor represents Figure 1 The body resistance of the body region 113. It should be noted that the resistance between the base of the bipolar NPN transistor Q2 and the ground may affect whether the IGBT device enters the latch mode. Figure 2 As shown, the collector current of the IGBT device includes two components. The first component is represented by the dotted line 201. The second component is represented by the dotted line 202. In operation, when the voltage (the product of the first component of the collector current and the body resistance) is greater than the turn-on threshold of the bipolar NPN transistor Q2, the parasitic NPN transistor is accidentally turned on. Due to the turn-on of the parasitic NPN transistor, latch-up occurs. As described below, the second NMOS transistor Q4 can prevent the IGBT device from entering the latch-up mode.

[0044] like Figure 2As shown, the body of the IGBT device is not directly connected to the emitter of the IGBT device. In addition, the second NMOS transistor Q4 is connected between the emitter of the IGBT device and ground. This configuration helps prevent latch-up. More specifically, the base and emitter of the bipolar NPN transistor Q2 form a semiconductor device that behaves like a diode. The base is the anode of this diode. The emitter is the cathode of this diode. In operation, the collector current is divided into two current components, as shown by dotted lines 201 and 202, respectively. The current flowing through the second NMOS transistor Q4 increases the emitter voltage of the bipolar NPN transistor Q2. In other words, the cathode of the diode has an increased voltage. The increased voltage on the cathode causes the diode to become reverse biased. The reverse bias voltage inhibits the diode from turning on, thereby preventing the parasitic NPN transistor from accidentally turning on.

[0045] It should be noted that the above method includes a negative feedback mechanism. More specifically, when a large current flows through the IGBT device, the voltage applied to the base of the NPN transistor increases accordingly. This increased base voltage may turn on the parasitic NPN transistor. However, at the same time, the large current flowing through the IGBT device may increase the current flowing through the second NMOS Q4. In response to the increased current flowing through the second NMOS Q4, the drain voltage of the second NMOS Q4 also increases. The increased drain voltage prevents the parasitic NPN transistor from accidentally turning on. The increased drain voltage of the second NMOS Q4 forms a negative feedback mechanism.

[0046] It should also be noted that the current flowing through the second NMOS Q4 can be adjusted by adjusting the channel width ratio of the MOSFET device (e.g., the second NMOS Q4) and the lateral IGBT device. Specifically, by adjusting the channel width ratio, a larger current can flow through the second NMOS Q4. Such a larger current can further increase the drain voltage of the second NMOS Q4, thereby effectively suppressing the conduction of the parasitic NPN transistor.

[0047] Figure 3 The various embodiments of the present disclosure are shown Figure 1 A simplified top view of a first embodiment of a layout of a latch-free IGBT device is shown in FIG. A first collector 301 , a gate 303 , and a second collector 302 are formed above a drift layer 304 . Return to Reference Figure 1 The latch-free IGBT device 100 further includes a plurality of p+ and n+ regions, such as a body contact (B), a source region (S), a drain region (D), and an emitter region (E). Return to Reference Figure 1 , the emitter region is electrically connected to the drain region. In the top view, the emitter region and the drain region are combined into one region. E / D is used to represent the single region (e.g., Figure 3 Return to reference Figure 1 , the body contact is electrically connected to the source region. In the top view, the body contact and source region are combined into one region. S / B is used to represent the single region (e.g., Figure 3 S / B areas 321 and 322 in FIG. Figure 3 As shown, the latch-free IGBT device includes a plurality of E / D regions and a plurality of S / B regions, which are arranged in an alternating manner.

[0048] like Figure 3 As shown, the latch-free IGBT device includes an upper portion including three IGBT cells and a lower portion including three IGBT cells. The upper portion of the latch-free IGBT device is formed by a first collector 301 and E / D regions 311, 312, and 313. The lower portion of the latch-free IGBT device is formed by a second collector 302 and E / D regions 311, 312, and 313. The upper portion and the lower portion are placed in a symmetrical manner. For simplicity, only the upper portion will be described in detail below.

[0049] The first IGBT cell at the top is formed by the first collector 301 and the first E / D region 311. The gate of the first IGBT cell is oriented from the first collector 301 to the first E / D region 311. An NMOS transistor is formed by the first E / D region 311 and its adjacent S / B region 321, as shown by the transistor symbol spanning these two regions. The gate of the NMOS transistor is oriented from the first E / D region 311 to its adjacent S / B region. The gate of the NMOS transistor may alternatively be referred to as a first polysilicon finger. Figure 3 As shown, the gate of the NMOS transistor is orthogonal to the gate of the first IGBT unit. Figure 2 , the NMOS transistor formed by the first E / D region 311 and its adjacent S / B region 321 is a part of the second NMOS transistor Q4. The first IGBT cell is a part of the IGBT device.

[0050] The second IGBT cell at the top is formed by the first collector 301 and the second E / D region 312. The gate of the second IGBT cell is oriented from the first collector 301 to the second E / D region 312. Two NMOS transistors are formed by the second E / D region 312 and its adjacent S / B regions 321 and 322, as shown by the transistor symbols coupled to the second E / D region 312. The gates of the two NMOS transistors are oriented from the second E / D region 312 to its adjacent S / B regions. The gates of the two NMOS transistors may alternatively be referred to as the second polysilicon finger and the third polysilicon finger, respectively. In summary, the gates of the two NMOS transistors are orthogonal to the gate of the second IGBT cell.

[0051] The third IGBT cell at the top is formed by the first collector 301 and the third E / D region 313. The gate of the third IGBT cell is oriented from the first collector 301 to the third E / D region 313. An NMOS transistor is formed by the third E / D region 313 and its adjacent S / B region 322, as shown by the transistor symbol spanning these two regions. The gate of the NMOS transistor is oriented from the third E / D region 313 to its adjacent S / B region. The gate of the NMOS transistor may alternatively be referred to as a fourth polysilicon finger. In summary, the gate of the NMOS transistor is orthogonal to the gate of the third IGBT cell.

[0052] Figure 4 The various embodiments of the present disclosure are shown Figure 1 A simplified top view of a second embodiment of a layout of a latch-free IGBT device is shown in FIG. Figure 4 The layout of the latch-free IGBT device shown in is similar to Figure 3 The layout shown in , except that the gate of the NMOS transistor is parallel to the gate of the corresponding IGBT cell.

[0053] The latch-free IGBT device includes an upper portion including an IGBT unit and a lower portion including an IGBT unit. The upper portion of the IGBT device is formed by the first collector 301 and the E / D region 411. The E / D region 411 and the source regions 421, 422, 423 and 424 form four NMOS transistors. The lower portion of the IGBT device is formed by the second collector 302 and the E / D region 412. The upper portion and the lower portion are placed in a symmetrical manner. The E / D region 412 and the source regions 421, 422, 423 and 424 form four NMOS transistors. The upper portion and the lower portion are placed in a symmetrical manner. For simplicity, only the upper portion will be described in detail below.

[0054] The upper first NMOS transistor is formed by the E / D region 411 and the first source region 421, as shown by the transistor symbol spanning these two regions. The gate of the first NMOS transistor is oriented from the E / D region 411 to the first source region 421. The gate of the first NMOS transistor is parallel to the gate of the first IGBT cell.

[0055] The upper second NMOS transistor is formed by the E / D region 411 and the second source region 422, as shown by the transistor symbol spanning these two regions. The gate of the second NMOS transistor is oriented from the E / D region 411 to the second source region 422. The gate of the second NMOS transistor is parallel to the gate of the first IGBT cell.

[0056] The upper third NMOS transistor is formed by the E / D region 411 and the third source region 423, as shown by the transistor symbol spanning these two regions. The gate of the third NMOS transistor is oriented from the E / D region 411 to the third source region 423. The gate of the third NMOS transistor is parallel to the gate of the first IGBT cell.

[0057] The upper fourth NMOS transistor is formed by the E / D region 411 and the fourth source region 424, as shown by the transistor symbol spanning these two regions. The gate of the fourth NMOS transistor is oriented from the E / D region 411 to the fourth source region 424. The gate of the fourth NMOS transistor is parallel to the gate of the first IGBT cell.

[0058] It should be noted that the above-mentioned NMOS transistors together constitute Figure 2 The second NMOS transistor Q4 is shown. The IGBT unit together constitutes Figure 2 The IGBT shown.

[0059] Figure 5 The method for forming the Figure 1 Flowchart of a method for a latch-free IGBT device shown in FIG. Figure 5 The flowchart shown is merely an example, which should not unduly limit the scope of the claims. Those of ordinary skill in the art will recognize many variations, substitutions, and modifications. For example, additions, removals, substitutions, rearrangements, and repetitions may be made. Figure 5 The various steps shown in .

[0060] The latch-free IGBT device includes a substrate having a first conductivity, a drift region having a second conductivity formed on the substrate, a body region having the first conductivity formed on the substrate, a first well region having the second conductivity formed in the drift region, a collector region having the first conductivity formed in the first well region, an emitter region having the second conductivity formed in the body region, a first body contact having the first conductivity formed in the body region, a first gate located between the collector region and the emitter region, and a first gate formed in the substrate.

[0061] A second well region with a first conductivity is formed above the bottom, a drain region with a second conductivity is formed in the second well region, wherein the drain region and the emitter region are electrically connected to each other, a source region with a second conductivity is formed in the second well region, wherein the source region and the first body contact are electrically connected to each other, and a second gate is located between the drain region and the source region, wherein the second gate and the first gate are electrically connected to each other.

[0062] In some embodiments, the collector region, the emitter region and the first gate form a lateral IGBT device. The drain region, the source region and the second gate form a MOSFET device. In some embodiments, the channel width ratio of the MOSFET device to the lateral IGBT device is selected to prevent the lateral IGBT device from entering a latched operating state.

[0063] The latch-free IGBT device further includes a second body contact having a first conductivity formed in the second well region. The second body contact and the source region are electrically connected to each other. The latch-free IGBT device further includes an STI region extending into the drift region. The first gate portion is located above the STI region.

[0064] In step 502, a drift region having a second conductivity (eg, Figure 1 The region 106 shown in FIG. 1 is formed on a substrate having a first conductivity (eg, Figure 1 In some embodiments, the first conductivity is p-type and the second conductivity is n-type.

[0065] At step 504, a first well region (eg, Figure 1 ), a body region having a first conductivity (eg, Figure 1 region 113 shown in FIG. 1 ) and a second well region having a first conductivity (eg, Figure 1 The region 112 shown in FIG. 1 is above the substrate. The first well region is surrounded by the drift region.

[0066] At step 506, a collector region (eg, Figure 1 An emitter region (eg, region 116 shown in FIG. 1 ) having a second conductivity formed in the body region Figure 1 A drain region (eg, region 114 shown in FIG. 1 ) having a second conductivity is formed in the second well region. Figure 1 ) and a source region having a second conductivity (e.g., Figure 1 The drain region and the emitter region are electrically connected to each other.

[0067] At step 508, a first gate (eg, Figure 1 In step 510, a second gate (eg, Figure 1 The second gate 162 is shown. The second gate is electrically connected to the first gate.

[0068] The method also includes growing an epitaxial layer on the substrate and forming a buried layer over the epitaxial layer.

[0069] The method also includes forming a first gate oriented in a first direction and forming a second gate oriented in a second direction. The first gate is a gate of a lateral IGBT device. The second gate is a gate of a MOSFET device. The first direction of the lateral IGBT device is orthogonal to the second direction of the MOSFET device.

[0070] The method also includes forming a first gate oriented in a first direction and forming a second gate oriented in a second direction. The first gate is a gate of a lateral IGBT device. The second gate is a gate of a MOSFET device. The first direction of the lateral IGBT device is parallel to the second direction of the MOSFET device.

[0071] The method also includes forming a first body contact having a first conductivity in the body region and forming a second body contact having the first conductivity in the second well region. The source region and the first body contact are electrically connected to each other. The second body contact and the source region are electrically connected to each other.

[0072] Although the embodiments of the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the disclosure as defined by the appended claims.

[0073] In addition, the scope of the present application is not intended to be limited to the specific embodiments of the processes, machines, manufactures, material compositions, devices, methods, and steps described in the specification. As can be easily understood by those of ordinary skill in the art from this disclosure, processes, machines, manufactures, material compositions, devices, methods, or steps having substantially the same functions or achieving substantially the same results as the corresponding embodiments described herein can be adopted according to this disclosure, and these processes, machines, manufactures, material compositions, devices, methods, or steps may be currently existing or developed in the future. Based on this, the appended claims are intended to include such processes, machines, manufactures, material compositions, devices, methods, or steps within their scope.

Claims

1. A semiconductor device comprising: a substrate having a first conductivity; forming a drift region having a second conductivity over the substrate; forming a body region having the first conductivity over the substrate; a first well region having the second conductivity formed in the drift region; a collector region having the first conductivity formed in the first well region; an emitter region having the second conductivity formed in the body region; a first body contact having the first conductivity formed in the body region; a first gate located between the collector region and the emitter region; forming a second well region having the first conductivity over the substrate; a drain region having the second conductivity formed in the second well region, wherein the drain region and the emitter region are electrically connected to each other; a source region having the second conductivity formed in the second well region, wherein the source region and the first body contact are electrically connected to each other; and A second gate is located between the drain region and the source region, wherein the second gate is electrically connected to the first gate.

2. The semiconductor device according to claim 1, further comprising: A second body contact having the first conductivity is formed in the second well region, wherein the second body contact and the source region are electrically connected to each other.

3. The semiconductor device according to claim 1, further comprising: A shallow trench isolation (STI) region extends into the drift region.

4. The semiconductor device according to claim 3, wherein: The first gate portion is located above the shallow trench isolation (STI) region.

5. The semiconductor device according to claim 1, wherein: The first conductivity is p-type; and The second conductivity is n-type.

6. The semiconductor device according to claim 1, wherein: The first gate is oriented in a first direction; and The second gate is oriented in a second direction orthogonal to the first direction.

7. The semiconductor device according to claim 1, wherein: The first gate is oriented in a first direction; and The second gate is oriented in a second direction parallel to the first direction.

8. The apparatus of claim 1, wherein: The collector region, the emitter region and the first gate constitute a lateral IGBT device; and The drain region, the source region and the second gate form a MOSFET device, wherein a channel width ratio between the MOSFET device and the lateral IGBT device is selected to prevent the lateral IGBT device from entering a latched operating state.

9. A method for manufacturing a semiconductor device, comprising: forming a drift region having a second conductivity on a substrate having a first conductivity; forming a first well region having the second conductivity, a body region having the first conductivity, and a second well region having the first conductivity over the substrate, wherein the first well region is surrounded by the drift region; forming a collector region having the first conductivity in the first well region, forming an emitter region having the second conductivity in the body region, forming a drain region having the second conductivity and a source region having the second conductivity in the second well region, wherein the drain region and the emitter region are electrically connected to each other; forming a first gate between the collector region and the emitter region; and A second gate is formed between the drain region and the source region, wherein the second gate and the first gate are electrically connected to each other.

10. The method for manufacturing a semiconductor device according to claim 9, further comprising: growing an epitaxial layer on the substrate; and A buried layer is formed on the epitaxial layer, wherein the epitaxial layer and the buried layer are located between the substrate and the drift region.

11. The method for manufacturing a semiconductor device according to claim 9, further comprising: forming the first gate oriented in a first direction, wherein the first gate is a gate of a lateral IGBT device; and The second gate is formed to be oriented in a second direction, wherein the second gate is a gate of a MOSFET device, and wherein the first direction is orthogonal to the second direction.

12. The method for manufacturing a semiconductor device according to claim 9, further comprising: forming the first gate oriented in a first direction, wherein the first gate is a gate of a lateral IGBT device; and A second gate is formed that is oriented in a second direction, wherein the second gate is a gate of a MOSFET device, and wherein the first direction is parallel to the second direction.

13. The method for manufacturing a semiconductor device according to claim 9, further comprising: The first conductivity is p-type; and The second conductivity is n-type.

14. The method for manufacturing a semiconductor device according to claim 9, further comprising: forming a first body contact having a first conductivity in the body region, wherein the source region and the first body contact are electrically connected to each other; and A second body contact having a first conductivity is formed in the second well region, wherein the second body contact and the source region are electrically connected to each other.

15. A semiconductor device comprising: a first collector region, a gate region, and a second collector region formed over the drift layer, wherein the gate region is oriented from the first collector region to the second collector region; and A plurality of emitter / drain regions and a plurality of source / body regions are alternately formed above the drift layer, wherein: The first collector region and the emitter region of the plurality of emitter / drain regions form an upper IGBT unit; The second collector region and the emitter region of the plurality of emitter / drain regions form a lower IGBT unit; and The drain regions of the plurality of emitter / drain regions and the source regions of the plurality of source / body regions form an NMOS transistor, wherein the drain region and the emitter region are electrically connected to each other.

16. The semiconductor device according to claim 15, wherein: The gate of the NMOS transistor is oriented in a direction orthogonal to the gate region direction.

17. The semiconductor device according to claim 16, wherein: The gate of the NMOS transistor is electrically connected to the gate region.

18. The semiconductor device according to claim 15, wherein: The gate of the NMOS transistor is oriented in a direction parallel to the gate region direction.

19. The semiconductor device according to claim 18, wherein: The gate of the NMOS transistor is electrically connected to the gate region.

20. The semiconductor device according to claim 15, further comprising: a first body contact electrically connected to the source region; and A second body contact is formed adjacent to the source region.

Images