Passivation contact structure, solar cell and preparation method

Abstract

The present invention relates to the field of photovoltaic technology, and provides a passivation contact structure, a solar cell and a preparation method, wherein the passivation contact structure includes a tunneling oxide layer and a doped polysilicon layer stacked on a silicon wafer substrate, the doped polysilicon layer is an integrated structure formed by a one-time deposition process, and the surface of the doped polysilicon layer away from the tunneling oxide layer includes a first area for setting a metal grid line and a second area outside the first area; the thickness of the second area is less than the thickness of the first area. The present invention is used to solve the defect of overall thinning of the doped polysilicon layer in the prior art, which affects the ohmic contact, realizes the reasonable design of the thickness of the doped polysilicon layer, reduces the parasitic absorption of light, provides good ohmic contact, and improves the conversion efficiency of the solar cell.

Description

Technical Field

[0001] The present invention relates to the field of photovoltaic technology, and in particular to a passivation contact structure, a solar cell and a preparation method thereof. Background Art

[0002] With the rapid development of photovoltaic technology, people's demand for efficient crystalline silicon solar cells is becoming more and more urgent. In traditional crystalline silicon solar cells, due to the direct contact between metal and semiconductor, the contact position is recombined and becomes larger, which is easy to capture carriers. In order to reduce the recombination of the contact position between metal and semiconductor and realize the one-dimensional transmission of carriers at the same time, a passivation contact structure can be set on the surface of the crystalline silicon solar cell. The passivation contact structure is mainly composed of a tunneling oxide layer and a doped polysilicon layer. Among them, the preparation of the doped polysilicon layer is one of the key processes in the preparation of crystalline silicon solar cells and one of the key research objects for improving efficiency. However, the doped polysilicon layer has a serious parasitic absorption effect on light, which seriously affects the short-circuit current of the battery. In order to reduce the parasitic absorption of light by the doped polysilicon layer, the thickness of the doped polysilicon layer needs to be thinned during the production process. In the prior art, a thinner doped polysilicon layer is often prepared by uniformly growing amorphous silicon on the entire surface. While thinning the doped polysilicon layer as a whole, it will affect the ohmic contact on the surface of the crystalline silicon solar cell, and it is easy to cause metal slurry burn-through and contact reduction. These have seriously limited the further improvement of the conversion efficiency of crystalline silicon solar cells. Therefore, there is an urgent need to provide a passivation contact structure with an optimized design of the thickness of the doped polysilicon layer and a preparation method thereof. Summary of the invention

[0003] The present invention provides a passivation contact structure, a solar cell and a preparation method thereof, which are used to solve the defect of overall thinning of the doped polysilicon layer in the prior art, which affects the ohmic contact, realize the reasonable design of the thickness of the doped polysilicon layer, reduce the parasitic absorption of light, provide good ohmic contact and improve the conversion efficiency of the solar cell.

[0004] The present invention provides a passivation contact structure, comprising: a tunneling oxide layer and a doped polysilicon layer stacked on a silicon wafer substrate, the doped polysilicon layer is an integrated structure formed by a one-time deposition process, the surface of the doped polysilicon layer away from the tunneling oxide layer comprises a first area for setting a metal gate line and a second area outside the first area; the thickness of the second area is less than the thickness of the first area.

[0005] According to a passivation contact structure provided by the present invention, a surface of the second region has a groove.

[0006] According to a passivation contact structure provided by the present invention, the groove is an arc-shaped groove.

[0007] The present invention also provides a method for preparing a passivation contact structure, comprising:

[0008] forming a tunnel oxide layer on a silicon wafer substrate;

[0009] A one-time deposition process is used to form an integrated doped polysilicon layer on the surface of the tunnel oxide layer. The surface of the doped polysilicon layer away from the tunnel oxide layer includes a first area for setting a metal gate line and a second area outside the first area; the thickness of the second area is less than the thickness of the first area.

[0010] According to a method for preparing a passivation contact structure provided by the present invention, a doped polysilicon layer of an integrated structure is formed on the surface of the tunnel oxide layer by a one-time deposition process, comprising:

[0011] A baffle for shielding the tunnel oxide layer is arranged at a preset distance on the surface of the tunnel oxide layer, wherein the preset distance is determined according to the thickness of the second region, the baffle has a shielding region and an unshielded region, and the shape of the unshielded region is consistent with the shape of the metal gate line;

[0012] Depositing doped amorphous silicon on the surface of the tunnel oxide layer provided with the baffle, wherein during the deposition process, the doped amorphous silicon forms a first deposition area through the unshielded area, and at the same time, bypasses the shielded area to form a second deposition area, wherein the second deposition area is a bypass plating area, and the first deposition area and the bypass plating area form a doped amorphous silicon layer of an integrated structure;

[0013] The doped amorphous silicon layer is annealed to form the doped polysilicon layer, wherein the first region corresponds to the first deposition region, and the second region corresponds to the bypass plating region.

[0014] According to a method for preparing a passivation contact structure provided by the present invention, the baffle includes a plurality of dispersed blocks, and adjacent blocks are connected by a wiring harness; the plurality of blocks form the shielding area, and the area outside the plurality of blocks forms the unshielded area.

[0015] According to a method for preparing a passivation contact structure provided by the present invention, the thickness of the stopper is determined based on the preset distance.

[0016] According to a method for preparing a passivation contact structure provided by the present invention, the size of the unshielded area is larger than the size of the metal gate line.

[0017] The present invention also provides a solar cell, comprising any one of the above passivation contact structures.

[0018] The present invention also provides a method for preparing a solar cell, including a method for preparing any of the above-mentioned passivation contact structures.

[0019] The passivation contact structure provided by the present invention comprises a tunneling oxide layer and a doped polysilicon layer stacked on a silicon wafer substrate, wherein the doped polysilicon layer is an integrated structure formed by a one-time deposition process, and has a simple structure, strong stability and is easy to prepare; the surface of the doped polysilicon layer away from the tunneling oxide layer comprises a first region and a second region, and the thickness of the second region is less than the thickness of the first region, wherein the thicker first region is used to set a metal gate line, which can be used as a metal contact region to ensure good ohmic contact, realize effective transmission of majority carriers and improve the fill factor, while the thinner second region can be used as a non-metallic contact region, which can effectively reduce the parasitic absorption of light and improve the conversion efficiency of the battery; therefore, the present invention realizes a compatible design of thin and thick regions by setting a first region and a second region of different thicknesses on the doped polysilicon layer of the integrated structure, thereby reducing the parasitic absorption of light while improving the ohmic contact, and effectively improving the comprehensive performance of the passivation contact structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solutions in the present invention or the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0021] Figure 1 is a schematic structural diagram of a passivation contact structure provided by the present invention;

[0022] Figure 2 It is a schematic flow chart of a method for preparing a passivation contact structure provided by the present invention;

[0023] Figure 3 It is a structural schematic diagram of the baffle provided by the present invention;

[0024] Figure 4 A schematic diagram of the structure of the carrier provided by the present invention;

[0025] Figure 5 It is a schematic diagram of the structure of the TOPCon battery provided by the present invention;

[0026] Figure 6 It is a schematic diagram of the structure of a conventional TOPCon battery in the prior art. DETAILED DESCRIPTION

[0027] In order to make the purpose, technical solution and advantages of the present invention clearer, the technical solution of the present invention will be clearly and completely described below in conjunction with the drawings of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0028] Combine the following Figure 1 The passivation contact structure of the present invention is described.

[0029] Figure 1 It is a schematic structural diagram of the passivation contact structure provided by the present invention.

[0030] like Figure 1 As shown, the passivation contact structure provided in this embodiment includes: a tunneling oxide layer 106 and a doped polysilicon layer 107 stacked on a silicon wafer substrate 105, the doped polysilicon layer 107 is an integrated structure formed by a one-time deposition process, and the surface of the doped polysilicon layer 107 away from the tunneling oxide layer 106 includes a first area for setting a metal gate line and a second area outside the first area; the thickness of the second area is less than the thickness of the first area.

[0031] The tunneling oxide layer 106 and the doped polysilicon layer 107 may be stacked in sequence on one surface or both surfaces of the silicon wafer substrate 105 . In this embodiment, for example, the tunneling oxide layer 106 and the doped polysilicon layer 107 may be stacked on the back side of the silicon wafer substrate 105 .

[0032] For example, the silicon wafer substrate 105 can be a single crystal silicon wafer or a polycrystalline silicon wafer, and the surface doping type of the silicon wafer substrate 105 can be P-type or N-type. The tunneling oxide layer 106 can be formed by thermal oxidation, thermal HNO3 oxidation or CVD (Chemical Vapor Deposition) deposition, and the thickness can be between 1-2 nanometers (nm). The doped polysilicon layer 107 can be prepared by a process of depositing a doped amorphous silicon layer by a PECVD (Plasma Enhanced Chemical Vapor Deposition) method and then annealing at high temperature, or by a process of depositing a doped amorphous silicon layer by a PVD (Physical Vapor Deposition) method and then annealing at high temperature.

[0033] In this embodiment, the first area is used to set the metal gate line and can be used as a metal contact area. The metal contact area requires a larger thickness to ensure good ohmic contact. The second area is an area outside the first area and is not used to set the metal gate line. It can be used as a non-metallic contact area and needs to be set with a smaller thickness to reduce parasitic absorption of light. Therefore, the thickness of the second area is less than that of the first area. By way of example, the thickness of the second area can be 20nm-60nm, and the thickness of the first area can be 120nm-200nm, thereby ensuring that the thickness of the metal contact area is significantly greater than that of the non-metallic contact area, and realizing an integrated layout of thin and thick areas in the doped polysilicon layer. By improving the structure of the doped polysilicon layer, the comprehensive performance of the passivation contact structure is improved.

[0034] For example, the surface of the second region has a groove. By providing a simple structure such as a groove, the thickness of the second region can be reduced, ensuring that the thickness of the second region is less than the thickness of the first region.

[0035] Specifically, the groove may be an arc-shaped groove or a square groove, etc. In this embodiment, preferably, the groove is an arc-shaped groove. The arc-shaped groove is more conducive to the conduction and collection of current than the square groove, and is conducive to the improvement of the filling factor.

[0036] In summary, the passivation contact structure provided by the present invention includes a tunneling oxide layer and a doped polysilicon layer stacked on a silicon wafer substrate, wherein the doped polysilicon layer is an integrated structure formed by a one-time deposition process, which has a simple structure, strong stability and is easy to prepare; the surface of the doped polysilicon layer away from the tunneling oxide layer includes a first region and a second region, and the thickness of the second region is less than the thickness of the first region, wherein the thicker first region is used to set the metal gate line, which can be used as a metal contact region to ensure good ohmic contact, achieve effective transmission of majority carriers, and improve the fill factor, while the thinner second region can be used as a non-metallic contact region, which can effectively reduce the parasitic absorption of light and improve the conversion efficiency of the battery; therefore, the present invention realizes a compatible design of thin and thick regions by setting the first region and the second region of different thicknesses in the doped polysilicon layer of the integrated structure, thereby reducing the parasitic absorption of light while improving the ohmic contact, and effectively improving the comprehensive performance of the passivation contact structure.

[0037] The following is a description of a method for preparing a passivation contact structure provided by the present invention. The method for preparing the passivation contact structure described below and the passivation contact structure described above can be referred to in correspondence with each other.

[0038] Figure 2 The present invention provides a flow chart of the method for preparing the passivation contact structure. Figure 2 As shown, the method for preparing the passivation contact structure provided in this embodiment at least includes the following steps:

[0039] S100, forming a tunnel oxide layer on a silicon wafer substrate.

[0040] Among them, the tunneling oxide layer can be generated on one surface or both surfaces of the silicon wafer substrate. Before forming the tunneling oxide layer, the silicon wafer substrate can be pre-treated by de-damaging, polishing or texturing. For example, the tunneling oxide layer can be deposited by thermal oxidation, thermal HNO3 oxidation or CVD method, and the thickness is between 1-2nm. Specifically, in this embodiment, the tunneling oxide layer is formed by a thermal oxidation method on the back side of the silicon wafer substrate, which is not affected by the subsequent preparation process of the doped polysilicon layer, thereby ensuring the integrity of the tunneling oxide layer, making the tunneling oxide layer more uniform, and the oxidation thickness can be determined according to actual needs.

[0041] S200, using a single deposition process to form an integrated doped polysilicon layer on the surface of the tunnel oxide layer, wherein the surface of the doped polysilicon layer away from the tunnel oxide layer includes a first area for setting a metal gate line and a second area outside the first area; the thickness of the second area is less than the thickness of the first area.

[0042] The one-time deposition process may include: a process of depositing a doped amorphous silicon layer by PECVD and then annealing at a high temperature, or a process of depositing a doped amorphous silicon layer by PVD and then annealing at a high temperature.

[0043] For example, this embodiment adopts a process of PVD deposition of a doped amorphous silicon layer and then high-temperature annealing to form a doped polysilicon layer of an integrated structure on the surface of the tunnel oxide layer. The use of the PVD method to deposit doped amorphous silicon can achieve in-situ doping and reduce the subsequent separate phosphorus doping process; furthermore, the PVD method has a low process temperature, which can greatly reduce the adverse effects caused by the bending of the silicon wafer. The preparation method of the passivation contact structure of the present invention can adjust the required doping ratio according to the process requirements to obtain a better passivation effect. Among them, the deposition process is carried out in the process chamber of the plate-type PVD equipment, the target material in the process chamber of the plate-type PVD equipment is a silicon target material, the silicon target material is a silicon source, and the gas in the PVD process chamber contains PH3, and PH3 is used as a phosphorus source.

[0044] For example, the method of forming a doped polysilicon layer of an integrated structure on the surface of the tunnel oxide layer by a single deposition process includes:

[0045] (1) A baffle for shielding the tunnel oxide layer is disposed at a preset distance on the surface of the tunnel oxide layer, wherein the preset distance is determined according to the thickness of the second region, and the baffle has a shielding region and an unshielded region, and the shape of the unshielded region is consistent with the shape of the metal gate line.

[0046] The thickness of the second region may be set according to actual needs, and then the preset distance is determined according to the set thickness of the second region.

[0047] For example, Figure 3 As shown, the baffle may include a plurality of dispersed blocks 301, and the adjacent blocks 301 are connected by a wiring harness 302; the plurality of blocks 301 form the shielding area, and the area outside the plurality of blocks 301 forms the unshielded area. The wiring harness 302 uses a thin wire, which will not affect the deposition of doped amorphous silicon. In addition, even if the block 301 is partially damaged or missing, resulting in the thickening of the amorphous silicon deposited in the second area, the battery conversion efficiency will be slightly weakened, but it will not affect the battery yield, which proves that the baffle has a high fault tolerance.

[0048] (2) doped amorphous silicon is deposited on the surface of the tunnel oxide layer provided with the baffle. During the deposition process, the doped amorphous silicon forms a first deposition area through the unblocked area. Meanwhile, the doped amorphous silicon bypasses the blocked area to form a second deposition area. The second deposition area is a bypass plating area. The first deposition area and the bypass plating area form a doped amorphous silicon layer with an integrated structure.

[0049] For example, doped amorphous silicon may be deposited onto the surface of the tunnel oxide layer through the baffle in a PVD coating manner to form a doped amorphous silicon layer of an integrated structure.

[0050] Among them, since the unblocked area is hollow, the doped amorphous silicon can be directly deposited on the surface of the corresponding tunneling oxide layer through the unblocked area to form a first deposition area of ​​normal deposition, and the blocked area will have a certain shielding effect. The doped amorphous silicon can bypass the blocked area and be deposited on the surface of the tunneling oxide layer below the blocked area to form a second deposition area, that is, the bypass plating area. The first deposition area and the bypass plating area are connected as a whole due to the deposition effect to form a doped amorphous silicon layer with an integrated structure.

[0051] (3) Annealing the doped amorphous silicon layer to form the doped polysilicon layer, wherein the first region corresponds to the first deposition region, and the second region corresponds to the bypass plating region.

[0052] For example, the doped amorphous silicon layer is annealed to form the doped polysilicon layer, and the doped polysilicon layer includes:

[0053] The silicon wafer substrate after depositing doped amorphous silicon is kept at a constant temperature of 800-1000° C. for 1-120 minutes, so that the doped amorphous silicon layer forms a doped polycrystalline silicon layer. Through the above high temperature annealing treatment, the doped amorphous silicon layer is rapidly crystallized to form a doped polycrystalline silicon layer.

[0054] In this embodiment, the function of the baffle is to partially shield the tunnel oxide layer, so that the thickness of the doped amorphous silicon deposited in different areas of the surface of the tunnel oxide layer is different. Among them, the surface of the tunnel oxide layer corresponding to the unshielded area is normally deposited with doped amorphous silicon. Due to the lack of shielding, the thickness of the deposited doped amorphous silicon is relatively large, forming a first deposition area corresponding to the first area of ​​the doped polysilicon layer. The shielding area will form a shielding effect, so that the doped amorphous silicon cannot be deposited normally, but due to the preset distance, there is a certain gap between the shielding area and the surface of the tunnel oxide layer. At this time, the doped amorphous silicon deposited from the unshielded area will be plated around the surface of the tunnel oxide layer corresponding to the shielding area. Due to the limitation of the shielding area, the deposition thickness of the doped amorphous silicon plated around is relatively small, forming a second deposition area, that is, the plating around area. The plating around area is integrated with the first deposition area normally deposited in the surrounding area. Since the thickness of the plating around area is relatively thin, a groove structure can be formed, corresponding to the second area of ​​the doped polysilicon layer. Therefore, the first region corresponds to the first deposition region, the second region corresponds to the wrap-around plating region, and the thickness of the second region is smaller than the thickness of the first region.

[0055] Among them, the preset distance between the surface of the tunneling oxide layer and the baffle determines the thickness of the doped amorphous silicon in the bypass plating area, and then the thickness of the second area can be obtained. Therefore, the set value of the thickness of the second area can be determined first according to actual needs, and then the preset distance can be adjusted based on the set value to obtain the required thickness of the second area. The thickness of the doped amorphous silicon in the first deposition area is the thickness of the first area. The thickness of the doped amorphous silicon in the first deposition area can be controlled by adjusting the transmission speed of the silicon wafer substrate in the coating equipment, adjusting the duration of the deposition process, and controlling the deposition thickness of the doped amorphous silicon in the first deposition area. For example, by reducing the transmission speed of the silicon wafer substrate in the coating equipment, the time for depositing doped amorphous silicon on the surface of the tunneling oxide layer becomes longer, and the doped amorphous silicon deposited in the first deposition area becomes thicker, thereby increasing the thickness of the first area. The first area can be used as a metal contact area for setting a metal gate line, and the second area can be used as a non-metal contact area. By adjusting the thickness of the first area and the second area, the required thickness of the metal contact area and the non-metal contact area can be obtained.

[0056] For example, Figure 4 Schematic diagram of the structure of the carrier provided by the present invention, such as Figure 4 As shown, the baffle can be detachably arranged on a carrier 303, and the carrier 303 is a structure for carrying the silicon wafer substrate during the coating or deposition process. The carrier 303 can be provided with a plurality of (for example, 6) bearing holes for carrying the silicon wafer substrate, and the baffle is arranged at the bearing holes. When the silicon wafer substrate is mounted on the carrier 303, the surface of the tunneling oxide layer faces the baffle. The material of the carrier 303 can be carbon fiber or graphite. Preferably, the carrier 303 can adopt a graphite frame. For example, the baffle can be connected to the carrier 303 by bolts, clamps, etc., which is convenient for disassembly and installation.

[0057] For example, the thickness of the block 301 is determined based on the preset distance. Wherein, on the carrier 303, the mounting position of the block is fixed, and the preset distance can be adjusted by replacing blocks 301 of different thicknesses. For example, the thicker the block 301 is, the closer the surface of the block 301 is to the surface of the tunnel oxide layer, and the smaller the preset distance is. In practical applications, the preset distance can be first determined according to the thickness of the second region, and then the block 301 that meets the preset distance can be selected.

[0058] For example, the unshielded area is larger than the size of the metal grid line, so as to ensure that the area of ​​the first region corresponding to the unshielded area is large enough to facilitate the printing of the metal grid line.

[0059] In summary, the preparation method of the passivation contact structure provided by the embodiment of the present invention is as follows: first, a tunneling oxide layer is formed on a silicon wafer substrate, and the tunneling oxide layer can be grown normally on the entire surface, and is independent of the deposition process of the doped amorphous silicon layer. The tunneling oxide layer can be grown separately by thermal oxidation or the like, and has better uniformity and the oxide thickness will not be affected by the deposition process temperature of the doped amorphous silicon layer, and it is more convenient to adjust the required oxide layer thickness; secondly, doped amorphous silicon is deposited on the surface of the tunneling oxide layer provided with a baffle to form a doped amorphous silicon layer of an integrated structure. Since the baffle includes a shielding area and an unshielded area, the doped amorphous silicon layer is formed on the surface of the tunneling oxide layer provided with a baffle. The tunnel oxide layer is formed by a single deposition process, so that the surface of the tunnel oxide layer is not uniformly deposited with doped amorphous silicon as a whole, but doped amorphous silicon of different thicknesses is deposited in different regions, and thicker doped amorphous silicon is normally deposited through the unblocked region, corresponding to the metal contact region, and thinner doped amorphous silicon is deposited by bypassing the blocked region, corresponding to the non-metal contact region, and finally a doped polysilicon layer of an integrated structure is obtained by annealing; through a one-time deposition process, the doped polysilicon layer of the integrated structure is reasonably divided into thin and thick regions, which greatly saves the preparation process, makes the process steps simpler, and makes it easier to control the process stability.

[0060] The present invention also provides a solar cell, comprising any one of the above passivation contact structures. For example, the solar cell may be a TOPCon cell, a HJT cell or an IBC cell. Figure 5 is a schematic diagram of the structure of the TOPCon battery provided by the present invention. Taking the TOPCon battery as an example, in this embodiment, Figure 5 As shown, the TOPCon cell includes a tunneling oxide layer 106, a doped polysilicon layer 107, a back anti-reflection layer 108 and a back electrode 109 arranged in sequence on the back side of a silicon wafer substrate 105, and an emitter 104, a passivation layer 103, a front anti-reflection layer 102 and a front electrode 101 arranged in sequence on the front side of the silicon wafer substrate 105.

[0061] The tunneling oxide layer 106 and the doped polysilicon layer 107 constitute the passivation contact structure.

[0062] For example, the doped polysilicon layer 107 is an integrated structure formed by a one-time deposition process, and the surface of the doped polysilicon layer 107 away from the tunnel oxide layer 106 includes a first region for setting a metal gate line and a second region outside the first region; the thickness of the second region is less than the thickness of the first region. The metal gate line set in the first region is a back electrode 109.

[0063] For example, the surface of the second region has a groove, and the groove is an arc-shaped groove.

[0064] The surface shape of the back anti-reflection layer 108 is consistent with that of the doped polysilicon layer 107 , and a region thereof corresponding to the second region has a groove.

[0065] For example, the back anti-reflection layer 108 and the front anti-reflection layer 102 may be made of silicon nitride; the passivation layer 103 may be made of aluminum oxide; and the emitter 104 may be a boron emitter.

[0066] In summary, the TOPCon battery provided in this embodiment realizes the setting of a thinner non-metallic contact area by setting the passivation contact structure, which can effectively reduce the parasitic absorption of light and improve the conversion efficiency of the battery. At the same time, the setting of a thicker metal contact area can reduce metal recombination and contact resistivity, ensure good metal contact, realize the effective transmission of majority carriers, and improve the fill factor, thereby improving the conversion efficiency of the battery.

[0067] The present invention also provides a method for preparing a solar cell, including any one of the methods for preparing the passivation contact structure described above. Taking a TOPCon cell as an example, in this embodiment, the method for preparing the TOPCon cell at least includes: texturing - boron diffusion - back etching - preparation of a passivation contact structure - post-cleaning - deposition of aluminum oxide - deposition of front silicon nitride - deposition of back silicon nitride - screen printing - sintering + light injection - testing and sorting.

[0068] For example, the specific process steps of the preparation method of the TOPCon battery are as follows:

[0069] Texturing: Select the silicon wafer substrate and perform surface texturing.

[0070] For example, a silicon wafer substrate is placed in a texturing tank, in which the volume concentration of KOH is 2%-20%, the temperature is 45-85°C, and the texturing additive is 2-20L, followed by water washing, acid washing, water washing, slow pulling, and drying; wherein the silicon wafer substrate can be an N-type original silicon wafer, and the acid washing can use an HF solution with a volume concentration of 2%-15%.

[0071] Boron diffusion: Place the silicon wafer substrate after texturing into the boron diffusion furnace tube to form a boron diffusion layer and a BSG layer (boron doped layer) on the front side of the silicon wafer substrate.

[0072] For example, the source temperature of the boron expansion furnace tube is 700-900° C., the diffusion time is 20-1000 s, the push-in temperature is 900-1100° C., and the push-in time is 100-6000 s.

[0073] Backside etching: Use the first solution to remove the BSG layer from the back and sides of the diffused silicon wafer substrate, then place it in the second solution for alkaline etching on the back to remove the boron diffusion layer on the back and sides of the silicon wafer substrate, followed by water washing, acid washing, water washing, slow pulling, and drying.

[0074] The first solution may include an HF solution with a volume concentration of 10%-80%, the second solution may include a KOH solution (volume concentration of 2%-30%, temperature of 40-80°C, additives of 2-20L, time of 50-500s), and the pickling may use an HF solution with a volume concentration of 1%-10%.

[0075] Preparation of passivation contact structure, including:

[0076] (1) Forming a tunnel oxide layer on a silicon wafer substrate. For example, a tunnel oxide layer can be prepared on the back of a silicon wafer substrate by oxygen thermal oxidation at a temperature of 500-700°C, and the tunnel oxide layer can be 1nm-2nm; using thermal oxidation or other methods to grow the tunnel oxide layer alone, the uniformity is better and the oxide thickness is not limited by the coating temperature, and the required oxide thickness can be adjusted more conveniently.

[0077] (2) A one-time deposition process is used to form an integrated doped polysilicon layer on the surface of the tunnel oxide layer, wherein the surface of the doped polysilicon layer away from the tunnel oxide layer includes a first region for setting a metal gate line and a second region outside the first region; the thickness of the second region is less than the thickness of the first region.

[0078] For example, the method of forming a doped polysilicon layer of an integrated structure on the surface of the tunnel oxide layer by a single deposition process includes:

[0079] A baffle for shielding the tunnel oxide layer is arranged at a preset distance on the surface of the tunnel oxide layer, the preset distance is determined according to the thickness of the second region, the baffle has a shielding region and an unshielded region, and the shape of the unshielded region is consistent with the shape of the metal gate line; illustratively, the preset distance is determined based on the thickness of the baffle; illustratively, the size of the unshielded region is larger than the size of the metal gate line;

[0080] Depositing doped amorphous silicon on the surface of the tunnel oxide layer provided with the baffle, wherein during the deposition process, the doped amorphous silicon forms a first deposition area through the unshielded area, and at the same time, bypasses the shielded area to form a second deposition area, wherein the second deposition area is a bypass plating area, and the first deposition area and the bypass plating area form a doped amorphous silicon layer of an integrated structure;

[0081] The doped amorphous silicon layer is annealed to form the doped polysilicon layer, wherein the first region corresponds to the first deposition region, and the second region corresponds to the bypass plating region.

[0082] The doped amorphous silicon layer is annealed to form the doped polysilicon layer, comprising: the silicon wafer substrate after depositing the doped amorphous silicon is kept at a constant temperature of 800-1000° C. for 1-120 minutes, so that the doped amorphous silicon film forms the doped polysilicon layer.

[0083] Post-cleaning: Place the annealed silicon wafer in an HF solution (volume concentration 5%-50%) to remove the BSG layer on the front side of the silicon wafer substrate and the silicon oxide on the back side of the silicon wafer substrate that is naturally formed in the air.

[0084] Deposition of aluminum oxide: A 4-12 nm aluminum oxide is deposited on the front side of the post-cleaned silicon wafer substrate using ALD (Atomic Layer Deposition).

[0085] Deposition of front silicon nitride: Use PECVD method to deposit 70-90nm silicon nitride on the front side of the silicon wafer substrate with silane and ammonia, with a refractive index of 1.7-1.9, a reaction temperature of 400-500℃, and a pressure of 100-1000pa.

[0086] Deposition of back silicon nitride: Use PECVD method to deposit 80-110nm silicon nitride on the back of the silicon wafer substrate with silane and ammonia, with a refractive index of 1.9-2.1, a reaction temperature of 400-500℃, and a pressure of 100-1000pa.

[0087] Screen printing: printing the metal grid lines corresponding to the front electrodes on the front side of the silicon wafer substrate, and printing the metal grid lines corresponding to the back electrodes on the back side of the silicon wafer substrate at a position corresponding to the first area of ​​the doped polysilicon layer.

[0088] Sintering + light injection: The screen-printed silicon wafer substrate is sintered and light-injected to form a good contact and passivation effect. The resulting cell structure is a TOPCon cell, such as Figure 5 shown.

[0089] Testing and sorting: Perform IV test and EL test on the prepared TOPCon batteries to check their electrical performance parameters and yield.

[0090] The TOPCon battery prepared by the TOPCon battery preparation method of the present invention is compared with the conventional TOPCon battery prepared by the prior art, and the data are shown in Table 1.

[0091] Table 1

[0092] Group Voc Isc Rs R FF Eta Example 1 0.7174 18.292 0.0008 732 83.11 24.73 Example 2 0.7171 18.313 0.0008 711 83.21 24.79 Comparative Example 1 0.7172 18.231 0.0009 662 82.76 24.54

[0093] Among them, in Example 1, the thickness of the metal contact area of ​​the TOPCon battery prepared by the above-mentioned TOPCon battery preparation method is 150nm, and the thickness of the non-metallic contact area is 40nm; in Example 2, similarly, in the TOPCon battery prepared by the above-mentioned TOPCon battery preparation method, when the doped amorphous silicon is deposited by PVD coating, the transmission speed of the silicon wafer substrate in the coating equipment is reduced, thereby increasing the thickness of the doped amorphous silicon in the metal contact area, and reducing the preset distance between the baffle and the surface of the tunneling oxide layer, reducing the thickness of the doped amorphous silicon in the non-metallic contact area, and the other process parameters and structures are the same as those in Example 1. The thickness of the metal contact area of ​​the TOPCon battery prepared in Example 2 is 180nm, and the thickness of the non-metallic contact area is 20nm. In Comparative Example 1, the doped polycrystalline silicon layer is prepared by the method of uniformly growing amorphous silicon on the entire surface of the prior art, and the other process parameters and structures are the same as those in Example 1. The prepared TOPCon battery is as follows Figure 6As shown, the back side of the silicon wafer substrate 105 includes a tunneling oxide layer 106, a doped polysilicon layer 207, a back side anti-reflection layer 208 and a back side electrode 109, and the front side of the silicon wafer substrate 105 includes an emitter 104, a passivation layer 103, a front side anti-reflection layer 102 and a front side electrode 101, wherein the overall thickness of the doped polysilicon layer 207 in Comparative Example 1 is 120 nm, which is significantly different from the structure of the doped polysilicon layer 107 in Example 1 of the present invention. Meanwhile, the structure of the back side anti-reflection layer 208 is different from that of the back side anti-reflection layer 108 in Example 1 of the present invention, and the other structures are the same.

[0094] After testing, the open circuit voltage Voc, short circuit current Isc, series resistance Rs, parallel resistance Rsh, fill factor FF, photoelectric conversion efficiency Eta and other parameters of the above three TOPCon battery structures were compared and it was found that the thicker doped polysilicon layer in the metal contact area can reduce the contact resistivity, while the thinner doped polysilicon layer in the non-metal contact area can reduce the light parasitic absorption loss. Therefore, the passivation contact structure provided by the present invention can simultaneously achieve the improvement of the fill factor FF and the short circuit current Isc, and then be applied to crystalline silicon solar cells to effectively improve the photoelectric conversion efficiency Eta of the battery.

[0095] In summary, the preparation method of the TOPCon battery provided in the embodiment of the present invention has a simple process. It only needs to add a baffle for patterned deposition during the preparation of the non-doped polysilicon layer. The non-doped polysilicon layer with an integrated structure is formed through a one-time deposition, which greatly saves the preparation process. It is compatible with the existing mass production process of crystalline silicon solar cells and does not require the addition of new processes. It can be quickly put into mass production, which plays a role in quickly improving efficiency and reducing costs.

[0096] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A passivation contact structure, characterized in that: include: A tunneling oxide layer and a doped polysilicon layer are stacked on a silicon wafer substrate, wherein the doped polysilicon layer is an integrated structure formed by a one-time deposition process, and a surface of the doped polysilicon layer away from the tunneling oxide layer includes a first area for arranging a metal gate line and a second area outside the first area; The thickness of the second region is less than the thickness of the first region; The surface of the second region has a groove, and the groove is an arc-shaped groove; The one-time deposition process includes: using PVD to deposit a doped amorphous silicon layer and then annealing at a high temperature; The method of forming a doped polysilicon layer with an integrated structure on the surface of the tunnel oxide layer by a single deposition process comprises: A baffle for shielding the tunnel oxide layer is arranged at a preset distance on the surface of the tunnel oxide layer, wherein the preset distance is determined according to the thickness of the second region, the baffle has a shielding region and an unshielded region, and the shape of the unshielded region is consistent with the shape of the metal gate line; Doped amorphous silicon is deposited on the surface of the tunnel oxide layer provided with the baffle. During the deposition process, the doped amorphous silicon forms a first deposition area through the unshielded area, and at the same time, bypasses the shielded area to form a second deposition area, the second deposition area is a bypass plating area, and the first deposition area and the bypass plating area form a doped amorphous silicon layer of an integrated structure; the baffle includes a plurality of dispersed blocks, and adjacent blocks are connected by a wire harness; the plurality of blocks form a shielded area, and the area outside the plurality of blocks forms an unshielded area; The doped amorphous silicon layer is annealed to form the doped polysilicon layer, wherein the first region corresponds to the first deposition region, and the second region corresponds to the bypass plating region.

2. A method for preparing a passivation contact structure, characterized in that: include: forming a tunnel oxide layer on a silicon wafer substrate; A doped polysilicon layer with an integrated structure is formed on the surface of the tunnel oxide layer by a single deposition process, wherein the surface of the doped polysilicon layer away from the tunnel oxide layer includes a first region for arranging a metal gate line and a second region outside the first region; The thickness of the second region is less than the thickness of the first region; The surface of the second region has a groove, and the groove is an arc-shaped groove; The one-time deposition process includes: using PVD to deposit a doped amorphous silicon layer and then annealing at a high temperature; The method of forming a doped polysilicon layer with an integrated structure on the surface of the tunnel oxide layer by a single deposition process comprises: A baffle for shielding the tunnel oxide layer is arranged at a preset distance on the surface of the tunnel oxide layer, wherein the preset distance is determined according to the thickness of the second region, the baffle has a shielding region and an unshielded region, and the shape of the unshielded region is consistent with the shape of the metal gate line; Doped amorphous silicon is deposited on the surface of the tunnel oxide layer provided with the baffle. During the deposition process, the doped amorphous silicon forms a first deposition area through the unshielded area, and at the same time, bypasses the shielded area to form a second deposition area, the second deposition area is a bypass plating area, and the first deposition area and the bypass plating area form a doped amorphous silicon layer of an integrated structure; the baffle includes a plurality of dispersed blocks, and adjacent blocks are connected by a wire harness; the plurality of blocks form a shielded area, and the area outside the plurality of blocks forms an unshielded area; The doped amorphous silicon layer is annealed to form the doped polysilicon layer, wherein the first region corresponds to the first deposition region, and the second region corresponds to the bypass plating region.

3. The method for preparing a passivation contact structure according to claim 2, characterized in that: The size of the unshielded area is greater than the size of the metal grid line.

4. A solar cell, characterized in that: Comprising the passivation contact structure as claimed in claim 1.

5. A method for preparing a solar cell, characterized in that: The invention comprises a method for preparing the passivation contact structure as claimed in claim 2 or 3.

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