Switch gate discharge circuit after rapid power-off of the load switch input

Abstract

A gate discharge circuit for a switch tube after a load switch input terminal quickly loses power, characterized in that the circuit includes a voltage stabilizing unit, a sensing unit, a discharge unit, and a load switch; wherein the voltage stabilizing unit is connected to the discharge unit and is used to provide a stable voltage to the discharge unit during a power-off process at the load input terminal; the sensing unit is connected to the discharge unit and is used to sense the input voltage at the load input terminal and control the on or off state of the discharge unit based on the input voltage; the discharge unit is connected to the voltage stabilizing unit and the sensing unit and is used to discharge the gate of the load switch based on the stable voltage and the input voltage, thereby controlling the gate voltage of the load switch; and the load switch is connected to the discharge unit and is used to control the load output based on the voltage at the load input terminal and the gate voltage. The circuit of the present invention can protect subsequent loads and has a simple structure, is easy to implement, has low cost, a high safety factor, and low power consumption.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuits, and more particularly to a switching tube gate discharge circuit after a load switch input terminal is quickly powered off. Background Art

[0002] Currently, load switch chips, as integrated power switches, are widely used because they can provide a simple, cost-effective and effective way to turn on and off power rails.

[0003] Most commonly used load switches in the prior art also feature an undervoltage lockout (UVLO) function. However, because the UVLO module's circuit power supply is the load input voltage, it cannot function properly when the load input voltage rapidly drops to a very low level. This prevents the UVLO module, which has a shorter trigger delay, from fully discharging the load switch's gate terminal. Consequently, in the event of a second rapid power-on, the load switch directly switches on, resulting in excessive output current and damage to downstream loads.

[0004] Furthermore, existing chips designed specifically for low-voltage input scenarios typically lack UVLO functionality. Consequently, they cannot guarantee sufficient discharge of the load switch gate after a rapid power loss at the input. Consequently, these chips also face the problem of difficulty ensuring downstream load safety during a rapid power loss at the input.

[0005] Therefore, there is an urgent need for a switch tube gate discharge circuit after the load switch input terminal is quickly powered off. Summary of the Invention

[0006] In order to solve the deficiencies in the prior art, the purpose of the present invention is to provide a gate discharge circuit for a switch tube after a load switch input terminal quickly loses power. By sensing the voltage at the load input terminal, the discharge circuit is selectively turned on or off so that the discharge circuit discharges the gate of the load switch.

[0007] The present invention adopts the following technical solution: a gate discharge circuit for a load switch after a rapid power-off of a load switch input terminal, the circuit comprising a voltage stabilizing unit, a sensing unit, a discharge unit, and a load switch; wherein the voltage stabilizing unit is connected to the discharge unit and is configured to provide a stable voltage to the discharge unit during a power-off process at the load input terminal; the sensing unit is connected to the discharge unit and is configured to sense the input voltage at the load input terminal and control the on / off state of the discharge unit based on the input voltage; the discharge unit is connected to the voltage stabilizing unit and the sensing unit and is configured to discharge the gate of the load switch based on the stable voltage and the input voltage, thereby controlling the gate voltage of the load switch; and the load switch is connected to the discharge unit and is configured to control the load output based on the voltage at the load input terminal and the gate voltage.

[0008] Preferably, the voltage stabilizing unit outputs a stable voltage V when the voltage at the load input terminal is stable. B The same as the load input voltage; the voltage stabilizing unit, when the load input voltage drops rapidly, delays the drop of the load input voltage to stabilize the voltage V B of the decline.

[0009] Preferably, the voltage stabilizing unit includes a voltage stabilizing resistor R3 and a voltage stabilizing capacitor C1; wherein, one end of the voltage stabilizing resistor is connected to the load input end, and the other end serves as the output end of the stable voltage; one end of the voltage stabilizing capacitor C1 is connected to the output end of the stable voltage, and the other end is grounded.

[0010] Preferably, the sensing unit provides a first sensing voltage V to the discharge unit when the voltage at the load input terminal is stable. C To control the first discharge branch of the discharge unit to be cut off and provide the second induced voltage V A To control the second discharge branch of the discharge unit to be cut off; the induction unit provides the first induction voltage V to the discharge unit when the voltage at the load input terminal drops rapidly. C To control the first discharge branch of the discharge unit to be turned on and provide the second induced voltage V A To control the second discharge branch of the discharge unit to be turned on.

[0011] Preferably, the sensing unit includes a first PMOS transistor Mp0, a first NMOS transistor Mn0, a second NMOS transistor Mn1, a first resistor R0, a second resistor R1 and a third resistor R2; wherein the source of the first PMOS transistor Mp0 is connected to the load input terminal, and the drain and gate serve as the first sensing voltage V C The output terminal of the first NMOS transistor Mn0 is connected to the output terminal of the load, and the drain and gate are grounded after passing through the first resistor R0; the drain and gate of the first NMOS transistor Mn0 are connected to the load input terminal through the second resistor R1, and the source is grounded; the gate of the second NMOS transistor Mn1 is connected to the drain and gate of the first NMOS transistor Mn0, and the source is grounded through the third resistor R2. The drain serves as the second induced voltage V A output terminal.

[0012] Preferably, the discharge unit includes a first discharge branch and a second discharge branch; wherein the first and second discharge branches are respectively based on the first induced voltage V C , the second induced voltage V A On or off.

[0013] Preferably, the first discharge branch includes a second PMOS transistor Mp1 and a fourth NMOS transistor Mn3; wherein the gate of the second PMOS transistor Mp1 is connected to the first induced voltage V C The source is connected to the source of the fourth NMOS tube Mn3, and the drain is connected to the second induced voltage VA Connect the gate of the fourth NMOS tube Mn3 to the stable voltage V B The drain is connected to the gate of the load switch.

[0014] Preferably, the second discharge branch includes a third NMOS transistor Mn2 and a fifth NMOS transistor Mn4; wherein the gate of the third NMOS transistor Mn2 is connected to the second induced voltage V A The source is grounded, and the drain is connected to the source of the fifth NMOS tube Mn4; the gate of the fifth NMOS tube Mn4 is connected to the stable voltage V B The drain is connected to the gate of the load switch.

[0015] Preferably, the gate of the load switch Mnpwr is connected to the discharge unit, the drain is connected to the load input terminal, and the source serves as the load output terminal.

[0016] Preferably, when the load input terminal voltage is stable, the gate voltage of the load switch is not affected by the discharge circuit; when the load input terminal voltage drops rapidly, the gate voltage of the load switch decreases based on the discharge effect of the discharge circuit.

[0017] The present invention has the beneficial effect of, compared to the prior art, providing a gate discharge circuit for a load switch after a rapid power loss at the load switch input. This circuit can selectively turn on or off the discharge circuit by sensing the voltage at the load input, causing the discharge circuit to discharge the gate of the load switch. This allows the load output to be controlled when the load input rapidly loses power, protecting subsequent loads. The circuit of the present invention has a simple structure, is easy to implement, has low cost, a high safety factor, and low power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 This is a schematic diagram of an output curve of a load switch chip in the prior art of the present invention;

[0019] Figure 2 This is a structural schematic diagram of a switch tube gate discharge circuit after a load switch input terminal is quickly powered off according to the present invention;

[0020] Figure 3 The figure is a schematic diagram of an output curve of a gate discharge circuit of a switch tube after a load switch input terminal is quickly powered off according to the present invention. DETAILED DESCRIPTION

[0021] The present application will be further described below in conjunction with the accompanying drawings. The following embodiments are only used to more clearly illustrate the technical solutions of the present invention and are not intended to limit the scope of protection of the present application.

[0022] Figure 1 This is a schematic diagram of the output curve of a load switch chip in the prior art of the present invention. Figure 1As shown, since the power supply of the undervoltage lockout module UVLO of the common load switch in the prior art is the input terminal IN of the load switch, when the IN terminal is quickly powered off, the undervoltage lockout module loses its working power supply and cannot work, and the Gate terminal of the load switch cannot be fully discharged, which causes the voltage of the Gate terminal to be placed in a non-zero voltage state at the end of the first power-on. During the process of rapid power-off of the IN terminal, the Gate terminal cannot be fully discharged. Therefore, the voltage of the Gate terminal remains at a high state after the IN terminal is powered off once. This causes the current at the load output terminal to be large. When a second rapid power-on occurs, the input of the IN terminal increases, and the load switch is directly turned on, so that the current at the output terminal OUT of the load switch rapidly increases to an excessively large state, thereby causing the risk of damage to the subsequent load.

[0023] Specifically, the load driven by the output end of the load switch can be equivalent to a parallel circuit consisting of a resistor R and a first capacitor C, with one end connected to the ground and the other end connected to the source of the switch tube Mnpwr, that is, the output end OUT.

[0024] If the load switch remains in a conducting state between the input terminal IN and the output terminal OUT and has a stable current, it can be assumed that the value of the stable current is I load =IN / R. Therefore, when the input terminal IN is powered on once, the switching current I between the input terminal IN and the output terminal OUT in After a short delay, the current I load Then, when the input terminal IN loses power quickly, the switch current I in It also decreases rapidly. However, since the Gate terminal is not fully discharged, the switch tube Mnpwr is still in the on state after the first power-off. Therefore, when the input terminal IN is quickly powered on for the second time, the switch tube Mnpwr is directly turned on. Generally, there must be a capacitive load in the subsequent load driven by the output terminal OUT of the switch tube. Since the capacitance C of the output terminal OUT to ground has the characteristic of extremely small impedance in transient state, it can be seen that at this time the switch current quickly rises to the overcurrent state, and its maximum current exceeds the stable current I load As can be seen from the above description, when the input terminal IN is powered on quickly for the second time, an excessive current will flow into the load, which can easily damage the load.

[0025] In order to solve the above problems, the present invention provides a switch tube gate discharge circuit after a load switch input terminal is quickly powered off, which is specifically described as follows.

[0026] Figure 2 This is a schematic diagram of the structure of the switch gate discharge circuit after a load switch input terminal is quickly powered off. Figure 2As shown, a gate discharge circuit of a switch tube after a load switch input terminal quickly loses power is characterized in that the circuit includes a voltage stabilizing unit, a sensing unit, a discharge unit and a load switch; wherein the voltage stabilizing unit is connected to the discharge unit and is used to provide a stable voltage for the discharge unit during the power-off process of the load input terminal; the sensing unit is connected to the discharge unit and is used to sense the input voltage of the load input terminal and control the on or off state of the discharge unit based on the input voltage; the discharge unit is connected to the voltage stabilizing unit and the sensing unit and is used to discharge the gate of the load switch based on the stable voltage and the input voltage, thereby controlling the gate voltage of the load switch; the load switch is connected to the discharge unit and is used to control the load output based on the voltage of the load input terminal and the gate voltage.

[0027] Preferably, the voltage stabilizing unit outputs a stable voltage V when the voltage at the load input terminal is stable. B Same as the load input voltage; when the load input voltage drops rapidly, the stable voltage V caused by delaying the drop of the load input voltage B Specifically, fast drop means that the speed at which the voltage at the load input terminal drops should be much smaller than the interval between each power-on of the load switch.

[0028] Preferably, the voltage stabilizing unit includes a voltage stabilizing resistor R3 and a voltage stabilizing capacitor C1; wherein, one end of the voltage stabilizing resistor is connected to the load input end, and the other end serves as the output end of the stable voltage; one end of the voltage stabilizing capacitor C1 is connected to the output end of the stable voltage, and the other end is grounded.

[0029] For the voltage stabilization unit, when the load input terminal IN does not experience a rapid power loss, the output stable voltage is the same as the voltage at the load input terminal, that is, V B =IN. When the load input terminal experiences a rapid power loss, due to the discharge effect of the voltage-stabilizing capacitor C1, the voltage at point B does not drop as quickly as the load input terminal, but remains near IN, thus providing a relatively stable voltage for the discharge unit.

[0030] Preferably, the sensing unit provides a first sensing voltage V to the discharge unit when the voltage at the load input terminal is stable. C To control the first discharge branch of the discharge unit to be cut off and provide the second induced voltage V A To control the second discharge branch of the discharge unit to be cut off; the induction unit provides the first induction voltage V to the discharge unit when the voltage at the load input terminal drops rapidly. C To control the first discharge branch of the discharge unit to be turned on and provide the second induced voltage V A To control the second discharge branch of the discharge unit to be turned on.

[0031] Preferably, the sensing unit includes a first PMOS transistor Mp0, a first NMOS transistor Mn0, a second NMOS transistor Mn1, a first resistor R0, a second resistor R1 and a third resistor R2; wherein the source of the first PMOS transistor Mp0 is connected to the load input terminal, and the drain and gate serve as the first sensing voltage V C The output terminal of the first NMOS transistor Mn0 is connected to the output terminal of the load, and the drain and gate are grounded after passing through the first resistor R0; the drain and gate of the first NMOS transistor Mn0 are connected to the load input terminal through the second resistor R1, and the source is grounded; the gate of the second NMOS transistor Mn1 is connected to the drain and gate of the first NMOS transistor Mn0, and the source is grounded through the third resistor R2. The drain serves as the second induced voltage V A output terminal.

[0032] Specifically, when the load input terminal IN does not experience a rapid power failure, the voltage at point C in the sensing unit should be the IN voltage minus the turn-on voltage V of the first PMOS transistor Mp0. gs0 , that is, V C =IN-V gs0 At this time, since the voltage at point B is IN, the voltage between the second PMOS transistor Mp1 and the fourth NMOS transistor Mn3 between points BC is V B -V C =V gs0 Since the first PMOS tube Mp0 has a conduction voltage V gs0 Therefore, the voltage cannot turn on the second PMOS transistor Mp1 and the fourth NMOS transistor Mn3 at the same time. Therefore, at this time, the first induction voltage V provided by the induction unit to the discharge unit is C The fourth NMOS transistor Mn3 and the second PMOS transistor Mp1 in the discharge unit are in the cut-off state.

[0033] Furthermore, when the fourth NMOS transistor Mn3 is in the cut-off state, the voltage at point A is pulled down to the ground potential, that is, the second induced voltage V A ≈0, which is less than the conduction threshold of the third NMOS transistor Mn2. After the second induced voltage is input to the discharge unit, the third NMOS transistor Mn2 of the discharge unit is also in the cut-off state.

[0034] On the other hand, when the load input terminal IN experiences a rapid power failure and its voltage drops to 0 V, the voltage at point C also drops to 0 V. At this time, the voltage difference between points BC is large, substantially equal to that at IN, thus enabling both the second PMOS transistor Mp1 and the fourth NMOS transistor Mn3 to be turned on simultaneously.

[0035] In addition, the second NMOS transistor Mn1, whose gate is connected to the load input terminal via the second resistor R1, enters the cutoff state and loses its ability to pull down the voltage at point A. Due to the turned-on second PMOS transistor Mp1 and fourth NMOS transistor Mn3, the voltage at point A increases, thereby turning on the third NMOS transistor Mn2.

[0036] Preferably, the discharge unit includes a first discharge branch and a second discharge branch; wherein the first and second discharge branches are respectively based on the first induced voltage V C , the second induced voltage V A On or off.

[0037] Preferably, the first discharge branch includes a second PMOS transistor Mp1 and a fourth NMOS transistor Mn3; wherein the gate of the second PMOS transistor Mp1 is connected to the first induced voltage V C The source is connected to the source of the fourth NMOS tube Mn3, and the drain is connected to the second induced voltage V A Connect the gate of the fourth NMOS tube Mn3 to the stable voltage V B The drain is connected to the gate of the load switch.

[0038] Preferably, the second discharge branch includes a third NMOS transistor Mn2 and a fifth NMOS transistor Mn4; wherein the gate of the third NMOS transistor Mn2 is connected to the second induced voltage V A The source is grounded, and the drain is connected to the source of the fifth NMOS tube Mn4; the gate of the fifth NMOS tube Mn4 is connected to the stable voltage V B The drain is connected to the gate of the load switch.

[0039] It is understood that when the IN terminal does not experience a rapid power loss, since both the first and second discharge branches are in the off state, the gate voltage of the load switch rises and falls freely, controlled only by the drive voltage, and the discharge circuit of the present invention has no effect on the gate voltage. However, when the IN terminal experiences a rapid power loss, the first and second discharge branches simultaneously conduct, causing the Gate terminal (i.e., the gate of the load switch) to be in a conductive state with respect to the ground potential. The Gate terminal is rapidly discharged, and its voltage quickly drops to a low potential.

[0040] Preferably, the gate of the load switch Mnpwr is connected to the discharge unit, the drain is connected to the load input terminal, and the source serves as the load output terminal.

[0041] Preferably, when the load input terminal voltage is stable, the gate voltage of the load switch is not affected by the discharge circuit; when the load input terminal voltage drops rapidly, the gate voltage of the load switch decreases based on the discharge effect of the discharge circuit.

[0042] Specifically, since the voltage at the Gate terminal is discharged to the ground potential when the load input terminal is quickly powered off, the output voltage of the load switch will not significantly follow the load input terminal during the next power-on process. Therefore, no excessive current will flow out of the load switch, thereby protecting the safety of the subsequent load.

[0043] Figure 3 This is a schematic diagram of the output curve of the switch gate discharge circuit after a load switch input terminal is quickly powered off. Figure 3 As shown, Figure 1 Compared with the output curve in , after the gate discharge circuit of the switch tube is connected to the circuit, the voltage at the Gate terminal will be discharged to 0 potential during the rapid power-off process of the input terminal IN, thereby turning off the switch tube. At this time, the voltage at the output terminal OUT also drops to 0, and the output current I in There will be no overcharging during the second power-on process.

[0044] The present invention has the beneficial effect of, compared to the prior art, providing a gate discharge circuit for a load switch after a rapid power loss at the load switch input. This circuit can selectively turn on or off the discharge circuit by sensing the voltage at the load input, causing the discharge circuit to discharge the gate of the load switch. This allows the load output to be controlled when the load input rapidly loses power, protecting subsequent loads. The circuit of the present invention has a simple structure, is easy to implement, has low cost, a high safety factor, and low power consumption.

[0045] The applicant of the present invention has made a detailed explanation and description of the implementation examples of the present invention in conjunction with the drawings in the specification. However, those skilled in the art should understand that the above implementation examples are only preferred implementation plans of the present invention, and the detailed description is only to help readers better understand the spirit of the present invention, and is not a limitation on the scope of protection of the present invention. On the contrary, any improvements or modifications based on the inventive spirit of the present invention should fall within the scope of protection of the present invention.

Claims

1. A gate discharge circuit for a load switch after a rapid power-off of the input terminal of the load switch, characterized in that: The circuit includes a voltage stabilizing unit, a sensing unit, a discharging unit and a load switch; wherein, The voltage stabilizing unit is connected to the discharge unit and is used to provide a stable voltage to the discharge unit during power failure of the load input terminal; The sensing unit is connected to the discharge unit and is used to sense the input voltage of the load input terminal and control the on or off state of the discharge unit based on the input voltage; The induction unit provides a first induction voltage V to the discharge unit when the voltage at the load input terminal is stable. C To control the first discharge branch of the discharge unit to be cut off and provide the second induced voltage V A To control the second discharge branch of the discharge unit to be cut off; The induction unit provides a first induction voltage V to the discharge unit when the voltage at the load input terminal drops rapidly. c To control the first discharge branch of the discharge unit to be turned on and provide the second induced voltage V A To control the second discharge branch of the discharge unit to be turned on; The discharge unit is connected to the voltage stabilizing unit and the sensing unit, and is used to discharge the gate of the load switch based on the stabilizing voltage and the input voltage, thereby controlling the gate voltage of the load switch; The load switch is connected to the discharge unit and is used to control the load output based on the voltage at the load input terminal and the gate voltage.

2. The switch gate discharge circuit after a rapid power-off of a load switch input terminal according to claim 1, characterized in that: The voltage stabilizing unit outputs a stable voltage V when the voltage at the load input terminal is stable. B The same as the load input voltage; The voltage stabilizing unit delays the stable voltage V caused by the drop of the load input terminal voltage when the load input terminal voltage drops rapidly. B of the decline.

3. The switch gate discharge circuit after rapid power-off of the load switch input terminal according to claim 2, characterized in that: The voltage stabilizing unit includes a voltage stabilizing resistor R3 and a voltage stabilizing capacitor C1; wherein, One end of the voltage-stabilizing resistor is connected to the load input end, and the other end serves as the output end of the stable voltage; One end of the voltage stabilizing capacitor C1 is connected to the output end of the stable voltage, and the other end is grounded.

4. The switch gate discharge circuit after rapid power-off of the load switch input terminal according to claim 1, characterized in that: The sensing unit includes a first PMOS transistor Mp0, a first NMOS transistor Mn0, a second NMOS transistor Mn1, a first resistor R0, a second resistor R1 and a third resistor R2; wherein, The source of the first PMOS transistor Mp0 is connected to the load input terminal, and the drain and gate serve as the first induced voltage V C The output end of , and the drain and gate are grounded after passing through a first resistor R0; The drain and gate of the first NMOS transistor Mn0 are connected to the load input terminal via a second resistor R1, and the source is grounded; The gate of the second NMOS transistor Mn1 is connected to the drain and gate of the first NMOS transistor Mn0, the source is grounded through the third resistor R2, and the drain serves as the second induced voltage V A output terminal.

5. The switch gate discharge circuit after rapid power-off of the load switch input terminal according to claim 4, characterized in that: The first discharge branch includes a second PMOS transistor Mp1 and a fourth NMOS transistor Mn3; wherein, The gate of the second PMOS transistor Mp1 is connected to the first induced voltage V C The source is connected to the source of the fourth NMOS tube Mn3, and the drain is connected to the second induced voltage V A connect; The gate of the fourth NMOS transistor Mn3 is connected to the stable voltage V B The drain is connected to the gate of the load switch.

6. The switch gate discharge circuit after rapid power-off of the load switch input terminal according to claim 5, characterized in that: The second discharge branch includes a third NMOS transistor Mn2 and a fifth NMOS transistor Mn4; wherein, The gate of the third NMOS transistor Mn2 is connected to the second induced voltage V A The source is grounded, and the drain is connected to the source of the fifth NMOS transistor Mn4; The gate of the fifth NMOS transistor Mn4 is connected to the stable voltage V B The drain is connected to the gate of the load switch.

7. The switch gate discharge circuit after rapid power-off of the load switch input terminal according to claim 1, characterized in that: The gate of the load switch is connected to the discharge unit, the drain is connected to the load input terminal, and the source serves as a load output terminal.

8. The switch gate discharge circuit after rapid power-off of the load switch input terminal according to claim 1, characterized in that: When the voltage at the load input terminal is stable, the gate voltage of the load switch is not affected by the discharge circuit; When the voltage at the load input terminal drops rapidly, the gate voltage of the load switch decreases based on the discharge action of the discharge circuit.

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