Battery protection chip and its power switch tube

Abstract

The present application relates to a battery protection chip and a power switch tube thereof, comprising two or more switch units connected in parallel, wherein the switch unit comprises a main power switch tube, a substrate selection tube and a substrate, wherein the substrate selection tube is evenly inserted on both sides of the main power switch tube, and the main power switch tube and the substrate selection tube are arranged between the substrate; the first end and the second end of the main power switch tube are respectively used to connect to the GND port and the VM port of the battery protection chip, and the control end of the main power switch tube is used to connect to the drive circuit of the battery protection chip; the control end of the substrate selection tube is used to connect to the drive circuit of the battery protection chip, the first end of the substrate selection tube is connected to the substrate, and the second end of the substrate selection tube located on one side of the main power switch tube is used to connect to the GND port of the battery protection chip, and the second end of the substrate selection tube located on the other side of the main power switch tube is used to connect to the VM port of the battery protection chip.

Description

Technical Field

[0001] The present application relates to the field of power semiconductor devices, and in particular to a battery protection chip and a power switch tube thereof. Background Art

[0002] Power switching transistors are essential components in lithium-ion battery protection chips. When abnormal conditions such as overcharge, overdischarge, charge overcurrent, discharge overcurrent, and discharge short circuit occur within the chip, the power transistors are shut down to isolate the battery's charge and discharge paths, thereby protecting the battery. As the core component of the lithium-ion battery safety protection circuit, the performance of the power transistors directly impacts the operational stability and safety of the entire battery system. Therefore, their rational design is crucial.

[0003] Currently, there are two main implementations for lithium battery protection. The first uses dual NMOS power switches. The two power switches can be external or packaged together with the lithium battery protection chip. This solution requires two low-on-resistance NMOS tubes connected in series, which is relatively expensive in terms of both packaging costs and power switch device costs. The second is to use a built-in power switch in the lithium battery protection chip. This solution only has one internally integrated NMOS tube, whose substrate is controlled by a logic drive circuit to achieve conversion between the GND port and the VM port. Compared with the above dual power switch solution, this solution has a significant cost reduction. However, this solution is not yet very mature and has many shortcomings. For example, the conduction uniformity of the power switch tube needs to be further improved. Summary of the Invention

[0004] Based on this, it is necessary to provide a battery protection chip and its power switch tube to address the problem of conduction uniformity of the power switch tube.

[0005] A power switch tube of a battery protection chip, comprising two or more switch units connected in parallel, wherein the switch unit comprises a main power switch tube, a substrate selection tube, and a substrate, wherein the substrate selection tubes are evenly inserted on both sides of the main power switch tube, and the main power switch tube and the substrate selection tube are arranged between the substrate;

[0006] The first end and the second end of the main power switch tube are respectively used to connect to the GND port and the VM port of the battery protection chip, and the control end of the main power switch tube is used to connect to the drive circuit of the battery protection chip; the control end of the substrate selection tube is used to connect to the drive circuit of the battery protection chip, the first end of the substrate selection tube is connected to the substrate, and the second end of the substrate selection tube located on one side of the main power switch tube is used to connect to the GND port of the battery protection chip, and the second end of the substrate selection tube located on the other side of the main power switch tube is used to connect to the VM port of the battery protection chip.

[0007] In one embodiment, the switch unit includes a first part and a second part that are symmetrically arranged, and both the first part and the second part include the main power switch tube and the substrate selection tubes uniformly inserted on both sides of the main power switch tube.

[0008] In one embodiment, the substrate is provided on both sides of the first portion and the second portion.

[0009] In one embodiment, the ratio of the number of substrate selection tubes on both sides of the main power switch tube to the main power switch tube is 1:1:(2N-1), where N is a positive integer from 2 to 20.

[0010] In one embodiment, the power switch tube further includes a deep N-well and an N-well, the deep N-well and the N-well are isolated to form the substrate, and the deep N-well and the N-well are connected to a GND port of the battery protection chip.

[0011] In one embodiment, the main power switch tube and the substrate selection tube are both MOS tubes.

[0012] A battery protection chip comprises a drive circuit and the power switch tube as described above.

[0013] In one embodiment, the driving circuit includes an inverter, a first-input OR gate circuit, a second-input OR gate circuit, and a two-input NOR gate circuit. The output end of the first-input OR gate circuit is connected to the first input end of the two-input NOR gate circuit, the output end of the second-input OR gate circuit is connected to the second input end of the two-input NOR gate circuit and the input end of the inverter. The output end of the inverter is connected to the control end of a substrate selection transistor located on one side of a main power switch tube. The output end of the two-input NOR gate circuit is connected to the control end of the main power switch tube. The output end of the second-input OR gate circuit is also connected to the control end of a substrate selection transistor located on the other side of the main power switch tube.

[0014] In one embodiment, the first input OR gate circuit is a three-input OR gate circuit, and the input terminals of the three-input OR gate circuit are respectively connected to a discharge signal port, a discharge overcurrent signal port, and a discharge short circuit port.

[0015] In one embodiment, the second input OR gate circuit is a two-input OR gate circuit, and the input ends of the two-input OR gate circuit are respectively connected to the charging signal port and the charging overcurrent signal port.

[0016] In the aforementioned battery protection chip and its power switch, substrate selection tubes are evenly inserted on both sides of the main power switch, with the main power switch and substrate selection tubes positioned between the substrate. The first and second ends of the main power switch are connected to the GND and VM ports of the battery protection chip, respectively. The first end of the substrate selection tube is connected to the substrate, and the second end of the substrate selection tube on one side of the main power switch is connected to the GND port of the battery protection chip, while the second end of the substrate selection tube on the other side of the main power switch is connected to the VM port of the battery protection chip. By evenly inserting the substrate selection tubes on both sides of the main power switch, the issue of conduction uniformity of the power switches can be effectively addressed. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 This is a schematic diagram of the structure of a traditional lithium battery protection chip using dual NMOS power tubes;

[0018] Figure 2 This is a schematic diagram of the structure of a traditional lithium battery protection chip using an internally integrated NMOS power tube;

[0019] Figure 3 This is a schematic diagram of the structure of a power switch tube in one embodiment;

[0020] Figure 4 This is a schematic cross-sectional view of the structure of a power switch tube in one embodiment;

[0021] Figure 5 Schematic diagram of the structure of the deep N-well and the N-well of the power switch tube when connected to a high potential in one embodiment;

[0022] Figure 6 Schematic diagram of the principle of a lithium battery protection chip in one embodiment. DETAILED DESCRIPTION

[0023] To make the above-mentioned objects, features, and advantages of the present invention more readily apparent, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings. The following description sets forth numerous specific details to facilitate a full understanding of the present invention. However, the present invention can be implemented in many other ways than those described herein, and those skilled in the art may make similar modifications without departing from the scope of the present invention. Therefore, the present invention is not limited to the specific embodiments disclosed below.

[0024] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application pertains. The terms used herein in the specification of this application are for the purpose of describing specific embodiments only and are not intended to limit this application.

[0025] It will be understood that the terms "first portion," "second portion," and the like used herein may be used to describe various components herein, but these components are not limited by these terms. These terms are used solely to distinguish a first component from another component. For example, resistor R1 may be referred to as resistor R2, and similarly, resistor R2 may be referred to as resistor R1, without departing from the scope of this application. Resistor R1 and resistor R2 are both resistors, but they are not the same resistor.

[0026] It can be understood that the "connection" and "connection" in the following embodiments should be understood as "electrical connection", "communication connection", etc. if the connected circuits, modules, units, etc. have electrical signals or data transmission with each other.

[0027] In the following embodiments, the terms “connection” and “connection” should be understood as “electrical connection”, “communication connection”, etc., if there is transmission of electrical signals or data between the connected circuits, modules, units, etc.

[0028] When used herein, the singular forms "a", "an", and "the" may also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" and the like specify the presence of stated features, integers, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, integers, steps, operations, components, parts, or combinations thereof.

[0029] It can be understood that power switching tubes mainly include bipolar power switching tubes BJT (bipolar transistor) and metal-oxide field effect transistors MOSFET (Metal Oxide Semiconductor Field Effect Transistor), and metal-oxide field effect transistors include N-type metal-oxide field effect transistors and P-type metal-oxide field effect transistors. The "power switching tube" in the following embodiments refers to the N-type metal-oxide field effect transistor NMOS.

[0030] like Figure 1As shown, one current battery protection implementation adopts this dual-NMOS power tube switch structure, where the VDD (Voltage Device) pin refers to the operating voltage port inside the device, the GND (Ground) pin refers to the wire ground port, and the VM (Voltage Maximum) pin refers to the overcurrent and short-circuit protection voltage detection port. The DO (Dout) pin refers to the over-discharge and over-current control port, which controls the on and off of the power switch tube Q1, and Q1 is the discharge tube; the CO (Cout) pin refers to the overcharge control port, which controls the on and off of the power switch tube Q2, and Q2 is the charging tube. The two power switches can be external or sealed together with the lithium battery protection chip.

[0031] like Figure 2 As shown, another current battery protection solution uses an internal power switch structure. This solution has a single integrated NMOS transistor, whose substrate is controlled by a logic drive circuit to switch between the GND port and the VM port. When the battery is fully charged, the NMOS transistor's substrate switches to the VM port, shutting off the charging path while retaining the discharge path. When the battery is fully discharged, the NMOS transistor's substrate switches to the GND port, shutting off the discharge path while retaining the charging path.

[0032] Based on the above analysis, a dual-NMOS power switch structure for battery protection requires two low-on-resistance NMOS transistors connected in series, resulting in high packaging and power switch device costs. When using an internal power switch (NMOS) structure for battery protection, the dual NMOS power switches are replaced with internally integrated NMOS transistors. This solution significantly reduces costs compared to the aforementioned dual-power switch protection solution. However, this solution is not yet fully mature. For example, differences in NMOS transistor internal parameters such as threshold voltage, on-resistance, inter-electrode capacitance, and transconductance can lead to dynamic and static current imbalance, which can easily cause power switch conduction uniformity issues. Furthermore, during the charging and discharging process of lithium batteries, static electricity can accumulate in instruments or equipment, and even in the components themselves. Unknowingly, if charged objects come into contact with these objects, a discharge path is formed, resulting in ESD (electrostatic discharge) uniformity issues. Excessive static electricity can instantly damage electronic components or systems.

[0033] Based on this, in one embodiment, Figure 3A schematic diagram of the structure of a power switch tube is provided. The power switch tube includes two or more parallel switch units, each of which includes a main power switch tube, a substrate selector tube, and a substrate. The substrate selector tubes are evenly inserted on both sides of the main power switch tube, and the main power switch tube and the substrate selector tube are disposed between the substrate. The first and second ends of the main power switch tube are respectively connected to the GND port and VM port of the battery protection chip. The control end of the main power switch tube is connected to the drive circuit of the battery protection chip. The control end of the substrate selector tube is connected to the drive circuit of the battery protection chip. The first end of the substrate selector tube is connected to the substrate. The second end of the substrate selector tube on one side of the main power switch tube is connected to the GND port of the battery protection chip, and the second end of the substrate selector tube on the other side of the main power switch tube is connected to the VM port of the battery protection chip.

[0034] The power switch unit may include a symmetrically arranged first and second parts, each of which includes a main power switch tube and substrate select tubes evenly inserted on both sides of the main power switch tube. Furthermore, substrates are provided on both sides of the first and second parts. Specifically, the main power switch tube and the substrate select tube are NMOS tubes of the same model. The first end of the power switch tube specifically refers to the source port of the NMOS tube, the second end of the power switch tube specifically refers to the drain port of the NMOS tube, and the control end of the power switch tube specifically refers to the gate port of the NMOS tube. The GATE0 pin refers to the gate port of the main power switch tube, the GATE1 and GATE2 pins respectively refer to the gate ports of the substrate select tubes on both sides of the main power switch tube, and the BULK port refers to the substrate port.

[0035] The power switch tube of the above-mentioned battery protection chip can effectively solve the conduction uniformity problem of the power switch tube by evenly inserting the substrate selection tube to both sides of the main power switch tube, and can also effectively solve the ESD uniformity problem of the power switch tube.

[0036] Furthermore, the relationship between the number of substrate selection tubes and the main power switch tubes is not unique. In one embodiment, the ratio of the number of substrate selection tubes on both sides of the main power switch tube to the main power switch tube is 1:1:(2N-1), where N is a positive integer between 2 and 20. By evenly inserting the substrate selection tubes on both sides of the main power switch tube and designing the substrate selection tubes and the main power switch tubes to be in a certain ratio, the conduction uniformity and ESD uniformity of the power switch tubes are further addressed.

[0037] In one embodiment, Figure 4The figure shows a cross-sectional structure diagram of a switch unit in which substrate select transistors are evenly inserted on both sides of the main power switch. STI (Shallow Trench Isolation), GOX (Gate Oxide), and POLY (polycrystalline) are polycrystalline silicon layers. The power switch also includes a deep N-well (DNW) and an N-well (NW). The deep N-well and N-well isolate each other and form the substrate PW of the power switch.

[0038] like Figure 5 As shown in the figure, a parasitic bipolar junction transistor (BJT) exists in the power switch. When the deep N-well and N-well of the power switch are connected to the VDD port, a parasitic NPN transistor Q1 is introduced from the VDD port to the VM port. NPN transistor Q1 has a gain of approximately 10x when conducting in the forward direction. Under normal operation, the transistor is cut off, preventing latch-up risk. However, when subjected to external interference from the power supply or ESD, the NPN transistor turns on, creating a continuously amplifying loop in the circuit. Current is continuously amplified within this structure, creating a latch-up risk.

[0039] Specifically, in Figure 5 In the circuit structure shown, when the lithium battery is operating in a state of parasitic charging, the forward PN junction from the GND port to the VM port is turned on. At this time, for the parasitic NPN transistor Q1, the emitter junction is forward biased and the collector junction is reverse biased, operating in the amplification region. This will generate an uncontrolled current from the VDD port to the VM port, causing a latch-up problem.

[0040] In this embodiment, if Figure 4 As shown, by connecting the deep N-well and N-well of the power switch tube to the GND port, when the battery operates in the parasitic charging state, the forward PN junction from the GND port to the VM port is turned on. At this time, for the parasitic NPN tube, the emitter junction is forward biased, and the collector junction is zero biased because the deep N-well and N-well are connected to the GND potential. The transistor changes from operating in an oversaturated state in the parasitic charging state to operating in a critical saturation state, and no uncontrolled current is generated from the VDD port to the VM port. This approach can effectively solve the latch-up risk problem.

[0041] In one embodiment, Figure 6As shown, a battery protection chip is also provided, comprising a drive circuit 10 and the aforementioned power switch 20. The power switch 20 includes a main power switch M0, a substrate selection transistor M1 located on one side of the main power switch M0, and a substrate selection transistor M2 located on the other side of the main power switch M0. For example, if the main power switch M0, the substrate selection transistor M1, and the substrate selection transistor M2 are all NMOS transistors, the substrate of the main power switch M0 is selected between the GND port and the VM port by the substrate selection transistor M1 and the substrate selection transistor M2, respectively. The substrates of the main power switch M0, the substrate selection transistor M1, and the substrate selection transistor M2 are all connected together and to the source terminals of the substrate selection transistor M1 and the source terminals of the substrate selection transistor M2. The drain terminal of the substrate selection transistor M1 is connected to the GND port, and the drain terminal of the substrate selection transistor M2 is connected to the VM port.

[0042] The drive circuit 10 includes an inverter I3, a first-input OR gate circuit I1, a second-input OR gate circuit I2, and a two-input NOR gate circuit I4. The output of the first-input OR gate circuit I1 is connected to the first input of the two-input NOR gate circuit I4, the output of the second-input OR gate circuit I2 is connected to the second input of the two-input NOR gate circuit I4 and the input of the inverter I3, the output of the inverter I3 is connected to the control end of the substrate selection transistor M1, the output of the two-input NOR gate circuit I4 is connected to the control end of the main power switch transistor M0, and the output of the second-input OR gate circuit I2 is also connected to the control end of the substrate selection transistor M2. In this embodiment, the first input OR gate circuit I1 is a three-input OR gate circuit, whose input ends are respectively connected to the over-discharge signal port, the discharge over-current signal port, and the discharge short-circuit port, and receives the over-discharge signal UV, the discharge over-current signal DOC, and the discharge short-circuit signal SHORT to detect whether the discharge is abnormal; further, the second input OR gate circuit I2 is a two-input OR gate circuit, whose input ends are respectively connected to the over-charge signal port and the charge over-current signal port, and receives the over-charge signal OV and the charge over-current signal COC to detect whether the charging is abnormal.

[0043] The working principle of the circuit in this embodiment can be explained from two aspects: control of the gate GATE0 of the main power switch tube M0 and control of the substrate BULK of the main power switch tube M0.

[0044] Control of the gate GATE0 of the main power switch M0: When any one of the five abnormal signals (overcharge signal OV, charge overcurrent signal COC, discharge signal UV, discharge overcurrent signal DOC, and discharge short circuit SHORT) is high, indicating a corresponding abnormal state, the gate GATE0 of the main power switch M0 must be set to a low level. For example, when a charging error related to overcharge or charge overcurrent occurs, the second-input OR gate I2 outputs a high level, and the output signal of the two-input NOR gate I4 is a low level, which means that the gate GATE0 of the main power switch M0 is low, thereby shutting down. For another example, when a discharge error related to overdischarge, discharge overcurrent, or discharge short circuit occurs, the first-input OR gate I1 outputs a high level, and the output signal of the two-input NOR gate I4 is a low level, which means that the gate GATE0 of the main power switch M0 is low, thereby shutting down.

[0045] Control of the substrate BULK of the main power switch tube M0: When a charging error related to overcharging or charging overcurrent occurs, the charging path needs to be cut off and the discharge path needs to be retained. Therefore, the substrate BULK of M0 needs to be connected to the VM port, the substrate selection tube M1 is turned off, the substrate selection tube M2 is turned on, and the forward conduction direction of the parasitic diode is from the VM port to the GND port; when a discharge error related to overdischarge, discharge overcurrent, or discharge short circuit occurs, the discharge path needs to be cut off and the charging path needs to be retained. Therefore, the substrate BULK of the main power switch tube M0 needs to be connected to the GND port, the substrate selection tube M1 is turned on, the substrate selection tube M2 is turned off, and the forward conduction direction of the parasitic diode is from the GND port to the VM port.

[0046] In battery protection applications, batteries can lose charge due to prolonged idleness, a phenomenon known as self-discharge. This self-discharge can cause the battery voltage to drop. To ensure proper battery charging, the parasitic diode charging path must be maintained. The substrate of the main power switch M0 must be connected to the GND port, preserving the charging path while disabling the discharge path. Therefore, by default, the substrate of the main power switch M0 must be connected to the GND port, and it should only be switched to the VM port in the event of an overcharge or overcurrent error.

[0047] According to the above principles, when no charging error related to overcharging or overcurrent occurs, both the charging signal OV and the charging overcurrent signal OCC are low, the second input OR gate circuit I2 outputs a low level, the substrate select transistor M2 connected to the VM port is off, the inverter I3 outputs a high level, the substrate select transistor M1 connected to the GND port is turned on, and the substrate of the main power switch M0 needs to be connected to the GND port. When a charging error related to overcharging or overcurrent occurs, at least one of the charging signal OV and the charging overcurrent signal OCC is low, the second input OR gate circuit I2 outputs a high level, the substrate select transistor M2 connected to the VM port is turned on, the inverter I3 outputs a low level, the substrate select transistor M1 connected to the GND port is turned off, and the substrate of the main power switch M0 needs to be connected to the VM port.

[0048] The battery protection chip detects and controls abnormal signals such as the overcharge signal OV, the charge overcurrent signal COC, the discharge signal UV, the discharge overcurrent signal DOC, and the discharge short-circuit signal SHORT by controlling the gate GATE0 and substrate BULK of the main power switch M0, thus protecting the battery from charge and discharge. By evenly placing the substrate select transistors M1 and M2 on either side of the main power switch M0 and maintaining a specific ratio between the substrate select transistors M1 and M2 and the main power switch M0, this approach effectively addresses power switch conduction uniformity and ESD uniformity.

[0049] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features in the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0050] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that a person skilled in the art could make various modifications and improvements without departing from the spirit of the present application, all of which fall within the scope of protection of the present application. Therefore, the scope of protection of the present patent application shall be determined by the appended claims.

Claims

1. A power switch tube of a battery protection chip, characterized in that: The switch unit comprises two or more switch units connected in parallel, wherein the switch unit comprises a main power switch tube, a substrate selection tube and a substrate, wherein the substrate selection tubes are evenly inserted on both sides of the main power switch tube, and the main power switch tube and the substrate selection tube are arranged between the substrate; The first and second ends of the main power switch tube are respectively used to connect to the GND port and VM port of the battery protection chip, and the control end of the main power switch tube is used to connect to the drive circuit of the battery protection chip; the control end of the substrate selection tube is used to connect to the drive circuit of the battery protection chip, the first end of the substrate selection tube is connected to the substrate, and the second end of the substrate selection tube located on one side of the main power switch tube is used to connect to the GND port of the battery protection chip, and the second end of the substrate selection tube located on the other side of the main power switch tube is used to connect to the VM port of the battery protection chip; The switch unit includes a first part and a second part that are symmetrically arranged, and both the first part and the second part include the main power switch tube and the substrate selection tube evenly inserted on both sides of the main power switch tube, and substrates are provided on both sides of the first part and the second part.

2. The power switch tube according to claim 1, characterized in that: The number ratio between the substrate selection tubes on both sides of the main power switch tube and the main power switch tube is 1:1:(2N-1), where N is a positive integer from 2 to 20.

3. The power switch tube according to claim 1, characterized in that: It also includes a deep N-well and an N-well, wherein the deep N-well and the N-well are isolated to form the substrate, and the deep N-well and the N-well are connected to the GND port of the battery protection chip.

4. The power switch tube according to any one of claims 1 to 3, characterized in that: The main power switch tube and the substrate selection tube are both MOS tubes.

5. A battery protection chip, characterized in that: The invention comprises a driving circuit and a power switch tube as claimed in any one of claims 1 to 4.

6. The battery protection chip according to claim 5, characterized in that: The driving circuit includes an inverter, a first-input OR gate circuit, a second-input OR gate circuit, and a two-input NOR gate circuit. The output end of the first-input OR gate circuit is connected to the first input end of the two-input NOR gate circuit, the output end of the second-input OR gate circuit is connected to the second input end of the two-input NOR gate circuit and the input end of the inverter, the output end of the inverter is connected to the control end of the substrate selection tube located on one side of the main power switch tube, the output end of the two-input NOR gate circuit is connected to the control end of the main power switch tube, and the output end of the second-input OR gate circuit is also connected to the control end of the substrate selection tube located on the other side of the main power switch tube.

7. The battery protection chip according to claim 6, characterized in that: The first input OR gate circuit is a three-input OR gate circuit, and the input ends of the three-input OR gate circuit are respectively connected to the over-discharge signal port, the discharge over-current signal port and the discharge short-circuit port.

8. The battery protection chip according to claim 6, characterized in that: The second input OR gate circuit is a two-input OR gate circuit, and the input ends of the two-input OR gate circuit are respectively connected to the charging signal port and the charging overcurrent signal port.

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