A chaotic power amplifier and a chaotic SPWM signal generation method

Abstract

This application provides a chaotic power amplifier and a method for generating a chaotic SPWM signal. The chaotic power amplifier includes: a chaotic time segment generation module, a chaotic SPWM signal generation module, and a circuit component module. It utilizes a computer and program to generate chaotic time segments, and a microcontroller, FPGA chip, or DSP microprocessor to generate the chaotic SPWM signal. An integrated circuit board or integrated chip is used in the circuit component module. These features make the chaotic power amplifier of this application simple to use and have a short development cycle. The chaotic SPWM signal generation method includes: generating a chaotic time segment based on a fundamental signal and a chaotic spread spectrum carrier signal; and generating a chaotic SPWM signal based on the chaotic time segment. The chaotic SPWM signal has the characteristics of a digital signal and carrier spread spectrum, has fewer harmonic components, and reduces electromagnetic interference to the circuit.

Description

Technical Field

[0001] This invention relates to the field of underwater acoustics, and in particular to a chaotic power amplifier and a method for generating chaotic SPWM signals. Background Technology

[0002] The general method for underwater detection and communication involves amplifying a modulated electrical signal and converting it into an acoustic signal using a transducer. The received acoustic signal is then converted back into an electrical signal, and useful information is obtained through signal processing. Generally, the transmitting sensitivity, receiving sensitivity, and efficiency of a transducer are limited. The most readily conceivable way to obtain a high signal-to-noise ratio underwater acoustic signal is to increase the power of the power amplifier. A crucial factor in increasing the power amplifier's power is its efficiency.

[0003] Class D power amplifiers are renowned for their high efficiency and are widely used in underwater acoustics. However, their drawbacks are also apparent: the PWM signal of a Class D power amplifier is a square wave with abundant harmonic components. These harmonics can cause severe electromagnetic interference to the circuit, potentially interfering with other surrounding electronic devices. Currently, the common method is to mitigate this interference to some extent through external passive filtering. In 2004, pseudo-random spread spectrum technology was applied to Class D audio amplifiers, and in 2008, a chaotic spread spectrum modulation technique was applied to Class D audio amplifiers. On the one hand, these technologies are only applicable to the audio range; on the other hand, these applications require complex chip designs and have long development cycles.

[0004] Currently, the PWM signal of power amplifiers has rich harmonic components, which in turn causes serious electromagnetic interference to the circuit. In addition, power amplifiers adopt complex chip designs and have long development cycles. Summary of the Invention

[0005] The purpose of this application is to address the deficiencies in the existing technology.

[0006] With the deepening research on chaotic phenomena and the application of chaos in circuits, modulation, and other fields, chaotic-based circuits and their transmissions have gained stronger electromagnetic suppression and anti-interference capabilities. Therefore, the chaotic power amplifier involved in this application is mentioned as a completely new concept.

[0007] This application provides a chaotic power amplifier and a method for generating a chaotic SPWM signal. Unlike the square wave PWM signal of a Class D power amplifier, the chaotic SPWM signal of the chaotic power amplifier in this application has very low harmonic content, which reduces the serious electromagnetic interference to the circuit. Furthermore, the chaotic power amplifier in this application adopts a simple design method, which is convenient for debugging and application.

[0008] In a first aspect, this application provides a chaotic power amplifier, the chaotic power amplifier comprising: a chaotic time segment generation module, which generates a chaotic time segment based on a fundamental signal and a chaotic spread spectrum carrier signal; a chaotic SPWM signal generation module, which generates a chaotic SPWM signal based on the chaotic time segment; and a circuit component module, which performs power amplification and low-pass filtering on the chaotic SPWM signal to generate an amplified fundamental signal.

[0009] In one feasible embodiment, the chaotic time segment generation module includes: the chaotic time segment generation module is compiled into an algorithm program and stored in a computer, and the computer and the program are used to generate chaotic time segments.

[0010] In one feasible embodiment, the chaotic SPWM signal generation module includes: a microcontroller, the output mode of which is set to reset / flip mode; or an FPGA chip; or a DSP microprocessor.

[0011] In one feasible embodiment, the circuit component module includes: an integrated circuit board, including a driving circuit, a MOS amplifier, and a low-pass filter; or an integrated chip.

[0012] Secondly, this application discloses a method for generating a chaotic SPWM signal, the method comprising: generating a chaotic time segment based on a fundamental wave signal and a chaotic spread spectrum carrier signal; and generating a chaotic SPWM signal based on the chaotic time segment.

[0013] In a feasible embodiment, generating a chaotic time segment based on the fundamental wave signal and the chaotic spread spectrum carrier signal includes: generating a chaotic sequence by selecting an initial value; adding the chaotic sequence to the carrier signal to obtain a chaotic spread spectrum carrier signal; and generating a chaotic time segment by calculating the intersection point of the fundamental wave signal and the chaotic spread spectrum carrier signal, i.e., finding the value where the difference between the chaotic spread spectrum carrier signal and the fundamental wave signal is zero.

[0014] In one feasible embodiment, the step of generating a chaotic sequence by selecting initial values ​​includes: employing the LogisticTent chaotic mapping, whose recursive formula is: x n =k(1-2|x n-1 -0.5|), k∈(0,1), select the initial value x0 of the chaotic sequence xn, and iterate to generate the chaotic sequence.

[0015] In one feasible embodiment, adding a chaotic sequence to a carrier signal to obtain a chaotic spread spectrum carrier signal includes: adding a chaotic sequence to a triangular wave carrier signal to obtain a chaotic spread spectrum carrier signal, wherein the period of the chaotic spread spectrum carrier signal is T. i =T r +Δ·xn , among which, T r The period of the triangular wave carrier signal is Δ, which is an arbitrarily given coefficient. The process of generating a chaotic time segment by calculating the intersection of the fundamental signal and the chaotic spread spectrum carrier signal, i.e., finding the value where the difference between the chaotic spread spectrum carrier signal and the fundamental signal is zero, includes: the chaotic spread spectrum carrier signal is f1(t), and the fundamental signal can be written as f2(t) = M cos(ωt). s t+θ), where M is the modulation depth, ω s θ is the frequency of the modulating signal and θ is the phase of the modulating signal. By calculating the intersection of f2(t) and f1(t), i.e. f1(t)-f2(t)=0, a chaotic time segment is generated.

[0016] In one feasible embodiment, generating a chaotic SPWM signal based on the chaotic time segment includes: setting the counting frequency of the chaotic SPWM signal generation module; multiplying the chaotic time segment by the counting frequency to obtain a counting vector; when the counter / comparator 1 counts to a predetermined count value, entering an interrupt to modify the final value of the counter / comparator 2; when the counter / comparator 1 overflows, entering an interrupt to modify the final values ​​of both the counter / comparator 1 and the counter / comparator 2, wherein the counter / comparator 1 is used to control the frequency of the chaotic SPWM signal, and the counter / comparator 2 is used to control the duty cycle of the chaotic SPWM signal.

[0017] In a feasible embodiment, multiplying the chaotic time segment by the counting frequency to obtain the counting vector includes: the counting vector includes a chaotic time counting vector PW and a chaotic carrier period counting vector PWTi, wherein the chaotic time segment counting vector is PW = SMCLK·t msp430 The chaotic carrier period counting vector is PWTi = SMCLK·Ti, where SMCLK is the counting frequency and t is the periodicity of the carrier. msp430 The chaotic time segment is Ti, which is the chaotic carrier period; the predetermined count value includes half of the spread spectrum carrier period.

[0018] This application provides a chaotic power amplifier and a method for generating chaotic SPWM signals. The chaotic power amplifier includes a chaotic time segment generation module, a chaotic SPWM signal generation module, and a circuit component module. The chaotic SPWM signal generation method includes: generating a chaotic time segment based on a fundamental signal and a chaotic spread spectrum carrier signal; and generating a chaotic SPWM signal based on the chaotic time segment. In this application's chaotic power amplifier, the chaotic time segment generation module is compiled into an algorithm program and stored in a computer. The computer and program are used to generate chaotic time segments usable by a microcontroller. The chaotic SPWM signal generation module can use a microcontroller, an FPGA chip, or a DSP microprocessor to generate the chaotic SPWM signal. The circuit component module can use an integrated circuit board including a driver circuit, a MOS amplifier tube, and a low-pass filter; or an integrated chip. These features make the chaotic power amplifier of this application simple to use and have a short development cycle. Furthermore, the chaotic SPWM signal of the chaotic power amplifier of this application has the characteristics of digital signal and carrier spread spectrum. The amplitude of the carrier signal and its harmonic signals is very low, which makes the chaotic SPWM signal of the chaotic power amplifier of this application have fewer harmonic components, thereby reducing the electromagnetic interference of harmonic components to the circuit from the source. Attached Figure Description

[0019] Figure 1 This is a schematic diagram of the composition of a chaotic power amplifier according to an embodiment of the present invention;

[0020] Figure 2 This is a flowchart of a microcontroller-based chaotic SPWM signal generation method according to an embodiment of the present invention;

[0021] Figure 3 This is a block diagram of a chaotic time segment generation method according to an embodiment of the present invention;

[0022] Figure 4 This is a schematic diagram of the fundamental wave signal and the triangular wave chaotic spread spectrum carrier signal in an embodiment of the present invention;

[0023] Figure 5 This is a block diagram of a microcontroller-based chaotic SPWM signal generation method according to an embodiment of the present invention.

[0024] Figure 6 This is a schematic diagram of a chaotic SPWM signal without DC component according to an embodiment of the present invention;

[0025] Figure 7 This is a schematic diagram of a chaotic SPWM signal with a DC component according to an embodiment of the present invention;

[0026] Figure 8 This is a screenshot of the oscilloscope output of the chaotic SPWM signal according to an embodiment of the present invention.

[0027] Figure 9 A complete diagram of the frequency domain analysis of the chaotic SPWM signal in an embodiment of the present invention;

[0028] Figure 10 This is a partially enlarged view of the frequency domain analysis of the chaotic SPWM signal in an embodiment of the present invention. Detailed Implementation

[0029] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. It should be understood that the specific embodiments described herein are for illustrative purposes only and are not intended to limit the invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0030] To provide the public with a better understanding of this invention, certain specific details are described in detail below. However, those skilled in the art will fully understand this invention even without these detailed descriptions.

[0031] With the deepening research into chaotic phenomena, the application of chaos in circuits, modulation, and other fields has enabled chaotic-based circuits and their transmissions to possess stronger electromagnetic suppression and anti-interference capabilities. Therefore, chaotic power amplifiers have emerged as a novel concept. It is foreseeable that chaos will find increasingly wider applications in power amplifier circuits, extending beyond signal modulation based on chaotic sequences. The concept of chaotic power amplifiers proposed in this application, as research into chaos deepens, will extend its application in power amplifier design beyond chaotic modulation. Any power amplifier designed using chaotic phenomena and algorithms falls under the category of chaotic power amplifiers.

[0032] Firstly, this application proposes a simple design method for a chaotic power amplifier, which is easy to use, convenient and flexible, and its application is not limited to the audio range.

[0033] For example, Figure 1 This is a schematic diagram illustrating the composition of a chaotic power amplifier according to an embodiment of the present invention. Figure 1 As shown, the chaotic power amplifier includes:

[0034] The chaotic time segment generation module generates chaotic time segments based on the fundamental wave signal and the chaotic spread spectrum carrier signal.

[0035] A chaotic SPWM signal generation module generates the chaotic SPWM signal based on the chaotic time segment;

[0036] The circuit component module is used to amplify and low-pass filter the chaotic SPWM signal to generate an amplified fundamental signal.

[0037] For example, Figure 1 As shown, the circuit component module includes, but is not limited to: a protection circuit for protecting the circuit of the circuit component module; a driving circuit for receiving the chaotic SPWM signal as a chaotic SPWM signal and driving the circuit; a MOS amplifier (power amplifier) ​​for amplifying the chaotic SPWM signal; and a low-pass filter for low-pass filtering the chaotic SPWM signal to generate an amplified fundamental signal.

[0038] For example, Figure 1 As shown, the chaotic power amplifier of this application can be connected to, but is not limited to, transformers, matching circuits, transducers, etc. The amplified fundamental signal generated by the chaotic power amplifier of this application is converted into an acoustic signal by a transducer. The received acoustic signal is converted into an electrical signal, and then useful information is obtained through certain signal processing methods.

[0039] For example, a chaotic power amplifier includes a computer algorithm program for generating appropriate chaotic time segments, a microcontroller for generating chaotic SPWM signals, and a circuit board.

[0040] For example, in a computer algorithm program that generates appropriate chaotic time segments, a computer and program generate time segments usable by a microcontroller. These time segments are then written to a storage device accessible to the microcontroller or stored directly within the microcontroller. The microcontroller then outputs an SPWM signal based on the programmed time segments. Different chaotic sequences have varying spread spectrum effects; different chaotic sequences can be selected depending on the input signal. By using a computer algorithm in conjunction with a microcontroller, we can obtain the desired chaotic SPWM signal at any time. Regarding the circuit board, the driver circuit can be designed independently, MOS amplifier transistors can be added, and low-pass filters can be added, depending on specific needs. The circuit board can also be replaced with integrated chips, thus significantly reducing the development cycle of the chaotic power amplifier. For various applications, the chaotic power amplifier is very simple and easy to implement.

[0041] Secondly. Figure 2 This is a flowchart illustrating a microcontroller-based chaotic SPWM signal generation method according to an embodiment of the present invention. Figure 2 As shown, this embodiment provides a method for generating chaotic SPWM signals using a microcontroller-based chaotic power amplifier. The chaotic SPWM signal generation method includes:

[0042] Step S100: Based on the fundamental wave signal and the chaotic spread spectrum carrier signal, a chaotic time segment is generated;

[0043] Step S200: Based on the chaotic time segment, generate a chaotic SPWM signal.

[0044] Further explanation of step S100. Figure 3 This is a block diagram of a chaotic time segment generation method according to an embodiment of the present invention. Figure 3 As shown, step 100 of generating chaotic time segments further includes:

[0045] Step S110: By selecting initial values, a chaotic sequence is generated;

[0046] Step S120: Add the chaotic sequence to the carrier signal to obtain a chaotic spread spectrum carrier signal;

[0047] Step S130: By calculating the intersection of the fundamental wave signal and the chaotic spread spectrum carrier signal, that is, finding the value where the difference between the chaotic spread spectrum carrier signal and the fundamental wave signal is equal to zero, a chaotic time segment is generated.

[0048] For example, in step S110, the LogisticTent chaotic mapping is used, and its recursive formula (1) is:

[0049] x n =k(1-2|x n-1 -0.5|), k∈(0,1) (1)

[0050] By selecting an initial value x0 for the chaotic sequence xn, a chaotic sequence can be iteratively generated. The parameters are chosen as follows: k = 0.999; x0 = 0.3. The first 400 chaotic sequences are obtained: x n = [0.599400000000000 0.800398800000000 0.3988031976000000.796808788804799 ...... 0.0871183572745485 0.174062477834548 0.347776830713427 0.694858107765427]

[0054] In step S120, in the chaotic spread spectrum carrier signal calculation formula (3), let T... i It is the period of the triangular wave when adding a chaotic sequence, T r It is a fixed triangular wave period without the addition of a chaotic sequence, where Δ is an arbitrarily given coefficient.

[0055] T i =T r +Δ·x n (2)

[0056] Let Tr =0.001, Δ=0.0003, thus obtaining T i = [0.00117982000000000 0.00124011964000000 0.001119640959280000.00123904263664144 ...... 0.00102613550718236 0.00105221874335036 0.001104333049214030.00120845743232963]

[0060] In step S130, Figure 4 This is a schematic diagram of the fundamental wave signal and the triangular wave chaotic spread spectrum carrier signal according to an embodiment of the present invention. Figure 4 As shown, the intersection point of the triangular wave chaotic spread spectrum carrier signal and the fundamental wave signal is calculated. Using the intersection point of the chaotic spread spectrum carrier signal and the fundamental wave signal and the chaotic spread spectrum carrier signal, a chaotic time segment that can be used by the microcontroller is generated.

[0061] Let the function of the triangular wave be represented as f1(t), and the modulation function be written as f2(t) = M cos(ωt). s Let t+θ),

[0062] f1(t)-f2(t)=0 (3)

[0063] The intersection point of the two waves is calculated. Where M is the modulation depth, and ω... s θ is the frequency of the modulating signal, and θ is the phase of the modulating signal.

[0064] Assumption The amplitude of f1(t) is 1, and the period is as previously set. A set of intersection points is obtained as follows: t = [0.000135345346981897 0.000992487520162398 0.00140629393776499 ...... 0.456726586386412 0.457713502136315 0.457830943442779 0.458894428895686]

[0068] This generates a chaotic time segment t. msp430 = [0.000135345346981897 0.000187332479837602 0.000226473937764990 ......

[0071] 5.57132866516041e-05 6.17280198120795e-05 8.32439596112344e-05]

[0072] For example, the method for generating chaotic time segments using a computer in this embodiment of the invention can change the period of the carrier signal and the fundamental signal as needed, so it is applicable to the entire underwater acoustic range, not just the audio range. By selecting initial values, different chaotic functions can be selected to generate different chaotic sequences, or the same chaotic function can be used to generate different chaotic sequences, which is very convenient and simple. The generated chaotic sequence is added to the period of the carrier signal to obtain chaotic spread spectrum carrier signals with different periods. The intersection point of the fundamental signal and the chaotic spread spectrum carrier signal is calculated, that is, the value where the difference between the chaotic spread spectrum carrier signal and the fundamental signal is equal to zero is found, and stored as a chaotic time segment.

[0073] Further explanation of step S200. Figure 5 This is a block diagram of a microcontroller-based chaotic SPWM signal generation method according to an embodiment of the present invention. Figure 5 As shown, after generating chaotic time segments that can be used by a microcontroller using a computer and program, the method for generating chaotic SPWM signals is further explained.

[0074] Step S210: Set the counting frequency of the microcontroller;

[0075] Step S220: Enable overflow interrupt and global interrupt;

[0076] Step S230: Set the microcontroller output to reset / toggle mode;

[0077] Step S240: Multiply the chaotic time segment by the counting frequency to obtain the counting vector;

[0078] Step S250: When counter / comparator 1 counts to a predetermined count value, an interrupt is entered to modify the final value of counter / comparator 2; when counter / comparator 1 overflows, an interrupt is entered to modify the final values ​​of counter / comparator 1 and counter / comparator 2. The counter / comparator 1 is used to control the frequency of the chaotic SPWM signal, and the counter / comparator 2 is used to control the duty cycle of the chaotic SPWM signal.

[0079] In step S210, different counting frequencies can be selected for different carrier frequencies. When the counting frequency of the microcontroller is insufficient, it can even be implemented using an FPGA or DSP.

[0080] In step S240, the chaotic time segment is multiplied by the counting frequency to obtain the counting vector.

[0081] The counting vector is obtained using formula (4).

[0082] PW = SMCLK·t msp430 ;PWTi=SMCLK·Ti (4)

[0083] PW represents the chaotic time count vector to be generated, SMCLK is the counting frequency, and PWTi is the chaotic carrier period count vector.

[0084] In step S250, counter / comparator 1 is used to control the frequency of the chaotic SPWM signal, and counter / comparator 2 is used to control the duty cycle of the chaotic SPWM signal. Within one spread spectrum carrier cycle, the final value of counter / comparator 1 is modified once, and the final value of counter / comparator 2 is modified twice. The microcontroller outputs the chaotic SPWM signal in reset / flip mode, resulting in a signal without DC component, as shown in step S250. Figure 6 The SPWM signal shown is further processed to form a DC component, such as... Figure 7 The SPWM signal shown.

[0085] For example, a chaotic time segment is imported into the microcontroller, and then... Figure 5 The program runs to generate an SPWM signal. First, the microcontroller's counting frequency must be set. Multiplying the chaotic time segment by the counting frequency yields a counting vector including the count count. Whenever a predetermined count value is reached, the main program enters an interrupt to modify the count value for the next cycle. After the main program completes the modification, it enters a waiting state, awaiting the next interrupt. This modular design further illustrates the invention's simplicity, ease of use, and shortened development cycle. Simultaneously, the use of a reset / flip output prevents unexpected deviations during operation, allowing the program to recover quickly. Therefore, this design makes the chaotic power amplifier more robust.

[0086] For example, assuming SMCLK = 8000000, we get the following: Figure 8 The screenshot shown is a screenshot of the oscilloscope output of the chaotic SPWM signal. Frequency domain analysis of the chaotic SPWM signal yields the following results: Figure 9 The complete diagram of the frequency domain analysis of the chaotic SPWM signal in the embodiment of the present invention is shown below, and as shown in the figure below. Figure 10 The enlarged view shown is a partial image. Analysis of the frequency domain results from the oscilloscope-acquired data shows that the output chaotic SPWM signal has fulfilled its design function, achieving high-frequency removal and exhibiting excellent electromagnetic radiation suppression capabilities.

[0087] For example, this embodiment proposes an easily implemented chaotic power amplifier. The chaotic power amplifier first generates a chaotic time segment usable by a microcontroller counter using a method for generating chaotic time segments. Then, the microcontroller generates a chaotic SPWM signal, which is input to a driver chip. The driver chip drives a MOS transistor to amplify the chaotic SPWM signal, which is then low-pass filtered to generate an amplified fundamental signal. This easily implemented chaotic power amplifier provided by this embodiment employs a simple design approach, facilitating debugging and application.

[0088] For example, Figure 1 As shown, the chaotic power amplifier in this embodiment features a simple circuit design, facilitating debugging and application. Traditional Class D power amplifier designs require a series of processing steps on the input signal, such as DC protection and overvoltage protection. Furthermore, the carrier wave design cannot be easily altered, hindering general experimental research and algorithm verification. The method of this invention, by modifying the algorithm and program and combining it with existing development boards, enables various experimental research and algorithm verification. Simultaneously, it can be immediately applied in practice, shortening the R&D and production cycle. Small-scale applications also have lower costs.

[0089] For example, in this embodiment, the period of the carrier signal and the fundamental signal can be changed as needed when generating chaotic time segments. Therefore, this embodiment is applicable to the entire underwater acoustic range, not just the audio range. This embodiment increases the frequency range of the power amplifier. Related patents apply to the audio frequency band, but in the field of underwater acoustics, ultrasonic and infrasonic frequency bands are used in different application scenarios. The chaotic power amplifier of this invention can be easily applied to all sound wave frequency bands.

[0090] For example, this embodiment suppresses the radiation of the carrier signal and its harmonics. Fourier analysis of a conventional Class D power amplifier and this embodiment reveals that the amplitude of the carrier signal and its harmonics is significantly reduced in this embodiment. Therefore, the electromagnetic radiation generated by this embodiment is greatly reduced.

[0091] For example, this embodiment has stronger anti-interference capabilities. SPWM signals are inherently less sensitive to noise due to their digital signal characteristics, and now, due to the spread spectrum characteristics of the carrier, the chaotic power amplifier in this embodiment has even stronger anti-interference capabilities.

[0092] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. Therefore, it should be understood that the above description is only one specific implementation method of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A chaotic power amplifier, characterized in that, The chaotic power amplifier includes: The chaotic time segment generation module generates chaotic time segments based on the fundamental wave signal and the chaotic spread spectrum carrier signal; it further includes: generating a chaotic sequence by selecting an initial value; adding the chaotic sequence to the carrier signal to obtain a chaotic spread spectrum carrier signal; and generating a chaotic time segment by calculating the intersection point of the fundamental wave signal and the chaotic spread spectrum carrier signal, i.e., finding the value where the difference between the chaotic spread spectrum carrier signal and the fundamental wave signal is zero. A chaotic SPWM signal generation module generates a chaotic SPWM signal based on the chaotic time segment; further comprising: setting the counting frequency of the microcontroller; enabling overflow interrupt and global interrupt; setting the microcontroller output to reset / flip mode; multiplying the chaotic time segment by the counting frequency to obtain a counting vector; when counter / comparator 1 counts to a predetermined count value, entering an interrupt to modify the final value of counter / comparator 2; when counter / comparator 1 overflows, entering an interrupt to modify the final values ​​of counter / comparator 1 and counter / comparator 2, wherein counter / comparator 1 is used to control the frequency of the chaotic SPWM signal, and counter / comparator 2 is used to control the duty cycle of the chaotic SPWM signal; The circuit component module is used to amplify and low-pass filter the chaotic SPWM signal to generate an amplified fundamental signal.

2. The chaotic power amplifier according to claim 1, characterized in that, The chaotic time segment generation module includes: The chaotic time segment generation module is compiled into an algorithm program and stored in a computer, and the computer and program are used to generate chaotic time segments.

3. The chaotic power amplifier according to claim 1, characterized in that, The chaotic SPWM signal generation module includes: The microcontroller is configured to output a reset / flip mode; or an FPGA chip; or a DSP microprocessor.

4. The chaotic power amplifier according to claim 1, characterized in that, The circuit component module includes: Integrated circuit board, including driver circuit, MOS amplifier tube, low-pass filter; or integrated chip.

5. A method for generating a chaotic SPWM signal, used in a chaotic power amplifier as described in any one of claims 1-4, characterized in that, The method for generating the chaotic SPWM signal includes: Chaotic time segments are generated based on the fundamental wave signal and the chaotic spread spectrum carrier signal. Based on the chaotic time segment, a chaotic SPWM signal is generated.

6. The chaotic SPWM signal generation method according to claim 5, characterized in that, The generation of chaotic time segments based on the fundamental wave signal and the chaotic spread spectrum carrier signal includes: By selecting initial values, a chaotic sequence is generated; Adding a chaotic sequence to a carrier signal yields a chaotic spread spectrum carrier signal. By calculating the intersection of the fundamental wave signal and the chaotic spread spectrum carrier signal, that is, finding the value at which the difference between the chaotic spread spectrum carrier signal and the fundamental wave signal is equal to zero, a chaotic time segment is generated.

7. The chaotic SPWM signal generation method according to claim 6, characterized in that, The process of generating a chaotic sequence by selecting initial values ​​includes: using the LogisticTent chaotic mapping, whose recursive formula is: x n =k(1-2|x n-1 Given -0.5|), k∈(0,1), select the initial value x0 of the chaotic sequence xn, and iterate to generate the chaotic sequence.

8. The chaotic SPWM signal generation method according to claim 6, characterized in that, The step of adding a chaotic sequence to a carrier signal to obtain a chaotic spread spectrum carrier signal includes: adding a chaotic sequence to a triangular wave carrier signal to obtain a chaotic spread spectrum carrier signal, wherein the period of the chaotic spread spectrum carrier signal is T. i =T r +Δ·x n , among which, T r It is the period of the triangular wave carrier signal, and Δ is an arbitrarily given coefficient; The process involves calculating the intersection of the fundamental signal and the chaotic spread spectrum carrier signal, i.e., finding the value where the difference between the chaotic spread spectrum carrier signal and the fundamental signal is zero, to generate a chaotic time segment. This segment includes: the chaotic spread spectrum carrier signal being f1(t), and the fundamental signal being f2(t) = M cos(ωt). s t+θ), where M is the modulation depth, ω s θ is the frequency of the modulating signal and θ is the phase of the modulating signal. By calculating the intersection of f2(t) and f1(t), i.e. f1(t)-f2(t)=0, a chaotic time segment is generated.

9. The chaotic SPWM signal generation method according to claim 5, characterized in that, The generation of a chaotic SPWM signal based on the chaotic time segment includes: Set the counting frequency of the chaotic SPWM signal generation module; Multiply the chaotic time segment by the counting frequency to obtain the counting vector; When counter / comparator 1 counts to a predetermined count value, an interrupt is entered to modify the final value of counter / comparator 2; when counter / comparator 1 overflows, an interrupt is entered to modify the final values ​​of both counter / comparator 1 and counter / comparator 2. Counter / comparator 1 is used to control the frequency of the chaotic SPWM signal, and counter / comparator 2 is used to control the duty cycle of the chaotic SPWM signal.

10. The chaotic SPWM signal generation method according to claim 9, characterized in that, The step of multiplying the chaotic time segment by the counting frequency to obtain the counting vector includes: the counting vector includes a chaotic time counting vector PW and a chaotic carrier period counting vector PWTi, wherein the chaotic time segment counting vector is PW = SMCLK·t msp430 The chaotic carrier period counting vector is PWTi = SMCLK·Ti, where SMCLK is the counting frequency and t is the periodicity of the carrier. msp430 The chaotic time segment is Ti, where Ti is the chaotic carrier period; The predetermined count value includes half of the spread spectrum carrier period.

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