A method and system for controlling transmission delay of Ethernet service in OTN

Abstract

The present invention discloses a transmission delay control method and system for Ethernet services in OTN, and relates to the field of communication technology. The method comprises: configuring a stable delay value TC from a source network element to a destination network element; after the source network element performs data transformation on the currently incoming data to form a 66-bit data block, marking the current time as T1 and carrying the T1 time information in the 66-bit data block; filling the 66-bit data block into the payload of the data message and sending it to the destination network element; the destination network element parses the received data message to obtain the T1 time information, and marks the current time as T2; judging whether the configured stable delay value TC is greater than T2-T1, if not, adjusting the stable delay value TC to be greater than T2-T1; and controlling the message data to be output at the time of T1+TC through FIFO. The present invention can ensure that the service transmission delay has consistent stability, reduce the deviation of delay jitter, and meet the actual application requirements.

Description

Technical Field

[0001] The present invention relates to the field of communication technology, and in particular to a transmission delay control method and system for Ethernet services in an OTN (Optical Transport Network). Background Art

[0002] At present, traditional OTN supports CBR (Constant Bit Rate) services, but with the rapid increase of data services, OTN is increasingly carrying Ethernet services. OTN equipment with synchronous Ethernet function extracts the high-precision clock transmitted by the network from the physical layer data stream of Ethernet services, and then tracks and processes it to form a system clock. The sending side then uses the system clock to send data, thereby achieving frequency synchronization between different nodes and providing the system with a frequency-based clock synchronization function that is not affected by service load flow.

[0003] When services such as CPRI (Common Public Radio Interface) / ECPRI (Enhanced Common Public Radio Interface) / FLEXE (Flex Ethernet) / 100GE (100 gigabit Ethernet) enter OTN equipment, the GFP (Generic Framing Procedure) encapsulation method is used, which cannot control the delay changes caused by the mapping process. In addition, when the system is powered on, the phase and frequency deviation of the service reference clock initially generated by the clock chip are also uncertain and will fluctuate within a large range, which is characterized by unstable delay jitter. This phenomenon is more obvious when transmitting low-speed services, and ultimately forms a transmission delay deviation.

[0004] Therefore, based on the above situation, how to control the delay within a stable range has become an urgent problem to be solved by technical personnel in this field. Summary of the invention

[0005] The object of the present invention is to provide a transmission delay control method and system for Ethernet services in OTN, which can ensure that the service transmission delay has consistent stability, reduce the deviation of delay jitter, and meet practical application requirements.

[0006] To achieve the above objectives, in a first aspect, an embodiment of the present invention provides a method for controlling transmission delay of Ethernet services in an OTN, the method comprising:

[0007] Configure the stable delay value TC from the source NE to the sink NE;

[0008] After the source network element transforms the currently incoming data to form a 66-bit data block, it marks the current time as T1 and carries the T1 time information in the 66-bit data block; fills the 66-bit data block into the payload of the data message and sends it to the sink network element;

[0009] The host network element parses the received data message to obtain the T1 time information and marks the current time as T2; determines whether the configured stable delay value TC is greater than T2-T1. If not, adjusts the stable delay value TC to be greater than T2-T1; and outputs the message data at T1+TC through FIFO.

[0010] As a preferred implementation scheme, the carrying of the T1 time information in a 66-bit data block includes: redefining the upper two bits of the 66-bit data block so that bit 64 in the 66-bit data block is used to indicate whether the current data block is data information or control information, and bit 65 is used to transmit the T1 time information and the synchronization code; defining the synchronization code to be represented by a specified 8-bit binary number, and inserting the T1 time information into the 80 66-bit data blocks after the synchronization code.

[0011] As a preferred implementation, the carrying of the T1 time information in a 66-bit data block further includes: scrambling the synchronization code to distinguish the synchronization code from the T1 time information.

[0012] As a preferred implementation scheme, when filling the 66-bit data block into the payload of the data message, the following operations are also included: defining a 66-bit data synchronization identifier in the overhead of the data message, and the 66-bit data synchronization identifier is used to indicate the position of the data header of the 66-bit data block in the next frame of data message.

[0013] As a preferred implementation scheme, the host network element parses the received data message to obtain T1 time information and marks the current time as T2, including: the host network element restores the received data message into a 66-bit data block according to the 66-bit data synchronization identifier; completes synchronization code framing according to the specified 8-bit binary representation of the synchronization code; extracts T1 time information according to the position of the synchronization code framing, and marks the current time as T2.

[0014] As a preferred implementation scheme, the host network element restores the received data message into a 66-bit data block according to the 66-bit data synchronization identifier, including: extracting the 66-bit data synchronization identifier from the overhead of the data message of the current frame, denoted as X; when the data message of the next frame arrives, according to the extracted X, re-splicing the low (66-X) bit data of the first data block of the data message of the next frame and the high Xbit data of the next data block into a new 66-bit data block; according to the above operations, all subsequent data blocks of the data message of the next frame are processed in sequence.

[0015] As a preferred implementation, the method of outputting the message data at time T1+TC through FIFO includes: the FIFO counts through a counter, when the counter counts to CNT, CNT=(T1+TC) / CLK, wherein CLK is a clock for FIFO to read once, then the message data is output.

[0016] As a preferred implementation, the FIFO meets the following requirements: the default water level of the FIFO is set at 1 / 3 during initialization, and the capacity of the FIFO is greater than the value of TC / CLK.

[0017] As a preferred implementation scheme, both T1 and T2 are obtained through 1588V2 technology.

[0018] In a second aspect, an embodiment of the present invention further provides a transmission delay control system for Ethernet services in an OTN, the system comprising a TC setting module, a source end processing module and a sink end processing module;

[0019] The TC setting module is used to: configure a stable delay value TC from a source network element to a sink network element;

[0020] The source end processing module is used to: after the source end network element performs data transformation on the currently incoming data to form a 66-bit data block, mark the current time as T1 and carry the T1 time information in the 66-bit data block; fill the 66-bit data block into the payload of the data message and send it to the sink end network element;

[0021] The host end processing module is used to: parse the received data message to obtain T1 time information, and mark the current time as T2; determine whether the configured stable delay value TC is greater than T2-T1, if not, adjust the stable delay value TC to be greater than T2-T1; and output the message data at T1+TC time through FIFO.

[0022] The beneficial effects of the present invention are:

[0023] (1) In the present invention, by controlling the sending time of the destination service export, a stable source-destination service transmission delay deviation is generated, thereby ensuring that the service transmission delay has consistent stability, solving the problem of uncontrollable transmission delay when the same service is powered on multiple times, and meeting the system's requirements for delay jitter stability. In particular, stable control can be achieved for the transmission delay of low-speed services.

[0024] (2) The changes to the current service link processing method are minor, and it is easy to implement based on the 1588V2 principle. It can be applied to various OTN systems that carry low-speed services, and has good engineering practicality. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 It is a flow chart of a transmission delay control method of Ethernet service in OTN in an embodiment of the present invention;

[0026] Figure 2 A schematic diagram of a service path link implementation in an embodiment of the present invention;

[0027] Figure 3 Schematic diagram of a 66-bit data block before and after redefinition in an embodiment of the present invention;

[0028] Figure 4 Schematic diagram of implementing scrambling / descrambling using NRZI in an embodiment of the present invention;

[0029] Figure 5 It is a schematic diagram of restoring a 66-bit data block according to a 66-bit data synchronization identifier in an embodiment of the present invention. DETAILED DESCRIPTION

[0030] It is understandable that when services such as CPRI / ECPRI / FLEXE / 100GE enter the OTN equipment, different services are mapped to different service time slots. During the mapping and de-mapping process through GMP (Generic Mapping Procedure), the initial water level of the FIFO inside the FPGA (Field Programmable Gate Array) is uncertain, and the starting time of the FIFO service output is also uncertain. At the beginning of the power-on of the entire system, the clock chip is initialized and powered on first. At this time, the phase and frequency deviation of the generated service reference clock are also uncertain, so that the delay of the entire link has uncertainty factors, which has a relatively large impact on the subsequent service processing and system time synchronization.

[0031] It is precisely because of the uncertainty of the system clock phase, the uncertainty of internal data processing of high-speed serdes (serializer / deserializer, a mainstream time division multiplexing TDM, point-to-point P2P serial communication technology), the difference in GMP mapping time slot allocation and other factors that the service delay will vary in a large area every time the system is powered on or multiple services pass through the device. Therefore, it is necessary to study the delay consistency of the device.

[0032] In this regard, in view of the above-mentioned problems existing in the prior art, the present invention aims to provide a transmission delay control method and system for Ethernet services in OTN, which can ensure that the service transmission delay has consistent stability and reduce the deviation of delay jitter, especially to achieve stable control effect on the transmission delay of low-speed services, and meet practical application needs.

[0033] The main design idea is: configure the stable delay value TC from the source network element to the sink network element; after the source network element performs data transformation on the currently incoming data to form a 66-bit data block, mark the current time as T1 and carry the T1 time information in the 66-bit data block; fill the 66-bit data block into the payload of the data message and send it to the sink network element; the sink network element parses the received data message to obtain the T1 time information and marks the current time as T2; determine whether the configured stable delay value TC is greater than T2-T1, if not, adjust the stable delay value TC to be greater than T2-T1; and control the message data to be output at the T1+TC time through FIFO.

[0034] In this solution, by controlling the sending time of the destination service export, a stable source-destination service transmission delay deviation is generated, thereby ensuring that the service transmission delay has consistent stability, solving the problem of uncontrollable transmission delay when the same service is powered on multiple times, and meeting the system's requirements for delay jitter stability.

[0035] In order to make the technical problems, technical solutions and advantages to be solved by the present invention more clear, the technical solutions of the present invention will be described in detail below with reference to the accompanying drawings and specific embodiments.

[0036] However, it should be noted that the examples to be introduced below are only some specific examples, and are not intended to limit the embodiments of the present invention to the following specific steps, values, conditions, data, sequences, etc. Those skilled in the art can apply the concept of the present invention to construct more embodiments not mentioned in this specification by reading this specification.

[0037] Embodiment 1

[0038] See also Figure 1As shown, this embodiment provides a method for controlling transmission delay of Ethernet services in OTN, and the method includes the following steps:

[0039] A. After the system is powered on, configure the stable delay value TC from the source network element to the sink network element. It can be understood that after the system is powered on, the initially configured stable delay value TC is a preset value, and the preset stable delay value TC will be adjusted once at the beginning of power-on (that is, in step C below, if the configured stable delay value TC is not greater than T2-T1, an adjustment will be made), and after the power-on system is stable, the stable delay value TC is stable (that is, after one adjustment, the stable delay value TC will stably meet the condition of being greater than T2-T1), so there is no need to adjust TC, so as to achieve the effect of delay stability control.

[0040] For example, in actual applications, when configuring the preset stable delay value TC, the line side can first implement the 1588 clock synchronization function to calculate the line delay; then, according to the calculated line delay and the delay requirement (for example, the preset stable delay value TC needs to be greater than the line delay), configure the preset stable delay value TC.

[0041] B. After the source network element transforms the currently incoming data to form a 66-bit data block, it marks the current time as T1 and carries the T1 time information in the 66-bit data block; fills the 66-bit data block into the payload of the data message and sends it to the destination network element through GMP mapping.

[0042] For example, see Figure 2 As shown in the figure, in actual applications, the data transmitted by the source network element through the serdes is 10-bit data. According to the transmission requirements of Ethernet services in OTN, the source network element will perform a series of data transformations on the current 10-bit data to form a 66-bit data block. Specifically, Figure 2 As shown, the source network element performs data transformation on the currently incoming data to form a 66-bit data block, which may specifically include the following operations: converting 10-bit data into 8-bit data through 10b / 8b decoding; then converting 8-bit data into 64-bit data through 8b / 64b conversion; and finally, encoding through 64b / 66b to form a 66-bit data block. In this embodiment, when the source network element completes the data transformation process to form a 66-bit data block, it will mark the current moment as T1 (in actual operation, the current moment T1 can be obtained through 1588V2 technology), and the T1 moment will be passed to the destination network element as a timestamp mark, so that the subsequent destination network element can determine the value of the transmission time TF that needs to be adjusted and controlled by FIFO based on the T1 moment and the stable delay value TC. The specific method of determining the TF value is described in step C below, which will not be repeated here.

[0043] Further, as an optional implementation, in step B, carrying the T1 time information in a 66-bit data block specifically includes the following operations:

[0044] (1) The upper two bits of the 66-bit data block (i.e., the data of bit64 and bit65) are redefined so that bit64 in the 66-bit data block is used to indicate whether the current data block is data information or control information, and bit65 is used to transmit T1 time information and synchronization code. It can be understood that in the prior art, in the 66-bit data block formed by 64b / 66b encoding, the originally defined upper two bits of data bit65 and bit64 are used to indicate whether the current data block is data information or control information by using 2'b01 or 2'b10. In this embodiment, the upper two bits of the 66-bit data block (i.e., the data of bit64 and bit65) are redefined, wherein bit64 is used to indicate whether the current data block is data information or control information, for example, it can be represented by 1'b0 or 1'b1; bit65 is used to transmit T1 time information and synchronization code. For example, see Figure 3 As shown in the figure, before definition refers to the actual data of the 66-bit data block formed after the original 64-bit data is encoded by 64b / 66b; after definition refers to the 66-bit data after redefining bit64 and bit65. Among them, the synchronization code occupies 8 bits, that is, it is extracted from 8 66-bit data blocks, and the T1 time information occupies 80 bits, that is, it is extracted from 80 66-bit data blocks. They all occupy the position of bit65 in the 66-bit data block.

[0045] (2) The synchronization code is defined as a binary representation of a specified 8 bits (such as 8'b100000001), and the T1 time information is inserted into the 80 66-bit data blocks after the synchronization code. For example, assuming that in this embodiment, the synchronization code is defined as 8'b100000001, then the T1 time information will be inserted into the bit 65 position of the subsequent 80 66-bit data blocks, and the T1 time information can be obtained through the 1588V2 technology. In other words, the 8-bit information of the synchronization code and the 80-bit information of the T1 time will be stored in the bit 65 position of the 88 66-bit data blocks in sequence. In addition, it can be understood that in this embodiment, the synchronization code will be repeated every N data cycles, N has nothing to do with the service type at this time, but N needs to be greater than the cycle length of 88 66-bit data blocks, and N also needs to be greater than the maximum clock cycle length of the maximum measured link. Furthermore, it can be understood that, in actual application, except for the useful data of 88 66-bit data blocks, the bit 65 of other 66-bit data blocks can preferably be filled with the value 1. Filling with the value 1 can make the subsequent scrambling / descrambling more intuitive and easy to implement.

[0046] On the basis of the above, as a preferred implementation, after the above step (2), the following operation is further included: scrambling the synchronization code to distinguish the synchronization code from the T1 time information. It can be understood that in order to effectively distinguish the synchronization code from the T1 time information and avoid affecting the search of the synchronization header due to the same value of the synchronization code and the T1 time information, it is necessary to scramble the synchronization code. Figure 4 As shown, in this embodiment, the NRZI (Non-Return-to-Zero Inverse) method is used to implement the scrambling operation of the synchronization code. In practical applications, other methods can also be used as a substitute, as long as the synchronization code and T1 time information can be distinguished, and this embodiment does not make specific limitations.

[0047] Furthermore, as an optional implementation, in step B, when filling the 66-bit data block into the payload of the data message, the following operations are also included:

[0048] A 66-bit data synchronization identifier is defined in the overhead of the data message, and the 66-bit data synchronization identifier is used to indicate the location of the data header of the 66-bit data block in the next frame message (i.e., used to indicate how the 66-bit data block in the next frame message should be extracted). It can be understood that when the FPGA fills the 66-bit data block into the payload of the message, when filling a frame message, the FPGA can know whether the last 66-bit data block can be completely filled into the message based on the frame traffic. For example, if Figure 5As shown, for example, the information of the last 66-bit data block is not completely filled into the message, only 62 bits of information are filled, and 4 bits of information are reserved. Then, these 4 bits of information will be filled in the next frame message. At this time, the FPGA needs to mark the reserved 4 bits of information in the current frame (i.e., the 66-bit data synchronization mark) and fill it into the current overhead. For example, it can be recorded as 4. This 66-bit data synchronization mark (4) can be used to indicate how the 66-bit data block in the next frame message should be extracted.

[0049] C. The sink network element parses the received data message to obtain the T1 time information and marks the current time as T2; determines whether the configured stable delay value TC is greater than T2-T1. If not, the stable delay value TC is adjusted to be greater than T2-T1, otherwise it is not adjusted; and the message data is output at the time T1+TC through the FIFO. Figure 2 As shown in the figure, when the sink network element parses the T1 time information from the received data message, it will mark the current time as T2, and TD in the figure represents the value of T2-T1; if it is determined that the configured stable delay value TC is not greater than TD (that is, T2-T1), the stable delay value TC needs to be adjusted to be greater than TD (that is, T2-T1), otherwise no adjustment is required; the adjusted TC is as follows Figure 2 Finally, the sink network element can determine the value of the transmission time TF that needs to be adjusted and controlled by FIFO according to the T1 moment and the current stable delay value TC, that is, TF = T1 + TC, which is as follows Figure 2 As shown, FIFO will output the message data at time TF.

[0050] It is understandable that when the sink network element marks the T2 moment, it will make a judgment on the initially configured stable delay value TC. If the configured stable delay value TC is not greater than T2-T1, it will be adjusted. Since the stable delay value TC will basically meet the condition of being greater than T2-T1 after one adjustment, there is no need to adjust TC afterwards. The message data can be directly controlled to be output at the T1+TC moment through FIFO, thereby ensuring that the service transmission delay has consistent stability and reducing the deviation of delay jitter.

[0051] For example, see Figure 2 As shown in the figure, in actual applications, after the sink network element outputs the message data at the TF time (i.e., the T1+TC time) through the FIFO, according to the transmission requirements of the Ethernet service in the OTN, the sink network element will perform a series of data transformations on the message data output by the FIFO, and finally send the transformed data out of the sink network element through the serdes. Specifically, Figure 2As shown, the host network element performs a series of data transformation processing on the message data output by the FIFO, which may specifically include the following operations: converting the 66-bit data into 64-bit data through 66b / 64b encoding; converting the 64-bit data into 8-bit data through 64b / 8b conversion; and finally converting the 8-bit data into 10-bit data through 8b / 10b encoding.

[0052] Further, as an optional implementation, in step C, the sink network element parses the received data message to obtain the T1 time information and marks the current time as T2, which specifically includes the following operations:

[0053] (1) The host network element restores the received data message into a 66-bit data block based on the 66-bit data synchronization identifier. In actual operation, the specific process may include: extracting a 66-bit data synchronization identifier from the overhead of the data message of the current frame, denoted as X; when the data message of the next frame arrives, based on the extracted X, re-joining the low (66-X) bit data of the first data block of the data message of the next frame and the high X bit data of the next data block into a new 66-bit data block; and processing all subsequent data blocks of the data message of the next frame in sequence. For example, if Figure 5 As shown, first, the 66-bit data synchronization identifier in frame 1 is taken out, and the identifier value at this time is 4; when frame 2 arrives, according to the previously taken out identifier value 4, the lower 62-bit data of data block 1 and the upper 4-bit data of data block 2 are re-joined into a new 66-bit data block; then, according to the previously taken out identifier value 4, the lower 62-bit data of data block 2 and the upper 4-bit data of data block 3 are re-joined into another new 66-bit data block; and so on, all subsequent data blocks of frame 2 are re-joined into new 66-bit data blocks in turn.

[0054] (2) According to the binary representation of the specified 8 bits of the synchronization code, the synchronization code framing is completed. In actual operation, the specific process may include: cyclically extracting the bit65 data of 8 consecutive 66-bit data blocks, and if the bit65 data of the specified 8 bits of the synchronization code can be assembled into the binary representation of the specified 8 bits of the synchronization code, then confirming that the position is the position of the synchronization code framing. It can be understood that since the synchronization code in this embodiment is repeated every N data cycles, in order to better ensure the accuracy of the synchronization code framing, a position mark can be made each time the specified 8-bit binary representation of the synchronization code is assembled. If the interval difference of multiple consecutive (for example, 3) position marks is N, then this position is confirmed as the position of the synchronization code framing. Otherwise, continue the above operation until the framing is completed. In addition, it can be understood that if the source network element also performs a scrambling operation on the synchronization code, then when the sink network element completes the synchronization code framing, it will perform a descrambling operation on the bit65 data of the 8 consecutive 66-bit data blocks extracted cyclically, and the descrambling method corresponds to the scrambling method.

[0055] (3) According to the position of the synchronization code framing, extract the T1 time information and mark the current time as T2. In actual operation, the specific process may include: according to the confirmed synchronization code framing position, extract the bit65 data of the subsequent 80 66-bit data blocks, and reassemble them into an 80-bit data, which is the T1 time information; at the same time, mark the current time as T2, which can be obtained through the 1588V2 technology.

[0056] Further, as an optional implementation, in step C, the message data is output at time T1+TC through FIFO, which specifically includes the following operations: FIFO counts through a counter, and when the counter counts to CNT, CNT=(T1+TC) / CLK, where CLK is the clock for FIFO to read once, the message data is output. In actual operation, the FIFO needs to meet the following requirements: the default water level of the FIFO is set to 1 / 3 during initialization, and the capacity of the FIFO is greater than the value of TC / CLK.

[0057] From the above content, it can be seen that this embodiment generates a stable source-destination service transmission delay deviation by controlling the sending time of the destination service export, solves the problem of uncontrollable transmission delay when the same service is powered on multiple times, and meets the system's requirements for delay jitter stability.

[0058] Embodiment 2

[0059] Based on the same inventive concept, an embodiment of the present invention further provides a transmission delay control system for Ethernet services in an OTN, the system comprising a TC setting module, a source end processing module and a sink end processing module.

[0060] The TC setting module is used to configure the stable delay value TC from the source network element to the sink network element.

[0061] The source end processing module is used to: after the source end network element performs data transformation on the currently incoming data to form a 66-bit data block, mark the current time as T1 and carry the T1 time information in the 66-bit data block; fill the 66-bit data block into the payload of the data message and send it to the destination end network element.

[0062] The host end processing module is used to: parse the received data message to obtain the T1 time information and mark the current time as T2; determine whether the configured stable delay value TC is greater than T2-T1, if not, adjust the stable delay value TC to be greater than T2-T1; and output the message data at the time T1+TC through the FIFO.

[0063] It can be understood that the system using this embodiment can ensure that the service transmission delay has consistent stability, reduce the deviation of delay jitter, and especially achieve stable control of the transmission delay of low-speed services to meet actual application needs.

[0064] It should be noted that the various variations and specific examples in the aforementioned method embodiments are also applicable to the system of this embodiment. Through the detailed description of the aforementioned method, those skilled in the art can clearly understand the implementation method of the system in this embodiment, so for the sake of brevity of the specification, it will not be described in detail here.

[0065] Note: The above-mentioned specific embodiments are only examples rather than limitations, and those skilled in the art can, based on the concept of the present invention, merge and combine some steps and devices from the various embodiments described separately above to achieve the effects of the present invention. Such merged and combined embodiments are also included in the present invention, and such merges and combinations are not described one by one here.

[0066] The advantages, strengths, effects, etc. mentioned in the embodiments of the present invention are only examples, not limitations, and it cannot be considered that these advantages, strengths, effects, etc. must be possessed by each embodiment of the present invention. In addition, the above specific details disclosed in the embodiments of the present invention are only for the purpose of illustration and facilitating understanding, not limitation, and the above details do not limit the embodiments of the present invention to be implemented by adopting the above specific details.

[0067] The block diagrams of the devices, apparatuses, equipment, and systems involved in the embodiments of the present invention are only illustrative examples, and are not intended to require or imply that they must be connected, arranged, and configured in the manner shown in the block diagrams. As will be appreciated by those skilled in the art, these devices, apparatuses, equipment, and systems may be connected, arranged, and configured in any manner. Words such as "including," "comprising," "having," and the like are open words, meaning "including but not limited to," and may be used interchangeably therewith. The words "or" and "and" used in the embodiments of the present invention refer to the words "and / or," and may be used interchangeably therewith, unless the context clearly indicates otherwise. The words "such as" used in the embodiments of the present invention refer to the phrase "such as but not limited to," and may be used interchangeably therewith.

[0068] The step flow charts and the above method descriptions in the embodiments of the present invention are only illustrative examples, and are not intended to require or imply that the steps of each embodiment must be performed in the order given. As will be appreciated by those skilled in the art, the order of the steps in the above embodiments can be performed in any order. Words such as "thereafter", "then", "next", etc. are not intended to limit the order of the steps; these words are only used to guide the reader through the description of these methods. In addition, any reference to a singular element, such as using the article "a", "an", or "the", is not to be construed as limiting the element to the singular.

[0069] In addition, the steps and devices in each embodiment of the present invention are not limited to be implemented in a certain embodiment. In fact, according to the concept of the present invention, relevant partial steps and partial devices in each embodiment of this document can be combined to conceive new embodiments, and these new embodiments are also included in the scope of the present invention.

[0070] Each operation in the embodiment of the present invention may be performed by any appropriate means capable of performing the corresponding functions, which may include various hardware and / or software components and / or modules, including but not limited to hardware circuits or processors.

[0071] The method of the embodiment of the present invention includes one or more actions for implementing the above-mentioned method. The method and / or action can be interchangeable with each other without departing from the scope of the claims. In other words, unless a specific order of actions is specified, the order and / or use of specific actions can be modified without departing from the scope of the claims.

[0072] The functions in the embodiments of the present invention can be implemented by hardware, software, firmware or any combination thereof. If implemented in software, the functions can be stored as one or more instructions on a tangible computer-readable medium. The storage medium can be any available tangible medium that can be accessed by a computer. By way of example and not limitation, such a computer-readable medium may include RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices or any other tangible medium that can be used to carry or store the desired program code in the form of instructions or data structures and can be accessed by a computer. As used herein, a disk and a disc include a compact disc (CD), a laser disc, an optical disc, a DVD (Digital Versatile Disc), a floppy disc and a blue disc, wherein the disc reproduces data magnetically, and the disc reproduces data optically using a laser.

[0073] Thus, a computer program product may perform the operations presented herein. For example, such a computer program product may be a computer-readable tangible medium having instructions tangibly stored (and / or encoded) thereon, which instructions may be executed by one or more processors to perform the operations described herein. The computer program product may include packaging materials.

[0074] Other examples and implementations are within the scope and spirit of the embodiments of the invention and the appended claims. For example, due to the nature of software, the functions described above can be implemented using software executed by a processor, hardware, firmware, hard wiring, or any combination of these. Features that implement the functions can also be physically located in various locations, including being distributed so that parts of the functions are implemented at different physical locations.

[0075] Various changes, substitutions and modifications of the techniques described herein may be made by those skilled in the art without departing from the teachings defined by the appended claims. In addition, the scope of the claims of the present disclosure is not limited to the specific aspects of the processes, machines, manufactures, components of events, means, methods and actions described above. Currently existing or later to be developed processes, machines, manufactures, components of events, means, methods or actions that perform substantially the same functions or achieve substantially the same results as the corresponding aspects described herein may be utilized. Thus, the appended claims include such processes, machines, manufactures, components of events, means, methods or actions within their scope.

[0076] The above description of the disclosed aspects is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these aspects will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other aspects without departing from the scope of the present invention. Therefore, the present invention is not intended to be limited to the aspects shown herein, but rather to the widest scope consistent with the principles and novel features disclosed herein.

[0077] The above description has been given for the purpose of illustration and description. In addition, this description is not intended to limit the embodiments of the present invention to the forms disclosed herein. Although a number of example aspects and embodiments have been discussed above, those skilled in the art will recognize certain variations, modifications, changes, additions and sub-combinations thereof. And the content not described in detail in this specification belongs to the prior art known to those skilled in the art.

Claims

1. A method for controlling transmission delay of Ethernet services in OTN, characterized in that: The method includes: Configure the stable delay value TC from the source NE to the sink NE; After the source network element transforms the currently incoming data to form a 66-bit data block, it marks the current time as T1 and carries the T1 time information in the 66-bit data block; fills the 66-bit data block into the payload of the data message and sends it to the sink network element; The sink network element parses the received data message to obtain the T1 time information and marks the current time as T2; determines whether the configured stable delay value TC is greater than T2-T1, if not, adjusts the stable delay value TC to be greater than T2-T1; and outputs the message data at T1+TC through FIFO; The step of carrying the T1 time information in a 66-bit data block includes: The upper two bits of the 66-bit data block are redefined so that bit 64 in the 66-bit data block is used to indicate whether the current data block is data information or control information, and bit 65 is used to transmit T1 time information and synchronization code; The synchronization code is defined as a binary representation of specified 8 bits, and the T1 time information is inserted into 80 66-bit data blocks after the synchronization code.

2. The transmission delay control method of Ethernet service in OTN according to claim 1, characterized in that: The step of carrying the T1 time information in a 66-bit data block further includes: The synchronization code is scrambled to distinguish the synchronization code from the T1 time information.

3. The transmission delay control method of Ethernet service in OTN as claimed in claim 1, characterized in that: When the 66-bit data block is filled into the payload of the data message, the following operations are also included: A 66-bit data synchronization identifier is defined in the overhead of the data message, and the 66-bit data synchronization identifier is used to indicate the position of the data header of the 66-bit data block in the next frame of data message.

4. The transmission delay control method of Ethernet service in OTN as claimed in claim 3, characterized in that: The sink network element parses the received data message to obtain T1 time information and marks the current time as T2, including: The sink network element restores the received data message into a 66-bit data block according to the 66-bit data synchronization identifier; According to the binary representation of the specified 8 bits of the synchronization code, the synchronization code framing is completed; According to the position of the synchronization code frame, the T1 time information is extracted and the current time is marked as T2.

5. The transmission delay control method of Ethernet service in OTN as claimed in claim 4, characterized in that: The sink network element restores the received data message into a 66-bit data block according to the 66-bit data synchronization identifier, including: Extract the 66-bit data synchronization flag from the overhead of the data message of the current frame, denoted as X; When the next frame of data message arrives, according to the extracted X, the low (66-X) bit data of the first data block of the next frame of data message and the high X bit data of the next data block are reassembled into a new 66-bit data block; According to the above operation, all subsequent data blocks of the data message of the next frame are processed in sequence.

6. The transmission delay control method of Ethernet service in OTN as claimed in claim 1, characterized in that: Outputting the message data at time T1 + TC through FIFO includes: FIFO counts through the counter. When the counter counts to CNT, CNT=(T1+TC) / CLK, where CLK is the clock for FIFO to read once, the message data is output.

7. The transmission delay control method of Ethernet service in OTN as claimed in claim 1, characterized in that: The FIFO meets the following requirements: During initialization, the default water level of the FIFO is set to 1 / 3, and the capacity of the FIFO is greater than the value of TC / CLK.

8. The transmission delay control method of Ethernet service in OTN as claimed in claim 1, characterized in that: Both T1 and T2 are obtained through 1588V2 technology.

9. A transmission delay control system for Ethernet services in OTN based on the method according to any one of claims 1 to 8, characterized in that: The system includes a TC setting module, a source end processing module and a sink end processing module; The TC setting module is used to: configure a stable delay value TC from a source network element to a sink network element; The source end processing module is used to: after the source end network element performs data transformation on the currently incoming data to form a 66-bit data block, mark the current time as T1 and carry the T1 time information in the 66-bit data block; fill the 66-bit data block into the payload of the data message and send it to the sink end network element; The sink processing module is used to: parse the received data message to obtain T1 time information, and mark the current time as T2; determine whether the configured stable delay value TC is greater than T2-T1, if not, adjust the stable delay value TC to be greater than T2-T1; And the message data is output at time T1+TC through FIFO; The source end processing module carries the T1 time information in a 66-bit data block, including: The upper two bits of the 66-bit data block are redefined so that bit 64 in the 66-bit data block is used to indicate whether the current data block is data information or control information, and bit 65 is used to transmit T1 time information and synchronization code; The synchronization code is defined as a binary representation of specified 8 bits, and the T1 time information is inserted into 80 66-bit data blocks after the synchronization code.

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