Method for manufacturing bonded wafer and bonded wafer

Abstract

A manufacturing method of a bonded wafer, which is a manufacturing method of a bonded wafer obtained by bonding a compound semiconductor wafer, which is formed by epitaxially growing a compound semiconductor on a growth substrate, and a bonded wafer, characterized in that the area of the bonding surface of the bonded wafer is larger than the area of the bonding surface of the compound semiconductor wafer, and the growth substrate is removed after the bonded wafer and the compound semiconductor wafer are bonded. Thus, a manufacturing method of a bonded wafer in which generation of cracks can be suppressed can be provided.

Description

Technical Field

[0001] This invention relates to a method for manufacturing a bonding wafer and to bonding wafers. Background Technology

[0002] Epitaxial wafers (EPWs) for various compound semiconductor devices can be realized using GaAs or InP substrates. The largest diameter GaAs substrate is 6 inches (150 mm), and the largest diameter InP substrate is 4 inches (100 mm).

[0003] After fabricating EPWs, electrodes need to be formed and components need to be assembled. However, manufacturing equipment with diameters of 8 inches (200 mm) and above is currently the mainstream, and it is difficult to obtain new equipment with diameters of 6 inches or less. Therefore, various methods have been proposed to perform component assembly on small-diameter wafers using equipment with large diameters.

[0004] One method involves cutting small-diameter slots into a large-diameter wafer to create a template, and then mounting the compound semiconductor wafer onto the template to perform the processing. This method is simple and inexpensive, but it suffers from the problem of insufficient physical adhesion between the template and the wafer.

[0005] In addition, in the photolithography process, a heating plate is needed to heat the wafer before and after photoresist exposure. However, if the adhesion between the wafer and the template decreases, the thermal resistance between the template and the wafer increases, which can lead to unstable photolithography conditions.

[0006] To solve the above problems, it is necessary to ensure a tight bond between the template wafer and the EPW. Patent Document 1 discloses a method for bonding the template wafer and the EPW using a polyimide temporary fixing material for processing.

[0007] This method is excellent in terms of its tight adhesion to the template, but it needs to be peeled off from the template after device fabrication. In principle, this requires an additional removal process because residue will be generated on the peeled surface. Since polyimide cannot be sufficiently removed by thermal decomposition or organic solvents, oxygen plasma ashing is required, which raises the issue of oxidation of the compound wafer surface during the removal process.

[0008] Furthermore, the compound EPW exhibits a heteroepitaxial structure. In heteroepitaxial growth, growth is performed using a growth temperature that maintains a roughly uniform lattice constant. However, as the temperature drops to room temperature, warping occurs due to differences in thermal expansion coefficients. That is, internal stress is generated in the compound semiconductor epitaxial layer at room temperature. This internal stress varies continuously with temperature.

[0009] The higher the bonding temperature, the greater the difference in internal stress when it drops to room temperature. When the wafer to be bonded, which serves as a template, and the EPW are made of different materials, stress caused by the difference in thermal expansion coefficients will, in principle, be applied to the compound semiconductor wafer.

[0010] When the coefficient of thermal expansion of the bonded components is less than that of the EPW substrate, tensile stress is applied to the EPW substrate as it cools from the bonding temperature to room temperature. The greater this tensile stress, the more easily the substrate cracks.

[0011] When the template substrate is silicon, since its coefficient of thermal expansion is less than that of compound semiconductors, tensile stress will be applied to the heat-bonded compound semiconductor EPW after its temperature is cooled to room temperature.

[0012] When bonding wafers of different diameters at temperatures above 200°C, multiple cracks typically form in the compound semiconductor, damaging the EPW. This problem arises from internal stress caused by the difference in thermal expansion coefficients, and cannot be resolved by conventional bonding methods.

[0013] Existing technical documents

[0014] Patent documents

[0015] Patent Document 1: Japanese Patent No. 6213977 Summary of the Invention

[0016] The technical problem to be solved by the present invention

[0017] The present invention was made in view of the above-mentioned technical problems, and its object is to provide a method for manufacturing a bonding wafer, which can suppress the generation of cracks in the epitaxial layer when bonding a small-diameter or small-size compound semiconductor epitaxial wafer onto a bonded wafer to create a device programmable substrate.

[0018] Technical means to solve technical problems

[0019] To achieve the above objectives, the present invention provides a method for manufacturing a bonding wafer, which is a method for bonding a compound semiconductor wafer, which is epitaxially grown on a growth substrate, to a wafer to be bonded. The method is characterized in that the area of ​​the bonding surface of the wafer to be bonded is larger than the area of ​​the bonding surface of the compound semiconductor wafer. After bonding the compound semiconductor wafer to the wafer to be bonded with the epitaxially grown compound semiconductor side as the bonding surface, the growth substrate is removed.

[0020] According to this method of manufacturing bonded wafers, when bonding small-diameter or small-sized compound semiconductor epitaxial wafers onto a bonded wafer to create a device programmable substrate, by removing the growth substrate after bonding, a bonded wafer capable of suppressing epitaxial layer cracking can be produced.

[0021] In this case, it is preferable that the bonding between the joined wafer and the compound semiconductor wafer is any one of the following methods: direct bonding without any material, metal bonding via metal, and bonding via resin or polymer.

[0022] With this bonding method, bonding can be performed more easily, and the resulting device can be used directly as the final device component after bonding.

[0023] In this case, it is preferable that the metal contains at least one of Au, Ag, Al, In, and Ga. Additionally, it is preferable that the resin or polymer is benzocyclobutene, polyimide, or glass using TEOS.

[0024] Therefore, it is possible to suppress poor bonding during the bonding process.

[0025] At this time, it is preferable to configure and perform bonding in such a way that the center of the compound semiconductor wafer is offset from the center of the wafer to be bonded by less than 5 mm.

[0026] This can further suppress the formation of cracks.

[0027] The total thickness of the compound semiconductor wafer after the growth substrate has been removed is set to less than 15 μm.

[0028] Therefore, it is possible to more effectively suppress the formation of cracks.

[0029] Preferably, the wafer to be bonded is made of silicon, sapphire, or quartz.

[0030] This enables the production of low-cost bonding wafers.

[0031] Furthermore, the present invention also provides a bonding wafer, which is a bonding wafer formed by bonding a bonding wafer on a compound semiconductor wafer with an area larger than the area of ​​the bonding surface of the compound semiconductor wafer, characterized in that the total thickness of the compound semiconductor wafer is 15 μm or less.

[0032] If such a bonding wafer is used, a bonding wafer that can suppress the formation of cracks in the epitaxial layer can be fabricated.

[0033] Invention Effects

[0034] As described above, according to the method for manufacturing a bonding wafer according to the present invention, when a small-diameter or small-sized compound semiconductor epitaxial wafer is bonded to a bonding wafer to fabricate a device programmable substrate, by removing the growth substrate after bonding and designing it to be thin-film, a bonding wafer capable of suppressing epitaxial layer cracking can be manufactured. Furthermore, if the bonding wafer is the one of the present invention, a bonding wafer capable of suppressing epitaxial layer cracking can be formed. Attached Figure Description

[0035] Figure 1 This is a diagram (first embodiment) showing an example of a schematic cross-sectional view of a compound semiconductor wafer (EPW) that can be used in the manufacturing method of the bonding wafer of the present invention.

[0036] Figure 2 A diagram illustrating an example of a compound semiconductor wafer (EPW) and a bonded wafer in the first embodiment.

[0037] Figure 3 A diagram illustrating an example of bonding a compound semiconductor wafer (EPW) in the first embodiment to a bonded wafer.

[0038] Figure 4 A diagram illustrating a circular compound semiconductor wafer (EPW) in the first embodiment and its center point (black dot).

[0039] Figure 5 A diagram illustrating the circular shape of the bonded wafer and its center point (black dot) in the first embodiment.

[0040] Figure 6 A diagram illustrating a rectangular compound semiconductor wafer (EPW) and its center point (black dot) in the first embodiment.

[0041] Figure 7 The figure illustrates an example of bonding a compound semiconductor wafer (EPW) according to the first embodiment to a bonded wafer after the growth substrate has been removed.

[0042] Figure 8 The figure illustrates an example of bonding a composite semiconductor wafer (EPW) of the first embodiment to a bonded wafer and covering it with a silicon wafer after removing the growth substrate.

[0043] Figure 9 This is a diagram (second embodiment) showing an example of a schematic cross-sectional view of a compound semiconductor wafer (EPW) that can be used in the manufacturing method of the bonding wafer of the present invention.

[0044] Figure 10The figure illustrates an example of a compound semiconductor wafer (EPW) surface on which Ti and Au layers are deposited in a second embodiment.

[0045] Figure 11 The figure illustrates an example of a Ti layer and an Au layer deposited on the surface of the bonded wafer in the second embodiment.

[0046] Figure 12 The figure illustrates an example of a compound semiconductor wafer (EPW) with Ti and Au layers deposited on its surface according to the second embodiment, and a bonded wafer with Ti and Au layers deposited on its surface.

[0047] Figure 13 This diagram illustrates an example of bonding a compound semiconductor wafer (EPW) with Ti and Au layers deposited on its surface in the second embodiment to a bonded wafer with Ti and Au layers deposited on its surface.

[0048] Figure 14 A diagram illustrating a circular compound semiconductor wafer (EPW) in the second embodiment and its center point (black dot).

[0049] Figure 15 A diagram illustrating the circularly bonded wafer and its center point (black dot) in the second embodiment.

[0050] Figure 16 A diagram illustrating a rectangular compound semiconductor wafer (EPW) and its center point (black dot) in the second embodiment.

[0051] Figure 17 An example diagram is provided to illustrate the removal of the growth substrate after bonding a compound semiconductor wafer (EPW) with Ti and Au layers deposited on its surface in the second embodiment to a bonding wafer with Ti and Au layers deposited on its surface.

[0052] Figure 18 This is a diagram (third embodiment) showing an example of a schematic cross-sectional view of a compound semiconductor wafer (EPW) that can be used in the manufacturing method of the bonding wafer of the present invention.

[0053] Figure 19 This diagram illustrates an example of a compound semiconductor wafer (EPW) with a BCB film formed on its surface according to the third embodiment, and a wafer being bonded.

[0054] Figure 20 This diagram illustrates an example of bonding a compound semiconductor wafer (EPW) with a BCB film formed on its surface to a bonded wafer, as described in the third embodiment.

[0055] Figure 21A diagram illustrating a circular compound semiconductor wafer (EPW) in the third embodiment and its center point (black dot).

[0056] Figure 22 A diagram illustrating the circular shape of the wafer being joined and its center point (black dot) in the third embodiment.

[0057] Figure 23 A diagram illustrating a rectangular compound semiconductor wafer (EPW) and its center point (black dot) in the third embodiment.

[0058] Figure 24 The figure illustrates an example of bonding a compound semiconductor wafer (EPW) with a BCB film formed on its surface to a bonded wafer after the growth substrate has been removed.

[0059] Figure 25 A graph illustrating the relationship between the deviation of the center of a compound semiconductor wafer from the center of the bonded wafer and the number of cracks.

[0060] Figure 26 A graph showing the relationship between the distance from the center of the compound semiconductor wafer and the height of the wafer (Example 4, Comparative Example). Detailed Implementation

[0061] The inventors of this application have repeatedly and carefully studied the above-mentioned technical problems and discovered that by using the following method for manufacturing a bonding wafer, when bonding a small-diameter or small-sized compound semiconductor wafer to a wafer to be bonded to create a device programmable substrate, it is possible to manufacture a bonding wafer that can suppress the generation of cracks in the epitaxial layer, thereby completing the present invention. The method for manufacturing a bonding wafer is a method for manufacturing a bonding wafer by bonding a compound semiconductor wafer grown epitaxially on a growth substrate to a wafer to be bonded. The method is characterized in that the area of ​​the bonding surface of the wafer to be bonded is larger than the area of ​​the bonding surface of the compound semiconductor wafer, and the compound semiconductor side of the compound semiconductor wafer that has undergone epitaxial growth is used as the bonding surface to bond it to the wafer to be bonded, and then the growth substrate is removed.

[0062] Furthermore, it has been discovered that if the following bonding wafer is used, a bonding wafer capable of suppressing the generation of cracks in the epitaxial layer can be fabricated, thereby completing the present invention. The bonding wafer is a bonding wafer on which a bonding surface larger than the area of ​​the bonding surface of the compound semiconductor wafer is bonded, characterized in that the total thickness of the compound semiconductor wafer is 15 μm or less.

[0063] The following describes in detail the bonding wafer of the present invention and the method for manufacturing the bonding wafer for bonding wafers with reference to the accompanying drawings, but the present invention is not limited thereto.

[0064] (First Implementation Plan)

[0065] like Figure 1 As shown, a compound semiconductor wafer (EPW) 110 is prepared. The compound semiconductor wafer (EPW) 110 uses a GaAs growth substrate (start substrate) 101 with a diameter of 6 inches and a thickness of 550 μm as an example. Using a method such as MOVPE (Metal-Organic Vapor-Phase Epitaxy), a light-emitting diode functional layer 103 made of AlGaInP and an etch-stop (ES) layer 102 made of InGaP, InAlP or AlGaInP located between the growth substrate and the light-emitting diode functional layer are formed.

[0066] The light-emitting diode functional layer 103, composed of AlGaInP, is configured such that, starting from the side of the starting substrate 101, it is 1 μm thick and has a carrier concentration of 1 × 10⁻⁶. 17 / cm 3 left and right p-type Al 1-y In y P layer 1031 (0.4≤y≤0.5), 0.6μm thick (Al) 1-x Ga x ) 1-y In y The P-layer (active layer) has a density of 1032 (0.45≤x≤1, 0.4≤y≤0.5) and a 1μm thick carrier layer with a concentration of 1×10⁻⁶. 17 / cm 3 left and right n-type Al 1-y In y P-layer 1033 (0.4≤y≤0.5). Additionally, the basic structure is shown here, but p-type Al... 1-y In y P-layer 1031, active layer 1032, n-type Al 1-y In y The thickness of layer 1033 is not limited to the values ​​shown.

[0067] In addition, the carrier concentration can be set up to 3 × 10⁻⁶ depending on the required function. 18 / cm 3 Within a range of approximately 100°. Furthermore, the carrier concentration distribution is not limited to a uniform distribution. Also, the carrier concentration illustrated is an average carrier concentration, and conceptually includes areas with lower carrier concentrations (e.g., 0.7 × 10⁻⁶). 15 / cm 3 (Left and right) state.

[0068] Additionally, a window layer can be added as needed. In the functional layer structure of AlGaInP type light-emitting diodes, GaP is a suitable choice for the window layer, and the window layer 1035 made of GaP can also be stacked to a thickness of about 10 μm. Furthermore, a GaP-based window layer 1035 can be placed between the window layer 1035 and the light-emitting diode functional layer 103 to mitigate band discontinuity. 1-y In y The mitigation layer 1034 is composed of P layers (0 < y < 1).

[0069] In addition, an AlGaInP type light-emitting diode functional layer is shown here, but as long as the material system matches the GaAs substrate lattice, any function and structure can be selected. In addition to AlGaInP type semiconductor lasers, InGaP type heterojunction bipolar transistors or field-effect transistors, InGaP / GaAs type solar cells, GaAsP type photodiodes, etc. can also be applied.

[0070] In addition, as long as the material system matches the InP substrate lattice, InGaAs heterojunction bipolar transistors or field-effect transistors, InGaAs light-emitting elements (semiconductor lasers and light-emitting diodes), and InGaAs(P) photodiodes can also be applied.

[0071] Furthermore, the aforementioned applicable functional layers are merely illustrative examples and are not limited to these material systems and applications.

[0072] At this point, it is preferable to set the total thickness of the functional layers, including those with window layers, i.e., the total thickness of the compound semiconductor wafer after the growth substrate has been removed (described later), to 15 μm or less. This prevents increased wafer warpage, suppresses crack formation, and inhibits yield reduction due to wafer breakage during bonding. Particularly preferred is a design that maintains a total thickness of 7 μm or less, which further suppresses crack formation. The lower limit of the total thickness is not particularly limited, but is preferably set to 0.5 μm or more.

[0073] Next, as Figure 2 As shown, a wafer 120 to be bonded is prepared. Preferably, the wafer to be bonded is a wafer with sufficient flatness, such as silicon, sapphire, or quartz. This reduces the cost of the wafer to be bonded. The wafer 120 can be, for example, an 8-inch diameter silicon wafer.

[0074] In this invention, the area of ​​the bonding surface of the wafer being bonded is larger than the area of ​​the bonding surface of the compound semiconductor wafer. Furthermore, while a circular wafer is used as an example in the first embodiment, the wafer shape is not particularly limited and can also be, for example, rectangular, square, etc.

[0075] Next, both the EPW110 and the wafer 120 to be bonded are subjected to a wet surface treatment using an alkaline solvent. For example, after immersion in a 5 wt% NaOH aqueous solution for 10 minutes, a rinsing process is performed, followed by air drying.

[0076] In this case, it is preferable to directly bond the compound semiconductor wafer to the wafer being bonded. This can suppress the decrease in yield caused by poor bonding during the bonding process.

[0077] like Figure 2 and Figure 3 As shown, the EPW110 and the wafer 120 are overlapped and introduced into the bonding machine so that the epitaxial surface 131 of the EPW110 is opposite to the polished surface 121 of the wafer 120 to be bonded, and then bonded at 200°C in a vacuum atmosphere to create a bonding substrate 150.

[0078] In this case, it is preferable to configure and perform bonding in such a way that the center of the compound semiconductor wafer deviates from the center of the wafer to be bonded by less than 5 mm. This helps to suppress the formation of cracks.

[0079] That is, in the first embodiment, it is preferable to join by... Figure 4 The center point 1101 of the EPW110 shown is configured such that its distance from the center point is within a certain range. Figure 5 The deviation of the center point 1201 of the bonded wafer 120 shown is suppressed to less than 5 mm.

[0080] When a wafer is circular, its center is clearly defined, but when it is not, its center is clearly defined. Figure 6 When the wafer 110 is a non-circular shape such as a rectangle, the center point 1101 is replaced by the centroid. (For example, when the wafer is rectangular, the point where the diagonals intersect is defined as the center point 1101.)

[0081] The epitaxially grown compound semiconductor side of the compound semiconductor wafer is used as the bonding surface to bond it to the wafer to be bonded. The bonding pressure is based on the pressure applied to EPW110, at 5 N / cm. 2 Above 400N / cm 2 The following steps involve joining.

[0082] The applied pressure illustrated is not limited to this range. When bonding is performed under conditions where the small-diameter EPW110 can withstand the applied pressure (e.g., increasing the substrate thickness), it goes without saying that it is not limited to the illustrated range, and it may also be applied to ranges beyond that.

[0083] Furthermore, since the surfaces treated with alkali are bonded through contact, bonding can be achieved even at pressures lower than those illustrated. For example, a method could be considered where an interference material is pre-placed between two wafers, and the interference material is then extracted in a vacuum to bring the two wafers into contact. In this case, no pressure is applied. During this stage of the process, since it is not necessary to apply pressure, the disclosed method of bringing the two wafers into contact in a vacuum can also be selected.

[0084] Next, the starting substrate 101 is removed from the bonding substrate 150 by wet etching. Wet etching is performed using a mixture of ammonia and hydrogen peroxide solution (APM). Since the APM solution is selectively etched onto the ES layer 102, it only etches GaAs, terminating the etching at the ES layer 102. Therefore, as... Figure 7 As shown, a wafer 160 with the starting substrate removed can be obtained by removing only the GaAs substrate, which serves as the growth substrate, from the bonding substrate 150.

[0085] Next, as Figure 8 As shown, a 6-inch diameter silicon wafer 170 is covered on the surface where the substrate has been removed. Silicon wafers are chosen as the cover material, but materials that ensure flatness and are inexpensive are preferred, and the choice is not limited to silicon. Furthermore, the silicon wafer 170 is not limited to 6-inch diameter silicon; wafers with a diameter of 8 inches or more, suitable for the diameter of the material 120 being bonded, can also be selected. The result will not differ regardless of the type of wafer chosen.

[0086] The bonding wafer, equipped with a cover wafer, was press-bonded under a vacuum atmosphere and then heat-treated at a temperature below 500°C. The pressing pressure was 5 N / cm. 2 Above 400N / cm 2 The following pressing is performed. The heat treatment time can be set to about 5 minutes. The longer the heat treatment time, the greater the strength will be. However, in this process, it is sufficient to maintain the strength to the point that the epitaxial layer will not peel off during the heat treatment of the next process. It is also possible to perform heat treatment for a time longer than disclosed.

[0087] Next, the silicon wafer 170 is removed, and the wafer 160, with the starting substrate removed, is introduced into a heat treatment furnace. The heat treatment furnace is set to an atmosphere suitable for the material on the substrate removal surface. In the first embodiment, since the InGaP layer is exposed, a P atmosphere (1×10⁻⁶) is used. 5 Heat treatment was performed using an As atmosphere (1×10⁻⁶ atm), but since GaAs and other As compounds were exposed when using an InP substrate, As atmosphere (1×10⁻⁶ atm) was used at this time. 5Heat treatment is performed at a temperature of 600–800°C. Higher temperatures allow for higher strength in a shorter time, therefore higher temperatures are preferred, but a correspondingly high group V pressure is required to suit the manufactured system or design.

[0088] By performing the above processes, the bonding strength is enhanced, thereby enabling the creation of wafers with only crack-free thin-film compound epitaxial functional layers on large-diameter silicon substrates.

[0089] (Second Implementation Plan)

[0090] like Figure 9 As shown, a compound semiconductor wafer (EPW) 210 is prepared. The compound semiconductor wafer (EPW) 210 uses a GaAs growth substrate (start substrate) 201 with a diameter of 6 inches and a thickness of 550 μm as an example. A light-emitting diode functional layer 203 made of AlGaInP and an etch-stop (ES) layer 202 made of InGaP, InAlP or AlGaInP are formed using a method such as MOVPE.

[0091] The light-emitting diode functional layer 203, composed of AlGaInP, is configured such that, starting from the side of the starting substrate 201, it is 1 μm thick and has a carrier concentration of 1 × 10⁻⁶. 17 / cm 3 left and right p-type Al 1-y In y P-layer 2031 (0.4≤y≤0.5), 0.6μm thick (Al) 1-x Ga x ) 1-y In y The P-layer (active layer) has a density of 2032 (0.45≤x≤1, 0.4≤y≤0.5) and a carrier concentration of 1×10⁻⁶ at a thickness of 1 μm. 17 / cm 3 left and right n-type Al 1-y In y P-layer 2033 (0.4≤y≤0.5). Additionally, the basic structure is shown in this example, but p-type Al... 1-y In y P-layer 2031, active layer 2032, n-type Al 1-y In y The thickness of layer 2033 P is not limited to the values ​​shown.

[0092] In addition, the carrier concentration can be set up to 3 × 10⁻⁶ depending on the required function. 18 / cm 3Within a range of approximately 100°. Furthermore, the carrier concentration distribution is not limited to a uniform distribution. Additionally, the carrier concentrations illustrated are average carrier concentrations, and conceptually include carriers with lower concentrations (e.g., 0.7 × 10⁻⁶). 15 / cm 3 (Left and right) state.

[0093] Additionally, a window layer can be added as needed. In the functional layer structure of AlGaInP type light-emitting diodes, GaP is a suitable choice for the window layer, and the window layer 2035 made of GaP can also be stacked to a thickness of about 10 μm. Furthermore, a GaP-based window layer 2035 can be placed between the window layer 2035 and the light-emitting diode functional layer 203 to mitigate band discontinuities. 1-y In y The mitigation layer 2034 is composed of P layers (0 < y < 1).

[0094] In addition, an AlGaInP type light-emitting diode functional layer is shown here, but as long as the material system matches the GaAs substrate lattice, any function and structure can be selected. In addition to AlGaInP type semiconductor lasers, InGaP type heterojunction bipolar transistors or field-effect transistors, InGaP / GaAs type solar cells, GaAsP type photodiodes, etc. can also be applied.

[0095] In addition, as long as the material system matches the InP substrate lattice, InGaAs heterojunction bipolar transistors or field-effect transistors, InGaAs light-emitting elements (semiconductor lasers and light-emitting diodes), and InGaAs(P) photodiodes can also be applied.

[0096] Furthermore, the aforementioned applicable functional layers are merely illustrative examples and are not limited to these material systems and applications.

[0097] At this point, it is preferable to set the total thickness of the functional layers, including those with window layers, i.e., the total thickness of the compound semiconductor wafer after the growth substrate has been removed (described later), to 15 μm or less. This prevents increased wafer warpage, suppresses crack formation, and inhibits yield reduction due to wafer breakage during bonding. Particularly preferred is a design that maintains a total thickness of 7 μm or less, which further suppresses crack formation. The lower limit of the total thickness is not particularly limited, but is preferably set to 0.5 μm or more.

[0098] Next, the wafer to be bonded 220 is prepared. At this time, the wafer to be bonded is preferably a wafer with sufficient flatness, such as silicon, sapphire, or quartz. This helps to reduce the cost of the wafer to be bonded. The wafer to be bonded 220 can be, for example, an 8-inch diameter silicon wafer.

[0099] In this invention, the area of ​​the bonding surface of the wafer being bonded is larger than the area of ​​the bonding surface of the compound semiconductor wafer. Furthermore, in the second embodiment, a circular wafer is used as an example, but the wafer shape is not particularly limited and can also be, for example, rectangular, square, etc.

[0100] In this case, it is preferable to perform a metal-to-metal bonding process between the wafer to be bonded and the compound semiconductor wafer. This allows for easier bonding and enables the wafer to be used directly as a final device component after bonding.

[0101] like Figure 10 and Figure 11 As shown, metal films are deposited on both the EPW210 and the wafer 220 to be bonded. For example, a 0.1 μm Ti layer 211 and a 1 μm Au layer 212 are deposited on the EPW210, and for example, a 0.1 μm Ti layer 221 and a 1 μm Au layer 222 are deposited on the silicon wafer. The above structure and film thickness are shown here, but it is self-evident that any material can be selected as needed for bonding.

[0102] In this case, the metal used for metal bonding preferably includes at least one of Au, Ag, Al, In, and Ga. This helps to suppress the decrease in yield caused by poor bonding during the bonding process.

[0103] To reduce bonding defects during bonding and improve yield, it is desirable that the material of the topmost layer (Au in the illustrated embodiment) contains at least one of Au, Ag, Al, In, and Ga, and that the film thickness is 0.3 μm or more. Furthermore, from the perspective of bonding yield, there is no limitation on increasing the film thickness, but even with increased thickness, the effect on yield is the same; therefore, the upper limit of the film thickness is determined based on economic efficiency. From an economic perspective, 3 μm or less is preferred.

[0104] Next, as Figure 12 and Figure 13 As shown, the EPW 210 and the wafer 220 to be bonded are overlapped and introduced into the bonding machine in such a way that the Au layer 212 of the EPW is opposite to the Au layer 222 of the wafer to be bonded, and then bonded to create the bonding substrate 250.

[0105] In this case, it is preferable to configure and perform bonding in such a way that the deviation between the center of the compound semiconductor wafer and the center of the wafer to be bonded is less than 5 mm. This can further suppress the formation of cracks.

[0106] That is, in the second embodiment, it is preferable to join by... Figure 14 The center point 2101 of the EPW210 shown is configured such that its distance from the center point is within a certain range. Figure 15The deviation of the center point 2201 of the bonded wafer 220 shown is suppressed to a position of less than 5 mm.

[0107] When a wafer is circular, its center is clearly defined, but when it is not, its center is clearly defined. Figure 16 When the wafer 210 is a non-circular shape such as a rectangle, the center point 2101 is defined instead as the centroid. (For example, when the wafer is rectangular, the point where the diagonals intersect is defined as the center point 2101.)

[0108] The epitaxially grown compound semiconductor side of the compound semiconductor wafer is used as the bonding surface to bond it to the wafer to be bonded. The bonding pressure is based on the pressure applied to a small-diameter compound EPW, at 5 N / cm². 2 Above 400N / cm 2 The bonding process is then performed. Additionally, temperatures below 400°C can be applied simultaneously. The applied pressure illustrated is not limited to this range; when bonding is performed under conditions where the small-diameter EPW210 can withstand the applied pressure (e.g., increasing the substrate thickness), it goes without saying that the illustrated range is not limited, and increases to above this range are also applicable. Furthermore, while heating is performed simultaneously with pressure application here, the pressure application and heat treatment can also be performed separately by applying pressure first and then heating.

[0109] Next, from wet etching Figure 13 The starting substrate 201 is removed from the bonding substrate 250 shown. Wet etching is performed using a mixture of ammonia and hydrogen peroxide solution (APM). Since the APM solution has etch selectivity for the ES layer 202, it only etches GaAs, terminating the etching at the ES layer 202. Therefore, as... Figure 17 As shown, a wafer 260 with the starting substrate removed can be obtained by removing only the GaAs substrate, which serves as the growth substrate, from the bonding substrate 250.

[0110] Additionally, an example of applying heat treatment before removing the substrate is shown here, but the same effect can be obtained by applying heat treatment after removing the substrate.

[0111] By performing the above processes, the bonding strength is enhanced, thereby enabling the creation of wafers with only crack-free thin-film compound epitaxial functional layers on large-diameter silicon substrates.

[0112] (Third Implementation Plan)

[0113] like Figure 18As shown, a compound semiconductor epitaxial wafer (EPW) 310 is prepared. The compound semiconductor epitaxial wafer (EPW) 310 uses a GaAs growth substrate (start substrate) 301 with a diameter of 6 inches and a thickness of 550 μm as an example, and has a light-emitting diode functional layer 303 made of AlGaInP type, and an etch stop (ES) layer 302 made of InGaP, InAlP or AlGaInP located between the start substrate and the functional layer.

[0114] The light-emitting diode functional layer 303, composed of AlGaInP, is configured such that, starting from the side of the starting substrate 301, it is 1 μm thick and has a carrier concentration of 1 × 10⁻⁶. 17 / cm 3 left and right p-type Al 1-y In y P-layer 3031 (0.4≤y≤0.5), 0.6μm thick (Al) 1-x Ga x ) 1-y In y The P-layer (active layer) is 3032 (0.45≤x≤1, 0.4≤y≤0.5), and the carrier concentration is 1×10⁻⁶ at a thickness of 1 μm. 17 / cm 3 left and right n-type Al 1-y In y P-layer 3033 (0.4≤y≤0.5). Furthermore, while a basic structure is illustrated here, the thicknesses of the p-type layer 3031, active layer 3032, and n-type layer 3033 are not limited to the illustrated values.

[0115] In addition, the carrier concentration can be set up to 3 × 10⁻⁶ depending on the required function. 18 / cm 3 The range is approximately 1000 to 10000. Furthermore, the carrier concentration distribution is not limited to a uniform distribution. Also, the carrier concentrations illustrated are average carrier concentrations, and conceptually include some areas with lower carrier concentrations (e.g., 0.7 × 10⁻⁶). 15 / cm 3 The state of (degree).

[0116] Additionally, a window layer can be provided as needed. In the functional layer structure of AlGaInP type light-emitting diodes, GaP is a suitable choice for the window layer, and the window layer 3035 made of GaP can also be stacked to a thickness of 10 μm. Furthermore, a GaP-based window layer 3035 can be placed between the window layer 3035 and the light-emitting diode functional layer 303 to mitigate band discontinuities. 1-y In y The mitigation layer 3034 is composed of P layers (0 < y < 1).

[0117] In addition, an AlGaInP type light-emitting diode functional layer is shown here, but as long as the material system matches the GaAs substrate lattice, any function and structure can be selected. In addition to AlGaInP type semiconductor lasers, InGaP type heterojunction bipolar transistors or field-effect transistors, InGaP / GaAs type solar cells, GaAsP type photodiodes, etc. can also be applied.

[0118] In addition, as long as the material system matches the InP substrate lattice, InGaAs heterojunction bipolar transistors or field-effect transistors, InGaAs light-emitting elements (semiconductor lasers and light-emitting diodes), and InGaAs(P) photodiodes can also be applied.

[0119] Furthermore, the aforementioned applicable functional layers are merely illustrative examples and are not limited to these material systems and applications.

[0120] At this point, it is preferable to set the total thickness of the functional layers, including those with window layers, i.e., the total thickness of the compound semiconductor wafer after the growth substrate has been removed (described later), to 15 μm or less. This prevents increased wafer warpage, suppresses crack formation, and inhibits yield reduction due to wafer breakage during bonding. Particularly preferred is a design that maintains a total thickness of 7 μm or less, which further suppresses crack formation. The lower limit of the total thickness is not particularly limited, but is preferably set to 0.5 μm or more.

[0121] Next, as Figure 19 As shown, a wafer 320 to be bonded is prepared. Preferably, the wafer to be bonded is a wafer with sufficient flatness, such as silicon, sapphire, or quartz. This allows for control over the cost of the wafer to be bonded. The wafer 320 can be, for example, an 8-inch diameter silicon wafer.

[0122] In this invention, the area of ​​the bonding surface of the bonded wafer is larger than the area of ​​the bonding surface of the compound semiconductor wafer. Furthermore, in the third embodiment, a circular wafer is used as an example, but the wafer shape is not particularly limited and can also be, for example, rectangular, square, etc.

[0123] In this case, it is preferable to bond the wafer to be bonded to the compound semiconductor wafer via a resin or polymer. This allows for easier bonding and enables direct use as a final device component after bonding.

[0124] Furthermore, it is preferable to use benzocyclobutene, polyimide, or glass using TEOS as the resin or polymer. This further suppresses the decrease in yield caused by poor bonding during assembly.

[0125] Benzocyclobutene is spin-coated onto EPW310. The viscosity and rotation speed are adjusted to form a BCB film 311 with a thickness of, for example, approximately 3 μm. Here, an example is shown of forming the BCB film 311 only on EPW310, but the same effect can also be achieved by forming the BCB film 311 on both EPW310 and the bonded wafer 320, or only on the bonded wafer 320.

[0126] Furthermore, while an example of a 3 μm BCB thickness is shown here, the film thickness can be adjusted to approximately 0.5–20 μm by changing the viscosity. However, since increasing the BCB film thickness increases thermal resistance, it is preferable to set the film thickness to approximately 0.5–20 μm. Additionally, forming a thicker BCB film also increases costs. From these perspectives, it is suitable to set the BCB film thickness to 12 μm or less, but it is permissible to exceed this range.

[0127] Additionally, this example illustrates spin-coating BCB, but polyimide can also be spin-coated in addition to BCB. Alternatively, TEOS can be spin-coated after forming a porous silicon film or other porous film on the EPW310, the bonded wafer 320, or both the EPW310 and the bonded wafer 320, to achieve the same effect.

[0128] Next, as Figure 19 and Figure 20 As shown, the EPW 310 and the wafer 320 to be bonded are overlapped and introduced into the bonding machine in such a way that the BCB layer 311 of the EPW is opposite to the surface 321 of the wafer to be bonded, and then bonded to create a bonding substrate 350.

[0129] In this case, it is preferable to configure and perform bonding in such a way that the center of the compound semiconductor wafer deviates from the center of the wafer to be bonded by less than 5 mm. This helps to suppress the formation of cracks.

[0130] That is, in the third embodiment, it is preferable to join by... Figure 21 The center point 3101 of the EPW310 shown is configured such that its distance from the center point is within a certain range. Figure 22 The deviation of the center point 3201 of the bonded wafer 320 shown is suppressed to less than 5 mm.

[0131] When a wafer is circular, its center is clearly defined, but when it is not, its center is clearly defined. Figure 23 When the wafer 310 is a non-circular shape such as a rectangle, the center point 3101 is defined instead of the centroid. (For example, when it is a rectangle, the point where the diagonals intersect is defined as the center point 3101.)

[0132] The epitaxially grown compound semiconductor side of the compound semiconductor wafer is used as the bonding surface to bond it to the wafer to be bonded. The bonding pressure is based on the pressure applied to a small-diameter compound EPW310, at 5 N / cm². 2 Above 400N / cm 2 The bonding process is then performed. The applied pressure illustrated is not limited to this range. When bonding is performed under conditions where the small-diameter EPW310 can withstand the applied pressure (e.g., by increasing the substrate thickness), it goes without saying that the applied pressure is not limited to the illustrated range, and it is also applicable to apply pressures exceeding this range. Furthermore, pressure application and heating can be performed simultaneously here. The same effect can be obtained by applying pressure separately and then performing heat treatment, such as applying pressure only first and then heating.

[0133] Next, the starting substrate 301 is removed from the bonding substrate 350 by wet etching. Wet etching is performed using a mixture of ammonia and hydrogen peroxide solution (APM). Since the APM solution has etch selectivity for the ES layer 302, it only etches GaAs, terminating the etching at the ES layer 302. Therefore, as... Figure 24 As shown, a wafer 360 with the starting substrate removed can be obtained by removing only the GaAs substrate, which serves as the growth substrate, from the bonding substrate 350.

[0134] Additionally, an example is shown here where no heat treatment was applied after removing the substrate, but the same effect was obtained by applying heat treatment after removing the substrate.

[0135] By performing the above processes, the bonding strength is enhanced, thereby enabling the creation of wafers with only crack-free thin-film compound epitaxial functional layers on large-diameter silicon substrates.

[0136] Example

[0137] The present invention will be described in detail below with examples, but these are not intended to limit the present invention.

[0138] (Example 1)

[0139] An epitaxial wafer (EPW) 110 is prepared, wherein the epitaxial wafer (EPW) 110 uses a 550 μm thick GaAs with a diameter of 6 inches (150 mm) as a growth substrate (start substrate) 101, and has a light-emitting diode functional layer 103 composed of AlGaInP, and an etch-stop (ES) layer 102 composed of InGaP located between the start substrate and the light-emitting diode functional layer.

[0140] The light-emitting diode functional layer 103, composed of AlGaInP, is configured to be 1 μm thick from the starting substrate 101 side, with a carrier concentration of 1 × 10⁻⁶. 17 / cm3 left and right p-type Al 1-y In y P layer 1031 (0.4≤y≤0.5), 0.6μm thick (Al) 1- x Ga x ) 1-y In y P layer (active layer) 1032 (0.45≤x)

[0141] ≤1, 0.4≤y≤0.5), and a carrier concentration of 1×10⁻⁶ in a 1μm thick layer. 17 / cm 3 left and right n-type

[0142] Al 1-y In y P layer 1033 (0.4≤y≤0.5).

[0143] Furthermore, a window layer 1035 made of GaP is stacked to a thickness of 10 μm. Additionally, a GaP-based layer is disposed between the window layer 1035 and the functional layer 103 to mitigate band discontinuities. 1-y In y The mitigation layer 1034 is composed of P layers (0 < y < 1).

[0144] A silicon wafer with a diameter of 8 inches (200 mm) is used as the wafer to be bonded 120.

[0145] Next, both the EPW110 and the wafer 120 to be bonded are subjected to a wet surface treatment using an alkaline solvent. In this embodiment, the EPW110 is immersed in a 5 wt% NaOH aqueous solution for 10 minutes, followed by rinsing and then air drying.

[0146] The EPW110 and the wafer 120 to be bonded are overlapped and introduced into the bonding machine in such a way that the epitaxial surface 131 of the EPW110 is opposite to the polished surface 121 of the wafer 120 to be bonded, and then bonded in a vacuum atmosphere at 200°C to create a bonding substrate 150.

[0147] During bonding, the center point 1101 of the EPW110 is kept within 1-9 mm of the center point 1201 of the wafer to be bonded by varying the distance in 1 mm increments. The bonding pressure is set to 50 N / cm. 2 The above data is shown in Table 1.

[0148] [Table 1]

[0149]

[0150] Next, the starting substrate 101 is removed from the bonding substrate 150 by wet etching. The wet etching is performed using a mixture of ammonia and hydrogen peroxide solution (APM). Since the APM solution has etch selectivity for the ES layer 102, it only etches GaAs, and the etching stops at the ES layer 102. Therefore, a wafer 160 with the starting substrate removed, which is obtained by removing only the GaAs substrate, which serves as the growth substrate, from the bonding substrate 150, is obtained.

[0151] Next, a 6-inch diameter silicon wafer 170 was overlaid on the surface where the substrate had been removed. The bonding wafer with the overlaid wafer was then press-fitted under a vacuum atmosphere and heat-treated at 200°C. A heat treatment of 50 N / cm was applied. 2 The pressure. In this embodiment, the heat treatment time is 5 minutes.

[0152] After removing silicon wafer 170, wafer 160, with the starting substrate removed, is introduced into a heat treatment furnace. In Example 1, since the InGaP layer is exposed, the heat treatment is carried out in a P atmosphere (1×10⁻⁶). 5 Heat treatment was performed at 700℃ for approximately 30 minutes.

[0153] The relationship between the number of cracks (cracks) of the above-prepared bonding wafer and the deviation of the center point 1101 of the bonding wafer EPW110 from the center point 1201 of the bonded wafer 120 is shown in the figure. Figure 25 .

[0154] (Example 2)

[0155] Prepare an epitaxial wafer (EPW) 210, wherein the epitaxial wafer (EPW) 210 uses a 550μm thick GaAs with a diameter of 6 inches as a growth substrate (start substrate) 201, and has a light-emitting diode functional layer 203 made of AlGaInP, and an etch-stop (ES) layer 202 made of InGaP located between the start substrate and the light-emitting diode functional layer.

[0156] The light-emitting diode functional layer 203, composed of AlGaInP, is configured to be 1 μm thick from the starting substrate 201 side, with a carrier concentration of 1 × 10⁻⁶. 17 / cm 3 left and right p-type Al 1-y In y P-layer 2031 (0.4≤y≤0.5), 0.6μm thick (Al) 1- x Ga x ) 1-y In yThe P-layer (active layer) has a density of 2032 (0.45≤x≤1, 0.4≤y≤0.5) and a carrier concentration of 1×10⁻⁶ at a thickness of 1 μm. 17 / cm 3 left and right n-type Al 1-y In y P layer 2033 (0.4≤y≤0.5).

[0157] Furthermore, a window layer 2035 made of GaP is stacked to a thickness of 10 μm. Additionally, a GaP-based layer is disposed between the window layer 2035 and the functional layer 203 to mitigate band discontinuities. 1-y In y The mitigation layer 2034 is composed of P layers (0 < y < 1).

[0158] Use an 8-inch diameter silicon wafer as the wafer to be bonded, 220.

[0159] Next, metal films are deposited on both the EPW210 and the wafer 220 to be bonded. Thus, a 0.1 μm Ti layer 211 and a 1 μm Au layer 212 are formed on the EPW210 as evaporated films, and a 0.1 μm Ti layer 221 and a 1 μm Au layer 222 are formed on the silicon wafer as evaporated films.

[0160] The EPW 210 and the wafer 220 to be bonded are overlapped and introduced into the bonding machine in such a way that the Au layer 212 of the EPW is opposite to the Au layer 222 of the wafer to be bonded, and then bonded to create a bonding substrate 250.

[0161] During bonding, the center point 2101 of the EPW210 is kept within a range of 1–9 mm from the center point 2201 of the wafer to be bonded by varying the distance in 1 mm increments. The bonding pressure is set to 50 N / cm. 2 Additionally, heating to 350°C is performed simultaneously. All the above data are shown in Table 1.

[0162] The starting substrate 201 is removed from the bonding substrate 250 by wet etching. Wet etching is performed using a mixture of ammonia and hydrogen peroxide solution (APM).

[0163] The relationship between the number of cracks (cracks) of the above-prepared bonding wafer and the deviation of the center point 2101 of the bonding wafer EPW210 from the center point 2201 of the bonded wafer 220 is shown together. Figure 25 .

[0164] (Example 3)

[0165] Prepare an epitaxial wafer (EPW) 310, wherein the epitaxial wafer (EPW) 310 uses a 550μm thick GaAs with a diameter of 6 inches as a growth substrate (start substrate) 301, and has a light-emitting diode functional layer 303 made of AlGaInP, and an etch-stop (ES) layer 302 made of InGaP located between the start substrate and the light-emitting diode functional layer.

[0166] The light-emitting diode functional layer 303, composed of AlGaInP, is configured to have a thickness of 1 μm starting from the starting substrate 301, with a carrier concentration of 1 × 10⁻⁶. 17 / cm 3 left and right p-type Al 1-y In y P-layer 3031 (0.4≤y≤0.5), 0.6μm thick (Al) 1- x Ga x ) 1-y In y The P-layer (active layer) is 3032 (0.45≤x≤1, 0.4≤y≤0.5), and the carrier concentration is 1×10⁻⁶ at a thickness of 1 μm. 17 / cm 3 left and right n-type Al 1-y In y P layer 3033 (0.4≤y≤0.5).

[0167] Furthermore, a window layer 3035 made of GaP is stacked to a thickness of 10 μm. Additionally, a GaP-based layer is disposed between the window layer 3035 and the functional layer 303 to mitigate band discontinuities. 1-y In y The mitigation layer 3034 is composed of P layers (0 < y < 1).

[0168] Use an 8-inch diameter silicon wafer as the wafer to be bonded, 320.

[0169] Next, benzocyclobutene (BCB) is spin-coated onto EPW310. After adjusting the viscosity and rotation speed to form a BCB film 311 with a thickness of about 3 μm, EPW310 and wafer 320 are overlapped and fed into a bonding machine with the BCB layer 311 of EPW facing the surface 321 of the wafer to be bonded, and then bonded to create bonding substrate 350.

[0170] During bonding, the center point 3101 of the EPW310 is kept within a range of 1–9 mm from the center point 3201 of the wafer to be bonded by varying the distance in 1 mm increments. The bonding pressure is set to 50 N / cm. 2Additionally, heating to 350°C is performed simultaneously. All the above data are shown in Table 1.

[0171] The starting substrate 301 is removed from the bonding substrate 350 by wet etching. The wet etching is performed using a mixture of ammonia and hydrogen peroxide solution (APM).

[0172] The relationship between the number of cracks (cracks) of the above-prepared bonding wafer and the deviation of the center point 3101 of the bonding wafer EPW310 from the center point 3201 of the bonded wafer 320 is also shown below. Figure 25 .

[0173] (Example 4)

[0174] A 2-inch (50 mm) diameter compound wafer is formed on a 4-inch (100 mm) diameter silicon wafer, without forming a window layer made of GaP or a mitigation layer made of GaInP. Otherwise, a bonding wafer is fabricated in the same manner as in Examples 1-3. The relationship between the distance from the end of the thus fabricated bonding wafer to the center of the compound semiconductor wafer and the wafer height is shown. Figure 26 In the middle. Also, regarding Figure 26 The horizontal axis in the figure sets the center of the compound semiconductor wafer to be bonded to 0 mm and the outermost perimeter to -25.4 mm (-1 inch).

[0175] (Comparative Example 1)

[0176] Prepare an epitaxial wafer (EPW) with a 550 μm thick, 6-inch diameter GaAs growth substrate (starting substrate) and a light-emitting diode functional layer made of AlGaInP type, and an etch-stop (ES) layer made of InGaP located between the starting substrate and the functional layer.

[0177] The functional layer of the light-emitting diode, composed of AlGaInP, is set to be 1 μm thick from the starting substrate side, with a carrier concentration of 1 × 10⁻⁶. 17 / cm 3 left and right p-type Al 1-y In y P layer (0.4≤y≤0.5), 0.6μm thick (Al) 1-x Ga x ) 1-y In y The P-layer (active layer) (0.45≤x≤1, 0.4≤y≤0.5), and a 1μm thick layer with a carrier concentration of 1×10⁻⁶. 17 / cm 3 left and right n-type Al 1-y In yP layer (0.4≤y≤0.5).

[0178] Next, a window layer made of GaP is stacked to a thickness of 10 μm. Additionally, a GaP-based layer is placed between the window layer and the functional layer to mitigate band discontinuities. 1-y In y The mitigation layer is composed of P layers (0 < y < 1).

[0179] After forming the EPW, the back side of the starting substrate is ground and then polished to form a polished surface with a thickness of 150 μm.

[0180] Use an 8-inch diameter silicon wafer as the wafer to be bonded.

[0181] Both the EPW and the wafer to be bonded were subjected to a wet surface treatment using an alkaline solvent. After immersion in a 5 wt% NaOH aqueous solution for 10 minutes, the wafers were rinsed and then air-dried.

[0182] The EPW and the wafer to be bonded are overlapped and introduced into the bonding machine in such a way that the polished surface of the starting substrate of the EPW is opposite to the polished surface of the wafer to be bonded, and then bonded in a vacuum atmosphere at 350°C to create a bonding substrate.

[0183] During bonding, the center point of the EPW is kept within 1-4 mm of the center point of the bonding wafer by varying the increments in 1 mm increments. The pressure applied to the EPW during bonding is set to 50 N / cm. 2 And then the connection is implemented.

[0184] The wafer with the starting substrate removed was introduced into a heat treatment furnace, and the atmosphere of the heat treatment furnace was set to be suitable for the material on the side where the substrate had been removed. Since the starting substrate was exposed in Comparative Example 1, an As atmosphere (1×10⁻⁶) was used. 5 The sample is heat-treated at 700℃ for about 30 minutes in an atm.

[0185] The relationship between the number of cracks in the above-mentioned bonded wafer and the deviation of the center point of the epitaxial layer of the bonded wafer from the center point of the bonded wafer is shown in the figure. Figure 25 .

[0186] (Comparative Example 2)

[0187] Except for forming a 2-inch diameter compound wafer on a 4-inch diameter silicon wafer, bonding is performed in the same manner as in Comparative Example 1.

[0188] Figure 25 It can be seen that the greater the deviation of the epitaxial layer from the center of the bonding wafer, the greater the tendency for the number of cracks to enter the epitaxial layer to increase.

[0189] On the other hand, in Examples 1 to 3 of the bonding wafer manufacturing method of the present invention, the deviation of the epitaxial layer from the center position of the bonding wafer is within 1 to 5 mm, which can suppress the increase in the number of cracks entering the epitaxial layer.

[0190] Furthermore, as shown in Comparative Example 2, in order to form a small-diameter wafer composed of compound semiconductors on a large-diameter silicon wafer in a permanent bonding manner, the starting substrate side of the small-diameter wafer needs to be planarized to a bonding-ready level at the atomic level. Additionally, since the growth material in epitaxial growth surrounds the starting substrate side, it needs to be removed. Therefore, polishing is required after grinding.

[0191] However, since compound wafers are brittle materials, the polishing speed at the outer periphery is fast, resulting in a reduction in film thickness at the periphery. Specifically, the film thickness decreases within approximately 1 mm of the outer periphery. While the wafer can be bonded in this state, a height distribution occurs between the outer periphery and the inner side, leading to a decrease in yield due to differences in focal depth during the photolithography process. Since the film thickness difference is on the micrometer scale, even a significant change in height in Comparative Example 2 makes it impossible to maintain a fixed focal depth, resulting in pattern size deviation within approximately 1 mm of the outer periphery and a substantial decrease in yield.

[0192] On the other hand, in Example 4, which uses the wafer bonding manufacturing method of the present invention, almost no significant differences in the height of the various peripheral portions (in other words, differences in film thickness) as seen in the comparative examples occurred in any case. It is evident that the method that essentially eliminates the polishing process after epitaxial growth in the examples is effective. Therefore, the aforementioned problems do not exist in Example 4, and its yield is stable.

[0193] Furthermore, this invention is not limited to the above-described embodiments. The above embodiments are illustrative examples, and any solutions that have substantially the same composition and perform the same effects as the technical concept described in the claims of this invention are included within the scope of this invention.

Claims

1. A method for manufacturing a bonding wafer, comprising a method for bonding a compound semiconductor wafer, formed by epitaxial growth of a compound semiconductor on a growth substrate, to a wafer to be bonded, characterized in that, The area of ​​the bonding surface of the wafer being bonded is larger than the area of ​​the bonding surface of the compound semiconductor wafer. The bonding between the wafer to be bonded and the compound semiconductor wafer can be achieved through any of the following methods: direct bonding without any material, metal-to-metal bonding, and bonding via polymers. The configuration is such that the center of the compound semiconductor wafer is offset from the center of the wafer to be bonded by 1~5mm. After bonding the epitaxially grown compound semiconductor side of the compound semiconductor wafer to the wafer to be bonded, the growth substrate is removed. The total thickness of the compound semiconductor wafer after the growth substrate has been removed is set to be less than 15 μm.

2. The method for manufacturing a bonding wafer according to claim 1, The metal contains one or more of Au, Ag, Al, In, and Ga.

3. The method for manufacturing a bonding wafer according to claim 1, The polymer is a resin.

4. The method for manufacturing a bonding wafer according to claim 3, The resin is benzocyclobutene, polyimide, or glass using TEOS.

5. The method for manufacturing a bonding wafer according to any one of claims 1 to 4, The wafer to be bonded is made of silicon, sapphire, or quartz.

6. A bonding wafer, which is formed by bonding a wafer to be bonded on a compound semiconductor wafer with an area larger than the area of ​​the bonding surface of the compound semiconductor wafer. Its features are, The bonding wafer is prepared by the method of manufacturing a bonding wafer according to any one of claims 1 to 5. The bonding between the wafer to be bonded and the compound semiconductor wafer can be achieved through any of the following methods: direct bonding without any material, metal-to-metal bonding, and bonding via polymers. The center of the compound semiconductor wafer is offset from the center of the wafer being bonded by 1~5mm. The total thickness of the compound semiconductor wafer is less than 15 μm.

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