Methods, apparatus, dielectrics, equipment, and circuit simulation methods for detecting parasitic capacitance

Abstract

This disclosure relates to the field of semiconductors and integrated circuits, providing a method, apparatus, dielectric, device, and circuit simulation method for detecting parasitic capacitance. The method for detecting parasitic capacitance in semiconductor devices includes: constructing a CBCM capacitance measurement circuit based on a preset circuit model; constructing multiple semiconductor devices with identical structures, wherein the device parameters of the multiple semiconductor devices are identical, and the device parameters include at least parasitic capacitance; constructing a composite device based on the semiconductor devices; and using the CBCM capacitance measurement circuit to detect the semiconductor devices and the composite device to determine the parasitic capacitance of the component under test constituting the semiconductor device. This disclosed detection method, by constructing a composite device and subtracting the parasitic capacitance of the composite device from the parasitic capacitance of the semiconductor device, has the advantage of high accuracy in test results. Furthermore, the constructed composite device can be parameter-adjusted, meaning that parasitic capacitance under different parameters can be detected, thus minimizing limitations.

Description

Technical Field

[0001] This disclosure relates to the fields of semiconductors and integrated circuits, and more specifically, to a method, apparatus, dielectric, device, and circuit simulation method for detecting parasitic capacitance. Background Technology

[0002] In integrated circuit design, the layout of metal lines is crucial. Different layouts will bring different parasitic effects (R / L / C), which will have a significant impact on circuit design. Therefore, a simulation model is needed for designers to evaluate the impact during the design process, so as to adjust the circuit to achieve optimal performance.

[0003] In model building, it is necessary to test all parasitic effects (R / L / C) and obtain measurement data to construct an accurate simulation model. Compared to parasitic inductance L and parasitic resistance R, parasitic capacitance C requires special measurement structures to be designed and accurate measurements to obtain accurate measurement data, in order to construct an accurate simulation model, because the influence of many other surrounding factors, including interference during the measurement process, must be taken into account.

[0004] In related technologies, it is impossible to accurately measure the parasitic capacitance of the BJT structure in a thyristor through simulation models.

[0005] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0006] The purpose of this disclosure is to overcome the shortcomings of the prior art and provide a method, apparatus, medium, device and circuit simulation method for detecting parasitic capacitance.

[0007] According to one aspect of this disclosure, a method for detecting parasitic capacitance in a silicon controlled rectifier (SCR) is provided, comprising: constructing a CBCM capacitance measurement circuit; constructing a first SCR device; constructing a composite device, wherein the composite device includes a second SCR device and a semiconductor device, the parameters of the second SCR device being the same as the parameters of the first SCR device, and the structure of the semiconductor device being the same as the structure of any transistor in the first SCR device that generates parasitic capacitance; providing an excitation signal to the first SCR device and the composite device connected thereto using the CBCM capacitance measurement circuit to detect the parasitic capacitance of the composite device; and determining the parasitic capacitance of any transistor in the first SCR device based on the capacitance difference between the parasitic capacitance of the composite device and the parasitic capacitance of the first SCR device.

[0008] In an exemplary embodiment of this disclosure, the first thyristor device includes a first N-type well, a first P-type well, a first P-doped region disposed in the first N-type well, and a first N-doped region disposed in the first P-type well.

[0009] In an exemplary embodiment of this disclosure, the composite device includes a second N-type well and a second P-type well; the second N-type well includes a first sub-N-type well, a second sub-N-type well, a first sub-P-doped region disposed in the first sub-N-type well, and a second N-doped region disposed in the second sub-N-type well, wherein the parameters of the first sub-N-type well and the second sub-N-type well are the same as the parameters of the first N-type well, and the parameters of the first sub-P-doped region and the second sub-P-doped region are the same as the parameters of the first P-doped region; the second P-type well includes a first sub-P-type well, a second sub-P-type well, and a first sub-N-doped region disposed in the first sub-P-type well and / or a second sub-N-doped region disposed in the second sub-P-type well, wherein the first sub-P-type well... The parameters of the first P-type well and the second sub-P-type well are the same as those of the first P-type well. The parameters of the first sub-N-type doped region and the second sub-N-type doped region are the same as those of the first N-type doped region. The first sub-N-type well, the first sub-P-type well, the first sub-P-type doped region, and the first sub-N-type doped region constitute the second thyristor device, and the second sub-N-type well, the second sub-P-type well, and the second sub-P-type doped region constitute the semiconductor device. Alternatively, the first sub-N-type well, the first sub-P-type well, the first sub-P-type doped region, and the first sub-N-type doped region constitute the second thyristor device, and the second sub-N-type well, the second sub-P-type well, and the second sub-N-type doped region constitute the semiconductor device.

[0010] In an exemplary embodiment of this disclosure, the first sub-N-type well and the second sub-N-type well are arranged adjacent to each other, and the first sub-P-type well and the second sub-P-type well are arranged adjacent to each other; the first sub-N-type well and the first P-type well are arranged adjacent to each other, and the second sub-N-type well and the second sub-P-type well are arranged adjacent to each other.

[0011] In an exemplary embodiment of this disclosure, the first sub-N-type well and the second sub-N-type well are disposed adjacent to each other; the first sub-P-type well is adjacent to the first sub-N-type well and located on the side of the first sub-N-type well away from the second sub-N-type well; the second sub-P-type well is adjacent to the second sub-N-type well and located on the side of the second sub-N-type well away from the first sub-N-type well.

[0012] In an exemplary embodiment of this disclosure, the first sub-P-type well and the second sub-P-type well are disposed adjacent to each other; the first sub-N-type well is adjacent to the first sub-P-type well and located on the side of the first sub-P-type well away from the second sub-P-type well; the second sub-N-type well is adjacent to the second sub-P-type well and located on the side of the second sub-P-type well away from the first sub-P-type well.

[0013] In an exemplary embodiment of this disclosure, the CBCM capacitance measurement circuit includes a first P-type transistor, a second P-type transistor, a first N-type transistor, and a second N-type transistor. The control terminals of the first P-type transistor and the second P-type transistor are connected to form a first control signal terminal of the CBCM capacitance measurement circuit, and the control terminals of the first N-type transistor and the second N-type transistor are connected to form a second control signal terminal of the CBCM capacitance measurement circuit. The second connection terminal of the first P-type transistor and the first connection terminal of the first N-type transistor are connected to form a first load terminal of the CBCM capacitance measurement circuit, and the second connection terminal of the second P-type transistor and the first connection terminal of the second N-type transistor are connected to form a second load terminal of the CBCM capacitance measurement circuit. The first connection terminals of the first P-type transistor and the second P-type transistor are respectively connected to a first power supply terminal, and the second connection terminals of the first N-type transistor and the second N-type transistor are both connected to a ground terminal. The parameters of the first P-type transistor and the second P-type transistor are the same, and the parameters of the first N-type transistor and the second N-type transistor are the same.

[0014] In an exemplary embodiment of this disclosure, the step of providing excitation signals to the first thyristor device and the composite device connected thereto using the CBCM capacitance measurement circuit to detect the parasitic capacitance of the composite device includes: connecting the first thyristor device and the composite device to two load terminals of the CBCM capacitance measurement circuit respectively; providing a first control signal to the first control signal terminal and a second control signal to the second control signal terminal to control the CBCM capacitance measurement circuit to provide a first charging current to the semiconductor device and a second charging current to the composite device, wherein the conduction level of the first control signal and the conduction level of the second control signal do not overlap, and the signal frequency of the first control signal is the same as the signal frequency of the second control signal; and detecting the parasitic capacitance of the composite device using the first charging current and the second charging current.

[0015] In an exemplary embodiment of this disclosure, the first N-doped region in the first thyristor device serves as the first connection terminal of the first thyristor device, and the first P-doped region in the first thyristor device serves as the second connection terminal of the first thyristor device; the first sub-N-doped region serves as the first connection terminal of the composite device, and the first sub-P-doped region and the second sub-P-doped region are connected to serve as the second connection terminal of the composite device; or, the first sub-N-doped region and the second sub-N-doped region are connected to serve as the first connection terminal of the composite device, and the first sub-P-doped region serves as the second connection terminal of the composite device.

[0016] In an exemplary embodiment of this disclosure, connecting the first thyristor device and the composite device to the two load terminals of the CBCM capacitance measurement circuit respectively includes: connecting the first connection terminal and the second connection terminal of the first thyristor device to the first load terminal and the ground terminal of the CBCM capacitance measurement circuit respectively; and connecting the first connection terminal and the second connection terminal of the composite device to the second load terminal and the ground terminal of the CBCM capacitance measurement circuit respectively.

[0017] According to a second aspect of this disclosure, an apparatus for detecting parasitic capacitance in a silicon controlled rectifier (SCR) is also provided, comprising: a circuit construction module for constructing a CBCM capacitance measurement circuit; a first device construction module for constructing a first SCR device; a second device construction module for constructing a composite device, wherein the composite device includes a second SCR device and a semiconductor device, the parameters of the second SCR device are the same as the parameters of the first SCR device, and the structure of the semiconductor device is the same as the structure of any transistor in the first SCR device that generates parasitic capacitance; a detection module for providing an excitation signal to the first SCR device and the composite device connected thereto using the CBCM capacitance measurement circuit to detect the parasitic capacitance of the composite device; and a calculation module for determining the parasitic capacitance of any transistor in the first SCR device based on the capacitance difference between the parasitic capacitance of the composite device and the parasitic capacitance of the first SCR device.

[0018] According to a third aspect of this disclosure, a computer-readable storage medium is also provided, having a computer program stored thereon, which, when executed by a processor, implements the method for detecting parasitic capacitance in a thyristor as described in any embodiment of this disclosure.

[0019] According to a fourth aspect of this disclosure, a test apparatus is also provided, comprising: one or more processors; and a storage device for storing one or more programs, which, when executed by the one or more processors, cause the one or more processors to implement the method for detecting parasitic capacitance in a thyristor as described in any embodiment of this disclosure.

[0020] According to a fifth aspect of this disclosure, a simulation method for an electrostatic discharge (ESD) protection circuit is also provided. The ESD protection circuit includes a thyristor. The method includes: constructing an NPN transistor model and a PNP transistor model containing parasitic capacitance values, wherein the parasitic capacitance values ​​of the NPN transistor and the PNP transistor are determined by the method described in any embodiment of this disclosure; constructing a thyristor model using the NPN transistor model and the PNP transistor model; obtaining a netlist of the ESD protection circuit; replacing the information corresponding to the thyristor in the netlist with the information of the thyristor model to generate an updated netlist; and performing simulation processing based on the updated netlist.

[0021] This disclosure discloses a method for detecting parasitic capacitance in a thyristor. First, a CBCM capacitance measurement circuit is constructed. Then, a first thyristor device is constructed. Using the parameters of the first thyristor device, a composite device is constructed. This composite device includes a second thyristor device and a semiconductor device. The parameters of the second thyristor device are the same as those of the first thyristor device, and the structure of the semiconductor device is the same as the structure of any transistor constituting the first thyristor device. This ensures that the composite device and the first thyristor device share a common structure. The constructed test circuit is then used to detect the parasitic capacitance of the first thyristor device and the composite device to obtain the parasitic capacitance of the composite device. The difference between the parasitic capacitance of the composite device and the parasitic capacitance of the first thyristor device is calculated to obtain the parasitic capacitance of any transistor within the first thyristor device. This method has the advantage of high accuracy. Furthermore, the constructed composite device allows for parameter adjustment, enabling the detection of parasitic capacitance under different parameters, thus minimizing limitations.

[0022] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0023] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0024] Figure 1 This is a flowchart of a method for detecting parasitic capacitance of a semiconductor device according to one embodiment of the present disclosure;

[0025] Figure 2 This is a schematic diagram of the structure of a CBCM capacitance measurement circuit according to one embodiment of the present disclosure;

[0026] Figure 3 This is a schematic diagram of the structure of a thyristor according to one embodiment of the present disclosure;

[0027] Figure 4 This is a schematic diagram of the structure of a composite device according to one embodiment of the present disclosure;

[0028] Figure 5 This is a schematic diagram of the structure of a composite device according to another embodiment of the present disclosure;

[0029] Figure 6a This is a schematic diagram of the structure of a composite device according to another embodiment of the present disclosure;

[0030] Figure 6b This is a schematic diagram of the structure of a composite device according to another embodiment of the present disclosure;

[0031] Figure 7 This is a schematic diagram of the structure of a composite device according to another embodiment of the present disclosure;

[0032] Figure 8 This is a schematic diagram of the structure of a composite device according to another embodiment of the present disclosure;

[0033] Figure 9 This is a structural block diagram of an apparatus for detecting parasitic capacitance in a silicon controlled rectifier according to one embodiment of the present disclosure;

[0034] Figure 10 This is a schematic diagram of the structure of a test device according to one embodiment of the present disclosure. Detailed Implementation

[0035] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, they are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and therefore detailed descriptions of them will be omitted. Furthermore, the drawings are merely illustrative of this disclosure and are not necessarily drawn to scale.

[0036] Although relative terms such as "up" and "down" are used in this specification to describe the relative relationship of one component of an icon to another, these terms are used only for convenience, such as according to the orientation of the examples shown in the accompanying drawings. It is understood that if the device of the icon is flipped upside down, the component described as "up" will become the component described as "down." When a structure is "up" of another structure, it may mean that the structure is integrally formed on the other structure, or that the structure is "directly" mounted on the other structure, or that the structure is "indirectly" mounted on the other structure through another structure.

[0037] The terms “a,” “one,” “the,” “the,” and “at least one” are used to indicate the presence of one or more elements / components / etc.; the terms “including” and “having” are used to indicate an open-ended inclusion and to mean that there may be other elements / components / etc. in addition to the listed elements / components / etc.; the terms “first,” “second,” and “third,” etc., are used only as markers and are not a limitation on the number of objects.

[0038] Figure 1 This is a flowchart illustrating a method for detecting parasitic capacitance in a semiconductor device according to one embodiment of this disclosure. The semiconductor device described in this disclosure includes, but is not limited to, a silicon controlled rectifier (SCR). The method disclosed herein can detect the parasitic capacitance of the internal transistor of a SCR. This detection method can be performed by a testing device, such as a computer or server running specific software. Figure 1 As shown, the detection method may include the following steps:

[0039] S110. Construct a CBCM (Charge Based Capacitance Measurement Method) capacitance measurement circuit;

[0040] S120, Construct the first thyristor device;

[0041] S130. Construct a composite device, wherein the composite device includes a second thyristor device and a semiconductor device, the parameters of the second thyristor device are the same as the parameters of the first thyristor device, and the structure of the semiconductor device is the same as the structure of any transistor in the first thyristor device that generates parasitic capacitance.

[0042] S140. The CBCM capacitance measurement circuit provides an excitation signal to the first thyristor device and the composite device connected thereto, so as to detect the parasitic capacitance of the composite device.

[0043] S150. The parasitic capacitance of any transistor in the first thyristor device is determined based on the capacitance difference between the parasitic capacitance of the composite device and the parasitic capacitance of the first thyristor device.

[0044] This disclosure discloses a method for detecting parasitic capacitance in a thyristor. First, a CBCM capacitance measurement circuit is constructed. Then, a first thyristor device is constructed. Using the parameters of the first thyristor device, a composite device is constructed. This composite device includes a second thyristor device and a semiconductor device. The parameters of the second thyristor device are the same as those of the first thyristor device, and the structure of the semiconductor device is the same as the structure of any transistor constituting the first thyristor device. This ensures that the composite device and the first thyristor device share a common structure. The constructed test circuit is then used to detect the parasitic capacitance of the first thyristor device and the composite device to obtain the parasitic capacitance of the composite device. The difference between the parasitic capacitance of the composite device and the parasitic capacitance of the first thyristor device is calculated to obtain the parasitic capacitance of any transistor within the first thyristor device. This method has the advantage of high accuracy. Furthermore, the constructed composite device allows for parameter adjustment, enabling the detection of parasitic capacitance under different parameters, thus minimizing limitations.

[0045] The steps described above in this example implementation will now be explained in more detail.

[0046] In step S110, a CBCM capacitance measurement circuit is constructed based on a preset circuit model.

[0047] For example, Figure 2 This is a schematic diagram of a CBCM capacitance measurement circuit according to one embodiment of the present disclosure. In the figure, Cp represents the parasitic capacitance of the first thyristor device, C represents the parasitic capacitance of the composite device, 10 represents the constructed first thyristor device, and 20 represents the constructed composite device. Figure 2As shown, the CBCM capacitance measurement circuit can include two P-type transistors and two N-type transistors, both of which can be MOSFETs. The parameters of the two P-type transistors are identical, and the parameters of the two N-type transistors are identical. The circuit comprises two P-type transistors, including a first P-type transistor Tp1 and a second P-type transistor Tp2, and two N-type transistors, including a first N-type transistor Tn1 and a second N-type transistor Tn2. The control terminals of the first P-type transistor Tp1 and the second P-type transistor Tp2 are connected to form the first control signal terminal of the CBCM capacitance measurement circuit. The control terminals of the first N-type transistor Tn1 and the second N-type transistor Tn2 are connected to form the second control signal terminal of the CBCM capacitance measurement circuit. The second connection terminal of the first P-type transistor Tp1 is connected to the first connection terminal of the first N-type transistor Tn1 to form the first load terminal of the CBCM capacitance measurement circuit. The second connection terminal of the second P-type transistor Tp2 is connected to the first connection terminal of the second N-type transistor Tn2 to form the second load terminal of the CBCM capacitance measurement circuit. The first connection terminals of the first P-type transistor Tp1 and the second P-type transistor Tp2 are respectively connected to the first power supply terminal, and the second connection terminals of the first N-type transistor Tn1 and the second N-type transistor Tn2 are both connected to the ground terminal.

[0048] During the detection process, a first control signal can be provided to the first control terminal A1 and a second control signal can be provided to the second control terminal A2 to control the CBCM capacitance measurement circuit to provide charging current to the devices connected to the two load terminals using the supply voltage of the first power supply terminal, and then use the charging current to calculate the parasitic capacitance of the composite device. For a detailed method for calculating the parasitic capacitance of the thyristor, please refer to the description in the subsequent embodiments.

[0049] In step S120, the first thyristor device is constructed.

[0050] The purpose of this step is to construct a first thyristor device based on predetermined parameters. The parameters of the constructed first thyristor device should be exactly the same as the parameters of the second thyristor device in the composite device constructed in subsequent steps.

[0051] For example, Figure 3 This is a schematic diagram of the structure of a thyristor according to one embodiment of the present disclosure, as shown below. Figure 3As shown, the first thyristor device may include a first P-type well PW1, a first N-type well NW1, a first N-doped region N1 disposed in the first P-type well PW1, and a first P-doped region P1 disposed in the first N-type well NW1. The first N-doped region N1, the first P-type well PW1, and the first N-type well NW1 form an NPN transistor, and the first P-doped region P1, the first N-type well NW1, and the first P-type well PW1 form a PNP transistor. The parameters of the NPN transistor and the PNP transistor can be adjusted by adjusting the parameters of the first P-type well PW1 and / or the first N-type well NW1 and / or the first N-doped region N1 and / or the first P-doped region P1. These parameters may include, for example, material, size, doping concentration, etc. Obviously, this disclosure can construct a corresponding first thyristor device according to the design parameters, and the parasitic capacitance of the first thyristor device can be measured. In other words, the method disclosed herein can detect the parasitic capacitance of a first silicon controlled rectifier device made of different materials and / or with different structures.

[0052] In addition, such as Figure 3 As shown, the first N-doped region N1 in the first thyristor can be used as the first connection terminal VDD of the first thyristor, and the first P-doped region P1 in the first thyristor can be used as the second connection terminal IO of the first thyristor. When connecting to the constructed CBCM capacitance measurement circuit, the first connection terminal VDD of the first thyristor can be connected to the corresponding load terminal, and the second connection terminal IO of the first thyristor can be connected to the ground terminal.

[0053] In step S130, a composite device is constructed, wherein the composite device includes a second thyristor device and a semiconductor device. The parameters of the second thyristor device are the same as those of the first thyristor device, and the structure of the semiconductor device is the same as the structure of any transistor in the first thyristor device that generates parasitic capacitance.

[0054] The composite device includes a second thyristor device and a semiconductor device, and the parameters of the second thyristor device are the same as those of the first thyristor device. Therefore, the composite device is equivalent to having the same structure as the first thyristor device. The same structure will produce the same parasitic effect. Therefore, the capacitance difference between the parasitic capacitance of the composite device and the parasitic capacitance of the first thyristor device is the parasitic capacitance of the semiconductor device with the different structure.

[0055] The parameters of the second thyristor are the same as those of the first thyristor. Specifically, the P-type well parameters, N-type well parameters, P-doped region parameters, and N-doped region parameters of the second thyristor correspond to the same parameters of the P-type well, N-type well, P-doped region, and N-doped region in the first thyristor, respectively. This makes the parasitic effect of the second thyristor the same as that of the first thyristor.

[0056] In this step, the structure of the semiconductor device is the same as the structure of any transistor in the first thyristor device that generates parasitic capacitance. Specifically, the structure of the semiconductor device can be the same as the structure of forming an NPN transistor and generating parasitic capacitance or the structure of forming a PNP transistor and generating parasitic capacitance, and the parameters of the two devices are also the same.

[0057] The structure of the composite device will be further described below with reference to the accompanying drawings.

[0058] For example, Figure 4 This is a schematic diagram of the structure of a composite device according to one embodiment of the present disclosure, as shown below. Figure 4 As shown, in an exemplary embodiment, the composite device may include a second N-type well NW2 and a second P-type well PW2; the second N-type well NW2 may include a first sub-N-type well NW21, a second sub-N-type well NW22, a first sub-P-doped region P21 disposed in the first sub-N-type well NW21, and a second sub-N-doped region N22 disposed in the second sub-N-type well NW22, wherein the parameters of the first sub-N-type well NW21 and the parameters of the second sub-N-type well NW22 are the same as the parameters of the first N-type well NW1, and the parameters of the first sub-P-doped region P21 and the parameters of the second sub-P-doped region P22 are the same. All parameters are the same as those of the first P-doped region P1; the second P-type well PW2 may include a first sub-P-type well PW21, a second sub-P-type well PW22, and a first sub-N-doped region N21 disposed in the first sub-P-type well PW21 and / or a second sub-N-doped region N22 disposed in the second sub-P-type well PW22, and the parameters of the first sub-P-type well PW21 and the second sub-P-type well PW22 are the same as those of the first P-type well PW1, and the parameters of the first sub-N-doped region N21 and the second sub-N-doped region N22 are the same as those of the first N-doped region N1.

[0059] Among them, the first sub-N-type well NW21, the first sub-P-type well PW21, the first sub-P-doped region P21, and the first sub-N-doped region N21 constitute the second thyristor device, and the second sub-N-type well NW22, the second sub-P-type well PW22, and the second sub-P-doped region P22 constitute the semiconductor device. At this time, the structure of the semiconductor device is the same as the structure of the PNP type transistor formed in the first thyristor device.

[0060] It can be seen that, Figure 4In the structure shown, the first sub-N-type well NW21 and the second sub-N-type well NW22 are arranged adjacent to each other, and the first sub-P-type well PW21 and the second sub-P-type well PW22 are arranged adjacent to each other. The first sub-N-type well NW21 is arranged adjacent to the first P-type well PW1, and the second sub-N-type well NW22 is arranged adjacent to the second sub-P-type well PW22. It is equivalent to that the first sub-N-type well NW21, the second sub-N-type well NW22, the first sub-P-type well PW21 and the second sub-P-type well PW22 form a "field" shaped structure.

[0061] Exemplarily, Figure 5 is a schematic structural diagram of a composite device according to another embodiment of the present disclosure. In Figure 5 the structure shown, the first sub-N-type well NW21, the first sub-P-type well PW21, the first sub-P-doped region P21 and the first sub-N-doped region N21 constitute a second thyristor device, and the second sub-N-type well NW22, the second sub-P-type well PW22 and the second sub-N-doped region N22 constitute a semiconductor device. At this time, the structure of the semiconductor device is the same as the structure forming an NPN-type triode in the first thyristor device, and the semiconductor device has the same parasitic effect as the structure forming an NPN-type triode in the first thyristor device.

[0062] The composite device can all include the second sub-P-doped region P22 and the second sub-N-doped region N22 at the same time. For example, when the second sub-N-type well NW22, the second sub-P-type well PW22 and the second sub-P-doped region P22 constitute a semiconductor device, the composite device can further include the second sub-N-doped region N22, and the structure of the composite device can be as Figure 6a shown. At this time, although the composite device further includes the second sub-N-doped region N22, since the second sub-N-doped region N22 is not connected to the connection terminal connecting the composite device to the external circuit, no parasitic capacitance is formed, that is, it will not affect the parasitic capacitance of the composite device. Similarly, when the second sub-N-type well NW22, the second sub-P-type well PW22 and the second sub-N-doped region N22 constitute a semiconductor device, the composite device can further include the second sub-P-doped region P22, and the structure of the composite device can be as Figure 6b shown. The second sub-P-doped region P22 does not form a parasitic capacitance because it is not connected to the connection terminal connecting the composite device to the external circuit, and similarly will not affect the parasitic capacitance of the composite device. Therefore, Figure 6b in the composite device shown, the semiconductor device has the same parasitic effect as the structure forming an NPN-type triode in the first thyristor device.

[0063] It should be understood that the various constituent structures in the composite device can have different arrangement manners.

[0064] Exemplarily, Figure 7 is a schematic structural diagram of a composite device according to still another embodiment of the present disclosure. In Figure 7 In the structure shown, the first sub-N-type well NW21 and the second sub-N-type well NW22 are arranged adjacent to each other. The first sub-P-type well PW21 is adjacent to the first sub-N-type well NW21 and located on the side of the first sub-N-type well NW21 away from the second sub-N-type well NW22. The second sub-P-type well PW22 is adjacent to the second sub-N-type well NW22 and located on the side of the second sub-N-type well NW22 away from the first sub-N-type well NW21. The first sub-N-type well NW21, the first sub-P-type well PW21, the first sub-P-doped region P21, and the first sub-N-doped region N21 constitute a second thyristor device, and the second sub-N-type well NW22, the second sub-P-type well PW22, and the second sub-P-doped region P22 constitute a semiconductor device. In this case, the structure of the semiconductor device is equivalent to the structure of a PNP-type transistor in the first thyristor device and has the same parasitic effects. Similarly, the second sub-P-type well PW22 in the composite device can also be provided with a second sub-N-doped region N22. When the second sub-N-doped region N22 is included, it is not connected to the connection terminal of the composite device to the external circuit. Therefore, the second sub-N-doped region N22 will not form parasitic capacitance with other structures in the composite device, i.e., it will not affect the parasitic capacitance of the composite device. Furthermore, in Figure 7 In the structure shown, the semiconductor device can also be composed of a second sub-N-type well NW22, a second sub-P-type well PW22, and a second sub-N-doped region N22. In this case, the structure of the semiconductor device is equivalent to the structure of the NPN transistor formed in the first thyristor device and has the same parasitic effect.

[0065] In an exemplary embodiment, Figure 8 This is a schematic diagram of the structure of a composite device according to another embodiment of the present disclosure. Figure 8 In the structure shown, the first sub-P-type well PW21 and the second sub-P-type well PW22 are arranged adjacent to each other; the first sub-N-type well NW21 is adjacent to the first sub-P-type well PW21 and located on the side of the first sub-P-type well PW21 away from the second sub-P-type well PW22; the second sub-N-type well NW22 is adjacent to the second sub-P-type well PW22 and located on the side of the second sub-P-type well PW22 away from the first sub-P-type well PW21. The first sub-N-type well NW21, the first sub-P-type well PW21, the first sub-P-doped region P21, and the first sub-N-doped region N21 constitute a second thyristor device, and the second sub-N-type well NW22, the second sub-P-type well PW22, and the second sub-P-doped region P22 constitute a semiconductor device, or the second sub-N-type well NW22, the second sub-P-type well PW22, and the second sub-N-doped region N22 constitute a semiconductor device. This structure is similar to... Figure 7The difference in the structure shown is that the relative positions of the first sub-P-type well PW21, the first sub-N-type well NW21, the second sub-P-type well PW22, and the second sub-N-type well NW22 are different. The structure and principle of the second thyristor device and the semiconductor device formed are the same, and will not be described in detail here.

[0066] In addition, Figure 4 , Figure 6a as well as Figure 7 In the composite device shown, the first sub-N-doped region N21 can serve as the first connection terminal VDD of the composite device, and the first sub-P-doped region P21 and the second sub-P-doped region P22, when connected, can serve as the second connection terminal IO of the composite device. Figure 5 , Figure 6b and Figure 8 In the composite device shown, the first sub-N doped region N21 and the second sub-N doped region N22 can be connected to serve as the first connection terminal VDD of the composite device, and the first sub-P doped region P21 can serve as the second connection terminal IO of the composite device.

[0067] In the subsequent steps of connecting the composite device to the CBCM capacitance measurement circuit, the first connection terminal VDD of the composite device is connected to a load terminal of the CBCM capacitance measurement circuit, and the second connection terminal IO of the composite device is connected to the ground terminal to detect the parasitic capacitance of the composite device.

[0068] In related technologies, since the parasitic capacitance of the internal structure of a thyristor cannot be directly and accurately detected, this disclosure constructs a composite device that has parameter and structural correlation with the first thyristor device. Then, through subsequent steps, the parasitic capacitance of the transistor inside the first thyristor device is calculated by subtracting the parasitic capacitance of the composite device from that of the first thyristor device. This eliminates interference from other factors, and the obtained parasitic capacitance of the transistor inside the first thyristor device is more accurate.

[0069] In step S140, the CBCM capacitance measurement circuit provides an excitation signal to the first thyristor device and the composite device connected thereto, so as to detect the parasitic capacitance of the composite device.

[0070] The parasitic capacitance of the composite device can be detected using the CBCM capacitance measurement circuit. Since the parasitic capacitance of the constructed first thyristor device can be directly detected, the parasitic capacitance of the corresponding transistor in the first thyristor device can be calculated based on the parasitic capacitance of the first thyristor device and the parasitic capacitance of the composite device.

[0071] In an exemplary embodiment, step S140 may specifically include the following steps:

[0072] S141. Connect the first thyristor device and the composite device to the two load terminals of the CBCM capacitance measurement circuit respectively.

[0073] S142. Provide a first control signal to a first control signal terminal and a second control signal to a second control signal terminal to control the CBCM capacitance measurement circuit to provide a first charging current to the semiconductor device and to provide a second charging current to the composite device, wherein the conduction level of the first control signal and the conduction level of the second control signal do not overlap, and the signal frequency of the first control signal and the signal frequency of the second control signal are the same.

[0074] S143. The parasitic capacitance of the composite device is detected using the first charging current and the second charging current.

[0075] In step S141, the first connection terminal VDD of the first thyristor device is first connected to... Figure 2 The CBCM capacitance measurement circuit shown has one load terminal connected to the second connection terminal IO of the first thyristor device, which is then connected to the ground terminal. The first connection terminal VDD of the composite device is connected to... Figure 2 The other load terminal of the CBCM capacitance measurement circuit shown connects the second connection terminal IO of the composite device to the ground terminal. This allows the CBCM capacitance measurement circuit to provide charging current to both the first thyristor device and the composite device in subsequent steps.

[0076] Then, in steps S142 and S143, the CBCM capacitance measurement circuit provides charging current to the connected first thyristor device and the composite device respectively in response to the provided control signal, and detects the parasitic capacitance of the composite device.

[0077] The control signals at the first and second control signal terminals have the same frequency, and the conduction levels of the first and second control signals do not overlap. In other words, when the first control signal is on, the second control signal is off; when the second control signal is on, the first control signal is off, meaning the on-levels of the first and second control signals alternate. Specifically, since the first control signal controls two P-type transistors, its on-level is low. The second control signal controls two N-type transistors, so its on-level is high. The second control signal can turn on the two N-type transistors to discharge the first thyristor and the composite device respectively. The first control signal can turn on the two P-type transistors to charge the first thyristor and the composite device respectively. Obviously, because the parasitic capacitance of the first thyristor is different from that of the composite device, the charging current provided by the CBCM capacitance measurement circuit to the first thyristor and the composite device are different.

[0078] This disclosure allows for the measurement of the charging current generated for the first thyristor device, i.e., the first charging current, at the first connection terminal of the first P-type transistor Tp1, i.e., the terminal connected to the first power supply. It also allows for the measurement of the charging current generated for the composite device structure, i.e., the second charging current, at the first connection terminal of the second P-type transistor Tp2, i.e., the terminal connected to the first power supply.

[0079] After obtaining the first charging current for the first thyristor device and the second charging current for the composite device structure module, the parasitic capacitance of the differential structure between the composite device and the first thyristor device can be calculated using the following formula based on the difference between these two currents:

[0080]

[0081] In the formula: ΔI represents the current difference between the first charging current and the second charging current, VDD represents the supply voltage of the first power supply terminal, f represents the signal frequency of the first control signal and the second control signal, and C represents the parasitic capacitance of the composite device.

[0082] In step S150, the parasitic capacitance of any transistor in the first thyristor device is determined based on the capacitance difference between the parasitic capacitance of the composite device and the parasitic capacitance of the first thyristor device.

[0083] In this process, after obtaining the parasitic capacitance of the composite device, the difference capacitance obtained by subtracting the parasitic capacitance of the composite device from the parasitic capacitance of the first thyristor device is the parasitic capacitance generated by the difference structure between the composite device and the first thyristor device.

[0084] It should be understood that this disclosure can construct a first composite device and a second composite device, respectively. The first composite device may include, for example, a second thyristor device and a first semiconductor device. The structure of the first semiconductor device is the same as that of the NPN transistor formed in the first thyristor device and has the same parasitic effect. Therefore, the parasitic capacitance of the PNP transistor in the first thyristor can be determined based on the difference between the parasitic capacitance of the first composite device and the parasitic capacitance of the first thyristor device. Similarly, the second composite device may be, for example, a second thyristor device and a second semiconductor device. The structure of the second semiconductor device is the same as that of the PNP transistor formed in the first thyristor device and has the same parasitic effect. Therefore, the parasitic capacitance of the NPN transistor in the first thyristor device can be determined based on the difference between the parasitic capacitance of the first composite device and the parasitic capacitance of the first thyristor device.

[0085] As can be seen, this disclosure constructs a first thyristor device and then constructs a composite device based on the parameters of the first thyristor device, so that the composite device and the first thyristor device have the same structure and have a semiconductor device structure equivalent to the transistor that forms parasitic capacitance in the first thyristor device. Then, the parasitic capacitance of the composite device can be detected by using the constructed CBCM capacitance measurement circuit. Thus, the difference capacitance between the parasitic capacitance of the composite device and the parasitic capacitance of the first thyristor device is the parasitic capacitance of the corresponding transistor in the first thyristor device, which solves the problem in related technologies that it is impossible to accurately detect the parasitic capacitance of the internal structure of the first thyristor device.

[0086] Furthermore, it is understood that after accurately detecting the parasitic capacitance of the internal structure of the first thyristor device using the method disclosed herein, a thyristor device with corresponding parasitic capacitance parameters can be constructed using simulation software. This allows for the creation of an accurate simulation model in the simulation software, and further adjustments to the circuit design based on the simulation results, enabling the circuit to achieve optimal performance.

[0087] This disclosure also provides a device 600 for detecting parasitic capacitance in a silicon controlled rectifier (SCR). Figure 9 Here is a structural block diagram of an apparatus for detecting parasitic capacitance in a silicon controlled rectifier according to one embodiment of this disclosure, as follows: Figure 9 As shown, the device 600 may include: a circuit construction module 610, a first device construction module 620, a second device construction module 630, a detection module 640, and a calculation module 650, wherein,

[0088] The circuit construction module is used to build CBCM capacitance measurement circuits;

[0089] The first device construction module is used to construct the first thyristor device;

[0090] The second device construction module is used to construct a composite device, wherein the composite device includes a second thyristor device and a semiconductor device. The parameters of the second thyristor device are the same as those of the first thyristor device, and the structure of the semiconductor device is the same as the structure of any transistor in the first thyristor device that generates parasitic capacitance.

[0091] The detection module is used to provide excitation signals to the first thyristor device and the composite device connected thereto using the CBCM capacitance measurement circuit, so as to detect the parasitic capacitance of the composite device.

[0092] The calculation module is used to determine the parasitic capacitance of any transistor in the first thyristor device based on the capacitance difference between the parasitic capacitance of the composite device and the parasitic capacitance of the first thyristor device.

[0093] In an exemplary embodiment, the first thyristor device includes a first N-type well, a first P-type well, a first P-doped region disposed in the first N-type well, and a first N-doped region disposed in the first P-type well.

[0094] In an exemplary embodiment, the composite device includes a second N-type well and a second P-type well; the second N-type well includes a first sub-N-type well, a second sub-N-type well, a first sub-P-doped region disposed in the first sub-N-type well, and a second N-doped region disposed in the second sub-N-type well, wherein the parameters of the first sub-N-type well and the second sub-N-type well are the same as the parameters of the first N-type well, and the parameters of the first sub-P-doped region and the second sub-P-doped region are the same as the parameters of the first P-doped region; the second P-type well includes a first sub-P-type well, a second sub-P-type well, and a first sub-N-doped region disposed in the first sub-P-type well and / or a second sub-N-doped region disposed in the second sub-P-type well. Furthermore, the parameters of the first sub-P-type well and the second sub-P-type well are the same as those of the first P-type well, and the parameters of the first sub-N-doped region and the second sub-N-doped region are the same as those of the first N-doped region; wherein, the first sub-N-type well, the first sub-P-type well, the first sub-P-doped region, and the first sub-N-doped region constitute a second thyristor device, and the second sub-N-type well, the second sub-P-type well, and the second sub-P-doped region constitute a semiconductor device; or, the first sub-N-type well, the first sub-P-type well, the first sub-P-doped region, and the first sub-N-doped region constitute a second thyristor device, and the second sub-N-type well, the second sub-P-type well, and the second sub-N-doped region constitute a semiconductor device.

[0095] In an exemplary embodiment, the first sub-N-type well and the second sub-N-type well are arranged adjacent to each other, and the first sub-P-type well and the second sub-P-type well are arranged adjacent to each other; the first sub-N-type well and the first P-type well are arranged adjacent to each other, and the second sub-N-type well and the second sub-P-type well are arranged adjacent to each other.

[0096] In an exemplary embodiment, the first sub-N-type well and the second sub-N-type well are arranged adjacent to each other; the first sub-P-type well is adjacent to the first sub-N-type well and located on the side of the first sub-N-type well away from the second sub-N-type well; the second sub-P-type well is adjacent to the second sub-N-type well and located on the side of the second sub-N-type well away from the first sub-N-type well.

[0097] In an exemplary embodiment, the first sub-P-type well and the second sub-P-type well are arranged adjacent to each other; the first sub-N-type well is adjacent to the first sub-P-type well and located on the side of the first sub-P-type well away from the second sub-P-type well; the second sub-N-type well is adjacent to the second sub-P-type well and located on the side of the second sub-P-type well away from the first sub-P-type well.

[0098] In an exemplary embodiment, the CBCM capacitance measurement circuit includes a first P-type transistor, a second P-type transistor, a first N-type transistor, and a second N-type transistor. The control terminals of the first P-type transistor and the second P-type transistor are connected to form a first control signal terminal of the CBCM capacitance measurement circuit, and the control terminals of the first N-type transistor and the second N-type transistor are connected to form a second control signal terminal of the CBCM capacitance measurement circuit. The second connection terminal of the first P-type transistor and the first connection terminal of the first N-type transistor are connected to form a first load terminal of the CBCM capacitance measurement circuit, and the second connection terminal of the second P-type transistor and the first connection terminal of the second N-type transistor are connected to form a second load terminal of the CBCM capacitance measurement circuit. The first connection terminals of the first P-type transistor and the second P-type transistor are respectively connected to a first power supply terminal, and the second connection terminals of the first N-type transistor and the second N-type transistor are both connected to a ground terminal. The parameters of the first P-type transistor and the second P-type transistor are the same, and the parameters of the first N-type transistor and the second N-type transistor are the same.

[0099] In an exemplary embodiment, the detection module can also be used to: connect the first thyristor device and the composite device to the two load terminals of the CBCM capacitance measurement circuit respectively; provide a first control signal to a first control signal terminal and a second control signal to a second control signal terminal to control the CBCM capacitance measurement circuit to provide a first charging current to the semiconductor device and to provide a second charging current to the composite device, wherein the conduction level of the first control signal and the conduction level of the second control signal do not overlap, and the signal frequency of the first control signal is the same as the signal frequency of the second control signal; and detect the parasitic capacitance of the composite device using the first charging current and the second charging current.

[0100] In an exemplary embodiment, the first N-doped region in the first thyristor device serves as the first connection terminal of the first thyristor device, and the first P-doped region in the first thyristor device serves as the second connection terminal of the first thyristor device; the first sub-N-doped region serves as the first connection terminal of the composite device, and the first sub-P-doped region and the second sub-P-doped region are connected to serve as the second connection terminal of the composite device; or, the first sub-N-doped region and the second sub-N-doped region are connected to serve as the first connection terminal of the composite device, and the first sub-P-doped region serves as the second connection terminal of the composite device.

[0101] In an exemplary embodiment, the detection module can also be used to: connect the first connection terminal and the second connection terminal of the first thyristor device to the first load terminal and the ground terminal of the CBCM capacitance measurement circuit, respectively; and connect the first connection terminal and the second connection terminal of the composite device to the second load terminal and the ground terminal of the CBCM capacitance measurement circuit, respectively.

[0102] Figure 10 This is a schematic diagram of the structure of a test device according to one embodiment of the present disclosure. It should be noted that... Figure 10 The test device 700 shown is merely an example and should not be construed as limiting the functionality and scope of the embodiments disclosed herein. Figure 10 As shown, the test equipment 700 may include, but is not limited to, a PC or server running pre-installed software.

[0103] like Figure 10 As shown, the test device 700 includes a central processing unit (CPU) 701, which can perform various appropriate actions and processes based on programs stored in read-only memory (ROM) 702 or programs loaded from storage section 708 into random access memory (RAM) 703. The RAM 703 also stores various programs and data required for system operation. The CPU 701, ROM 702, and RAM 703 are interconnected via a bus 704. An input / output (I / O) interface 705 is also connected to the bus 704.

[0104] The following components are connected to the (I / O) interface 705: an input section 706 including a keyboard, mouse, etc.; an output section 707 including a cathode ray tube (CRT), liquid crystal display (LCD), etc., and speakers, etc.; a storage section 708 including a hard disk, etc.; and a communication section 709 including a network interface card such as a LAN card, modem, etc. The communication section 709 performs communication processing via a network such as the Internet. A drive 710 is also connected to the (I / O) interface 705 as needed. A removable medium 711, such as a disk, optical disk, magneto-optical disk, semiconductor memory, etc., is installed on the drive 710 as needed so that computer programs read from it can be installed into the storage section 708 as needed.

[0105] Specifically, according to embodiments of this disclosure, the above reference flow Figure 3 The described process can be implemented as a computer software program. For example, embodiments of this disclosure include a computer program product comprising a computer program carried on a computer-readable storage medium, the computer program containing program code for performing the methods shown in the flowchart. In such embodiments, the computer program can be downloaded and installed from a network via communication section 709, and / or installed from removable medium 711. When the computer program is executed by central processing unit (CPU) 701, it performs the various functions defined in the methods and apparatus of this disclosure.

[0106] It should be noted that the computer-readable storage medium disclosed herein may be a computer-readable signal medium or a computer-readable storage medium, or any combination thereof. A computer-readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of a computer-readable storage medium may include, but are not limited to: an electrical connection having one or more wires, a portable computer disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination thereof. In this disclosure, a computer-readable storage medium may be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, apparatus, or device. In this disclosure, a computer-readable signal medium may include a data signal propagated in baseband or as part of a carrier wave, carrying computer-readable program code. Such propagated data signals may take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. Computer-readable signal media can also be any computer-readable storage medium other than a computer-readable storage medium, which can send, propagate, or transmit a program for use by or in connection with an instruction execution system, apparatus, or device. The program code contained on the computer-readable storage medium can be transmitted using any suitable medium, including but not limited to: wireless, wire, optical fiber, etc., or any suitable combination thereof.

[0107] In another aspect, this disclosure also provides a computer-readable storage medium, which may be included in the test device 700 described in the above embodiments; or it may exist independently and not assembled into the test device 700. The computer-readable storage medium carries one or more programs that, when executed by the test device 700, cause the test device 700 to implement the methods in the above embodiments. For example, the test device 700 may implement... Figure 1 The various steps shown are as follows.

[0108] Furthermore, this disclosure also provides a simulation method for an electrostatic discharge (ESD) protection circuit, which may include a silicon controlled rectifier (SCR). This method can be implemented using simulation software and may include:

[0109] S210. Construct NPN and PNP transistor models that include parasitic capacitance values;

[0110] S220. Construct a thyristor model using NPN and PNP transistor models.

[0111] S230. Obtain the netlist of the electrostatic protection circuit, and replace the information of the corresponding thyristor in the netlist with the information of the thyristor model to generate an updated netlist.

[0112] S240. Simulation processing is performed based on the updated netlist.

[0113] In step S210, the parasitic capacitance values ​​of the NPN transistor and PNP transistor in the thyristor are obtained according to the method for detecting the parasitic capacitance of semiconductor devices disclosed herein. Then, in the simulation software, the selected NPN and PNP transistors are assigned corresponding parasitic capacitance values, thus obtaining the corresponding NPN and PNP transistor models. In step S220, the thyristor device is constructed using the already constructed NPN and PNP transistor models. Clearly, since the parameters and parasitic capacitance parameters of both the NPN and PNP transistors are known values, the simulation method of this disclosure allows for free adjustment of the size and parameters of the thyristor device according to design needs, improving the simulation accuracy of the circuit. Finally, in steps S230 and S240, the matching electrostatic discharge (ESD) protection circuit is simulated using simulation software.

[0114] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the generality of this disclosure and include, but are not disclosed herein, common knowledge or customary techniques in the art. The specification and embodiments are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the claims.

Claims

1. A method for detecting parasitic capacitance in a silicon controlled rectifier (SCR), characterized in that, include: Construct a CBCM capacitance measurement circuit; Constructing the first thyristor device; Construct a composite device, wherein the composite device includes a second thyristor device and a semiconductor device, the parameters of the second thyristor device are the same as those of the first thyristor device, and the structure of the semiconductor device is the same as the structure of any transistor in the first thyristor device that generates parasitic capacitance. The CBCM capacitance measurement circuit provides an excitation signal to the first thyristor device and the composite device connected thereto, so as to detect the parasitic capacitance of the composite device. The parasitic capacitance of any transistor in the first thyristor device is determined based on the capacitance difference between the parasitic capacitance of the composite device and the parasitic capacitance of the first thyristor device. The first thyristor device includes a first N-type well, a first P-type well, a first P-doped region disposed in the first N-type well, and a first N-doped region disposed in the first P-type well; The composite device includes a second N-type well and a second P-type well; The second N-type well includes a first sub-N-type well, a second sub-N-type well, a first sub-P-doped region disposed in the first sub-N-type well, and a second N-doped region disposed in the second sub-N-type well. The parameters of the first sub-N-type well and the second sub-N-type well are the same as the parameters of the first N-type well. The parameters of the first sub-P-doped region and the second sub-P-doped region are the same as the parameters of the first P-doped region. The second P-type well includes a first sub-P-type well, a second sub-P-type well, and a first sub-N-doped region disposed in the first sub-P-type well and / or a second sub-N-doped region disposed in the second sub-P-type well. The parameters of the first sub-P-type well and the second sub-P-type well are the same as the parameters of the first P-type well. The parameters of the first sub-N-doped region and the second sub-N-doped region are the same as the parameters of the first N-doped region. The first sub-N-type well, the first sub-P-type well, the first sub-P-doped region, and the first sub-N-doped region constitute the second thyristor device, and the second sub-N-type well, the second sub-P-type well, and the second sub-P-doped region constitute the semiconductor device. Alternatively, the first sub-N-type well, the first sub-P-type well, the first sub-P-doped region, and the first sub-N-doped region constitute the second thyristor device, and the second sub-N-type well, the second sub-P-type well, and the second sub-N-doped region constitute the semiconductor device.

2. The method according to claim 1, characterized in that, The first sub-N-type well and the second sub-N-type well are arranged adjacent to each other, and the first sub-P-type well and the second sub-P-type well are arranged adjacent to each other; The first sub-N-type well is arranged adjacent to the first P-type well, and the second sub-N-type well is arranged adjacent to the second sub-P-type well.

3. The method according to claim 1, characterized in that, The first sub-N-type well and the second sub-N-type well are arranged adjacent to each other; The first sub-P-type well is adjacent to the first sub-N-type well and is located on the side of the first sub-N-type well that is far away from the second sub-N-type well; The second sub-P-type well is adjacent to the second sub-N-type well and is located on the side of the second sub-N-type well away from the first sub-N-type well.

4. The method according to claim 1, characterized in that, The first sub-P-type well and the second sub-P-type well are arranged adjacent to each other; The first sub-N-type well is adjacent to the first sub-P-type well and is located on the side of the first sub-P-type well that is far away from the second sub-P-type well; The second sub-N-type well is adjacent to the second sub-P-type well and is located on the side of the second sub-P-type well away from the first sub-P-type well.

5. The method according to claim 1, characterized in that, The CBCM capacitance measurement circuit includes a first P-type transistor, a second P-type transistor, a first N-type transistor, and a second N-type transistor; The control terminal of the first P-type transistor is connected to the control terminal of the second P-type transistor to form the first control signal terminal of the CBCM capacitance measurement circuit, and the control terminal of the first N-type transistor is connected to the control terminal of the second N-type transistor to form the second control signal terminal of the CBCM capacitance measurement circuit. The second connection terminal of the first P-type transistor is connected to the first connection terminal of the first N-type transistor to form the first load terminal of the CBCM capacitance measurement circuit, and the second connection terminal of the second P-type transistor is connected to the first connection terminal of the second N-type transistor to form the second load terminal of the CBCM capacitance measurement circuit. The first connection terminal of the first P-type transistor and the first connection terminal of the second P-type transistor are respectively connected to the first power supply terminal, and the second connection terminal of the first N-type transistor and the second connection terminal of the second N-type transistor are both connected to the ground terminal; The parameters of the first P-type transistor are the same as those of the second P-type transistor, and the parameters of the first N-type transistor are the same as those of the second N-type transistor.

6. The method according to claim 5, characterized in that, The step of using the CBCM capacitance measurement circuit to provide an excitation signal to the first thyristor device and the composite device connected thereto, in order to detect the parasitic capacitance of the composite device, includes: The first thyristor device and the composite device are respectively connected to the two load terminals of the CBCM capacitance measurement circuit; A first control signal is provided to the first control signal terminal and a second control signal is provided to the second control signal terminal to control the CBCM capacitance measurement circuit to provide a first charging current to the semiconductor device and to provide a second charging current to the composite device. The conduction level of the first control signal and the conduction level of the second control signal do not overlap, and the signal frequency of the first control signal and the signal frequency of the second control signal are the same. The parasitic capacitance of the composite device is detected using the first charging current and the second charging current.

7. The method according to claim 6, characterized in that, The first N-doped region in the first thyristor device serves as the first connection terminal of the first thyristor device, and the first P-doped region in the first thyristor device serves as the second connection terminal of the first thyristor device. The first sub-N doped region serves as the first connection terminal of the composite device, and the first sub-P doped region and the second sub-P doped region, after being connected, serve as the second connection terminal of the composite device; or, the first sub-N doped region and the second sub-N doped region, after being connected, serve as the first connection terminal of the composite device, and the first sub-P doped region serves as the second connection terminal of the composite device.

8. The method according to claim 7, characterized in that, The step of connecting the first thyristor device and the composite device to the two load terminals of the CBCM capacitance measurement circuit includes: Connect the first and second connection terminals of the first thyristor device to the first load terminal and ground terminal of the CBCM capacitance measurement circuit, respectively; and... The first and second connection terminals of the composite device are respectively connected to the second load terminal and the ground terminal of the CBCM capacitance measurement circuit.

9. A device for detecting parasitic capacitance in a silicon controlled rectifier (SCR), characterized in that, include: The circuit construction module is used to build CBCM capacitance measurement circuits; The first device construction module is used to construct the first thyristor device; The second device construction module is used to construct a composite device, wherein the composite device includes a second thyristor device and a semiconductor device, the parameters of the second thyristor device are the same as those of the first thyristor device, and the structure of the semiconductor device is the same as the structure of any transistor in the first thyristor device that generates parasitic capacitance. The detection module is used to provide excitation signals to the first thyristor device and the composite device connected thereto using the CBCM capacitance measurement circuit, so as to detect the parasitic capacitance of the composite device. The calculation module is used to determine the parasitic capacitance of any transistor in the first thyristor device based on the capacitance difference between the parasitic capacitance of the composite device and the parasitic capacitance of the first thyristor device. The first thyristor device includes a first N-type well, a first P-type well, a first P-doped region disposed in the first N-type well, and a first N-doped region disposed in the first P-type well. The composite device includes a second N-type well and a second P-type well; The second N-type well includes a first sub-N-type well, a second sub-N-type well, a first sub-P-doped region disposed in the first sub-N-type well, and a second N-doped region disposed in the second sub-N-type well. The parameters of the first sub-N-type well and the second sub-N-type well are the same as the parameters of the first N-type well. The parameters of the first sub-P-doped region and the second sub-P-doped region are the same as the parameters of the first P-doped region. The second P-type well includes a first sub-P-type well, a second sub-P-type well, and a first sub-N-doped region disposed in the first sub-P-type well and / or a second sub-N-doped region disposed in the second sub-P-type well. The parameters of the first sub-P-type well and the second sub-P-type well are the same as the parameters of the first P-type well. The parameters of the first sub-N-doped region and the second sub-N-doped region are the same as the parameters of the first N-doped region. The first sub-N-type well, the first sub-P-type well, the first sub-P-doped region, and the first sub-N-doped region constitute the second thyristor device, and the second sub-N-type well, the second sub-P-type well, and the second sub-P-doped region constitute the semiconductor device. Alternatively, the first sub-N-type well, the first sub-P-type well, the first sub-P-doped region, and the first sub-N-doped region constitute the second thyristor device, and the second sub-N-type well, the second sub-P-type well, and the second sub-N-doped region constitute the semiconductor device.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the program is executed by the processor, it implements the method for detecting parasitic capacitance in a thyristor as described in any one of claims 1 to 8.

11. A testing device, characterized in that, include: One or more processors; A storage device for storing one or more programs, which, when executed by one or more processors, cause the one or more processors to implement the method for detecting parasitic capacitance in a thyristor as described in any one of claims 1 to 8.

12. A simulation method for an electrostatic discharge (ESD) protection circuit, wherein the ESD protection circuit includes a silicon controlled rectifier (SCR), characterized in that, include: Construct an NPN transistor model and a PNP transistor model that include parasitic capacitance values, wherein the parasitic capacitance values ​​of the NPN transistor and the PNP transistor are determined by the method described in any one of claims 1-8; A thyristor model is constructed using the NPN transistor model and the PNP transistor model. Obtain the netlist of the electrostatic discharge protection circuit, and replace the information corresponding to the thyristor in the netlist with the information of the thyristor model to generate an updated netlist; Simulation processing is performed based on the updated netlist.

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