Addressable Test Array

Abstract

The invention discloses an addressable test array, which is used to solve the problem of low utilization rate of test structure area and test process time. The array comprises a plurality of addressable controllable open and close low leakage switches, wherein the low leakage switches comprise: a first MOS tube, whose drain end is connected to a drain voltage signal line; a second MOS tube, whose drain end is connected to a signal protection path, and the signal protection path is configured to be equal to the voltage on the drain voltage signal line; the well end voltages of the first MOS tube and the second MOS tube are configured to be equal to the voltage on the signal protection path, and the source ends of the first MOS tube and the second MOS tube are interconnected; each low leakage switch is configured to: when a first voltage control signal is loaded on the gate end of the first MOS tube to turn it on, and a second voltage control signal is loaded on the gate end of the second MOS tube to turn it off, the low leakage switch is turned on; when the first voltage control signal is loaded on the gate end of the first MOS tube to turn it off, and the second voltage control signal is loaded on the gate end of the second MOS tube to turn it on, the low leakage switch is turned off.

Description

Technical Field

[0001] The invention belongs to the technical field of semiconductor testing, and in particular relates to an addressable testing array. Background Art

[0002] In the semiconductor development process, it is usually necessary to use semiconductor test structures to test process maturity and semiconductor device performance. Figure 1 A commonly used test structure includes a pad for connecting the test lines led out from each port of the device under test, and the pad is contacted by a probe connected to the instrument to read the corresponding measurement data.

[0003] In this test structure, for example, if the size of the DUT is 1μm×1μm, the size of a corresponding pad is 60μm×60μm. Since a DUT requires 2 to 4 or more Pads to test, most of the area of ​​the test structure is occupied by the Pad, resulting in very low area utilization of the test structure. In addition, when testing different DUTs, it is also necessary to frequently use mechanical components such as motors to move the probe to the Pad of other test structures; in some cases, the probe movement process time may be longer than the measurement time, resulting in low time utilization efficiency of the test process. Summary of the invention

[0004] The object of the present invention is to provide an addressable test array, which is used to solve the problem of low area utilization of current test structures and low time utilization of test processes.

[0005] To achieve the above object, the present invention provides an addressable test array for testing a plurality of devices under test, comprising a plurality of addressable low leakage switches for controlling opening and closing, each of the low leakage switches comprising:

[0006] A first MOS transistor, wherein a drain end of the first MOS transistor is connected to a drain end voltage signal line;

[0007] A second MOS transistor, wherein a drain end of the second MOS transistor is connected to a first signal protection path, and the first signal protection path is configured to be equal to a voltage on a drain end voltage signal line;

[0008] The well terminal voltages of the first MOS transistor and the second MOS transistor are configured to be equal to the voltage on the first signal protection path, the source terminals of the first MOS transistor and the second MOS transistor are interconnected and used to connect the device under test; each of the low leakage switches is configured as:

[0009] When a first voltage control signal is loaded on the gate terminal of the first MOS transistor to turn on the first MOS transistor, and a second voltage control signal is loaded on the gate terminal of the second MOS transistor to turn off the second MOS transistor, the low leakage switch is turned on;

[0010] When a first voltage control signal is loaded on the gate terminal of the first MOS tube to turn off the first MOS tube, and a second voltage control signal is loaded on the gate terminal of the second MOS tube to turn on the second MOS tube, the low leakage switch is turned off.

[0011] In one embodiment, the first signal protection path replicates the voltage on the drain voltage signal line through a voltage follower buffer; or,

[0012] The drain voltage signal line and the first signal protection path are respectively connected to pads of equal voltage.

[0013] In one embodiment, the well end of the first MOS transistor is connected to the drain voltage signal line or the first signal protection path, and the well end of the second MOS transistor is connected to the drain voltage signal line or the first signal protection path.

[0014] In one embodiment, the well ends of the first MOS transistor and the second MOS transistor are interconnected and connected to the drain voltage signal line or the first signal protection path.

[0015] In one embodiment, in the extension direction of the drain voltage signal line, the first signal protection path is arranged to surround the circumference of the drain voltage signal line.

[0016] In one embodiment, each of the low leakage switches further comprises a high impedance voltage measurement loop that can be controlled to open and close, one end of the high impedance voltage measurement loop is connected to the source end of the first MOS tube, and the other end is connected to the drain sensing signal line;

[0017] The addressable test array further includes a second signal protection path, and the second signal protection path is configured to be equal to the voltage on the drain sensing signal line.

[0018] In one embodiment, the high-resistance voltage measurement loop includes a third MOS tube, a source end of the third MOS tube is connected to the source end of the first MOS tube, a drain end of the third MOS tube is connected to the drain sensing signal line, a gate end of the third MOS tube is interconnected with the gate end of the first MOS tube, and a well end of the third MOS tube is connected to the second signal protection path.

[0019] In one embodiment, the second signal protection path replicates the voltage on the drain sensing signal line through a voltage follower buffer; or,

[0020] The drain sensing signal line and the second signal protection path are respectively connected to pads of equal voltage.

[0021] In one embodiment, in the extension direction of the drain sensing signal line, the second signal protection path is arranged to surround the circumference of the drain sensing signal line.

[0022] The present invention also provides an addressable test array for testing a plurality of devices under test, comprising a plurality of addressable low leakage switches for controlling opening and closing, each of the low leakage switches comprising:

[0023] A first MOS transistor, wherein a drain end of the first MOS transistor is connected to a drain end voltage signal line;

[0024] A high-resistance voltage measurement loop that can be controlled to open and close, one end of the high-resistance voltage measurement loop is connected to the source end of the first MOS tube, and the other end is connected to the drain sensing signal line;

[0025] A second MOS tube, wherein a drain end of the second MOS tube is connected to a signal protection path;

[0026] The signal protection path, the drain sensing signal line, and the drain voltage signal line are configured to have equal voltages, the well terminal voltages of the first MOS transistor and the second MOS transistor are configured to be equal to the voltage on the signal protection path, and the source terminals of the first MOS transistor and the second MOS transistor are interconnected and used to connect the device under test; each of the low leakage switches is configured as:

[0027] When a first voltage control signal is loaded on the gate terminal of the first MOS transistor to turn on the first MOS transistor, and a second voltage control signal is loaded on the gate terminal of the second MOS transistor to turn off the second MOS transistor, the low leakage switch is turned on;

[0028] When a first voltage control signal is loaded on the gate terminal of the first MOS tube to turn off the first MOS tube, and a second voltage control signal is loaded on the gate terminal of the second MOS tube to turn on the second MOS tube, the low leakage switch is turned off.

[0029] The present invention also provides an addressable test array for testing a plurality of devices under test, comprising a plurality of addressable low leakage switches for controlling opening and closing, each of the low leakage switches comprising:

[0030] A first MOS transistor, wherein a drain end of the first MOS transistor is connected to a drain end voltage signal line;

[0031] A high-resistance voltage measurement loop that can be controlled to open and close, one end of the high-resistance voltage measurement loop is connected to the source end of the first MOS tube, and the other end is connected to the drain sensing signal line;

[0032] A second MOS transistor, wherein the drain end of the second MOS transistor can be controllably connected to the drain end voltage signal line or the drain end sensing signal line;

[0033] A signal protection path, wherein the signal protection path is configured to be equal to the voltage on the drain voltage signal line and the drain sensing signal line;

[0034] The well terminal voltages of the first MOS transistor and the second MOS transistor are configured to be equal to the voltage on the signal protection path, the source terminals of the first MOS transistor and the second MOS transistor are interconnected and used to connect the device under test; each of the low leakage switches is configured as:

[0035] When a first voltage control signal is loaded on the gate terminal of the first MOS transistor to turn on the first MOS transistor, and a second voltage control signal is loaded on the gate terminal of the second MOS transistor to turn off the second MOS transistor, the low leakage switch is turned on;

[0036] When a first voltage control signal is loaded on the gate terminal of the first MOS tube to turn off the first MOS tube, and a second voltage control signal is loaded on the gate terminal of the second MOS tube to turn on the second MOS tube, the low leakage switch is turned off.

[0037] In one embodiment, the high-resistance voltage measurement loop includes a third MOS tube, a source end of the third MOS tube is connected to the source end of the first MOS tube, a drain end of the third MOS tube is connected to the drain sensing signal line, a gate end of the third MOS tube is interconnected with the gate end of the first MOS tube, and a well end of the third MOS tube is connected to the signal protection path.

[0038] In one embodiment, the signal protection path replicates the voltage on the drain sensing signal line or the drain voltage signal line through a voltage follower buffer; or,

[0039] The drain sensing signal line, the drain voltage signal line, and the signal protection path are respectively connected to pads of equal voltage.

[0040] In one embodiment, in the extending direction of the drain voltage signal line and the drain sensing signal line, the signal protection path is arranged to surround the circumference of the drain voltage signal line and the drain sensing signal line.

[0041] In one embodiment, the plurality of low leakage switches, drain voltage signal lines, drain sensing signal lines and signal protection paths constitute an addressable test circuit, and the addressable test array includes:

[0042] The addressable test circuit is used to connect to the drain terminals of multiple devices under test; and / or,

[0043] The addressable test circuit is used to connect to the gate terminals of multiple devices under test; and / or,

[0044] The addressable test circuit is used to connect to the source terminals of multiple devices under test; and / or,

[0045] The addressable test circuit is used to be connected to the well terminals of multiple devices under test.

[0046] In one embodiment, the addressable test array further comprises a coaxial cable connected between the probe and the instrument panel, and the outside of the coaxial cable replicates the voltage of the lead wire at the current device under test through a voltage follower buffer.

[0047] Compared with the prior art, the addressable test array of the present application can selectively switch on and off the devices under test connected to each low leakage switch according to the test needs by setting a plurality of addressable low leakage switches that can be controlled to open and close, and the test ends of the plurality of devices under test can share the pad, thereby improving the area of ​​the test structure and the time utilization rate of the test process;

[0048] On the other hand, since the signal protection path of the testable array is configured to be equal to the voltage on the drain voltage signal line, the inherent drain leakage of the first MOS tube when the low leakage switch is turned off and the leakage from the drain end to the well end of the first MOS tube when the low leakage switch is turned on can be eliminated;

[0049] On the other hand, the signal protection path of the addressable test is arranged to surround the drain voltage signal line and the drain sensing signal line. Since the signal protection path has the same voltage as the drain voltage signal line and the drain sensing signal line, the influence of leakage on the drain voltage signal line and the drain sensing signal line on the measurement result can be reduced.

[0050] On the other hand, the coaxial cable between the addressable test array connection probe and the instrument panel replicates the wire of the lead wire at the current device under test through the voltage follower buffer, eliminating the potential difference between the wire at the device under test and the coaxial cable, and reducing the leakage of the external coaxial cable;

[0051] On the other hand, the addressable test array can be set to be multi-terminal addressable according to the needs of the device under test, thereby reducing the impact of leakage current at other ends of each device under test accumulating into the signal protection path when the low-leakage switch is in the intermediate state of disconnection and conduction, and finally flowing into the shared end of the current device under test on the detection. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] Figure 1 is a schematic diagram of a semiconductor test structure in the prior art;

[0053] Figure 2 is a schematic structural diagram of an implementation of an addressable test array;

[0054] Figure 3 A schematic diagram of the structure of an addressable test array according to an embodiment of the present application;

[0055] Figure 4 A schematic diagram of the structure of an addressable test array according to another embodiment of the present application;

[0056] Figure 5 It is a structural schematic diagram of a signal protection path surrounding a drain voltage signal line in an addressable test array in one embodiment of the present application;

[0057] Figure 6 A schematic diagram of the structure of an addressable test array with addressable drain and gate terminals according to an embodiment of the present application;

[0058] Figure 7 It is a schematic diagram of the structure of a four-terminal addressable addressable test array according to an embodiment of the present application;

[0059] Figure 8 is a schematic diagram of the structure of an addressable test array according to an embodiment of the present application;

[0060] Fig. 9 is a schematic structural diagram of an addressable test array in another embodiment of the present application;

[0061] Fig.10 It is a structural schematic diagram of a four-terminal addressable addressable test array according to another embodiment of the present application;

[0062] Fig.11 is a schematic structural diagram of an addressable test array in another embodiment of the present application;

[0063] Fig.12 It is a circuit diagram of a 32×1 row and column addressable test array of the present application. DETAILED DESCRIPTION

[0064] The specific implementation modes of the present invention are described in detail below in conjunction with the accompanying drawings, but it should be understood that the protection scope of the present invention is not limited by the specific implementation modes.

[0065] Unless explicitly stated otherwise, throughout the specification and claims, the term “comprise” or variations such as “include” or “comprising”, etc., will be understood to include the stated elements or components but not to exclude other elements or components.

[0066] Ginseng Figure 2 , a test array with a shared pad is introduced. Taking the device under test having a gate terminal (G), a source terminal (S), a drain terminal (D), and a well terminal (B) as an example, the gate terminals, source terminals, and well terminals of multiple devices under test can be connected to a common pad (Pad), while the drain terminal that cannot be reused is connected to another Pad through multiple switches. The test array can control whether the switch is connected to the drain terminal of the device under test through a controller, and at the same time, the test array will only select one device under test for testing.

[0067] Ginseng Figure 3 , a specific implementation of the addressable test array 100 of the present application is introduced. In this implementation, the addressable test array 100 includes a plurality of addressable low leakage switches 11 whose opening and closing can be controlled.

[0068] The addressable test array 100 can be used for testing multiple devices under test. Usually, each low leakage switch 11 corresponds to one device under test. It should be noted that, depending on the different devices under test, the number of test ports corresponding to each device under test may also be different. Here, "each low leakage switch 11 corresponds to one device under test" means that the low leakage switch 11 only corresponds to controlling the connection to the device under test or a port of the device under test.

[0069] Each low leakage switch 11 includes two MOS transistors: a first MOS transistor 111 and a second MOS transistor 112. The drain end of the first MOS transistor 111 is connected to the drain voltage signal line 12, the drain end of the second MOS transistor 112 is connected to the first signal protection path 131, and the well end voltages of the first MOS transistor 111 and the second MOS transistor 112 are configured to be equal to the voltage on the first signal protection path 131, and the source ends of the first MOS transistor 111 and the second MOS transistor 112 are interconnected.

[0070] In such a low leakage switch 11, different voltage control signals can be loaded on the gate terminals of the first MOS transistor 111 and the second MOS transistor 112 to control the conduction or disconnection of the entire low leakage switch 11. Specifically, when the first voltage control signal is loaded on the gate terminal of the first MOS transistor 111 to turn on the first MOS transistor 111, and the second voltage control signal is loaded on the gate terminal of the second MOS transistor 112 to turn off the second MOS transistor 112, the low leakage switch 11 is turned on; correspondingly, when the first voltage control signal is loaded on the gate terminal of the first MOS transistor 111 to turn off the first MOS transistor 111, and the second voltage control signal is loaded on the gate terminal of the second MOS transistor 112 to turn on the second MOS transistor 112, the low leakage switch 11 is turned off.

[0071] Taking the measurement of the current and voltage at the drain terminal of the device under test as an example, a corresponding voltage may be applied to the drain terminal of the device under test, and the corresponding current and voltage may be measured at a suitable position on the drain terminal voltage signal line 12 .

[0072] In the low leakage switch 11 of the above structure, leakage is still possible. Including: ① leakage from the drain end to the source end of the first MOS tube 111 when the low leakage switch 11 is turned off; ② leakage from the drain end to the well end of the first MOS tube 111 when the low leakage switch 11 is turned on. Correspondingly, in this embodiment, the first signal protection path 131 is configured to be equal to the voltage on the drain voltage signal line 12 to eliminate the above leakage.

[0073] Specifically, when the low leakage switch 11 is turned off, the inherent drain leakage of the first MOS transistor 111 includes: leakage from the drain end to the well end, leakage from the drain end to the source end, and leakage from the well end to the source end. At this time, since the second MOS transistor 112 is in the on state, and the well end voltage of the first MOS transistor 111 is equal to the voltage on the drain end voltage signal line 12, the drain end voltage, the well end voltage, and the source end voltage of the first MOS transistor 111 are pulled to be equal, thereby effectively eliminating the inherent source end leakage of the first MOS transistor 111 at this time. Similarly, when the low leakage switch 11 is turned on, the leakage from the drain end to the well end of the first MOS transistor 111, at this time, since the well end voltage of the first MOS transistor 111 is pulled to be equal to the drain end voltage, the leakage from the drain end to the well end can also be effectively eliminated.

[0074] In a specific structure, such as Figure 3 As shown, the first signal protection path 131 can be a voltage follower buffer 15 that copies the voltage on the drain voltage signal line 12, or, as shown in FIG. Figure 4 As shown, the drain voltage signal line 12 and the first signal protection path 131 can be connected to pads of equal voltage, respectively.

[0075] In this embodiment, each of the above-mentioned low leakage switches 11 can also be arranged in a deep well for isolation from the substrate, thereby eliminating leakage from the well end to the substrate. In addition, in the above embodiments, the first MOS transistor 111 and the second MOS transistor 112 can select NMOS transistors or PMOS transistors according to different application scenarios to construct the basic function of the low leakage switch 11.

[0076] Taking the first MOS transistor 111 and the second MOS transistor 112 in the low leakage switch 11 as NMOS as an example, in such an embodiment, the low leakage switch 11 can be arranged in a deep N-well (DNW). Since the NMOS itself is made on a P-type substrate, the isolation of the deep N-well can also effectively eliminate the crosstalk of the current noise passing through the P-type substrate.

[0077] Continue to participate Figure 3 In this embodiment, the well terminals of the first MOS transistor 111 and the second MOS transistor 112 are interconnected and connected to the first signal protection path 131 to achieve that the well terminal voltages of both are equal to the voltage on the first signal protection path 131 .

[0078] In some alternative embodiments, since the voltages on the drain voltage signal line 12 and the first signal protection path 131 are equal, the well ends of the first MOS transistor 111 and the second MOS transistor 112 may be connected to the drain voltage signal line 12 after being interconnected. Alternatively, the well ends of the first MOS transistor 111 and the second MOS transistor 112 may not be interconnected, and the well end of the first MOS transistor 111 may be selectively connected to the drain voltage signal line 12 or the first signal protection path 131, and the well end of the second MOS transistor 112 may be selectively connected to the drain voltage signal line 12 or the first signal protection path 131.

[0079] In this embodiment, the addressable test array 100 further includes a coaxial cable (not shown) connected between the probe and the instrument panel, and the voltage of the lead wire at the current device under test is replicated on the outside of the coaxial cable through a voltage follower buffer. In this way, there is no potential difference between the wire at the current device under test and the coaxial cable, thereby minimizing the leakage of the external coaxial cable in this path.

[0080] It should be noted that the "lead wire from the current device under test" mentioned here refers to the lead wire from the test end of the current device under test. For example, when the addressable test array 100 measures the drain current of a MOS tube, the addressable test array 100 has a section of wire connected to the drain end of the MOS tube, and this section of wire is understood as the lead wire from the MOS tube at this time.

[0081] With reference Figure 5 In this embodiment, in the extension direction of the drain voltage signal line 12, the first signal protection path 131 is configured to surround the peripheral side of the drain voltage signal line 12. When measuring the leakage current of the device under test, the leakage on the drain voltage signal line 12 will also affect the measurement result, especially when the device under test is turned off, the leakage current intensity is close to the weak current intensity flowing through the circuit. By configuring the first signal protection path 131 to surround the peripheral side of the drain voltage signal line 12, since the voltages of the two are equal, this part of the measurement error source can be effectively eliminated.

[0082] In this embodiment, a plurality of low leakage switches 11, a drain voltage signal line 12 and a first signal protection path 131 together constitute an addressable test circuit. Figure 3 In the embodiment shown in FIG. 1 , the addressable test array 100 includes the addressable test circuit connected to the drain terminals of the multiple devices under test, that is, the addressable test array 100 implements “drain addressability” for the multiple devices under test through the addressable test circuit.

[0083] In the embodiment where only the drain end is set to be addressable, it can be achieved that there is no leakage when the low leakage switch 11 is turned off or on, and the leakage measurement of the device under test is not affected. However, since all the devices under test share the gate terminal control, all the devices under test are controlled at the same time, and the current of the corresponding port of the current device under test that is selected to be turned on is on the drain terminal voltage signal line 12, while the leakage of all other ends of the devices under test will flow into the first signal protection path 131 and accumulate, for example, it can reach the milliampere level, and finally flow to the gate end of the current device under test, which will affect the leakage detection of the current device under test.

[0084] With reference Figure 6 In order to cope with the above challenges, in one embodiment, the addressable test array 100 can be set to be "gate-addressable", that is, it includes the above-mentioned addressable test circuit that can be connected to the gate terminals of multiple devices under test. In this way, when measuring the corresponding terminal (e.g., drain terminal) of the current device under test, the low leakage switch 11 corresponding to the gate terminal of other devices under test can be disconnected, so that the leakage current is blocked at the low leakage switch 11 to avoid flowing to the gate terminal of the current device under test, thereby ensuring the accuracy of the current measurement of the corresponding terminal of the device under test.

[0085] By analogy, in an embodiment where the device under test shares a source terminal and a well terminal, in the intermediate state between the disconnection and conduction of the low leakage switch 11, the accumulated leakage current will also flow into the source terminal and the well terminal of the current device under test, which will also affect the leakage detection of the current device under test.

[0086] With reference Figure 7 Similarly, in one embodiment, the addressable array can be set to be "source-addressable and well-addressable", that is, it includes the above-mentioned addressable test circuit that can be connected to the source ends of multiple devices under test, and the above-mentioned addressable test circuit that can be connected to the well ends of multiple devices under test.

[0087] In the above embodiments / examples, the source ends of the first MOS tube 111 and the second MOS tube 112 in each low leakage switch 11 are interconnected to connect the device to be tested, that is, the source ends of the first MOS tube 111 and the second MOS tube 112 are interconnected to form the "connection end" of the low leakage switch 11 connected to the device to be tested. For example, in an embodiment where the drain end is addressable, the connection end is connected to the drain end of each device to be tested; by analogy, in an embodiment where other ends are addressable, the connection end of each low leakage switch 11 in the corresponding addressable circuit is also connected to the corresponding device end to be tested. In addition, it should be noted that in the above embodiments / examples, the addressable setting of the addressable test array 100 for the specific end of the device to be tested can be determined, for example, based on factors such as test accuracy requirements and cost.

[0088] With reference Figure 8In this embodiment, the addressable test array 100 may further include a second signal protection path 132 and a high-resistance voltage measurement loop that can be controlled to open and close, one end of the high-resistance voltage measurement loop is connected to the source end of the first MOS tube 111, and the other end is connected to the drain sensing signal line 14, and the second signal protection path 132 is configured to be equal to the voltage on the drain sensing signal line 14.

[0089] Similarly, taking the measurement of the voltage at the drain terminal of the device under test as an example, a corresponding voltage can be applied to the drain terminal of the device under test, and a signal line 14 ( Figure 8 The corresponding voltage is measured by the voltage measuring terminal on DS).

[0090] The "high-resistance voltage measurement loop" mentioned here may refer to a measurement loop that can be connected to a measuring instrument with extremely high input resistance, so that the current on it can approach zero during measurement. Since the low leakage switch 11 may flow through a milliampere level of current in the on state, and the inherent on-resistance of the low leakage switch 11, the milliampere level of current will cause significant voltage transmission loss, and ultimately lead to errors in the leakage current measurement results. By configuring the voltage measurement of the drain-end sensing signal line 14 to be connected to a high-voltage resistance measurement loop, the interference of the resistance of the addressable test array 100 itself can be eliminated, and the voltage on the drain-end voltage signal line 12 does not affect the voltage on the high-resistance voltage measurement loop, so the voltage of the device under test can be accurately measured at the voltage measurement end of the drain-end sensing signal line 14.

[0091] It can be seen that by setting up the high-resistance voltage measurement loop, the voltage of the device under test can be measured on the drain-end sensing signal line 14 without affecting the current measurement of the device under test on the drain-end voltage signal line 12 .

[0092] In some different embodiments, the high-resistance voltage measurement loop can be implemented in various forms, for example, a resistor with a very high resistance value can be connected in series to the loop, or a high-resistance voltmeter can be directly configured at the voltage measurement end of the drain sensing signal line 14 to perform voltage measurement. It can be seen that the "high-resistance voltage measurement loop" can have a high-resistance characteristic itself, or cooperate with an external high-resistance measuring instrument to achieve high-resistance measurement.

[0093] It should be noted that the "current measurement terminal" and "voltage measurement terminal" mentioned in the various implementation modes / examples of the present application are not limited to structures or components that are set for measuring current and voltage; in fact, the current measurement terminal and the voltage measurement terminal can be, for example, any suitable position on the corresponding signal line.

[0094] Continue to participate Figure 8In this embodiment, the high-resistance voltage measurement loop includes a third MOS transistor 113, and the on-off of the high-resistance voltage measurement loop is controlled by the third MOS transistor 113. Specifically, the source end of the third MOS transistor 113 is connected to the source end of the first MOS transistor 111, the drain end of the third MOS transistor 113 is connected to the drain sensing signal line 14, the gate end of the third MOS transistor 113 is interconnected with the gate end of the first MOS transistor 111, and the well end of the third MOS transistor 113 is connected to the second signal protection path 132.

[0095] When the addressable test array 100 selects a device under test for measurement, the corresponding low leakage switch 11 is turned on, and the first voltage control signal is simultaneously loaded on the gate ends of the first MOS transistor 111 and the third MOS transistor 113 to turn on the first MOS transistor 111 and the third MOS transistor 113; the second voltage control signal is loaded on the gate end of the second MOS transistor 112 to turn off the second MOS transistor 112, thereby realizing the measurement of the current and voltage of the corresponding port of the device under test.

[0096] Correspondingly, when the low leakage switch 11 is disconnected, the first voltage control signal simultaneously controls the first MOS transistor 111 and the third MOS transistor 113 to be turned off, and the second voltage control signal controls the second MOS transistor 112 to be turned on, so as to maintain the low leakage characteristic of the low leakage switch 11 in the disconnected state.

[0097] In the extending direction of the drain sensing signal line 14 , the second signal protection path 132 is arranged to surround the peripheral side of the drain sensing signal line 14 , so as to also reduce the influence of leakage current on the drain sensing signal line 14 on the measurement result.

[0098] In this embodiment, the second signal protection path 132 can replicate the voltage on the drain sensing signal line 14 through a voltage follower buffer, or the drain sensing signal line 14 and the second signal protection path 132 can be respectively connected to pads with equal voltages.

[0099] It can be understood that after adding a drain-end sensing signal line 14 to the addressable test array 100, the drain-end sensing signal line 14 can also be used as a component of the above-mentioned addressable test circuit, and can cooperate to enable the addressable test array 100 to achieve "multi-terminal addressability" for multiple devices under test through the addressable test circuit.

[0100] Ginseng Fig. 9 , another specific implementation of the addressable test array 200 of the present application is introduced. In this implementation, the addressable test array 200 includes a plurality of addressable low leakage switches 11 whose opening and closing can be controlled.

[0101] Similar to the previous embodiment, each low leakage switch 11 includes a first MOS tube 111 and a second MOS tube 112, the drain end of the first MOS tube 111 is connected to the drain voltage signal line 12, the drain end of the second MOS tube 112 is connected to the signal protection path 13, and the well terminal voltages of the first MOS tube 111 and the second MOS tube 112 are configured to be equal to the voltage on the signal protection path 13, and the source ends of the first MOS tube 111 and the second MOS tube 112 are interconnected and used to connect the device under test.

[0102] Taking the measurement of the current at the drain end of the device under test as an example, the voltage signal line 12 ( Fig. 9 The corresponding voltage is applied to the drain terminal voltage signal line 12 (DF), and the low leakage switch connected thereto is set to the on state, and then Fig. 9 The corresponding current is measured by the current measuring terminal on DF).

[0103] In this embodiment, the addressable test array 200 also includes a controllable high-impedance voltage measurement loop, one end of which is connected to the source end of the first MOS transistor 111 and the other end is connected to the drain sensing signal line 14.

[0104] Similarly, taking the measurement of the voltage at the drain terminal of the device under test as an example, a corresponding voltage can be applied to the drain terminal of the device under test, and a signal line 14 ( Fig. 9 The corresponding voltage is measured by the voltage measuring terminal on DS).

[0105] Continue to participate Fig. 9 In this embodiment, the high-resistance voltage measurement loop includes a third MOS transistor 113, and the on-off of the high-resistance voltage measurement loop is controlled by the third MOS transistor 113. Specifically, the source end of the third MOS transistor 113 is connected to the source end of the first MOS transistor 111, the drain end of the third MOS transistor 113 is connected to the drain sensing signal line 14, the gate end of the third MOS transistor 113 is interconnected with the gate end of the first MOS transistor 111, and the well end of the third MOS transistor 113 is connected to the signal protection path 13 ( Fig. 9 in GRD).

[0106] When the addressable test array 100 selects a device under test for measurement, the corresponding low leakage switch 11 is turned on, and the first voltage control signal is simultaneously loaded on the gate ends of the first MOS transistor 111 and the third MOS transistor 113 to turn on the first MOS transistor 111 and the third MOS transistor 113; the second voltage control signal is loaded on the gate end of the second MOS transistor 112 to turn off the second MOS transistor 112, thereby realizing the measurement of the current and voltage of the corresponding port of the device under test.

[0107] Correspondingly, when the low leakage switch 11 is disconnected, the first voltage control signal simultaneously controls the first MOS transistor 111 and the third MOS transistor 113 to be turned off, and the second voltage control signal controls the second MOS transistor 112 to be turned on, so as to maintain the low leakage characteristic of the low leakage switch 11 in the disconnected state.

[0108] In this embodiment, the well end of the third MOS transistor 113 is connected to the drain end of the second MOS transistor 112 and then connected to the signal protection path 13. Of course, in an alternative embodiment, the well end of the third MOS transistor 113 can also be directly connected to the signal protection path 13.

[0109] With reference Figure 5 and Fig. 9 In the present embodiment, in the extension direction of the drain voltage signal line 12 and the drain sensing signal line 14, the signal protection path 13 is arranged to surround the circumference of the drain voltage signal line 12 and the drain sensing signal line 14, so as to also reduce the influence of leakage current on the drain voltage signal line 12 and the drain sensing signal line 14 on the measurement result.

[0110] In a specific structure, the drain voltage signal line 12 and the drain sensing signal line 14 may have substantially the same direction, and surround the drain voltage signal line 12 and the drain sensing signal line 14 at the same time through a signal protection path 13. Alternatively, corresponding signal protection paths 13 may be configured for the drain voltage signal line 12 and the drain sensing signal line 14, respectively.

[0111] In this embodiment, the signal protection path 13 can replicate the voltage on the drain sensing signal line 14 or the drain voltage signal line 12 through a voltage follower buffer, or the drain sensing signal line 14, the drain voltage signal line 12, and the signal protection path 13 can be respectively connected to pads with equal voltages.

[0112] Among them, due to the inherent on-resistance of the low leakage switch 11, there is a non-negligible voltage transfer loss on the drain voltage signal line 12; and since the drain sensing signal line 14 is connected to the high-resistance voltage measurement loop, the current on it is almost zero, and the voltage transfer loss can be ignored. In this way, the signal protection path 13 can more accurately replicate the voltage applied to the corresponding port of the device under test from the drain sensing signal line 14, which can avoid leakage from the well end to the source end of the first MOS tube 111 in the low leakage switch 11 when measuring large currents.

[0113] With reference Fig.10In this embodiment, a plurality of low leakage switches 11, drain voltage signal lines 12, drain sensing signal lines 14, and signal protection paths 13 together constitute an addressable test circuit. Similarly, the addressable test circuit in the addressable test array 100 can also be set as "drain addressable", "gate addressable", "source addressable", or "well addressable" according to the test requirements of the device under test. The specific setting method can refer to the previous embodiment and will not be repeated here.

[0114] Ginseng Fig.11 , another specific implementation of the addressable test array 300 of the present application is introduced. In this implementation, the addressable test array 300 also includes a plurality of addressable low leakage switches 11 whose opening and closing can be controlled.

[0115] Different from the previous embodiment, in this embodiment, the drain terminal of the second MOS transistor 112 can be controllably connected to the drain terminal voltage signal line 12 or the drain terminal sensing signal line 14. That is, the drain terminal voltage of the second MOS transistor 112 can be controllably equal to the voltage on the drain terminal voltage signal line 12 or the drain terminal sensing signal line 14.

[0116] In one embodiment, the drain terminals of the second MOS transistors 112 of the plurality of low leakage switches 11 may all be connected to a drain leakage protection signal line 15, and the drain leakage protection signal line 15 is controlled to be connected to the drain voltage signal line 12 or the drain sensing signal line 14. Exemplarily, the drain leakage protection signal line 15 may selectively copy the voltage from the drain voltage signal line 12 or the drain sensing signal line 14 through a voltage follower buffer to achieve the connection between the drain terminal of the second MOS transistor 112 and the drain voltage signal line 12 or the drain sensing signal line 14.

[0117] In a specific application scenario, depending on the type of device under test, the drain end of the second MOS tube 112 can be selectively connected to the drain voltage signal line 12 or the drain sensing signal line 14, and the signal protection path 13 can also be selectively copied to the voltage on the drain voltage signal line 12 or the drain sensing signal line 14.

[0118] Exemplarily, the type of the device under test here can be distinguished as an NMOS tube or a PMOS tube.

[0119] It should be noted that, since it involves the field of precise measurement, in the various implementation modes / embodiments of the present application, the "equality" defined in a functionally defined manner does not take into account the influence of unavoidable factors such as the characteristics of each device in the circuit and the circuit transmission loss. Therefore, in these implementation modes / embodiments, the definition of "equality" should be considered as an ideal state definition after ignoring these factors, and should not be regarded as an absolute definition of the equal state between the comparison objects. Exemplarily, taking "the signal protection path 13 is configured to be equal to that on the drain voltage signal line 12" as an example, the voltage transmission loss on the drain voltage signal line 12 is not considered at this time. The actual purpose of such a setting is to make the voltage on the signal protection path 13 infinitely close to the actual voltage at the current measurement end of the device under test; therefore, in the implementation mode of setting a high-impedance voltage measurement loop, the signal protection path 13 can be better set to: copy the voltage on the voltage sensing signal line with almost no voltage transmission loss.

[0120] Ginseng Fig.12 , taking a 32×1 row and column addressable test array as an example, the technical solution of the above implementation mode / embodiment of the present application is explained.

[0121] In this embodiment, the devices under test in the same row are controlled by the shift register driving the low leakage switch. Among them, RN is to initialize all triggers to zero to close all switches; SI is the scan input signal, which contains the specific parameter information of controlling the low leakage switch; CK is the clock of the row and column shift registers. At each rising edge of the CK signal, the register moves forward one bit to change the controlled low leakage switch; SO is the scan output signal to determine the conduction of the low leakage switch corresponding to the specific device under test DUT. The shift register can only select one device under test DUT at any time, and the drain voltage signal line DF of the test current and the drain sensing signal line DS of the test voltage are always wired in the signal protection path GRD to prevent leakage.

[0122] When the device under test is in the on state and its current is measured, the other devices under test are in the off state. At this time, the measurement error mainly comes from the voltage drop loss caused by the on resistance of the low leakage switch in the on state. By connecting the voltage sensing signal line DS, the voltage sensing signal line DS is connected to the high-resistance voltmeter, and the voltage borne by the device under test can be accurately measured, solving the problem of voltage measurement error caused by the voltage drop of the series resistance when the low leakage switch corresponding to the device under test is closed.

[0123] When the device under test is in a low current state and its current is measured, any tiny leakage will also significantly affect the measurement results. Here, the low current state of the device under test can be that the device under test itself is in a closed state, or the device under test is in a conducting state but the current applied to it is small. Therefore, in order to ensure that there is no leakage at the input and output nodes of the device under test (each end of the device), the low leakage switch 1 is turned on, and the well end of each MOS tube in the low leakage switch 1 is connected to the signal protection path GRD to ensure that the leakage of the low leakage switch 1 itself is almost zero. At this time, the low leakage switches 2 to 32 are disconnected, and the current is connected through the signal protection path GRD, which will not interfere with the measurement on the drain voltage signal line DF and the drain sensing signal line DS of the test voltage.

[0124] The foregoing description of specific exemplary embodiments of the present invention is for the purpose of illustration and demonstration. These descriptions are not intended to limit the present invention to the precise form disclosed, and it is clear that many changes and variations can be made based on the above teachings. The purpose of selecting and describing the exemplary embodiments is to explain the specific principles of the present invention and its practical application, so that those skilled in the art can realize and utilize various different exemplary embodiments of the present invention and various different selections and changes. The scope of the present invention is intended to be limited by the claims and their equivalents.

Claims

1. An addressable test array for testing a plurality of devices under test, characterized in that: The invention comprises a plurality of addressable low leakage switches capable of controlling opening and closing, each of the low leakage switches comprising: A first MOS transistor, wherein a drain end of the first MOS transistor is connected to a drain end voltage signal line; A second MOS transistor, wherein a drain end of the second MOS transistor is connected to a first signal protection path, and the first signal protection path is configured to be equal to a voltage on a drain end voltage signal line; The well terminal voltages of the first MOS transistor and the second MOS transistor are configured to be equal to the voltage on the first signal protection path, the source terminals of the first MOS transistor and the second MOS transistor are interconnected and used to connect the device under test; each of the low leakage switches is configured as: When a first voltage control signal is loaded on the gate terminal of the first MOS transistor to turn on the first MOS transistor, and a second voltage control signal is loaded on the gate terminal of the second MOS transistor to turn off the second MOS transistor, the low leakage switch is turned on; When a first voltage control signal is loaded on the gate terminal of the first MOS tube to turn off the first MOS tube, and a second voltage control signal is loaded on the gate terminal of the second MOS tube to turn on the second MOS tube, the low leakage switch is turned off.

2. The addressable test array according to claim 1, characterized in that: The first signal protection path replicates the voltage on the drain voltage signal line through a voltage follower buffer; or, The drain voltage signal line and the first signal protection path are respectively connected to pads of equal voltage.

3. The addressable test array according to claim 1, characterized in that: The well end of the first MOS transistor is connected to the drain voltage signal line or the first signal protection path, and the well end of the second MOS transistor is connected to the drain voltage signal line or the first signal protection path.

4. The addressable test array according to claim 3, characterized in that: The well ends of the first MOS transistor and the second MOS transistor are interconnected and connected to the drain voltage signal line or the first signal protection path.

5. The addressable test array according to claim 1, characterized in that: In the extending direction of the drain voltage signal line, the first signal protection path is arranged to surround the peripheral side of the drain voltage signal line.

6. The addressable test array according to claim 1, characterized in that: Each of the low leakage switches further comprises a high impedance voltage measurement loop that can be controlled to open and close, one end of the high impedance voltage measurement loop is connected to the source end of the first MOS tube, and the other end is connected to the drain sensing signal line; The addressable test array further includes a second signal protection path, and the second signal protection path is configured to be equal to the voltage on the drain sensing signal line.

7. The addressable test array according to claim 6, characterized in that: The high-resistance voltage measurement loop includes a third MOS tube, a source end of the third MOS tube is connected to the source end of the first MOS tube, a drain end of the third MOS tube is connected to the drain end sensing signal line, a gate end of the third MOS tube is interconnected with the gate end of the first MOS tube, and a well end of the third MOS tube is connected to the second signal protection path.

8. The addressable test array according to claim 6, characterized in that: The second signal protection path replicates the voltage on the drain sensing signal line through a voltage follower buffer; or, The drain-end sensing signal line and the second signal protection path are respectively connected to pads of equal voltage.

9. The addressable test array according to claim 6, characterized in that: In the extending direction of the drain sensing signal line, the second signal protection path is arranged to surround the peripheral side of the drain sensing signal line.

10. An addressable test array for testing a plurality of devices under test, characterized in that: The invention comprises a plurality of addressable low leakage switches capable of controlling opening and closing, each of the low leakage switches comprising: A first MOS transistor, wherein a drain end of the first MOS transistor is connected to a drain end voltage signal line; A high-resistance voltage measurement loop that can be controlled to open and close, one end of the high-resistance voltage measurement loop is connected to the source end of the first MOS tube, and the other end is connected to the drain sensing signal line; A second MOS tube, wherein a drain end of the second MOS tube is connected to a signal protection path; The signal protection path, the drain sensing signal line, and the drain voltage signal line are configured to have equal voltages, the well terminal voltages of the first MOS transistor and the second MOS transistor are configured to be equal to the voltage on the signal protection path, and the source terminals of the first MOS transistor and the second MOS transistor are interconnected and used to connect the device under test; each of the low leakage switches is configured as: When a first voltage control signal is loaded on the gate terminal of the first MOS transistor to turn on the first MOS transistor, and a second voltage control signal is loaded on the gate terminal of the second MOS transistor to turn off the second MOS transistor, the low leakage switch is turned on; When a first voltage control signal is loaded on the gate terminal of the first MOS tube to turn off the first MOS tube, and a second voltage control signal is loaded on the gate terminal of the second MOS tube to turn on the second MOS tube, the low leakage switch is turned off.

11. An addressable test array for testing a plurality of devices under test, characterized in that: The invention comprises a plurality of addressable low leakage switches capable of controlling opening and closing, each of the low leakage switches comprising: A first MOS transistor, wherein a drain end of the first MOS transistor is connected to a drain end voltage signal line; A high-resistance voltage measurement loop that can be controlled to open and close, one end of the high-resistance voltage measurement loop is connected to the source end of the first MOS tube, and the other end is connected to the drain sensing signal line; A second MOS transistor, wherein the drain end of the second MOS transistor can be controllably connected to the drain end voltage signal line or the drain end sensing signal line; A signal protection path, wherein the signal protection path is configured to be equal to the voltage on the drain voltage signal line and the drain sensing signal line; The well terminal voltages of the first MOS transistor and the second MOS transistor are configured to be equal to the voltage on the signal protection path, the source terminals of the first MOS transistor and the second MOS transistor are interconnected and used to connect the device under test; each of the low leakage switches is configured as: When a first voltage control signal is loaded on the gate terminal of the first MOS transistor to turn on the first MOS transistor, and a second voltage control signal is loaded on the gate terminal of the second MOS transistor to turn off the second MOS transistor, the low leakage switch is turned on; When a first voltage control signal is loaded on the gate terminal of the first MOS tube to turn off the first MOS tube, and a second voltage control signal is loaded on the gate terminal of the second MOS tube to turn on the second MOS tube, the low leakage switch is turned off.

12. The addressable test array according to claim 10 or 11, characterized in that: The high-resistance voltage measurement loop includes a third MOS tube, a source end of the third MOS tube is connected to the source end of the first MOS tube, a drain end of the third MOS tube is connected to the drain sensing signal line, a gate end of the third MOS tube is interconnected with the gate end of the first MOS tube, and a well end of the third MOS tube is connected to the signal protection path.

13. The addressable test array according to claim 10 or 11, characterized in that: The signal protection path replicates the voltage on the drain sensing signal line or the drain voltage signal line through a voltage follower buffer; or, The drain sensing signal line, the drain voltage signal line, and the signal protection path are respectively connected to pads of equal voltage.

14. The addressable test array according to claim 10 or 11, characterized in that: In the extending direction of the drain voltage signal line and the drain sensing signal line, the signal protection path is arranged to surround the peripheral side of the drain voltage signal line and the drain sensing signal line.

15. The addressable test array according to claim 10 or 11, characterized in that: The plurality of low leakage switches, drain voltage signal lines, drain sensing signal lines and signal protection paths constitute an addressable test circuit, and the addressable test array comprises: The addressable test circuit is used to connect to the drain terminals of multiple devices under test; and / or, The addressable test circuit is used to connect to the gate terminals of multiple devices under test; and / or, The addressable test circuit is used to connect to the source terminals of multiple devices under test; and / or, The addressable test circuit is used to be connected to the well terminals of multiple devices under test.

16. The addressable test array according to any one of claims 1 to 11, characterized in that: The addressable test array further comprises a coaxial cable connected between the probe and the instrument panel, and the outside of the coaxial cable replicates the voltage of the lead wire at the current device under test through a voltage follower buffer.

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