Memory fault reporting method, bmc and electronic device

Abstract

A memory fault reporting method, a BMC and an electronic device, the method comprising: receiving correctable error (CE) information, the CE information comprising a physical address of a current CE error; determining a fault type of the current CE error according to the physical address of the current CE error; determining that the current CE error information is not repeated with previously reported CE error information based on the fault type of the current CE error and the physical address of the current CE error; and reporting the current CE error information; wherein the CE error information comprises the fault type of the CE error and the physical address of the CE error. According to the embodiment of the present application, by screening, the reporting of repeated CE error information can be reduced, thereby reducing the risk of system service freezing and downtime caused by SMI interruption triggered by BIOS submitted fault isolation request.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of computers, and in particular to a memory fault reporting method, a BMC and an electronic device. BACKGROUND

[0002] With the rapid development of the computer industry, the memory capacity supported by the processor is getting larger and larger, and the running frequency is getting higher and higher, resulting in more and more memory failures. At present, the prediction and self-recovery method based on memory failure has become the mainstream solution in the industry.

[0003] In this solution, the system identifies each correctable error fault type, generates its corresponding CE error information, and reports each CE error information to the basic input output system (BIOS). However, when the system receives a large number of correctable errors in a short period of time, the system will generate a large number of CE error information of memory failure, and then if a large number of CE error information or fault repair requests for each CE error information are submitted to the BIOS in a short period of time, the system management interruption (SMI) will be triggered continuously, causing system business to be stuck, and even causing the system to be down. SUMMARY

[0004] The embodiments of the present application provide a memory fault reporting method, a BMC and an electronic device, which can reduce the reporting of repeated CE error information, thereby reducing the risk of system business being stuck and down caused by the reporting of repeated CE error information.

[0005] In a first aspect, the embodiments of the present application provide a memory fault reporting method, comprising:

[0006] receiving correctable fault CE information, wherein the CE information includes the physical address of the current CE error;

[0007] determining the fault type of the current CE error according to the physical address of the current CE error;

[0008] determining that the current CE error information is not repeated with the last reported CE error information based on the fault type of the current CE error and the physical address of the current CE error, and reporting the current CE error information; wherein the CE error information includes the fault type of the CE error and the physical address of the CE error.

[0009] The method can be executed or implemented by an electronic device, a processor in the electronic device, or a BMC, or a processor in the BMC.

[0010] The method can reduce the reporting of repeated CE error information, thereby reducing the risk of system service interruption and downtime caused by the SMI interrupt triggered by the BIOS submitted fault isolation request.

[0011] In a possible implementation, the method can further include: determining, based on the fault type of the current CE error and the physical address of the current CE error, that the current CE error information is repeated with the last reported CE error information, and that the interval between the time of the last reported CE error information and the current time is greater than or equal to a first time threshold; and reporting the current CE error information.

[0012] The method can timely report the CE error information while reducing the reporting of repeated CE error information, thereby avoiding failure to repair in time.

[0013] In a possible implementation, the method can further include: determining, based on the fault type of the current CE error and the physical address of the current CE error, that the current CE error information is repeated with the last reported CE error information; and determining, after the interval between the time of the last reported CE error information and the current time is greater than or equal to the first time threshold, that the interval between the time of the last reported CE error information and the current time is greater than or equal to a second time threshold; and reporting the current CE error information.

[0014] The method can avoid reporting the current CE error information when the current CE error information is repeated, by first determining whether the interval between the reporting time of the last reported CE error information and the current time is greater than a first time threshold, and then determining whether the interval is greater than a second time threshold, and reporting the current CE error information only when both determinations are positive. On the one hand, this avoids failure to report repeated CE error information in time. On the other hand, the interval between two adjacent reported CE error information is not less than the second time threshold, thereby avoiding a large amount of CPU resource consumption caused by a large amount of CE error information reported in a short time, and reducing the risk of downtime.

[0015] In a possible implementation, the method can further include: determining, based on the fault type of the current CE error and the physical address of the current CE error, that the current CE error information is repeated with the last reported CE error information; and determining, after the interval between the time of the last reported CE error information and the current time is greater than or equal to the first time threshold, that the interval between the time of the last reported CE error information and the current time is less than the second time threshold; and reporting the current CE error information after waiting for a first duration, wherein the first duration is the difference between the second time threshold and the interval between the reporting time of the last reported CE error information and the current time.

[0016] The method avoids repeated CE error information from being reported in time, and makes the time interval between two adjacent reported CE error information not less than the second time threshold, thereby avoiding a large amount of CPU resource consumption caused by a large amount of CE error information reported in a short time, and reducing the risk of downtime.

[0017] In a possible implementation, the determining that the current CE error information is not repeated with the last reported CE error information based on the fault type of the current CE error and the physical address of the current CE error comprises: determining that the current CE error information is not repeated with the last reported CE error information based on the fault type of the current CE error and the physical address of the current CE error, and a time interval between a time of the last reported CE error information and a current time is greater than or equal to the second time threshold, and reporting the current CE error information.

[0018] The method makes the time interval between two adjacent reported CE error information not less than the second time threshold by judging whether the interval time between the reporting time of the last CE error information and the current time is greater than the second time threshold when the current CE error information is not repeated, and further avoids a large amount of CPU resource consumption caused by a large amount of CE error information reported in a short time, thereby reducing the risk of downtime.

[0019] In a possible implementation, the determining that the current CE error information is not repeated with the last reported CE error information based on the fault type of the current CE error and the physical address of the current CE error comprises: determining that the current CE error information is not repeated with the last reported CE error information based on the fault type of the current CE error and the physical address of the current CE error, and a time interval between a time of the last reported CE error information and a current time is less than the second time threshold, and reporting the current CE error information after waiting for a first time length; the first time length is a difference between the second time threshold and the time interval between the time of the last reported CE error information and the current time.

[0020] The method makes the time interval between two adjacent reported CE error information not less than the second time threshold by judging whether the interval time between the reporting time of the last CE error information and the current time is greater than the second time threshold when the current CE error information is not repeated, and further avoids a large amount of CPU resource consumption caused by a large amount of CE error information reported in a short time, thereby reducing the risk of downtime.

[0021] In a possible implementation, the fault type comprises at least one of a single-bit error, a row error, a column error, a storage array error, a chip grain fault, a DIMM fault, and a channel fault.

[0022] In a possible implementation, determining whether the current CE error information is repeated includes but is not limited to the following implementations:

[0023] When the fault type of the current CE error is a single-bit error, if the physical address of the last reported CE error information is the same as the physical address of the current CE error, and the fault type of the last reported CE error information is a single-bit error, it is determined that the current CE error information is repeated.

[0024] When the fault type of the current CE error is a row error, if the physical address of the last reported CE error information is the same as the physical address of the current CE error, and the fault type of the last reported CE error information is a row error, it is determined that the current CE error information is repeated.

[0025] When the fault type of the current CE error is a column error, if the physical address of the last reported CE error information is the same as the physical address of the current CE error, and the fault type of the last reported CE error information is a column error, it is determined that the current CE error information is repeated.

[0026] When the fault type of the current CE error is a chip grain error, if the physical address of the last reported CE error information is the same as the physical address of the current CE error, and the fault type of the last reported CE error information is a chip grain error, it is determined that the current CE error information is repeated.

[0027] The method for determining whether the CE error information is repeated is accurate and fast.

[0028] In a possible implementation, the specific implementation of determining the fault type of the current CE error according to the physical address of the current CE error can include the following implementations:

[0029] When the number or frequency of faults occurring in the row where the current CE error is located is greater than a first threshold, it is determined that the fault type of the current CE error is a row error.

[0030] When the number or frequency of faults occurring in the column where the current CE error is located is greater than a second threshold, it is determined that the fault type of the current CE error is a column error.

[0031] When the storage unit where the current CE error is located has a fault, and the row where the current CE error is located does not belong to a row error and the column where the current CE error is located does not belong to a column error, it is determined that the fault type of the current CE error is a single-bit error.

[0032] when the current CE error is located in a storage array including multiple row errors or multiple column errors or including at least one row error and including at least one column error, then determining that the fault type of the current CE error is a storage array error;

[0033] when multiple storage arrays in the chip particle in which the current CE error is located all have storage array errors, then determining that the fault type of the current CE error is a chip particle fault.

[0034] The method provides a prediction method of fault types, which is accurate and fast.

[0035] In a second aspect, the embodiments of the present application further provide a baseboard management controller (BMC), comprising a processor, a memory and a communication interface, the communication interface and the memory being coupled with the processor respectively; the memory is configured to store computer instructions; the processor is configured to invoke the computer instructions to perform the following operations:

[0036] receiving correctable fault (CE) information, the CE information comprising a physical address of a current CE error;

[0037] determining a fault type of the current CE error according to the physical address of the current CE error;

[0038] determining that the current CE error information is not repeated with previously reported CE error information based on the fault type of the current CE error and the physical address of the current CE error, and reporting the current CE error information; wherein the CE error information comprises a fault type of a CE error and a physical address of the CE error.

[0039] In some possible implementations, the processor is further configured to perform the steps in any one of the possible implementations of the first aspect, which will not be repeated here.

[0040] In a third aspect, the embodiments of the present application further provide a server, comprising at least one first processor, a memory and a BMC as in the second aspect or any one of the possible implementations of the second aspect, the first processor being coupled with the memory and the BMC; the first processor is configured to send CE information to the BMC when detecting that a CE error occurs in the memory.

[0041] In a fourth aspect, the embodiments of the present application further provide an electronic device, comprising at least one processor and a memory, the processor being coupled with the memory; the processor is configured to detect that a CE error occurs in the memory; the processor is further configured to invoke instructions stored in the memory to perform the method as in the first aspect or any one of the possible implementations of the first aspect. The electronic device can be a server, or a mobile phone, a tablet computer, a notebook computer, a vehicle-mounted device, a smart television or other terminal.

[0042] In a fifth aspect, the embodiments of the present application further provide a computer storage medium, including computer instructions, when the computer instructions are run on a server, causing the server to execute the method described in the first aspect or any possible implementation of the first aspect.

[0043] In a sixth aspect, the embodiments of the present application further provide a computer program product, when the computer program product is run on a server, causing the server to execute the method described in the first aspect or any possible implementation of the first aspect.

[0044] It can be understood that the second aspect, the third aspect, the fourth aspect, the fifth aspect and the sixth aspect all can realize the method provided by the first aspect. Therefore, the beneficial effects achieved by the first aspect can be referred to the corresponding beneficial effects of the first aspect, which will not be repeated here. BRIEF DESCRIPTION OF DRAWINGS

[0045] Figure 1A is a hardware architecture example diagram of an electronic device provided by the embodiments of the present application;

[0046] Figure 1B is a structure example diagram of an electronic device provided by the embodiments of the present application;

[0047] Figure 2 is a structure schematic diagram of a memory provided by the embodiments of the present application;

[0048] Figure 3 is a structure schematic diagram of a BMC provided by the embodiments of the present application;

[0049] Figure 4 is a schematic diagram of a memory fault reporting method provided by the embodiments of the present application;

[0050] Figure 5 is a flowchart of a memory fault reporting method provided by the embodiments of the present application;

[0051] Figure 6 is a flowchart of another memory fault reporting method provided by the embodiments of the present application;

[0052] Figure 7 is an example schematic diagram of applying the method shown in the above Figure 5

[0053] Figure 8 is an example schematic diagram of applying the method shown in the above Figure 6 DETAILED DESCRIPTION ​​

[0054] First, the terms involved in the embodiments of the present application are explained.

[0055] (1) Interrupt and System Management Interruption (SMI).

[0056] Interrupt refers to the process in which the computer device automatically stops the running program and enters the program for processing new situations when some unexpected situations occur during the running of the computer device, and returns to the original suspended program for continuous running after the processing is completed. The interrupt can include but is not limited to SMI interrupt.

[0057] SMI interrupt is a special interrupt used for basic input output system (BIOS) or firmware, which is not directly used for operating system (OS). After triggering the SMI interrupt, the OS enters the system management mode (SMM), at which time the execution flow related to the OS is suspended, and the interrupt service routine (ISR) registered in the BIOS is executed. After the interrupt service processing is completed, the original work is continued at the place where it is suspended.

[0058] (2) Correctable Error (CE) and Uncorrected Error (UCE).

[0059] CE error is an error that occurs in the running of the server, but the error can be corrected through error checking and correction (ECC). Therefore, the CE error is sometimes referred to as ECC error. For example, occasional address command error, single grain multi-bit error of x4 grain memory, and single grain single-bit error of x8 grain memory can all lead to ECC error. When the CE error in the memory column reaches the threshold overflow, the SMI interrupt is triggered.

[0060] UCE error is an error that occurs in the running of the server and the error cannot be corrected through ECC. For example, multi-bit error of x8 grain memory, multi-grain multi-bit error of x4 grain, and continuous address command error can all lead to UCE error.

[0061] As Figure 1AAs shown, it is an example diagram of a hardware architecture of an electronic device provided by an embodiment of the present application. The electronic device can be a server, a gateway device or a network device such as a base station, a router, or a terminal device such as a notebook computer, a desktop computer, a tablet computer, or a mobile phone. The server can be a file server, a domain server, a database server, a mail server, a web server, a multimedia server, a communication server, a terminal server, an infrastructure server, a virtualization server, etc. The server can be tower type, rack type, blade type, etc. The electronic device can be but not limited to X86 architecture, reduced instruction set computer (RISC) architecture, advanced RISC machine (ARM) architecture, etc.

[0062] The electronic device can include but not limited to some or all of one or more central processing units (CPU) 110, one or more memories 120, a platform controller hub (PCH) 130, a BIOS chip 140, a baseboard management controller (BMC) 150, etc.

[0063] The CPU 110 can integrate a memory controller 111. Integrating the memory controller 111 into the CPU 110 can effectively control the memory controller to work at the same frequency as the CPU 110 core, and can effectively reduce the transmission delay because the data exchange between the memory and the CPU 110 does not need to pass through the north bridge.

[0064] The memory controller 111 is an important component of the electronic device that controls the memory 120 and is responsible for data exchange between the memory 120 and the CPU. The memory controller 111 is also used to identify the storage unit in which the CE error occurs in the memory, and sends the indication information, such as CE information, indicating that the storage unit has a CE error to the BMC 140 through the BIOS. The CE information includes the physical address of the CE error, such as the physical location of the storage unit in which the CE error occurs in the memory.

[0065] In another computer system architecture, the memory controller 111 can not be integrated in the CPU 110, but located in a north bridge chip. In this case, the communication between the CPU 110 and the memory needs to be transmitted through the north bridge chip.

[0066] In some embodiments, the electronic device can further include other processing units, such as an application processor (AP), a graphics processing unit (GPU), a neural-network processing unit (NPU), a modem processor, an image signal processor (ISP), a memory, a video codec, a digital signal processor (DSP), a baseband processor, and the like. Different processing units can be independent devices or integrated into one or more processors.

[0067] The memory in the CPU 110 can also be configured to store instructions and data. In some embodiments, the memory in the CPU 110 is a cache memory. The memory can store instructions or data that have just been used or are frequently used by the CPU 110. If the CPU 110 needs to use the instructions or data again, it can directly call them from the memory. This avoids repeated access and reduces the waiting time of the CPU 110, thereby improving the data processing efficiency of the electronic device.

[0068] The memory 120 can be a dynamic random access memory (DRAM), a synchronous dynamic random access memory (SDRAM), a double data rate synchronous dynamic random access memory (DDR SDRAM), or the like. The memory 120 can include one or more dual inline memory modules (DIMMs). It should be understood that, in some embodiments, the memory 120 can include one or more single inline memory modules (SIMMs).

[0069] The platform controller hub (PCH) 130, the BIOS chip 140, the baseboard management controller (BMC) 150, and the like can be a chipset on the mainboard of the electronic device. Among them, the CPU 110 and the PCH 130 can be connected through a DMI bus, the PCH 130 and the BIOS chip 140 can be connected through an SPI bus, and the PCH 130 and the BMC 150 can be connected through PCIe, LPC, USB, and the like.

[0070] The PCH 130 is a south bridge chip, mainly responsible for the input and output functions of the electronic device, and mainly responsible for low-speed input / output. The BIOS chip 140 and the BMC 150 need to communicate with the CPU 110 through the PCH 130.

[0071] The BIOS chip 140 is used to store a BIOS program, which is the first software to run after the server is started, including a basic input / output control program, a power-on self-test program, a system startup bootstrap program, system setting information, and the like to set hardware such as a hard disk drive, a memory, and the like for OS running. After the CPU 110 runs the BIOS program stored in the BIOS chip 140, the CPU 110 and the BMC 150 can realize the transmission of CE information and CE error information through a functional unit (also referred to as BIOS in the embodiment of the application) running the BIOS program.

[0072] The BMC 150 is mainly used for monitoring and managing the electronic device, is a small operating system independent of the electronic device, and is a chip integrated on the mainboard. In the embodiment of the application, the BMC 150 can identify the fault type of the CE error according to the CE information of the memory reported by the BIOS, obtain the corresponding CE error information (including the fault type of the CE error and the physical address of the CE error), and filter the CE error information. Report the filtered CE error information, and then the BMC 150 submits a fault isolation request to the BIOS based on the reported CE error information to repair the fault of the memory. By filtering the CE error information, repeated reporting or a large number of reports in a short period of time are avoided, and then the downtime of the electronic device is avoided. The structure of the BMC 150 can be referred to in the following Figure 3 , and the specific implementation of the BMC 150 filtering the CE error information can be referred to in the following embodiment of the memory fault reporting method, which will not be described here.

[0073] Not limited to Figure 1AThe chip set shown can also be a chip set of other structure, for example, the chip set can include a South Bridge chip, a North Bridge chip, and the like, and the North Bridge chip mainly provides support for the CPU 110, the memory 120, and the like. The South Bridge chip mainly provides support for the keyboard, the interface, and the like. The BMC 150 can communicate with the CPU 110 through the South Bridge chip and the North Bridge chip.

[0074] It should also be understood that the application is not limited to Figure 1A The electronic device referred to can further include more or fewer units,

[0075] It can be understood that the structure shown in the embodiments of the application does not constitute a specific limitation on the electronic device. In other embodiments of the application, the electronic device can include more or fewer components than shown, or combine certain components, or split certain components, or different component arrangements. The components shown can be implemented in hardware, software, or a combination of software and hardware.

[0076] As Figure 1B As shown, an electronic device provided by the embodiments of the application can include one or more central processing units (CPUs) 210, one or more memories 220, and the like. The CPU 210 is coupled to the memory 220. The electronic device 200 can be a server, a mobile phone, a tablet computer, a personal computer, a smart television, a vehicle-mounted device, or the like, and can also be a base station, a router, or the like, without limitation.

[0077] The CPU 210 can integrate a memory controller 211. Integrating the memory controller 211 into the CPU 210 can effectively control the memory controller to work at the same frequency as the CPU 210 core, and can effectively reduce transmission delay because data exchange between the memory and the CPU 210 does not need to pass through the North Bridge.

[0078] The memory controller 211 is an important component of the electronic device that controls the memory 120 and is responsible for data exchange between the memory 220 and the CPU. The memory controller 211 is also used to identify the storage unit in which the CE error occurs in the memory, and sends the indication information, such as CE information, indicating that the storage unit has a CE error to the operating system (OS) through the BIOS or to the application layer. The CE information includes the physical address of the CE error, such as the physical location of the storage unit in which the CE error occurs in the memory.

[0079] In some embodiments, the memory controller 211 can be integrated in the CPU 210. In other embodiments, the memory controller 211 can not be integrated in the CPU 210, but located in a north bridge chip. In this case, the communication between the CPU 210 and the memory needs to be transmitted through the north bridge chip.

[0080] In some embodiments, the electronic device can further include other processing units, such as an application processor (AP), a graphics processing unit (GPU), a neural-network processing unit (NPU), a modem processor, an image signal processor (ISP), a memory, a video codec, a digital signal processor (DSP), a baseband processor, and the like. Different processing units can be independent devices or integrated in one or more processors.

[0081] The CPU 210 can further be provided with a memory for storing instructions and data. In some embodiments, the memory in the CPU 210 is a cache memory. The memory can store instructions or data that have just been used or are frequently used by the CPU 210. If the CPU 210 needs to use the instructions or data again, the CPU 210 can directly call the instructions or data from the memory. This avoids repeated access and reduces the waiting time of the CPU 210, thereby improving the data processing efficiency of the electronic device.

[0082] The memory 220 can be a dynamic random access memory (DRAM), a synchronous dynamic random access memory (SDRAM), a double data rate synchronous dynamic random access memory (DDR SDRAM), or the like. The memory 220 can include one or more dual inline memory modules (DIMMs). It should be understood that, in some embodiments, the memory 220 can include one or more single inline memory modules (SIMMs).

[0083] In some embodiments, the electronic device 200 can further include a PCH, or a north bridge chip, a south bridge chip, a BIOS chip storing a BIOS program, and the like.

[0084] Among them, BIOS is the BIOS program, which runs in the functional unit of the CPU core. The memory controller 211 can transmit CE information and CE error information with the OS or application layer through BIOS.

[0085] The operating system or application layer may include a fault handling system. In this embodiment, the fault handling system in the operating system or application layer can identify the fault type of the CE error based on the memory CE information reported by the BIOS, obtain its corresponding CE error information, filter the CE error information, and report the filtered CE error information. Then, the operating system or application layer can submit a fault isolation request to the BIOS based on the reported CE error information to repair the memory fault. By filtering the CE error information, duplicate reporting or a large number of reports in a short period of time can be avoided, thereby preventing the electronic device from crashing.

[0086] like Figure 2 The diagram illustrates an example of a memory structure. Figure 2 The memory diagram illustrates the encoding method of the physical address of the storage unit. Figure 2 Taking a channel that can accommodate two DIMMs (DIMM0 and DIMM1) as an example, each DIMM consists of two memory columns (rank0 and rank1), each rank consists of 8 memory chips, and each memory chip consists of 8 memory arrays. Each memory array includes multiple memory cells arranged in an array, and the physical location of a memory cell in the memory array is determined by its row number and column number.

[0087] Therefore, the physical address included in the CE information may include, but is not limited to, one or more of the following: the channel number, DIMM slot number, rank number, chip number, bank number, row number, and column number of the memory cell where the CE error occurred. Optionally, when there are multiple CPUs, the physical address may also include the CPU node number where the CE error occurred.

[0088] The addressing method for physical addresses that cause CE errors is not limited to the one mentioned above; other addressing methods may also be included, which will not be elaborated here.

[0089] like Figure 3 The diagram shown is a structural schematic of a BMC 150 provided in an embodiment of this application. The BMC 150 may include a processor 1501 and a memory 1502. The processor 1501 is coupled to the memory 1502.

[0090] The memory 1502 is configured to store computer instructions, such as inference programs, screening programs, and self-recovery decision programs, in addition to storing the OS of the BMC 150. The processor 1501 executes the computer instructions stored in the memory 1502, and can implement the steps performed by the BMC in the embodiments of the memory fault reporting method described below. Details are not described herein.

[0091] It should be understood that the BMC 150 can use an embedded system, such as a Linux system. The BMC can adopt a layered architecture, which can include, but is not limited to, an application layer, a system layer, a driver layer, and a hardware layer.

[0092] The application layer thereof can include, but is not limited to, a memory fault prediction and self-recovery management system, which can include an AI module and a self-recovery decision module. The AI module can include an inference unit and a screening unit.

[0093] The inference unit is configured to identify the fault type of the CE error after receiving the CE information, and then obtain the CE error information corresponding to the CE information, respectively. One CE information corresponds to one CE error information, and the CE error information corresponding to one CE information can include the fault type of the CE error and the physical address carried by the CE information.

[0094] The screening unit is configured to screen each CE error information to determine whether to report the CE error information to the self-recovery decision module.

[0095] The self-recovery decision module is configured to submit a fault isolation request to the BIOS based on the received CE error information to repair the memory fault.

[0096] The specific implementation of each unit can also refer to the related description in the method embodiments described below Figure 5 or Figure 6 Details are not described herein.

[0097] The following describes a memory fault reporting method with reference to the schematic diagram of the memory fault reporting method shown in Figure 4 and the flowchart shown in Figure 5 , Figure 6 The method can be implemented by the electronic device shown in Figure 1A and the electronic device 200 shown in Figure 1B .

[0098] For example, the electronic device shown in Figure 1A may be implemented. As shown in Figure 5 , the method can include, but is not limited to, some or all of the following steps:

[0099] S01: When detecting a CE error of the memory, the memory controller invokes the BIOS to obtain CE information.

[0100] The CE error is a correctable error. The CE information includes a physical address of a storage unit where the CE error occurs, and the physical address is used to determine a physical position of the CE error in the memory, i.e., a physical position of the storage unit where the CE error occurs in the memory. It should be noted that one CE error corresponds to one CE information.

[0101] It should be noted that, in addition to the physical address of the storage unit where the CE error occurs, the CE information can also include other information required for other fault type prediction, for example, the time when the CE error occurs.

[0102] S02: The BIOS sends the CE information to an inference unit in the BMC.

[0103] The BIOS is an input / output control unit, the memory controller cannot directly communicate with the BMC, and needs to pass through the BIOS. In addition, the BMC cannot actively communicate with the BIOS. The BIOS is a functional unit running a BIOS program in the processor, and the communication between the BIOS and the BMC mainly uses IPM. The BIOS sends the CE information to the screening unit in the BMC through IPMI.

[0104] It can be understood that, when detecting a CE error of the memory, the CPU can not send the CE information to the BMC through the BIOS, such as directly sending the CE information to the BMC.

[0105] S03: The inference unit in the BMC determines a fault type to which the current CE error belongs based on the physical address of the current CE error.

[0106] The fault type can include at least one of the following types:

[0107] (1) Single bit error, i.e., one or more CE errors occur in the same storage unit.

[0108] (2) Row error, i.e., the CE errors are arranged by rows, and the CE errors occur in multiple column storage units in the same row.

[0109] (3) Column error, i.e., the CE errors are arranged by columns, and the CE errors occur in multiple row storage units in the same column.

[0110] (4) a bank error, i.e., a composite mode of at least two fault types of row errors, column errors and single bit errors, such as, at least multiple rows or at least multiple columns of memory cells in the same memory bank have CE errors, or at least one row or one column of memory cells in the same memory bank has CE errors and memory cells in other rows or columns contain at least one single bit error. Wherein, a row has CE errors means that at least N memory cells in the row send CE. N can be a positive integer not less than 2, and N is not greater than the total number of columns of the memory bank.

[0111] (5) a chip particle fault, i.e., multiple memory banks in the same chip particle have hard errors.

[0112] (6) a DIMM fault, i.e., multiple memory banks in multiple chip particles in the same DIMM have hard errors, and are not concentrated in fixed rows and columns.

[0113] (7) a channel fault, i.e., multiple chip particles in multiple DIMMs in the same channel have a large number of errors, but are concentrated in fixed rows and / or columns. Wherein, "a large number" can refer to the number of CE errors, row errors or column errors being greater than a threshold (such as 100).

[0114] It should be understood that memory errors can also be divided into soft faults and hard faults. Wherein, soft errors are mainly accidental errors caused by external factors, for example, bit flips caused by cosmic rays; hard errors are mainly repeatable errors caused by internal factors, for example, caused by memory medium defects, solder joint aging, device aging, etc. Wherein, hard errors can cause memory faults, and can produce uncorrectable errors. Most of the repeatable memory errors are hard errors caused by memory hard faults, and such errors are the result of the joint action of memory defects and operating environment. Row errors, column errors or their composite distribution usually belong to hard errors, or are hard errors.

[0115] In an implementation manner, the method of the inference unit in the BMC for determining the fault type to which the current CE error belongs based on the physical address of the current CE error can be: the BMC can predict the fault type of the current CE fault based on historical CE information (i.e., historical received CE information). The principle can be: by analyzing the spatial distribution or spatio-temporal distribution of CE faults through historical received CE information, and then determining the fault type to which the current CE error belongs based on the physical address of the current CE error. Wherein, the historical received CE information includes the CE information of the current CE error.

[0116] In a specific implementation, the fault analysis model can be used to intelligently analyze the faults of the memory, i.e., the BMC can input the historical CE information into the fault analysis model to obtain the fault type of the current CE error.

[0117] For example, the fault analysis model is based on historical CE information to count the number or frequency of faults occurring in each row, each column, each memory cell, etc. in a historical time period. When the number or frequency of faults occurring in the row where the current CE error is located is greater than a first threshold, the fault type is determined to be a row error. When the number or frequency of faults occurring in the column where the current CE error is located is greater than a second threshold, the fault type is determined to be a column error. When the memory cell where the current CE error is located has a fault and the row where the current CE error is located does not belong to a row error and the column where the current CE error is located does not belong to a column error, the fault type is determined to be a single-bit error. If the memory array where the current CE error is located includes multiple rows of row errors or multiple columns of column errors, or includes at least one row of row errors and includes at least one column of column errors, the fault type is determined to be a memory array error. If multiple memory arrays in the chip grain where the current CE error is located all have a memory array error, the fault type is determined to be a chip grain fault. Similarly, other fault types can also be analyzed.

[0118] The prediction method of the fault types listed above is not limited, and other prediction methods of fault types can also be included, which are not limited here.

[0119] S04: The screening unit in the BMC determines whether the current CE error information is repeated with the last reported CE error information based on the fault type of the current CE error and the physical address of the current CE error. If yes, S05 is performed, otherwise S06 is performed.

[0120] The CE error information includes the fault type of the CE error and the physical address of the CE error. To avoid repeated reporting, the fault type of the current CE error and the physical address of the current CE error can be determined before reporting whether they are repeated with the fault type and the physical address of the last reported error. The method is as follows:

[0121] When the fault type of the current CE error is a single-bit error, it can be determined whether the physical address contained in the last reported CE error information is the same as the physical address of the current CE error and the fault type is a single-bit error. If yes, the current CE error information is repeated, otherwise it is not repeated. The last reported CE error information is the CE error information obtained according to the historical CE fault prediction. The same physical address means that the channel number, DIMM slot number, rank number, chip grain number, bank number, row number, and column number are all the same.

[0122] When the fault type of the current CE error is row error, it can be judged whether the physical address contained in the last reported CE error information and the physical address of the current CE error are the same row and the fault type is row error, if yes, the current CE error information is repeated, otherwise, it is not repeated. Wherein, the same row means that the channel number, DIMM slot number, rank number, chip particle number, bank number and row number are all the same, but the column number can be the same or different.

[0123] When the fault type of the current CE error is column error, it can be judged whether the physical address contained in the last reported CE error information and the physical address of the current CE error are the same column and the fault type is column error, if yes, the current CE error information is repeated, otherwise, it is not repeated. Wherein, the same column means that the channel number, DIMM slot number, rank number, chip particle number, bank number and column number are all the same, but the row number can be the same or different.

[0124] When the fault type of the current CE error is storage array error, it can be judged whether the physical address contained in the last reported CE error information and the physical address of the current CE error are the same storage array and the fault type is the CE error information of storage array error, if yes, the CE error information is repeated, otherwise, it is not repeated. Wherein, the same storage array means that the channel number, DIMM slot number, rank number, chip particle number and bank number are all the same, but the column number and row number can be the same or different.

[0125] When the fault type of the current CE error is chip particle fault, it can be judged whether the physical address contained in the last reported CE error information and the physical address of the current CE error are the same chip particle and the fault type is chip particle fault, if yes, the current CE error information is repeated, otherwise, it is not repeated. Wherein, the same chip particle means that the channel number, DIMM slot number, rank number and chip particle number are all the same, but the bank number, column number and row number can be the same or different.

[0126] When the fault type of the current CE error is DIMM fault, it can be judged whether the physical address contained in the last reported CE error information and the physical address of the current CE error are the same DIMM and the fault type is DIMM fault, if yes, the current CE error information is repeated, otherwise, it is not repeated. Wherein, the same DIMM means that the channel number and DIMM slot number are all the same, but the rank number, chip particle number, bank number, column number and row number can be the same or different.

[0127] When the current CE error type is channel fault, it can be determined whether the physical address contained in the previously reported CE error message is the same as the physical address of the current CE error and whether the fault type is channel fault. If so, the current CE error message is a duplicate; otherwise, it is not. Here, "same channel" means the channel number is the same, but the DIMM slot number, rank number, chip number, bank number, column number, and row number can be the same or different.

[0128] S05: The filtering unit in the BMC determines whether the interval t1 between the time of the last reported CE error message and the current time is greater than the time threshold T1. If so, execute S06; otherwise, do not report the CE error message.

[0129] The previously reported CE error message is a duplicate of the current CE error message, with both having the same error type and physical address. The current time can be the time the current CE fault occurred, the time the BMC received the CE information, or the time the current CE error message was generated. The time threshold T1 can be 5s, 10s, 12s, or other durations.

[0130] S06: The BMC reports the current CE error information.

[0131] Reporting CE error information means inputting the error information into the self-healing decision module or proceeding to the next step to submit a fault isolation request to the BIOS based on the error information in order to repair the memory fault.

[0132] In some embodiments, if it is determined in step S04 that the current CE error message is repeated, the error message may not be reported and step S05 may not be executed.

[0133] It is evident that by filtering, the reporting of duplicate error messages can be reduced, thereby reducing the number of fault isolation requests submitted by the BIOS that trigger SMI interrupts, thus reducing the risk of system service lag and downtime caused by SMI interrupts.

[0134] like Figure 6 The diagram shown is a flowchart illustrating another memory fault reporting method provided in an embodiment of this application. In this embodiment, following steps S04 and S05, if the judgment result of S04 is negative, step S07 is executed; if the judgment result of step S05 is positive, step S07 is executed.

[0135] S07: The filtering unit in the BMC determines whether the time interval t2 between the last reported CE error information and the current time is greater than the time threshold T2. If yes, then execute S06; otherwise, execute S08.

[0136] The last reported CE error information is the error information reported last time. The time threshold T2 can be 50 ms, 100 ms, 500 ms, 1 s, 5 s, or other time lengths.

[0137] S08: The screening unit in the BMC waits for t3, where t3 is the difference between T2 and t2.

[0138] After S08, the BMC can perform S06, i.e., the BMC reports the CE error information.

[0139] In some embodiments, after step S06, the method can further include:

[0140] S09: The BMC can also send a fault isolation request to the BIOS according to the current CE error information to repair the memory.

[0141] When a large number of different fault types are continuously reported to the self-recovery decision module within a predetermined time, the fault isolation request submitted by the self-recovery decision module to the BIOS will also continuously trigger SMI interrupts, so that the self-recovery will cause a large CPU resource overhead, thereby causing the system business to be stuck.

[0142] In the above embodiments, by judging whether the interval time t2 between the time of the last reported CE error information and the current time is greater than the time threshold T2, the time interval between two adjacent reported error information is not less than T2, and thus the reporting of a large number of CE error information in a short time is avoided, thereby reducing the risk of downtime.

[0143] In some embodiments, the time threshold T1 or T2 can be dynamically changed, which can be adjusted based on at least one of the load of the CPU, the temperature of the CPU, the load of the memory, the density of the CE, etc. For example, when the load or temperature of the CPU increases, or the load of the memory increases, T1 or T2 can be increased to reduce the CPU resources occupied by self-recovery; conversely, when the load or temperature of the CPU decreases, or the load of the memory decreases, T1 or T2 can be decreased to utilize the idle time of the CPU to quickly repair the memory. For another example, when the density of the CE increases, T1 can be decreased or T2 can be increased to quickly repair the memory; conversely, when the density of the CE decreases, T1 can be increased or T2 can be decreased to avoid a large amount of CPU resource occupation in a short time and reduce the risk of downtime.

[0144] In other embodiments, the method shown in the above Figure 5 or Figure 6 The method shown in the above Figure 1BThe electronic device shown is used to implement this, where the aforementioned BMC can be replaced by a fault handling system in the OS or application layer. In this case, the fault handling system in the OS or application layer includes an AI module and a self-healing decision module, wherein the AI ​​module includes an inference unit and a filtering unit.

[0145] The following describes the application of the above. Figure 5 and Figure 6 An example of the method shown.

[0146] like Figure 7 As shown, the occurrence time and fault type of multiple CE errors are listed. It is assumed that after the AI ​​module infers the 3rd, 4th, 5th and 6th CE errors, four fault types are obtained. The first three are row faults, and their physical addresses are all in the same row (assuming the row number is 200). The interval between these row faults is no more than 1 minute. The fourth is a column fault.

[0147] If no filtering is performed, the CE error messages of these 3 row errors and 1 column error will be directly reported to the self-healing decision module.

[0148] If the above is applied Figure 4 The memory fault reporting method shown involves filtering CE error messages. If the time threshold T1 is 5 minutes, the CE error messages for the second and third row errors will not be reported because the interval between them is less than T1. The time interval between the fourth column error and the last reported CE error message is t2 (t2 = 1 minute). Assuming the time threshold T2 is 2 minutes, the CE error message for the fourth column error needs to wait for a period of time (1 minute) before being reported to the self-healing decision module.

[0149] like Figure 8 As shown, the occurrence time and fault type of multiple CE errors are listed. It is assumed that after the AI ​​module inferences, the 3rd, 4th and 5th CEs result in 3 fault types, namely row error, single bit error and column error, and the interval between these fault type CE error messages does not exceed 1 minute.

[0150] If the CE error messages are not filtered, these three CE error messages will be directly reported to the self-healing decision module.

[0151] If the above is applied Figure 4 The method for reporting memory faults, as shown, filters CE error messages. Since there are no duplicate CE error messages, the process can proceed. Figure 4In step S07 of the illustrated memory fault reporting method, it is determined whether the interval time t2 between the reporting time of the previous CE error information and the current time is greater than the time threshold T2. Assuming that the time threshold T2 is 2 minutes, then the CE error information of the second CE error (the fault type is single-bit error) needs to wait for a period of time (1 minute) before being reported. Similarly, the CE error information of the third CE error (the fault type is column error) also needs to wait for a period of time (67 seconds) before being reported because the interval time between the reporting time of the previous CE error information (the second CE error information) and the current time is also less than T2.

[0152] The terminology used in the above-described embodiments is for the purpose of describing particular embodiments only and is not intended to be limiting of the present application. As used in this specification and the appended claims, the singular forms "a," "an" and "the" are intended to include both singular and plural forms, unless the context clearly indicates otherwise. It will be further understood that the terms "and / or," as used in the specification and in the claims, is used to mean "one or the other or both" unless otherwise indicated.

[0153] As used in the above description of embodiments, the term "when" can be interpreted to mean "if" or "upon" or "in response to determining" or "in response to detecting," depending on the context. Similarly, the phrase "in response to determining" or "if it is detected that (a stated condition or event)" can be interpreted to mean "if determining" or "in response to determining" or "upon detecting (a stated condition or event)" or "in response to detecting (a stated condition or event)," depending on the context.

[0154] In the above embodiments, all or part of the embodiments can be implemented by software, hardware, firmware or any combination thereof. When implemented by software, all or part of the embodiments can be implemented in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of the present application are generated. The computer can be a general purpose computer, a special purpose computer, a computer network, or other programmable apparatus. The computer instructions can be stored in a computer readable storage medium or transmitted from one computer readable storage medium to another computer readable storage medium, for example, the computer instructions can be transmitted from one website, computer, server or data center to another website, computer, server or data center through wired (such as coaxial cable, optical fiber, digital subscriber line) or wireless (such as infrared, wireless, microwave, etc.) manner. The computer readable storage medium can be any available medium that can be accessed by a computer or a data storage device such as a server, data center, etc. integrated with one or more available media. The available media can be a magnetic medium (for example, a floppy disk, a hard disk, a magnetic tape), an optical medium (for example, a DVD), or a semiconductor medium (for example, a solid state disk) and the like.

[0155] Those of ordinary skill in the art understand that all or part of the processes in the above embodiments can be implemented by a computer program to instruct the relevant hardware, which can be stored in a computer readable storage medium. The program can include the processes of the above method embodiments when executed. The aforementioned storage medium includes ROM or random access memory (RAM), magnetic disk or optical disk, and various media that can store program codes.

Claims

1. A method for reporting memory faults, characterized in that, include: Receive CE information that can correct faults, the CE information including the physical address of the current CE error; Determine the fault type of the current CE error based on the physical address of the current CE error; Based on the fault type and physical address of the current CE error, it is determined that the current CE error information is not the same as the previously reported CE error information, and the current CE error information is reported; wherein, the CE error information includes the fault type and physical address of the CE error.

2. The method according to claim 1, characterized in that, The method further includes: Based on the fault type and physical address of the current CE error, if the current CE error information is found to be the same as the previously reported CE error information, and the time interval between the time of the previous CE error information report and the current time is greater than or equal to a first time threshold, the current CE error information is reported.

3. The method according to claim 2, characterized in that, The method further includes: Based on the fault type and physical address of the current CE error, it is determined that the current CE error information is duplicated with the previously reported CE error information; and after the interval between the time of the previous CE error information report and the current time is greater than or equal to a first time threshold, it is determined that the interval between the time of the previous CE error information report and the current time is greater than or equal to a second time threshold, and the current CE error information is reported.

4. The method according to claim 2, characterized in that, The method further includes: Based on the fault type and physical address of the current CE error, it is determined that the current CE error information is duplicated with the previously reported CE error information; and after the interval between the time of the previous CE error information report and the current time is greater than or equal to a first time threshold, it is determined that the interval between the time of the previous CE error information report and the current time is less than a second time threshold, and the current CE error information is reported after waiting for a first duration; wherein, the first duration is the difference between the second time threshold and the time interval between the previous reporting time and the current time.

5. The method according to any one of claims 1-4, characterized in that, Based on the fault type and physical address of the current CE error, it is determined that the current CE error information is not a duplicate of the previously reported CE error information, including: Based on the fault type and physical address of the current CE error, if the current CE error information is determined to be different from the previously reported CE error information, and the time interval between the time of the previous CE error information report and the current time is greater than or equal to the second time threshold, the current CE error information is reported.

6. The method according to any one of claims 1-4, characterized in that, Based on the fault type and physical address of the current CE error, it is determined that the current CE error information is not a duplicate of the previously reported CE error information, including: Based on the fault type and physical address of the current CE error, it is determined that the current CE error information is not the same as the previously reported CE error information, and the time interval between the time of the last reported CE error information and the current time is less than a second time threshold. After waiting for a first duration, the current CE error information is reported. The first duration is the difference between the second time threshold and the time interval between the last reported time and the current time.

7. A baseboard management controller (BMC), characterized in that, include: A processor, a memory, and the memory being coupled to the processor; the memory is used to store computer instructions; the processor is used to invoke and execute the computer instructions. Receive CE information that can correct faults, the CE information including the physical address of the current CE error; Determine the fault type of the current CE error based on the physical address of the current CE error; Based on the fault type and physical address of the current CE error, it is determined that the current CE error information is not the same as the previously reported CE error information, and the current CE error information is reported; wherein, the CE error information includes the fault type and physical address of the CE error.

8. The BMC according to claim 7, characterized in that, The processor is also used to perform: Based on the fault type and physical address of the current CE error, it is determined that the current CE error information is the same as the previously reported CE error information; and the time interval between the time of the previous CE error information report and the current time is greater than or equal to a first time threshold, the current CE error information is reported.

9. The BMC according to claim 8, characterized in that, The processor is also used to perform: Based on the fault type and physical address of the current CE error, it is determined that the current CE error information is duplicated with the previously reported CE error information; and after the interval between the time of the previous CE error information report and the current time is greater than or equal to a first time threshold, it is determined that the interval between the time of the previous CE error information report and the current time is greater than or equal to a second time threshold, and the current CE error information is reported.

10. The BMC according to claim 9, characterized in that, The processor is also used to perform: Based on the fault type and physical address of the current CE error, it is determined that the current CE error information is duplicated with the previously reported CE error information; and after the interval between the time of the previous CE error information report and the current time is greater than or equal to a first time threshold, it is determined that the interval between the time of the previous CE error information report and the current time is less than a second time threshold, and the current CE error information is reported after waiting for a first duration; wherein, the first duration is the difference between the second time threshold and the time interval between the previous reporting time and the current time.

11. The BMC according to any one of claims 7-9, characterized in that, The processor is further configured to perform: determining that the current CE error information is not a duplicate of the previously reported CE error information based on the fault type of the current CE error and the physical address of the current CE error, including performing: Based on the fault type and physical address of the current CE error, if the current CE error information is determined to be different from the previously reported CE error information, and the time interval between the time of the previous CE error information report and the current time is greater than or equal to the second time threshold, the current CE error information is reported.

12. The BMC according to any one of claims 7-10, characterized in that, The processor is further configured to perform: determining that the current CE error information is not a duplicate of the previously reported CE error information based on the fault type of the current CE error and the physical address of the current CE error, including performing: Based on the fault type and physical address of the current CE error, it is determined that the current CE error information is not the same as the previously reported CE error information, and the time interval between the time of the last reported CE error information and the current time is less than a second time threshold. After waiting for a first duration, the current CE error information is reported. The first duration is the difference between the second time threshold and the time interval between the last reported time and the current time.

13. An electronic device, characterized in that, It includes at least one first processor, memory, and a BMC as described in any one of claims 7-12, wherein the first processor is coupled to the memory and the BMC; the first processor is configured to send CE information to the BMC when a CE error is detected in the memory.

14. An electronic device, characterized in that, It includes at least one processor and memory, the processor being coupled to the memory; the processor is used to detect a CE error occurring in the memory; the processor is also used to perform the reporting method as described in any one of claims 1-6.

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