Semiconductor Device and Preparation Method

Abstract

The present application discloses a semiconductor device and a manufacturing method thereof, which can reduce the probability of the existence of gate leakage current, thereby reducing the probability of electrical damage to the semiconductor device. A manufacturing method of a semiconductor device provided by the present application includes the following steps: providing a substrate, including an insulating region and a plurality of active regions, and each active region is separated by the insulating region; forming a trench in the substrate, and the trench is used to form a buried gate; in the trench, in a direction perpendicular to the upper surface of the substrate and upward, a first filling layer and a second filling layer are sequentially filled, and the upper surface of the second filling layer is higher than the upper surface of the substrate; performing a recess treatment on the second filling layer to make the upper surface of the second filling layer lower than the upper surface of the substrate; performing a reduction treatment on the sidewall surface of the trench and the upper surface of the second filling layer to repair the sidewall surface of the trench and the upper surface of the second filling layer; forming a third filling layer above the second filling layer, and the third filling layer fills the trench.

Description

Technical Field

[0001] This application relates to the field of semiconductor devices, and particularly to semiconductor devices and manufacturing methods thereof. Background Art

[0002] In the process of manufacturing semiconductor devices, an embedded gate structure is often used. The embedded gate structure is located inside the substrate and formed in the active region of the substrate. In the process of manufacturing the embedded gate structure, trenches need to be formed on the surface of the substrate, conductive metal is formed in the trenches, and a gate capping covering the conductive metal is formed above the conductive metal.

[0003] It has been found that the embedded gate is prone to gate leakage current, which causes electrical damage to the semiconductor device. Therefore, how to reduce the probability of the existence of gate leakage current, thereby reducing the probability of electrical damage to the semiconductor device, is an urgent problem to be solved in this field. Summary of the Invention

[0004] In view of this, this application provides a semiconductor device and a manufacturing method thereof, which can reduce the probability of the existence of gate leakage current, thereby reducing the probability of electrical damage to the semiconductor device.

[0005] A manufacturing method of a semiconductor device provided by this application includes the following steps: providing a substrate, including an insulating region and a plurality of active regions, each of the active regions being separated by the insulating region; forming trenches in the substrate, the trenches being distributed in both the insulating region and the active region inside the substrate for forming an embedded gate; in the trenches, in a direction perpendicular to the upper surface of the substrate and upward, filling a first filling layer and a second filling layer in sequence, the upper surface of the second filling layer being higher than the upper surface of the substrate; performing a recessing process on the second filling layer to make the upper surface of the second filling layer lower than the upper surface of the substrate; performing a reduction process on the sidewall surface of the trench and the upper surface of the second filling layer to repair the sidewall surface of the trench and the upper surface of the second filling layer; forming a third filling layer above the second filling layer, the third filling layer filling the trench.

[0006] Optionally, the reduction process includes repairing the materials of the sidewall surface of the trench and the upper surface of the second filling layer to the materials before the recessing process.

[0007] Optionally, the first filling layer includes a dielectric layer, a metal nitride layer, and a metal material layer formed in sequence along the inner wall of the trench, and an etch-back process is performed on the metal nitride layer and the metal material layer to make the top surfaces of the metal nitride layer and the metal material layer lower than the upper surface of the substrate.

[0008] Optionally, at least a part of the second filling layer located above the upper surface of the substrate is removed by at least one of a dry etching process or a wet etching process, and at least a second filling layer with a first thickness is retained in the trench.

[0009] Optionally, the material for preparing the second filling layer includes a semiconductor material.

[0010] Optionally, the second filling layer and the dielectric layer in the first filling layer are made of the same material.

[0011] Optionally, before forming a third filling layer above the second filling layer, the following steps are further included: forming an oxide layer on the upper surface of the second filling layer after reduction treatment, and the oxide layer is used to separate the second filling layer and the subsequent formed third filling layer.

[0012] Optionally, the back-etching process can form vacancies on the sidewall surface of the trench.

[0013] Optionally, the reduction treatment of the sidewall surface of the trench includes the following steps: providing a reduction gas into the trench, and repairing the sidewall surface of the trench and the upper surface of the second filling layer through the reduction gas.

[0014] Optionally, the reduction gas includes hydrogen and oxygen, and the gas volume ratio of hydrogen to oxygen is 0.95:0.05.

[0015] Optionally, the back-etching process includes at least one of a dry etching process or a wet etching process.

[0016] Optionally, the material for preparing the metal material layer includes at least one of tungsten, aluminum, copper, titanium, and titanium nitride.

[0017] Optionally, the material of the third filling layer includes at least one of silicon nitride, silicon oxide, or single crystal silicon.

[0018] This application also provides a semiconductor device, which is formed by using the described preparation method, and includes: a substrate, including an insulating region and a plurality of active regions, the insulating region is arranged between two adjacent active regions, and the substrate further includes trenches, and the trenches are distributed in both the insulating region and the active region inside the substrate and are used to form buried gates; a first filling layer, a second filling layer, and a third filling layer, which are located in the trenches and are distributed in sequence upward along the direction perpendicular to the upper surface of the substrate, and the upper surface of the second filling layer is lower than the upper surface of the substrate, and is formed by a back-etching process, and the sidewall surface of the trench and the upper surface of the second filling layer also undergo reduction treatment, and the surfaces are flat.

[0019] The semiconductor device and preparation method of the present application use a reduction treatment to repair the materials on the sidewall surface of the trench and the upper surface of the second filling layer into the materials before the etch-back treatment, thereby repairing the surface damage of the formation substrate of the third filling layer, reducing the problem of gate leakage current caused by the surface damage, and reducing the probability of electrical damage to the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] To more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present application. For those skilled in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0021] Figure 1 It is a schematic flow chart of the steps of the preparation method of the semiconductor device in an embodiment of the present application;

[0022] Figures 2 to 7 It is a schematic structural diagram corresponding to each step of the preparation method of the semiconductor device in the embodiment of the present application. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0023] It is found that the buried gate is prone to gate leakage current. An important reason for the electrical damage to the semiconductor device is that during the process of forming a conductive metal in the trench and forming a gate capping covering the conductive metal above the conductive metal, it is necessary to form a phosphorus-doped silicon layer above the conductive metal and then perform an etch-back treatment until the thickness above the conductive metal meets the standard, and then form the gate capping. Whether depositing the phosphorus-doped silicon layer or performing the etch-back treatment on the phosphorus-doped silicon layer will affect the flatness of the sidewall surface of the trench, resulting in possible voids in the buried gate and leakage current in the buried gate.

[0024] Therefore, in the embodiments of the present application, a semiconductor device and its preparation method are provided to reduce the probability of the existence of gate leakage current, thereby reducing the probability of electrical damage to the semiconductor device.

[0025] The following will further explain the semiconductor device and its preparation method in conjunction with the drawings and embodiments.

[0026] The present application provides a preparation method of a semiconductor device in a first aspect.

[0027] Please refer to Figure 1 , which is a schematic flow chart of the steps of the preparation method of the semiconductor device in an embodiment of the present application.

[0028] In this embodiment, the method for manufacturing the semiconductor device includes the following steps: Step S1: Provide a substrate including an insulating region and a plurality of active regions, and each of the active regions is separated by the insulating region; Step S2: Form trenches in the substrate, and the trenches are distributed in both the insulating region and the active regions inside the substrate for forming buried gates; Step S3: In the trenches, sequentially fill a first filling layer and a second filling layer in a direction perpendicular to the upper surface of the substrate, and the upper surface of the second filling layer is higher than the upper surface of the substrate; Step S4: Perform a recessing process on the second filling layer to make the upper surface of the second filling layer lower than the upper surface of the substrate; Step S5: Perform a reduction process on the sidewall surface of the trench and the upper surface of the second filling layer to repair the sidewall surface of the trench and the upper surface of the second filling layer; Step S6: Form a third filling layer above the second filling layer, and the third filling layer fills the trench.

[0029] The reduction process is used to repair the materials on the sidewall surface of the trench and the upper surface of the second filling layer to the materials before the recessing process, thereby repairing the surface damage of the formation substrate of the third filling layer, reducing the problem of gate leakage current caused by the surface damage, and reducing the probability of electrical damage of the semiconductor device.

[0030] Please refer to Figures 2 to 7 , which is a schematic structural diagram corresponding to each step of the method for manufacturing the semiconductor device in the embodiment of the present application

[0031] Please refer to Figure 2 , and a plurality of trenches 100 are formed on the surface of the substrate 101 for forming a buried gate structure 102 (please refer to Figure 7 ).

[0032] The substrate 101 includes silicon (Si), such as at least one of crystalline Si, polysilicon or amorphous Si, and may also include other semiconductor materials, such as germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs) or indium phosphide (InP).

[0033] In some embodiments, the active region 1021 in the substrate 101 is a conductive region, which may be a well doped with impurities or other structures doped with impurities.

[0034] In some embodiments, the active region 1021 may have a regular shape, such as a long strip shape, and is arranged in a regular arrangement. A gate structure is formed in the active region 1021.

[0035] In Figure 3In the illustrated embodiment, the insulating region 103 is used to partition the active region 1021. Each active region 1021 can be arranged at equal intervals. In some embodiments, the insulating region 103 may include a shallow trench isolation (STI), and the shallow trench isolation is composed of a trench 100 and an insulating material filled in the trench 100. The insulating material includes at least one of insulating dielectric materials such as silicon oxide, silicon nitride, and silicon oxynitride.

[0036] The trench 100 is used to form an embedded gate structure 102. The first filling layer 200 is composed of the dielectric layer 300, the metal nitride layer 104, and the metal material layer 105.

[0037] The dielectric layer 300 not only includes the part formed on the inner wall of the trench 100, but also includes the part formed on the upper surface of the substrate 101. In some embodiments, when forming the dielectric layer 300, a dielectric material layer is filled in the trench 100 until the trench 100 is filled and the surface of the substrate 101 is covered. Then, based on the dielectric material layer, a back-off process such as chemical mechanical polishing and etching is performed to form the dielectric layer 300 as shown in Figure 3 the figure.

[0038] When forming the embedded gate, an etching process needs to be performed on the metal nitride layer 104 and the metal material layer 105 so that the top surfaces of the metal nitride layer 104 and the metal material layer 105 are lower than the upper surface of the substrate 101, which conforms to the structural characteristics of the embedded gate. The steps of preparing the metal nitride layer 104 and the metal material layer 105 are similar to the steps of forming the dielectric layer 300, and both are filled and then subjected to a back-off process.

[0039] In some embodiments, the metal material layer 105 can be prepared from metal conductive materials such as tungsten, aluminum, copper, titanium, and titanium nitride, and is used to construct the gate electrode of the embedded gate. In the Figure 3 illustrated embodiment, the gate electrode is prepared from metal tungsten.

[0040] In some embodiments, the dielectric layer 300 and the metal nitride layer are disposed around the gate electrode, and the dielectric layer 300 includes at least one material layer of an oxide layer, a nitride layer, and a nitrogen oxide layer. In the Figure 3 illustrated embodiment, the dielectric layer 300 is a silicon dioxide layer. In some other embodiments, the dielectric layer 300 can also be a silicon nitride (SiN x ) layer. The metal nitride layer includes a titanium nitride layer.

[0041] In some embodiments, the second filling layer 106 may serve as a gate capping layer of the buried gate and is formed above the first filling layer 200. The second filling layer 106 includes at least one material layer of an oxide layer, a nitride layer, and a nitroxide layer. In Figure 3 the illustrated embodiment, the gate capping layer is a silicon nitride (SiN x ) layer.

[0042] In Figure 3 the illustrated embodiment, the buried gate structure may also be formed into the insulating region 103. Specifically, reference may be made to Figure 3 the leftmost and rightmost buried gate structures in. At this time, the dielectric layer 300 of the buried gate may be formed by the dielectric material film layer in the insulating region.

[0043] In some embodiments, the insulating region 103 includes isolation trenches and a plurality of film layers formed in the isolation trenches.

[0044] Since at least one deposition of the second filling layer 106 and the etch-back process of the second filling layer 106 are performed before forming the third filling layer 107, both the deposition operation and the etch-back operation will damage the formation substrate of the third filling layer 107, making the formation substrate uneven. Filling the third filling layer 107 based on the uneven surface causes the final gate leakage current.

[0045] After the etch-back process, the second filling layer 106 that originally filled the trench 100 and covered the surface of the substrate 101 is etched back to only have a first thickness. Here, reference may be made to Figures 4 to 5 the change. In some embodiments, the etch-back process will form vacancies on the sidewall surface of the trench 100. In fact, the etch-back process will not form vacancies on the sidewall surface of the trench 100, and the reduction process can also play a certain role in tamping the surface.

[0046] In some embodiments, the etch-back process includes at least one of dry etching or wet etching. The etching gas and etching solution can be selected according to specific needs.

[0047] In some embodiments, the reduction process includes repairing the materials on the sidewall surface of the trench 100 and the upper surface of the second filling layer 106 to the materials before the etch-back process, thereby repairing the surface damage of the formation substrate of the third filling layer 107 and reducing the problem of gate leakage current caused by the damage in these regions.

[0048] The reduction treatment of the sidewall surface of the trench 100 includes the following steps: providing a reducing gas into the trench 100, repairing the sidewall surface of the trench 100, and the upper surface of the second filling layer 106 with the reducing gas.

[0049] In some embodiments, the reducing gas includes hydrogen and oxygen, and the gas volume ratio of hydrogen to oxygen is 0.95:0.05. In fact, the ratio of hydrogen to oxygen in the reducing gas can also be other ratios, and the types of gases in the reducing gas can also be other types, which can be set according to needs.

[0050] In some other embodiments, the steps of the reduction treatment can also be changed according to needs. The reduction treatment is preferably a treatment process that can repair the sidewall surface of the trench 100 and the upper surface of the second filling layer 106.

[0051] In some embodiments, at least a part of the second filling layer 106 located above the upper surface of the substrate 101 is removed by at least one of a dry etching process or a wet etching process, and at least a second filling layer 106 with a first thickness is retained in the trench 100.

[0052] The first thickness is related to the specific structure of the semiconductor device. When forming a semiconductor memory structure, the thickness of the second filling layer 106 is consistent with the thickness of the phosphorus-doped silicon on the metal electrode of the buried gate in the semiconductor memory structure, about at the micron level.

[0053] In some embodiments, the preparation material of the second filling layer 106 includes a semiconductor material. In some embodiments, the second filling layer 106 includes phosphorus-doped silicon.

[0054] In some embodiments, the second filling layer 106 has the same material as the dielectric layer 104 in the first filling layer 200.

[0055] In some embodiments, before forming the third filling layer 107 above the second filling layer 106, the following steps are further included: forming an oxide layer 108 on the upper surface of the second filling layer 106 after the reduction treatment, and the oxide layer 108 is used to separate the second filling layer 106 and the subsequently formed third filling layer 107. Please refer here Figure 6 .

[0056] When the second filling layer 106 is phosphorus-doped silicon, the oxide layer formed on the upper surface of the second filling layer 106 is a silicon oxide layer.

[0057] In some embodiments, the material of the third filling layer 107 includes at least one of silicon nitride, silicon oxide, or single crystal silicon.

[0058] On the other hand, the present application also provides a semiconductor device.

[0059] The semiconductor device is fabricated by using the fabrication method described above, and includes: a substrate 101, including an insulating region 103 and a plurality of active regions 1021, the insulating region 103 is disposed between two adjacent active regions 1021, and the substrate 101 further includes trenches 100 which are distributed in both the insulating region and the active regions inside the substrate 101 and are used to form buried gates; a first filling layer 200, a second filling layer 106, and a third filling layer 107, which are located in the trenches 100 and are sequentially distributed upward in a direction perpendicular to the upper surface of the substrate 101, and the upper surface of the second filling layer 106 is lower than the upper surface of the substrate 101 and is formed by a recessing process, and the sidewall surfaces of the trenches 100 and the upper surface of the second filling layer 106 are also subjected to a reduction process to make the surfaces flat.

[0060] By using the reduction process, the materials on the sidewall surfaces of the trenches 100 and the upper surface of the second filling layer 106 are repaired to the materials before the recessing process, so as to repair the surface damage of the formation substrate of the third filling layer 107, reduce the problem of gate leakage current caused by the surface damage, and reduce the probability of electrical damage of the semiconductor device.

[0061] The above are only embodiments of the present application, and do not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made by using the specification and drawings of the present application, such as the mutual combination of technical features between embodiments, or direct or indirect application in other related technical fields, shall be included in the patent protection scope of the present application by the same token.

Claims

1. A method for manufacturing a semiconductor device, characterized in that, Including the following steps: Providing a substrate, which includes an insulating region and a plurality of active regions, and each of the active regions is separated by the insulating region; Forming a trench in the substrate, and the trench is distributed in both the insulating region and the active regions inside the substrate, for forming a buried gate; In the trench, filling a first filling layer and a second filling layer in sequence along the direction perpendicular to the upper surface of the substrate, the upper surface of the second filling layer is higher than the upper surface of the substrate, and the first filling layer includes a dielectric layer, a metal nitride layer, and a metal material layer formed in sequence along the inner wall of the trench, wherein the dielectric layer is a silicon dioxide layer or a silicon nitride layer; Performing a recessing process on the second filling layer to make the upper surface of the second filling layer lower than the upper surface of the substrate; Performing a reduction process on the sidewall surface of the trench and the upper surface of the second filling layer, including: providing a reduction gas into the trench, and repairing the sidewall surface of the trench and the upper surface of the second filling layer through the reduction gas, and the reduction gas includes hydrogen and oxygen; Forming a third filling layer above the second filling layer, and the third filling layer fills the trench; 2. The manufacturing method according to claim 1, characterized in that, The reduction process includes repairing the materials on the sidewall surface of the trench and the upper surface of the second filling layer to the materials before the recessing process; 3. The manufacturing method according to claim 1, characterized in that, Performing an etch-back process on the metal nitride layer and the metal material layer to make the top surfaces of the metal nitride layer and the metal material layer lower than the upper surface of the substrate; 4. The manufacturing method according to claim 1, characterized in that, Removing the part of the second filling layer above the upper surface of the substrate through at least one of a dry etching process or a wet etching process, and at least retaining a second filling layer with a first thickness in the trench; 5. The manufacturing method according to claim 1, characterized in that, The preparation material of the second filling layer includes a semiconductor material; 6. The manufacturing method according to claim 1, characterized in that, The material of the second filling layer is the same as that of the dielectric layer in the first filling layer; 7. The manufacturing method according to claim 1, characterized in that, Before forming the third filling layer above the second filling layer, the following steps are further included: Forming an oxide layer on the upper surface of the second filling layer after the reduction process, and the oxide layer is used to separate the second filling layer and the subsequent formed third filling layer; 8. The manufacturing method according to claim 1, characterized in that, The recessing process can form vacancies on the sidewall surface of the trench; 9. The manufacturing method according to claim 1, characterized in that, The gas volume ratio of the hydrogen and the oxygen is 0.95:0.05; 10. The manufacturing method according to claim 1, characterized in that, The recessing process includes at least one of a dry etching or a wet etching; 11. The manufacturing method according to claim 1, characterized in that, The preparation material of the metal material layer includes at least one of tungsten, aluminum, copper, titanium, and titanium nitride; 12. The manufacturing method according to claim 1, characterized in that, The material of the third filling layer includes at least one of silicon nitride, silicon oxide, and single crystal silicon; 13. A semiconductor device, characterized in that, Prepared and formed by using the preparation method according to any one of claims 1 to 12, including: A substrate, which includes an insulating region and a plurality of active regions, the insulating region is arranged between two adjacent active regions, and the substrate further includes a trench, and the trench is distributed in both the insulating region and the active regions inside the substrate, for forming a buried gate; The first filling layer, the second filling layer, and the third filling layer are located in the trench and are sequentially distributed upward along a direction perpendicular to the upper surface of the substrate. The upper surface of the second filling layer is lower than the upper surface of the substrate and is formed by a retraction process. The sidewall surface of the trench and the upper surface of the second filling layer are also subjected to a reduction process, and the surfaces are flat.

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