Semiconductor structure and method of manufacturing the same, memory and method of manufacturing the same

Abstract

Embodiments of the present application provide a semiconductor structure and a manufacturing method thereof, a memory and a manufacturing method thereof. The semiconductor structure comprises a plurality of transistors and a plurality of isolation structures arranged in an array along a first direction and a second direction in a semiconductor layer. Each transistor comprises a channel region, the channel region comprises a first sidewall arranged opposite along the first direction and a second sidewall arranged opposite along the second direction, a source, a drain, and a gate structure surrounding the sidewalls of the channel region. The gate structure comprises a first sub-gate structure covering the first sidewall and a second sub-gate structure covering the second sidewall. The gate structures of each transistor in each row of transistors arranged along the first direction are physically connected to each other. Each isolation structure separates the gate structures of two adjacent rows of transistors arranged along the first direction from each other. Each isolation structure and the first sub-gate structures on both sides of the isolation structure are located in the same groove.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and to, but is not limited to, a semiconductor structure and its manufacturing method, and a memory and its manufacturing method. Background Technology

[0002] Transistors in semiconductor structures are widely used as switching devices or driving devices in electronic devices. For example, transistors can be used in Dynamic Random Access Memory (DRAM) to control the capacitance in each memory cell. The basic memory cell structure of DRAM consists of a transistor and a storage capacitor. Its main operating principle is to use the amount of charge stored in the capacitor to represent whether a binary bit is 1 or 0.

[0003] However, transistors in existing related technologies still have many problems that need to be improved. Summary of the Invention

[0004] To address the related technical issues, embodiments of this application propose a semiconductor structure and its manufacturing method, as well as a memory and its manufacturing method.

[0005] This application provides a semiconductor structure, including:

[0006] A plurality of transistors and a plurality of isolation structures are located in a semiconductor layer and arranged in an array along a first direction and a second direction, respectively; wherein each of the transistors includes:

[0007] The trench area includes a first sidewall disposed opposite to each other along the first direction and a second sidewall disposed opposite to each other along the second direction;

[0008] Source pole;

[0009] Drain; wherein the source and the drain are opposite ends of the channel region extending in the direction of extension; the extension direction is parallel to the thickness direction of the semiconductor layer and perpendicular to both the first direction and the second direction;

[0010] A gate structure surrounds the sidewalls of the channel region; the gate structure includes a first sub-gate structure covering the first sidewall and a second sub-gate structure covering the second sidewall; the gate structures of each transistor in each row of transistors arranged along the first direction are physically connected to each other;

[0011] Each isolation structure separates the gate structures of two adjacent rows of transistors arranged along the first direction; each isolation structure and the first sub-gate structures on both sides of the isolation structure are located in the same groove.

[0012] This application provides another semiconductor structure, including:

[0013] Multiple rows of transistors and multiple isolation structures are located in a semiconductor layer and are alternately arranged along a first direction; wherein each row of transistors includes:

[0014] A plurality of active pillars are arranged along a second direction, each active pillar comprising: a channel region, and source and drain electrodes located at opposite ends of the channel region along its extension direction; the extension direction is parallel to the thickness direction of the semiconductor layer and perpendicular to both the first and second directions; and

[0015] The word line includes a first part and a second part; wherein the first part is located on both sides of the plurality of active posts and extends along the second direction, and each second part is located between two adjacent active posts and is physically connected to the first part;

[0016] Each isolation structure separates the word lines of two adjacent rows of transistors; each isolation structure and the first portions on both sides of the isolation structure are located in the same recess.

[0017] In the above scheme, the isolation structure includes an air gap.

[0018] In the above scheme, the orthogonal projection of the channel region onto the semiconductor layer includes a square shape.

[0019] In the above scheme, the dimension of the first part along the first direction is smaller than the width of the second part along the second direction.

[0020] In the above scheme, the direction in which the multiple rows of transistors and multiple isolation structures are alternately arranged has an angle with the extension direction of the word line, and the angle range is 0-90 degrees.

[0021] This application provides an embodiment of a memory, including:

[0022] The semiconductor structure described in the above scheme;

[0023] Multiple memory cells, each of which is connected to the source or drain of a transistor in the semiconductor structure; and

[0024] Multiple bit lines, each of which is connected to the drain or source of each transistor in a row of transistors arranged along a second direction in the semiconductor structure.

[0025] In the above scheme, the memory includes: dynamic random access memory, ferroelectric memory, phase change memory, magnetic change memory, or resistive change memory.

[0026] This application provides a method for manufacturing a semiconductor structure, including:

[0027] Provides a semiconductor layer;

[0028] Multiple first sacrificial strips are formed in the semiconductor layer at intervals along the second direction;

[0029] Multiple first trenches are formed in the semiconductor layer at intervals along the first direction; the first sacrificial strips and the first trenches divide at least a portion of the semiconductor layer into multiple active pillars arranged in an array; the extension direction of the active pillars is parallel to the thickness direction of the semiconductor layer and perpendicular to both the first direction and the second direction;

[0030] In each of the first trenches, a second sacrificial strip is formed on two opposite sidewalls along the first direction;

[0031] Remove the first sacrificial bar and the second sacrificial bar to form a gate structure surrounding the sidewall of the active pillar;

[0032] A source and a drain are formed at opposite ends of the active post along its extension direction; the extension direction is perpendicular to both the first direction and the second direction.

[0033] In the above scheme, forming multiple first sacrificial strips spaced apart along the second direction includes:

[0034] Multiple second trenches are formed in the semiconductor layer at intervals along the second direction; each second trench is filled with a first sacrificial material to form multiple first sacrificial strips.

[0035] The method in the above scheme further includes:

[0036] Before filling each of the second trenches with the first sacrificial material, a first insulating layer is partially filled in the second trenches; the thickness of the first insulating layer along the extension direction is substantially the same as the thickness of the source or drain near the bottom of the second trench along the extension direction.

[0037] The filling of each of the second trenches with the first sacrificial material includes:

[0038] A first sacrificial material is filled into each of the second trenches in which the first insulating layer is formed.

[0039] In the above solution, providing the semiconductor layer includes:

[0040] A substrate is provided; the substrate includes silicon on insulator, the silicon on insulator including a bottom silicon layer, an intermediate silicon oxide layer on the bottom silicon layer, and a top silicon layer on the intermediate silicon oxide layer; the top silicon layer is the semiconductor layer;

[0041] The first trench and the second trench penetrate the top silicon layer.

[0042] In the above scheme, forming a second sacrificial strip on two opposite sidewalls in the first direction in each of the first trenches includes:

[0043] A second sacrificial material is deposited on the sidewall of each of the first trenches;

[0044] The second sacrificial material on the two opposite sidewalls along the second direction in each of the first trenches is removed to form a third trench; the remaining second sacrificial material in the sidewalls of each of the first trenches forms the second sacrificial strip;

[0045] The method further includes:

[0046] An isolation structure is formed in the third trench.

[0047] The method in the above scheme further includes:

[0048] Before depositing a second sacrificial material on the sidewall of each of the first trenches, a second insulating layer is partially filled in the first trenches; the thickness of the second insulating layer along the extension direction is substantially the same as the thickness of the source or drain near the bottom of the first trench along the extension direction.

[0049] A second sacrificial material is deposited on the sidewall of each of the first trenches, comprising:

[0050] A second sacrificial material is deposited on the sidewall of each of the first trenches where the second insulating layer is formed.

[0051] In the above scheme, forming an isolation structure in the third trench includes:

[0052] Before forming the gate structure surrounding the active pillar sidewall, an isolation material is formed in the third trench, the isolation material serving as an isolation structure;

[0053] or,

[0054] Before forming the gate structure surrounding the active pillar sidewall, an isolation material is formed in the third trench; after forming the gate structure surrounding the active pillar sidewall, the isolation material is removed to form an air gap, which serves as an isolation structure.

[0055] In the above scheme, the air gap is used as an isolation structure, and the method further includes:

[0056] Before forming the air gap, a portion of the gate structure is removed along the extending direction;

[0057] A third insulating layer is formed at the location where the gate structure is removed;

[0058] A fourth insulating layer is formed, covering the third insulating layer and the air gap.

[0059] In the above scheme, the gate structure includes a gate oxide layer and a gate; forming the gate structure surrounding the active pillar sidewall includes:

[0060] A gate oxide layer is formed around the sidewall of the active pillar;

[0061] A gate is formed surrounding the gate oxide layer.

[0062] This application provides a method for manufacturing a memory, the method comprising:

[0063] A semiconductor structure is formed; the semiconductor structure is manufactured by the semiconductor structure manufacturing method provided in the above scheme;

[0064] Multiple memory cells are formed, and each memory cell is connected to the source or drain of a transistor in the semiconductor structure.

[0065] Multiple bit lines are formed, and each bit line is connected to the source or drain of each row of transistors arranged along the second direction in the semiconductor structure.

[0066] This application provides a semiconductor structure and its manufacturing method, as well as a memory and its manufacturing method. The manufacturing method of the semiconductor structure includes: providing a semiconductor layer; forming a plurality of first sacrificial strips spaced apart along a second direction in the semiconductor layer; forming a plurality of first trenches spaced apart along a first direction in the semiconductor layer; the first sacrificial strips and the first trenches dividing at least a portion of the semiconductor layer into a plurality of active pillars arranged in an array; the extending direction of the active pillars is parallel to the thickness direction of the semiconductor layer and perpendicular to both the first and second directions; in each first trench, forming a second sacrificial strip on two opposite sidewalls along the first direction; removing the first and second sacrificial strips to form a gate structure surrounding the sidewalls of the active pillars; and forming a source and a drain at opposite ends along the extending direction of the active pillars, respectively; the extending direction is perpendicular to both the first and second directions. In the various embodiments of this application, the active pillars are directly formed in the semiconductor structure by etching the first sacrificial strip and the first trench. The process is simple and avoids the extremely high process requirements imposed by growing active pillars in deep holes using single-crystal epitaxy. Furthermore, by forming the second sacrificial strip directly on the two opposite sidewalls of the first trench, and using the position of the second sacrificial strip to form the gate structure, the self-alignment of the gate structure of each transistor in each row of transistors arranged along the first direction can be achieved directly by relying on the sidewalls of the first trench. At the same time, an isolation structure smaller than the size of the first trench can be obtained, thus breaking through the limit of the minimum size of the isolation structure obtained by the minimum resolution method of photolithography. Attached Figure Description

[0067] Figure 1 A schematic diagram illustrating the implementation flow of a semiconductor structure manufacturing method provided in this application embodiment;

[0068] Figures 2a-2d A cross-sectional schematic diagram of the manufacturing process of a semiconductor structure provided in an embodiment of this application;

[0069] Figures 3a-3b This is a cross-sectional schematic diagram of a semiconductor structure provided in an embodiment of this application;

[0070] Figures 4a-4c This is a cross-sectional schematic diagram of another semiconductor structure provided in an embodiment of this application;

[0071] Figure 5 A schematic diagram illustrating the implementation flow of another semiconductor structure manufacturing method provided in this application embodiment;

[0072] Figures 6a-6t This is a cross-sectional schematic diagram of the manufacturing process of another semiconductor structure provided in an embodiment of this application. Detailed Implementation

[0073] Exemplary embodiments of the present application will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present application are shown in the drawings, it should be understood that the present application may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided to enable a more thorough understanding of the present application and to fully convey the scope of the disclosure of the present application to those skilled in the art.

[0074] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this application. However, it will be apparent to those skilled in the art that this application can be practiced without one or more of these details. In other instances, to avoid confusion with this application, some technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0075] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0076] It should be understood that spatial relation terms such as “below,” “under,” “below,” “below,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0077] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0078] In order to gain a more detailed understanding of the features and technical content of the embodiments of this application, the implementation of the embodiments of this application will be described in detail below with reference to the accompanying drawings. The accompanying drawings are for reference and illustration only and are not intended to limit the embodiments of this application.

[0079] This application provides a semiconductor structure and a method for manufacturing the same.

[0080] Figure 1 This is a schematic diagram illustrating the implementation flow of a semiconductor structure manufacturing method provided in an embodiment of this application. Figure 1 As shown, the method for manufacturing the semiconductor structure includes the following steps:

[0081] Step S101: Provide a stacked structure, the stacked structure including a padding layer, a first insulating layer, a sacrificial layer, and a second insulating layer stacked sequentially; form a plurality of holes in the stacked structure; each hole penetrates the first insulating layer, the sacrificial layer, and the second insulating layer, and extends to the padding layer.

[0082] Step S102: An active post is formed in the hole;

[0083] Step S103: Remove the sacrificial layer to form a gap; the gap exposes part of the sidewall of the active column;

[0084] Step S104: A gate oxide layer is formed in the gap surrounding the sidewall of the active pillar; a gate is formed in the gap surrounding the sidewall of the gate oxide layer.

[0085] Step S105: A source and a drain are formed at opposite ends of the active post along its extension direction; the extension direction is perpendicular to both the first direction and the second direction.

[0086] Figures 2a-2d This is a cross-sectional schematic diagram of the manufacturing process of a semiconductor structure provided in an embodiment of this application.

[0087] refer to Figure 2aIn step S101, a first insulating layer 2202, a sacrificial layer 2203, and a second insulating layer 2204 can be sequentially formed on the pad layer 2201. The material of the pad layer 2201 may include silicon (Si), germanium (Ge), silicon germanide (SiGe) substrates, etc.; the materials of the first insulating layer 2202 and the second insulating layer 2204 may include, but are not limited to, silicon dioxide; the material of the sacrificial layer 2203 may include, but is not limited to, silicon nitride. In practical applications, the first insulating layer 2202, the sacrificial layer 2203, and the second insulating layer 2204 can all be formed using processes such as physical vapor deposition (PVD), chemical vapor deposition (CVD), and atomic layer deposition (ALD).

[0088] Hole 1H is formed by etching the stacked structure using photolithography; the hole 1H penetrates the first insulating layer 2202, the sacrificial layer 2203, the second insulating layer 2204, and extends to the pad layer 2201.

[0089] refer to Figure 2b In step S102, in the active pillar hole 1H, an active pillar 2208 can be formed on the liner layer 2201 by an epitaxial growth process (EGP).

[0090] refer to Figure 2c In step S103, the sacrificial layer 2203 is removed by etching to form a gap 2212; the gap 2212 exposes part of the sidewall of the active pillar 2208.

[0091] refer to Figure 2d In step S104, a gate oxide layer 2209 surrounding the exposed sidewall of the active pillar 2208 can be selectively formed in the gap 2212 by a process such as PVD, CVD or ALD, and a gate 2210 surrounding the sidewall of the gate oxide layer can be formed in the gap.

[0092] Here, the active pillar 2208 can be oxidized in situ on the exposed sidewall surface in the gap 2212 by heating or pressurizing to form a gate oxide layer 2209. The material of the gate oxide layer 2209 includes, but is not limited to, silicon dioxide.

[0093] The gate 2210 can be formed by depositing conductive material in the gap 2212 with the gate oxide layer 2209 using PVD or CVD processes. The material of the gate 2210 can be a metallic material or a semiconductor conductive material, such as copper, cobalt, tungsten, doped silicon, polysilicon, or any combination thereof.

[0094] Refer to the above Figure 2d In step S105, a source 1S and a drain 1D are formed at opposite ends of the active pillar 2208 along its extension direction; the extension direction is perpendicular to both the first and second directions. The source 1S, channel 1C, drain 1D, and gate 2210 constitute a vertical transistor, which implements the industry's most advanced 4F^2 (a unit transistor occupies an area F^2 of 4 feature dimensions) structure.

[0095] Figures 3a-3b This is a cross-sectional schematic diagram of a semiconductor structure provided in an embodiment of this application. Please refer to... Figure 3a and 3b , Figure 3a This is a sectional view of the YZ plane. Figure 3b This is a top view of the XY plane. Figure 3b for Figure 3a Top view along section AA. It should be noted that here, Figure 3a This can be understood as a YZ plane that passes through the channel area but does not pass through the isolation structure.

[0096] The semiconductor structure provided in this application embodiment can be formed by the manufacturing method of the semiconductor structure provided in the following embodiment.

[0097] In some embodiments, such as Figure 3b As shown, the semiconductor structure also includes an isolation structure 2207, which separates the gates 2210 of two adjacent rows of transistors arranged along the first direction.

[0098] like Figure 3a As shown, an active pillar 2208 needs to be grown in the hole 1H using EGP technology to serve as the carrier for the source 1S, channel 1C, and drain 1D of the vertical transistor. In particular, with a high depth-to-width ratio in the source pillar hole 1H, extremely high requirements are placed on the EGP process. The EGP process must be able to avoid damage to the pad layer 2201, and high demands are placed on the etching process and EGP integration. Meanwhile, as... Figure 3b As shown, the gap 2212 (refer to the above) is filled by PVD or CVD processes. Figure 2cWhen depositing conductive material to form the gate 2210, it is also necessary to further physically connect the gates 2210 of each transistor in each row of transistors arranged along the first direction to form a word line that extends continuously along the second direction. During the formation of the word line, the two ends Side1 and Side2 of the word line extension direction (i.e., the second direction) are the entry points for depositing conductive material. The conductive material is more likely to be deposited at the two ends Side1 and Side2 to form a seal, resulting in a space in the middle of the word line that cannot be filled by conductive material. Therefore, this causes discontinuity of the word line in the word line extension direction, forming a high-resistivity region and causing problems such as RC delay.

[0099] Based on at least one of the problems mentioned above in the above embodiments, this application provides another semiconductor structure and its manufacturing method, and a memory and its manufacturing method.

[0100] Figures 4a-4c This is a cross-sectional schematic diagram of another semiconductor structure provided in an embodiment of this application. Please refer to... Figure 4a and Figure 4c , Figure 4a This is a sectional view of the XZ plane. Figure 4c This is a top view of the XY plane. Figure 4c for Figure 4a Top view along section AA. Please refer to... Figure 4b and Figure 4c , Figure 4b This is a sectional view of the XZ plane. Figure 4c This is a top view of the XY plane. Figure 4c for Figure 4b Top view along section AA. It should be noted that here, Figure 4a This can be understood as an XZ plane passing through the aforementioned channel region. Figure 4b This can be understood as an XZ plane that does not pass through the aforementioned channel region.

[0101] like Figure 4a , Figure 4b and Figure 4c As shown in the embodiment of this application, a semiconductor structure includes:

[0102] A plurality of transistors and a plurality of isolation structures 107 are located in the semiconductor layer 103 and arranged in an array along a first direction and a second direction, respectively; wherein each of the transistors T includes:

[0103] The channel area C includes a first sidewall disposed opposite to each other along the first direction and a second sidewall disposed opposite to each other along the second direction.

[0104] Source S;

[0105] Drain D; wherein the source S and the drain D are opposite ends in the extension direction of the channel region C; the extension direction is parallel to the thickness direction of the semiconductor layer and perpendicular to both the first direction and the second direction;

[0106] A gate structure 1100 surrounds the sidewall of the channel region; the gate structure 1100 includes a first sub-gate structure 1102 covering the first sidewall and a second sub-gate structure 1101 covering the second sidewall; the gate structures 1100 of each transistor in each row of transistors arranged along the first direction are physically connected to each other.

[0107] Each isolation structure 107 separates the gate structures 1100 of two adjacent rows of transistors arranged along the first direction, and each isolation structure 107 and the first sub-gate structures 1102 on both sides of the isolation structure are located in the same groove.

[0108] Continue to refer to Figure 4a , Figure 4b and Figure 4c Another semiconductor structure provided in this application embodiment includes:

[0109] Multiple rows of transistors AT and multiple isolation structures 107 are located in the semiconductor layer and are alternately arranged along a first direction; wherein each row of transistors includes:

[0110] A plurality of active pillars are arranged along a second direction, each active pillar comprising: a channel region C, and a source electrode S and a drain electrode D located at opposite ends in the extension direction of the channel region C; the extension direction is parallel to the thickness direction of the semiconductor layer and perpendicular to both the first and second directions; and

[0111] The word line WL includes a first part 1201 and a second part 1202; wherein, the first part 1201 is located on both sides of the plurality of active posts 108 and extends along the second direction, and each second part 1202 is located between two adjacent active posts 108 and is physically connected to the first part 1201.

[0112] Each isolation structure 107 separates the word lines WL of two adjacent rows of transistors AT from each other; each isolation structure 107 and the first portions 1201 on both sides of the isolation structure 107 are located in the same recess. In some embodiments, such as Figure 4c As shown, in the first part 1201 along the first direction, the dimension W1 of the first part 1201 on one side of the isolation structure 107 is smaller than the dimension W2 of the second part 1202 along the second direction.

[0113] It can be understood that the second part 1202 can be understood as the channel region C of two adjacent transistors in each row of transistors arranged along the first direction (or it can be understood as...). Figure 4c The partial gate structure between the active pillar 108 in the middle, the partial gate structure having a dimension of W2 along the second direction, and a plurality of the second portions 1202 are spaced apart along the second direction in each word line WL; the first portion 1201 can be understood as the isolation structure 107 and the channel region C (or can be understood as the isolation structure 107 and the channel region C). Figure 4c Another portion of the gate structure between the active pillars 108 in the channel region, the other portion of the gate structure is distributed on both sides of the channel region along the first direction and extends and is continuous along the second direction, and the dimension of the other portion of the gate structure along the first direction is W1.

[0114] It should be noted that, here and below, each word line WL includes a first part 1201 and a second part 1202. In the embodiments of this application, the first part 1201 and the second part 1202 are not multiple independent structures, but belong to multiple different regions of the word line WL, used to describe the relevant dimensions of different regions of the word line WL.

[0115] In some embodiments, the isolation structure includes an air gap 112 (see below). Figure 6s and Figure 6t It is understandable that... Figure 4a and Figure 4c The isolation structure 107 described herein includes an air gap 112.

[0116] In various embodiments of this application, the isolation structure 107 spaces the gate structures 1100 of two adjacent rows of transistors arranged along the first direction apart from each other. In particular, when the isolation structure 107 includes an air gap 112, the parasitic effect between the gate structures 1100 of two adjacent rows of transistors arranged along the first direction is reduced, thereby improving the RC delay problem and thus improving the performance of the device.

[0117] In some embodiments, the orthographic projection of the channel region onto the semiconductor layer comprises a square.

[0118] Here, the surface of the semiconductor layer is parallel to the plane formed by the intersection of the first direction and the second direction. In some specific examples, the orthographic projection of the channel region onto the surface of the semiconductor layer includes a rectangle or a square. For example... Figure 4c for Figure 4a A cross-sectional view along the XY plane and passing through the channel region C, the cross-sectional view showing that the orthographic projection of the channel region C in the XY plane comprises a square.

[0119] In some embodiments, such as Figure 4cAs shown, a gate oxide layer 109 is further included between the gate structure 1100 and the channel region C. The channel region C (which can also be understood as...) Figure 4c The orthographic projection of the active pillar 108 in the XY plane includes a square, and the orthographic projection of the gate oxide layer 109 in the XY plane includes a square ring, the square ring surrounding the active pillar 108.

[0120] In some embodiments, the direction in which the multiple rows of transistors and multiple isolation structures are alternately arranged forms an angle with the extension direction of the word line, the angle ranging from 0 to 90 degrees. This can be understood as the angle between the first direction and the second direction ranging from 0 to 90 degrees.

[0121] In some specific embodiments, the first direction may be perpendicular to the second direction. It is understood that the angle between the first direction and the second direction determines the positional relationship of the array arrangement of the transistors along the first and second directions.

[0122] In this document and hereinafter, for ease of description, the first and second directions in the embodiments of this application are represented as two orthogonal directions parallel to the substrate plane; the third direction is a direction perpendicular to the substrate plane, that is, the extension direction of the channel region; wherein, the substrate plane can be understood as a plane perpendicular to the extension direction of the channel region. Exemplarily, the first direction is represented by the X direction in the figures; the second direction by the Y direction in the figures; and the third direction by the Z direction in the figures.

[0123] This application provides an embodiment of a memory, which will continue to be referred to... Figure 4a and Figure 4c ,include:

[0124] The semiconductor structure described in the embodiments of this application;

[0125] Multiple storage units ( Figure 4a and Figure 4c (Not shown), each of the memory cells is connected to the source S or drain D of a transistor in the semiconductor structure; and

[0126] Multiple bit lines arranged side by side along the second direction ( Figure 4a and Figure 4c (Not shown), each of the bit lines is connected to the drain (D) or source (S) of each transistor in a row of transistors arranged along the second direction in the semiconductor structure.

[0127] In practical applications, the memory also includes multiple word lines, each of which is connected to the gate structure of each transistor in a row of transistors arranged along the first direction in the semiconductor structure. The word lines provide a word line voltage and control the conduction or cutoff of the channel region in each transistor. The memory also includes multiple bit lines, each of which is connected to the drain of each semiconductor structure. The bit lines are used to perform read or write operations on the memory cell when each transistor is turned on.

[0128] In this embodiment of the application, the materials of the word lines and the bit lines include, but are not limited to, tungsten, cobalt, copper, aluminum, polycrystalline silicon, doped silicon, silicides or nitrides, or any combination thereof.

[0129] It is understood that in the memory, if each memory cell is connected to the source of a transistor in the semiconductor structure, then each bit line is connected to the drain of a row of transistors arranged along the second direction in the semiconductor structure; or, if each memory cell is connected to the drain of a transistor in the semiconductor structure, then each bit line is connected to the source of a row of transistors arranged along the second direction in the semiconductor structure.

[0130] In some embodiments, the memory includes: dynamic random access memory, ferroelectric memory, phase change memory, magnetic change memory, or resistive change memory.

[0131] In some embodiments, the memory provided in this application includes various types of memory. For example, DRAM, Static Random Access Memory (SRAM), Phase-Change Memory (PCM), Ferroelectric Random Access Memory (FRAM), Magnetic Random Access Memory (MRAM), or Resistive Random Access Memory (RRAM).

[0132] In some embodiments, the memory includes DRAM, and the memory cell includes a capacitor; the capacitor includes a columnar second electrode, a dielectric covering the sidewalls and bottom of the second electrode, and a first electrode covering the dielectric. In practical applications, the second electrode may be connected to the source of a transistor in the transistor array, and the first electrode may be connected to a reference voltage, which may be ground or other voltages. The capacitor represents logical "1" and "0" by the amount of charge stored therein.

[0133] In some embodiments, the memory includes a resistive random access memory (RRAM), and the memory cell includes an adjustable resistor connected between the bit line and the source of a transistor in the semiconductor structure; or, the adjustable resistor is connected between the bit line and the drain of a transistor in the semiconductor structure, and the adjustable resistor is used to adjust the state of the memory cell's resistance value (high or low) by the bit line voltage provided by the bit line to represent logical "0" and "1".

[0134] It should be noted that only some common memories are listed here as examples, and the scope of protection of this application is not limited to these. Any memory containing transistors provided in the embodiments of this application is within the scope of protection of this application.

[0135] In the various embodiments of this application, the active pillars are directly formed in the semiconductor structure by etching the first sacrificial strip and the first trench. The process is simple and avoids the extremely high process requirements imposed by growing active pillars in deep holes using single-crystal epitaxy. Furthermore, by forming the second sacrificial strip directly on the two opposite sidewalls of the first trench, and using the position of the second sacrificial strip to form the gate structure, the self-alignment of the gate structure of each transistor in each row of transistors arranged along the first direction can be achieved directly by relying on the sidewalls of the first trench. At the same time, an isolation structure smaller than the size of the first trench can be obtained, thus breaking through the limit of the minimum size of the isolation structure obtained by the minimum resolution method of photolithography.

[0136] The semiconductor structure provided in this application embodiment can be formed by the manufacturing method of the semiconductor structure provided in the following embodiment.

[0137] Figure 5 This is a schematic diagram illustrating the implementation flow of another semiconductor structure manufacturing method provided in an embodiment of this application. For example... Figure 5 As shown, the method for manufacturing the semiconductor structure includes the following steps:

[0138] Step S501: Provide a semiconductor layer;

[0139] Step S502: Form a plurality of first sacrificial strips spaced apart along the second direction in the semiconductor layer;

[0140] Step S503: A plurality of first trenches are formed in the semiconductor layer at intervals along the first direction; the first sacrificial strips and the first trenches divide at least a portion of the semiconductor layer into a plurality of active pillars arranged in an array; the extension direction of the active pillars is parallel to the thickness direction of the semiconductor layer and perpendicular to both the first direction and the second direction.

[0141] Step S504: In each of the first trenches, a second sacrificial strip is formed on two sidewalls opposite each other in the first direction;

[0142] Step S505: Remove the first sacrificial bar and the second sacrificial bar to form a gate structure surrounding the sidewall of the active pillar;

[0143] Step S506: A source and a drain are formed at opposite ends of the active post along its extension direction; the extension direction is perpendicular to both the first direction and the second direction.

[0144] Figures 6a-6t This is a cross-sectional schematic diagram illustrating the manufacturing process of another semiconductor structure provided in an embodiment of this application. It should be understood that... Figure 5 The steps shown are not exclusive; other steps may be performed before, after, or between any of the steps shown. Figure 5 The steps shown can be rearranged in order according to actual needs. The following section combines... Figure 5 , Figures 6a to 6t The manufacturing method of the semiconductor structure provided in the embodiments of this application will be described in detail.

[0145] First, please refer to Figure 6a and Figure 6b , Figure 6a This is a sectional view of the YZ plane. Figure 6b This is a top view of the XY plane. Figure 6b for Figure 6a Top view along section AA; perform steps S501 and S502.

[0146] In some embodiments, forming a plurality of first sacrificial strips 105 spaced apart along the second direction includes:

[0147] Multiple second trenches T2 are formed in the semiconductor layer 103 at intervals along the second direction; each second trench T2 is filled with a first sacrificial material to form the multiple first sacrificial strips 105.

[0148] In some embodiments, the formation method of the semiconductor layer 103 can be selected according to the actual needs of the device. A pad insulating layer 102 can be formed on the pad layer 101, and the semiconductor layer 103 can be formed on the pad insulating layer 102. The material of the pad layer 101 may include silicon (Si), germanium (Ge), silicon germanide (SiGe) substrates, etc.; the material of the pad insulating layer 102 may include, but is not limited to, silicon oxide. In practical applications, the semiconductor layer 103 can be formed using processes such as PVD, CVD, and ALD.

[0149] In some embodiments, the plurality of spaced-apart first sacrificial strips 105 are formed by the following steps: forming a pad insulating layer 102 on a pad layer 101, forming a semiconductor layer 103 on the pad insulating layer 102, using a shallow trench isolation (STI) process, etching a second trench T2 through the semiconductor layer 103 along a third direction (the third direction is perpendicular to both the first and second directions, and the third direction is the same as the direction in which the trench region extends), the bottom of the second trench T2 extending to the pad insulating layer 102 in the substrate, depositing a first sacrificial material in the second trench T2, and performing chemical mechanical polishing (CMP) on the first sacrificial material so that the surface of the first sacrificial material is flush with the surface of the semiconductor layer 103, thereby forming the plurality of first sacrificial strips 105; wherein, the plurality of first sacrificial strips 105 divide the semiconductor layer 103 into a plurality of strip-shaped semiconductor layers (which can be understood as the semiconductor layer 103 between two adjacent first sacrificial strips 105).

[0150] In this embodiment, the material of the first sacrificial strip 105 can be silicon nitride or other insulating materials. In practical applications, the material of the first sacrificial strip 105 is different from the material of the padding insulating layer 102.

[0151] In some embodiments, the method further includes:

[0152] Before filling each of the second trenches T2 with the first sacrificial material, a first insulating layer 104 is partially filled into the second trenches; the thickness of the first insulating layer 104 along the extension direction is substantially the same as the thickness of the source or drain near the bottom of the second trench along the extension direction (refer to the following). Figure 6s Along the third direction upwards, the filling thickness of the first insulating layer 104 is less than the depth of the second trench;

[0153] The filling of each of the second trenches T2 with the first sacrificial material includes:

[0154] A first sacrificial material is filled in each of the second trenches T2 in which the first insulating layer 104 is formed.

[0155] In practical applications, the term "basically the same" can be understood as meaning that in the fabrication processes of the first insulating layer 104 and the source or drain at the bottom of the second trench, due to dimensional errors in each process and significant differences in fabrication methods (e.g., using thin-film deposition to fabricate the first insulating layer, while using ion implantation + thermal diffusion to fabricate the source or drain), the thickness of the first insulating layer 104 cannot be completely controlled to be exactly the same as the thickness of the source or drain. In some specific embodiments, the thickness of the first insulating layer 104 along the extension direction is the same as the thickness of the source or drain at the bottom of the second trench along the extension direction, or, within the process error range, the thickness of the first insulating layer 104 along the extension direction is slightly less than or greater than the thickness of the source or drain at the bottom of the second trench along the extension direction. The first insulating layer 104 can be used to isolate the gate 110 in subsequent processes (see below). Figure 6m and Figure 6n It can also be used to define the depth of the gate 110 along the extension direction.

[0156] In this embodiment, the material of the first insulating layer 104 is different from the material of the first sacrificial strip 105. The material of the first insulating layer 104 may include, but is not limited to, silicon dioxide, and the material of the first sacrificial strip 105 may include, but is not limited to, silicon nitride. In some specific examples, the material of the first insulating layer 104 may be the same as the material of the pad insulating layer 102.

[0157] Please refer to Figure 6c and Figure 6d , Figure 6c This is a sectional view of the XZ plane. Figure 6d This is a top view of the XY plane. Figure 6d for Figure 6c Top view along section AA; proceed to step S503.

[0158] A first trench T1 is formed by etching along a third direction in the semiconductor layer 103 and the first sacrificial strip 105, penetrating the semiconductor layer 103 and the first sacrificial strip 105. The first trench T1 is spaced apart along the first direction, and the first sacrificial strip 105 and the first trench T1 divide at least a portion of the semiconductor layer 103 into a plurality of active pillars 108 arranged in an array. The extension direction of the active pillars is parallel to the thickness direction of the semiconductor layer and perpendicular to both the first direction and the second direction. A portion of the sidewalls 1081 of the active pillars are exposed in the first trench T1.

[0159] Here, a dry etching process can be used to etch the semiconductor layer 103 and the first sacrificial strip 105, such as plasma etching or reactive ion etching.

[0160] refer to Figure 6a and Figure 6c In some embodiments, the provision of the semiconductor layer 103 includes:

[0161] A substrate is provided; the substrate comprises silicon-on-insulator (SOI), wherein the SOI comprises an underlying silicon layer (understood as...). Figure 6a The padding layer 101), located on the underlying silicon, is an intermediate silicon oxide layer (understood as) Figure 6a The intermediate silicon oxide layer 103 is a semiconductor layer 103, consisting of a padding insulating layer 102 and a top silicon layer on top of the intermediate silicon oxide layer.

[0162] The first trench T1 and the second trench T2 penetrate the top silicon layer. The first trench T1 and the second trench T2 can penetrate the top silicon layer all the way to the surface of the intermediate silicon oxide layer.

[0163] In this embodiment, the substrate can also be germanium-on-insulator (GOI). The semiconductor layer 103 is doped with certain impurity ions as needed. The impurity ions can be N-type impurity ions or P-type impurity ions.

[0164] In various embodiments of this application, SOI is used as the substrate. A second trench T2 extending in a first direction and a first trench T1 extending in a second direction are formed in the semiconductor layer 103 of SOI. The second trench T2 and the first trench T1 divide the semiconductor layer 103 into a plurality of active pillars 108 arranged in an array. The plurality of active pillars 108 serve as the channel region, source, and drain of a transistor. Simultaneously, in subsequent processes, a self-aligned isolation structure 107 is formed in the first trench T1 (refer to the following). Figures 6e to 6h ).

[0165] Please refer to Figures 6e to 6h , Figure 6e , Figure 6g This is a sectional view of the XZ plane. Figure 6f , Figure 6h This is a top view of the XY plane. Figure 6f , Figure 6h They are respectively Figure 6e , Figure 6g Top view along section AA; proceed to step S504.

[0166] In some embodiments, forming a second sacrificial strip on two opposite sidewalls in the first direction in each of the first trenches includes:

[0167] Step a, deposit a second sacrificial material on the sidewall of each of the first trenches;

[0168] Step b: Remove the second sacrificial material from the two opposite sidewalls along the second direction in each of the first trenches to form a third trench; the remaining second sacrificial material in the sidewalls of each of the first trenches forms the second sacrificial strip;

[0169] The method further includes:

[0170] Step c, forming an isolation structure in the third trench.

[0171] Perform step a. Here, the second sacrificial material can be selectively deposited on the sidewalls of the first trench T1 using processes such as PVD, CVD, or ALD, while no second sacrificial material is deposited on the bottom of the first trench T1. Alternatively, the second sacrificial material can be non-selectively deposited on both the sidewalls and bottom of the first trench T1 using processes such as PVD, CVD, or ALD, and then the second sacrificial material at the bottom of the first trench T1 can be removed using a selective etching process, while retaining the second sacrificial material on the sidewalls of the first trench T1. Here, the etching process can employ a dry etching process to etch the second sacrificial material at the bottom of the first trench T1, for example, a plasma etching process or a reactive ion etching process.

[0172] refer to Figure 6e and Figure 6f Proceed to step b. Here, a portion of the second sacrificial material extending along the first direction on the sidewall of each of the first trenches T1 can be selectively removed using a photolithography process (see reference). Figure 6f In each of the first trenches, two opposing edge regions edge1 and edge2 along the second direction form a third trench T3; the remaining second sacrificial material in the sidewall of each first trench T1 forms the second sacrificial strip 106. It is understood that the third trench T3 and the second sacrificial strip 106, both extending along the second direction, are formed in the first trench T1, and the third trench T3 divides the second sacrificial strip 106 into two sub-regions (see reference...). Figure 6e The second sacrificial strip 106, that is, the two sub-parts of the second sacrificial strip 106 are respectively attached to the two opposite sidewalls in the first groove T1 along the first direction, and the third groove T3 is located in the middle of the two sub-parts of the second sacrificial strip 106.

[0173] In this embodiment, before performing the photolithography process, a self-aligned second sacrificial material is formed in the first trench T1 by deposition; then, the second sacrificial material of the two edge regions edge1 and edge2 is selectively removed by photolithography to form the self-aligned third trench T3. It should be emphasized that although a photolithography process is performed here, it is only used to remove the two opposing edge regions edge1 and edge2 along the second direction in each of the first trenches. The exposure area is small, and the two edge regions edge1 and edge2 are not located in the active pillar area of ​​the array arrangement. The exposure area is not concentrated, and strict control of critical dimensions is not required. It is only necessary to ensure that the second sacrificial material of the edge regions edge1 and edge2 is removed and the second sacrificial material is divided into two parts (i.e., two sub-parts of the second sacrificial strip 106) on the two opposing sidewalls along the first direction in the first trench T1. Therefore, the photolithography process window for the edge regions edge1 and edge2 is greatly improved. Meanwhile, the dimension of the self-aligned third trench T3 along the first direction can be smaller than the minimum feature size of the photolithography process, meaning that the feature size of the third trench T3 can break through the limits of the photolithography process; and the dimension uniformity of the self-aligned third trench T3 is better. In this embodiment, the smaller third trench T3 is formed by photolithography (here and hereinafter, it can be understood as lithography-etching (LE)) and self-aligned double patterning (SADP) process, and the dimension uniformity of the self-aligned third trench T3 is better.

[0174] Assuming that during the formation of the second trench T2 and the first trench T1 (refer to the above) Figure 6c and 6d After that, the third trench T3 is formed directly in the first trench T1 using a photolithography process (refer to the above). Figure 6f (To understand), at this point, the photolithography process needs to ensure alignment accuracy and strictly control the key dimensions (the third trench T3 is located in the middle or exactly in the middle of the first trench T1 along the first direction); at the same time, the dimension of the third trench T3 formed directly by the photolithography process along the first direction is limited by the minimum feature size of the photolithography process and cannot be smaller than the minimum feature size of the photolithography process. In other words, the feature size of the third trench T3 formed in this way cannot break through the limit of the photolithography process, and the uniformity of the third trench T3 is also poor.

[0175] Compared to the third trench T3 formed directly by photolithography, in this embodiment, the third trench T3 is formed by a photolithography-etching process and a self-aligned dual patterning process, resulting in a smaller, self-aligned third trench T3 with better dimensional uniformity.

[0176] In this embodiment, the material of the second sacrificial strip 106 may include, but is not limited to, silicon nitride, and may be the same as the material of the first sacrificial strip 105. In practical applications, the material of the second sacrificial strip 106 is different from the material of the first insulating layer 104.

[0177] refer to Figure 6g and Figure 6h Proceed to step c. Here, the isolation material 107' can be deposited in the third trench T3 using processes such as PVD, CVD, or ALD.

[0178] In this embodiment, the insulating material 107' may include, but is not limited to, silicon dioxide, and the insulating material 107' is different from the materials of the first sacrificial strip 105 and the second sacrificial strip 106. In practical applications, the insulating material 107' may be the same as the materials of the first insulating layer 104 and the padding insulating layer 102.

[0179] It should be noted that the isolation material 107' is used to form the solid isolation structure 107 in subsequent processes (see above). Figures 4a to 4c ) or air gap 112 (see below) Figures 6s to 6t After forming the gate structure surrounding the active pillar sidewalls, a third insulating layer is formed covering the insulating material (see below). Figures 6s to 6t The insulating material 107' covered by the third insulating layer becomes the insulating structure 107 (see above). Figures 4a to 4c ).

[0180] In this embodiment, a smaller, self-aligned third trench T3 is formed by photolithography and self-aligned dual patterning. Insulating material is deposited in the third trench T3 to form a smaller, self-aligned isolation material 107'. In other words, the feature size of the isolation material 107' formed in this way breaks through the limits of photolithography. At the same time, the isolation structure 107 is formed by self-alignment, and the size uniformity of the isolation material 107' is better.

[0181] In some embodiments, the method further includes:

[0182] Before depositing the second sacrificial material on the sidewall of each of the first trenches T1, a second insulating layer 104 is filled in the first trenches T1; the thickness of the second insulating layer 104 along the extending direction is substantially the same as the thickness of the source or drain near the bottom of the first trench along the extending direction.

[0183] A second sacrificial material is deposited on the sidewall of each of the first trenches T1, including:

[0184] A second sacrificial material is deposited on the sidewall of each of the first trenches T1 where the second insulating layer 104 is formed.

[0185] In this embodiment, the material of the second insulating layer 104 may include, but is not limited to, silicon dioxide, and the material of the second insulating layer 104 is different from that of the second sacrificial material. The material of the second insulating layer 104 may be the same as that of the first insulating layer 104 and the padding insulating layer 102.

[0186] Please refer to Figures 6i to 6n , Figure 6i , Figure 6k , Figure 6m This is a sectional view of the XZ plane. Figure 6j , Figure 6l , Figure 6n This is a top view of the XY plane. Figure 6j , Figure 6l , Figure 6n They are respectively Figure 6i , Figure 6k , Figure 6m Top view along section AA; proceed to step S505.

[0187] refer to Figure 6i and Figure 6j The first sacrificial strip 105 and the second sacrificial strip 106 are removed to form a plurality of fourth grooves T4; wherein the isolation material 107' is not removed but retained. The fourth grooves T4 expose the sidewalls 1081 of the active posts and the sidewalls of the isolation material 107'. The isolation material 107' and the fourth grooves T4 are spaced apart along a first direction, and adjacent fourth grooves T4 arranged along the first direction are separated by the isolation material 107'. That is, the sidewalls of each active post 108 in each row of active posts arranged along the first direction are exposed in the same fourth groove T4. It is understood that since the isolation material 107' is self-aligned in the first groove T1 (refer to the above). Figures 6e to 6h The fourth groove T4, located between two adjacent insulating materials 107', is also self-aligned. A gate structure 1110 is self-aligned and formed in the fourth groove T4, each gate structure 1110 surrounding the sidewall of each active pillar 108 in each row of active pillars arranged along the first direction (refer to the following). Figures 6k to 6n ).

[0188] In this embodiment, the material of the insulating material 107' is different from the materials of the first sacrificial strip 105 and the second sacrificial strip 106. The material of the insulating material 107' may include, but is not limited to, silicon dioxide, and the materials of the first sacrificial strip 105 and the second sacrificial strip 106 may include, but are not limited to, silicon nitride.

[0189] refer to Figures 6k to 6n In some embodiments, the gate structure 1100 includes a gate oxide layer 109 and a gate 110; the gate structure forming the sidewalls surrounding the active pillar 108 includes:

[0190] A gate oxide layer 109 is formed around the sidewall of the active pillar 108;

[0191] A gate 110 is formed surrounding the gate oxide layer 109.

[0192] refer to Figure 6k and Figure 6l A gate oxide layer 109 is formed on the sidewall of each of the active pillars 108, including: in-situ oxidation of the active pillars 108 in the corresponding fourth trench T4 (refer to the above). Figure 6i and Figure 6j The active pillar 108 has exposed sidewalls, and a gate oxide layer 109 is formed around the sidewalls of each active pillar 108.

[0193] After the gate oxide layer 109 is formed in the fourth trench T4, a fifth trench T5 is simultaneously formed. The fifth trench T5 exposes the sidewalls of the gate oxide layer 109 and the sidewalls of the isolation material 107'. The isolation material 107' and the fifth trench T5 are spaced apart along a first direction, and adjacent fifth trenches T5 arranged along the first direction are separated by the isolation material 107'. That is, the sidewalls of each active pillar 108 in each row of active pillars arranged along the first direction are surrounded by the gate oxide layer 109, and the sidewalls of the gate oxide layer 109 are exposed in the same fifth trench T5. Here, the gate oxide layer 109 can be formed by in-situ oxidation of the exposed sidewalls in the fourth trench T4 by heating or pressurizing, and the material of the gate oxide layer 109 includes, but is not limited to, silicon dioxide.

[0194] refer to Figure 6m and Figure 6n In the fifth groove T5 (refer to the above) Figure 6k and Figure 6l A conductive material is filled in the fifth groove T5 to form the gate 110 of each transistor. The conductive material can be deposited in the fifth groove T5 by a PVD process or a CVD process.

[0195] In this embodiment, the material of the bit line can be a metallic material or a semiconductor conductive material, such as copper, cobalt, tungsten, doped silicon, polycrystalline silicon, or any combination thereof.

[0196] It needs to be emphasized that, such as Figure 6n As shown, the gates 110 of each transistor in each row of transistors arranged along the first direction are physically connected to each other. That is, the gates 110 surround the sidewall of the active pillar 108 and include a second sub-gate structure 1101 surrounding the active pillar 108 along the first direction and a second sub-gate structure 1102 surrounding the sidewall of the active pillar 108 along the second direction. The dimension W2 of the second sub-gate structure 1101 along the second direction is larger than the dimension W1 of the second sub-gate structure 1102 along the first direction; the gates 110 of each transistor in each row of transistors arranged along the first direction are physically connected to each other.

[0197] In various embodiments of this application, SOI is used as a substrate, and a second trench T2 extending in a first direction and a first trench T1 extending in a second direction are formed in the semiconductor layer 103 of SOI. The second trench T2 and the first trench T1 divide the semiconductor layer 103 into a plurality of active pillars 108 arranged in an array. The plurality of active pillars 108 serve as the channel region, source, and drain of a transistor. Then, a smaller, self-aligned isolation material 107' is formed using photolithography and a self-aligned dual patterning process; and, the first sacrificial strip 105 and the second sacrificial strip 106 located between two adjacent isolation materials 107' are removed, and the fourth groove T4 is formed in a self-aligned manner. The sidewall of each active pillar 108 in each row of active pillars arranged along the first direction is exposed in the same fourth groove T4. The fourth groove T4 is filled with conductive material to form a self-aligned gate structure 1100. That is, by replacing the first sacrificial strip 105 and the second sacrificial strip 106 with conductive material, a gate structure 1100 is formed surrounding the sidewall of the active pillars. The gate structure 1100 physically connects the gate structures of each transistor in each row of transistors arranged along the first direction to each other. The isolation material 107' spaces the gate structures 1100 of two adjacent rows of transistors arranged along the first direction to each other, thereby forming a self-aligned vertical transistor with better dimensional uniformity.

[0198] Please refer to Figures 6o to 6t , Figure 6o , Figure 6q , Figure 6s This is a sectional view of the XZ plane. Figure 6p , Figure 6r , Figure 6t This is a top view of the XY plane. Figure 6p, Figure 6r , Figure 6t They are respectively Figure 6o , Figure 6q , Figure 6s Top view along section AA.

[0199] refer to Figures 6o to 6t In some embodiments, an isolation structure is formed in the third trench, including:

[0200] Before forming the gate structure 1100 surrounding the sidewalls of the active pillar 108, an insulating material 107' is formed in the third trench (refer to the above). Figures 6m to 6n The insulating material 107' is used as an insulating structure (refer to the above). Figures 4a to 4c (Isolation structure 107 in the middle).

[0201] or,

[0202] Before forming the gate structure 1100 surrounding the sidewalls of the active pillar 108, an isolation material is formed in the third trench; after forming the gate structure surrounding the sidewalls of the active pillar, the isolation material 107' is removed to form an air gap 112, which serves as an isolation structure (see below). Figures 6s to 6t (Air gap 112 in the middle).

[0203] refer to Figure 6o and Figure 6p Remove the isolation material 107' (refer to the above) Figures 6m to 6n A plurality of sixth recesses T6 are formed. Each of the sixth recesses T6 exposes the sidewall of the gate structure 1100. In some embodiments, the insulating material 107' may be completely or partially removed. For example, the insulating material 107' may be completely removed.

[0204] refer to Figures 6q to 6t In some embodiments, the air gap is used as an isolation structure, and the method further includes:

[0205] Before forming the air gap 112, a portion of the gate structure 1100 is removed along the extending direction;

[0206] A third insulating layer 113 is formed at the location where the gate structure 1100 is removed;

[0207] The formation of the fourth insulating layer 111 covering the air gap 112 includes:

[0208] A fourth insulating layer 111 is formed to cover the third insulating layer 113 and the air gap.

[0209] refer to Figure 6q and Figure 6rConductive material can be deposited in the fifth groove T5 by PVD or CVD process; then, part of the gate structure 1100 can be removed by etch-back process along the extension direction of the active pillar 108; here, the etching process can be a dry etching process, such as plasma etching process or reactive ion etching process.

[0210] At the location where the gate structure 1100 is removed, an insulating material is deposited using a PVD or CVD process to form a third insulating layer 113. The material of the third insulating layer 113 includes, but is not limited to, silicon nitride, silicon oxynitride, silicon carbide, silicon dioxide, or any combination thereof.

[0211] refer to Figure 6s and Figure 6t An insulating material is deposited using a PVD or CVD process to form a fourth insulating layer 111 covering the third insulating layer 113 and the air gap 112. The material of the fourth insulating layer 111 includes, but is not limited to, silicon nitride, silicon oxynitride, silicon carbide, silicon dioxide, or any combination thereof.

[0212] Step S506 is executed, in which a source S and a drain D are formed at opposite ends of the active post 108 in the extension direction; the extension direction is perpendicular to both the first direction and the second direction.

[0213] In some embodiments, refer to the above Figure 6s and Figure 6t The first end face S1 of each active pillar 108 is exposed by photolithography, and the drain D of each transistor is formed on the first end face S1 of each active pillar 108, including: performing ion implantation on the first end face S1 of each active pillar 108 to form the drain D of each transistor.

[0214] In some embodiments, refer to the above Figure 6s and Figure 6t The above Figure 6s After the semiconductor structure shown is inverted along the third direction, the pad layer 101 and the pad insulating layer 102 are removed in sequence to expose the second end face S2 of each active pillar 108. The source S of each transistor is formed on the second end face S2 of each active pillar 108, including: performing ion implantation on the second end face S2 of each active pillar 108 to form the source S of each transistor.

[0215] In some embodiments, the positions of the source S and the drain D can be interchanged, meaning that the source S can be formed first or the drain can be formed first. The source S is located at the first end of the channel region C; the drain D is located at the second end of the channel region C, and the positions of the first and second ends can be interchanged. The first and second ends are respectively two interchangeable positions of the channel region C in a third direction.

[0216] In various embodiments of this application, the active pillars are directly formed in the semiconductor structure by etching the first sacrificial strip and the first trench. This process is simple and avoids the extremely high process requirements imposed by growing active pillars in deep holes using single-crystal epitaxy. At the same time, smaller, self-aligned isolation structures and gate structures are formed by lithography-etching (LE) and self-aligned double patterning (SADP) processes. The self-aligned isolation structures and gate structures have better dimensional uniformity, allowing the more uniform isolation structures and gate structures to extend continuously along the second direction. This reduces the resistance of the gate structure and improves problems such as RC delay between multiple gate structures, thereby enhancing the performance of the device.

[0217] This application provides a method for manufacturing a memory, the method comprising:

[0218] A semiconductor structure is formed; the semiconductor structure is manufactured using the semiconductor structure manufacturing method provided in the embodiments of this application.

[0219] Multiple memory cells are formed, and each memory cell is connected to the source or drain of a transistor in the semiconductor structure.

[0220] Multiple bit lines are formed, and each bit line is connected to the source or drain of each row of transistors arranged along the second direction in the semiconductor structure.

[0221] In practical applications, the word lines are connected to the gate of each of the semiconductor structures. The word lines provide a word line voltage and control the conduction or cutoff of the channel region in each transistor. The bit lines, extending along the first direction, are connected to the drain of each of the semiconductor structures. The bit lines are used to perform read or write operations on the memory cell when each transistor is turned on.

[0222] The memory manufactured by the method of manufacturing the memory provided in this application is similar to the memory in the above embodiments. For technical features not disclosed in detail in the embodiments of this application, please refer to the above embodiments for understanding. Here, they will not be repeated.

[0223] It should be understood that the phrase "one embodiment" or "an embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this application. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this application, the sequence numbers of the above-described processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application. The sequence numbers of the above-described embodiments are merely descriptive and do not represent the superiority or inferiority of the embodiments.

[0224] The methods disclosed in the several method embodiments provided in this application can be arbitrarily combined without conflict to obtain new method embodiments.

[0225] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A semiconductor structure, characterized in that, include: A plurality of transistors and a plurality of isolation structures are located in a semiconductor layer and arranged in an array along a first direction and a second direction, respectively; wherein each of the transistors includes: The trench area includes a first sidewall disposed opposite to each other along the first direction and a second sidewall disposed opposite to each other along the second direction; Source pole; Drain; wherein the source and the drain are opposite ends in the extension direction of the channel region; the extension direction is parallel to the thickness direction of the semiconductor layer and perpendicular to both the first direction and the second direction; A gate structure surrounds the sidewalls of the channel region; the gate structure includes a first sub-gate structure covering the first sidewall and a second sub-gate structure covering the second sidewall; the gate structures of each transistor in each row of transistors arranged along the first direction are physically connected to each other; Each isolation structure separates the gate structures of two adjacent rows of transistors arranged along the first direction; each isolation structure and the first sub-gate structures on both sides of the isolation structure are located in the same groove.

2. A semiconductor structure, characterized in that, include: Multiple rows of transistors and multiple isolation structures are located in a semiconductor layer and are alternately arranged along a first direction; wherein each row of transistors includes: A plurality of active pillars are arranged along a second direction, each active pillar comprising: a channel region, and source and drain electrodes located at opposite ends of the channel region along its extension direction; the extension direction is parallel to the thickness direction of the semiconductor layer and perpendicular to both the first and second directions; and The word line includes a first part and a second part; wherein the first part is located on both sides of the plurality of active posts and extends along the second direction, and each second part is located between two adjacent active posts and is physically connected to the first part; Each isolation structure separates the word lines of two adjacent rows of transistors; each isolation structure and the first portions on both sides of the isolation structure are located in the same recess.

3. The semiconductor structure according to claim 1 or 2, characterized in that, The isolation structure includes an air gap.

4. The semiconductor structure according to claim 1 or 2, characterized in that, The orthographic projection of the channel region onto the semiconductor layer comprises a square.

5. The semiconductor structure according to claim 2, characterized in that, The dimensions of the first part along the first direction are all smaller than the dimensions of the second part along the second direction.

6. The semiconductor structure according to claim 2, characterized in that, The direction in which the multiple rows of transistors and multiple isolation structures are alternately arranged has an angle with the direction in which the word lines extend, and the angle ranges from 0 to 90 degrees.

7. A memory, characterized in that, include: The semiconductor structure according to any one of claims 1 to 6; Multiple memory cells, each of which is connected to the source or drain of a transistor in the semiconductor structure; as well as Multiple bit lines, each of which is connected to the drain or source of each transistor in a row of transistors arranged along a second direction in the semiconductor structure.

8. The memory according to claim 7, characterized in that, The memory includes: dynamic random access memory, ferroelectric memory, phase change memory, magnetic change memory, or resistive change memory.

9. A method for manufacturing a semiconductor structure, characterized in that, include: Provides a semiconductor layer; Multiple first sacrificial strips are formed in the semiconductor layer at intervals along the second direction; Multiple first trenches are formed in the semiconductor layer at intervals along a first direction; the first sacrificial strips and the first trenches divide at least a portion of the semiconductor layer into multiple active pillars arranged in an array; the extension direction of the active pillars is parallel to the thickness direction of the semiconductor layer and perpendicular to both the first direction and the second direction; In each of the first trenches, a second sacrificial strip is formed on two opposite sidewalls along the first direction, and an isolation material is formed thereon; the isolation material and the second sacrificial strip extend along the second direction, and the isolation material divides the second sacrificial strip into two sub-parts; the two sub-parts of the second sacrificial strip are respectively attached to two opposite sidewalls along the first direction in the first trench, and the isolation material is located between the two sub-parts of the second sacrificial strip; Remove the first sacrificial bar and the second sacrificial bar to form a gate structure surrounding the sidewall of the active pillar; A source and a drain are formed at opposite ends of the active post along its extension direction; the extension direction is perpendicular to both the first direction and the second direction.

10. The method according to claim 9, characterized in that, The formation of multiple first sacrificial strips spaced apart along the second direction includes: Multiple second trenches are formed in the semiconductor layer at intervals along the second direction; Each of the second trenches is filled with the first sacrificial material to form a plurality of the first sacrificial strips.

11. The method according to claim 10, characterized in that, The method further includes: Before filling each of the second trenches with the first sacrificial material, a first insulating layer is partially filled in the second trenches; the thickness of the first insulating layer along the extension direction is substantially the same as the thickness of the source or drain near the bottom of the second trench along the extension direction. The filling of each of the second trenches with the first sacrificial material includes: A first sacrificial material is filled into each of the second trenches in which the first insulating layer is formed.

12. The method according to claim 10, characterized in that, The provision of the semiconductor layer includes: A substrate is provided; the substrate includes silicon on insulator, the silicon on insulator including a bottom silicon layer, an intermediate silicon oxide layer on the bottom silicon layer, and a top silicon layer on the intermediate silicon oxide layer; the top silicon layer is the semiconductor layer; The first trench and the second trench penetrate the top silicon layer.

13. The method according to claim 9, characterized in that, The step of forming a second sacrificial strip on two opposite sidewalls in the first direction in each of the first trenches includes: A second sacrificial material is deposited on the sidewall of each of the first trenches; The second sacrificial material on the two opposite sidewalls along the second direction in each of the first trenches is removed to form a third trench; the remaining second sacrificial material in the sidewalls of each of the first trenches forms the second sacrificial strip; The method further includes: An isolation structure is formed in the third trench.

14. The method according to claim 13, characterized in that, The method further includes: Before depositing a second sacrificial material on the sidewall of each of the first trenches, a second insulating layer is partially filled in the first trenches; the thickness of the second insulating layer along the extension direction is substantially the same as the thickness of the source or drain near the bottom of the first trench along the extension direction. A second sacrificial material is deposited on the sidewall of each of the first trenches, comprising: A second sacrificial material is deposited on the sidewall of each of the first trenches where the second insulating layer is formed.

15. The method according to claim 13, characterized in that, An isolation structure is formed in the third trench, including: Before forming the gate structure surrounding the active pillar sidewall, the isolation material is formed in the third trench, the isolation material serving as an isolation structure; or, Before forming the gate structure surrounding the active pillar sidewall, the isolation material is formed in the third trench; after forming the gate structure surrounding the active pillar sidewall, the isolation material is removed to form an air gap, which serves as an isolation structure.

16. The method according to claim 15, characterized in that, The air gap is used as an isolation structure, and the method further includes: Before forming the air gap, a portion of the gate structure is removed along the extending direction; A third insulating layer is formed at the location where the gate structure is removed; A fourth insulating layer is formed, covering the third insulating layer and the air gap.

17. The method according to claim 9, characterized in that, The gate structure includes a gate oxide layer and a gate; the formation of the gate structure surrounding the active pillar sidewall includes: A gate oxide layer is formed around the sidewall of the active pillar; A gate is formed surrounding the gate oxide layer.

18. A method for manufacturing a memory, characterized in that, The method includes: A semiconductor structure is formed; the semiconductor structure is manufactured by the semiconductor structure manufacturing method provided by any one of claims 9 to 17; Multiple memory cells are formed, and each memory cell is connected to the source or drain of a transistor in the semiconductor structure. Multiple bit lines are formed, and each bit line is connected to the source or drain of each row of transistors arranged along the second direction in the semiconductor structure.

Images