A finned transistor and its fabrication method

Abstract

This invention provides a finned transistor and its fabrication method. In this method, an amorphous layer is first formed by ion implantation on the surface of the fin. This reduces the impact of internal stress on the fin during the subsequent formation of the dielectric layer, preventing defects such as stacking faults and bending. Because the fin itself is a single-crystal material, its atoms are arranged in a periodic, ordered manner. Stress during dielectric layer deposition easily extends along the crystal arrangement direction, causing significant crystal defects. In contrast, the amorphous layer exhibits significant atomic disorder, thus dispersing stress and preventing it from extending deeply along certain directions, thereby avoiding crystal defects. Furthermore, high-temperature ion implantation is preferably used to form the amorphous layer, allowing it to revert to a single-crystal state during the subsequent peak annealing process.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a fin transistor and its fabrication method. Background Technology

[0002] Integrated circuits, including CPUs and storage devices, require numerous circuit components to be formed on a chip according to a specified circuit layout. Among these, metal-oxide-semiconductor field-effect transistors (MOSFETs or FETs) are crucial circuit components, essentially determining the performance of the integrated circuit. Typically, an FET includes a source region, a drain region, a channel region, and a gate structure. The current flowing through the FET is controlled by the voltage applied to the gate electrode. For example, in a MOS device, if no external voltage is applied to the gate electrode, no current flows through the NMOS device. However, when an appropriate positive voltage is applied to the gate electrode, the channel region of the NMOS device becomes conductive, allowing current to flow between the source and drain regions through the conductive channel region.

[0003] To improve the operating speed of FETs and increase their density in integrated circuit devices, engineers have significantly reduced the actual size of FETs over the past few decades. With the continuous expansion of MOS scale, FinFET devices have become a further technological extension of CMOS. Compared with traditional devices, FinFET technology has the advantages of increasing transistor density and electrical performance. The morphology and size of the fins in the device are decisive factors in the device's electrical parameters, and the high-temperature processing after fin formation will affect the morphology and size of the fins. After fin formation, a dielectric layer needs to be filled in the gaps between the fins, such as... Figure 1 As shown. The process of filling the dielectric layer typically employs fluid chemical vapor deposition (FCVD), which uses a flowable dielectric material to fill voids in the gaps. Generally, this involves the following steps: adding several chemicals to a silicon-containing precursor to allow the deposited film to flow. The flowable film is then cured, followed by annealing to remove the added chemicals and form the dielectric layer (e.g., silicon oxide). The flowable film is typically cured and annealed at high temperatures (e.g., above 1000°C).

[0004] During the aforementioned high-temperature curing and annealing process, significant film shrinkage occurs. Because the fins are arranged in a regular single-crystal pattern, the internal stress generated during this process easily compresses the narrow-width fins, causing them to exhibit stacking fault defects related to crystal orientation (such as...). Figure 2 Process defects such as (as indicated by the arrow) and fin bending further alter the shape and size of the fins, ultimately affecting device performance.

[0005] Therefore, a method is needed to protect the fins and eliminate the adverse effects of the high-temperature curing and annealing process in the FCVD process on the fins.

[0006] It should be noted that the above introduction to the technical background is only for the purpose of providing a clear and complete explanation of the technical solutions of this application and facilitating understanding by those skilled in the art. It should not be assumed that these technical solutions are known to those skilled in the art simply because they have been described in the background section of this application. Summary of the Invention

[0007] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a fin transistor and its fabrication method, which solves the problem of stress causing defects in the fin body during the formation of the dielectric layer in the prior art.

[0008] To achieve the above and other related objectives, the present invention provides a method for fabricating a finned transistor, comprising the following steps:

[0009] S1: A semiconductor substrate is provided, on which fins are formed;

[0010] S2: Ion implantation is performed on the surface of the fin to achieve doping and form an amorphous layer;

[0011] S3: A dielectric layer is formed on the semiconductor substrate, and the dielectric layer fills the trench between the fins.

[0012] Preferably, the process further includes step S4: applying an annealing process to restore the amorphous layer to a single-crystal state.

[0013] Preferably, the method for forming the semiconductor substrate in step S1 includes the following steps:

[0014] S1-1: Provide a substrate material layer, and form an auxiliary material layer on the substrate material layer;

[0015] S1-2: Etch the auxiliary material layer to form a mandrel;

[0016] S1-3: A hard mask layer is deposited on the surface of the substrate material layer, as well as on the surface and sidewalls of the mandrel;

[0017] S1-4: The hard mask layer located on the surface of the mandrel and the surface of the substrate material layer is removed by etching, while the hard mask layer covering the sidewall of the mandrel is retained to form a sidewall;

[0018] S1-5: Remove the mandrel, and etch the substrate material layer using the sidewall as a mask to form the semiconductor substrate and the fins located on the semiconductor substrate.

[0019] Preferably, the thickness of the amorphous layer is 1–10 nm, and the doping concentration is 1e15–1e20 atom / cm. 3 .

[0020] Preferably, the temperature for ion implantation is 180–500°C.

[0021] Preferably, the doping element of the amorphous layer is germanium.

[0022] Preferably, during ion implantation, the angle between the direction of ion implantation and the surface of the fin is less than 30°.

[0023] The present invention also provides a finned transistor, the finned transistor comprising:

[0024] Semiconductor substrate;

[0025] A fin, the fin being located on the semiconductor substrate and having an amorphous layer formed on its surface;

[0026] A dielectric layer is formed on the semiconductor substrate and fills the trenches between the fins.

[0027] Preferably, the amorphous layer is formed by ion implantation on the surface of the fin.

[0028] Preferably, during ion implantation, the angle between the direction of ion implantation and the surface of the fin is less than 30°.

[0029] Preferably, the temperature for ion implantation is 180–500°C.

[0030] Preferably, the thickness of the amorphous layer is 1–10 nm, and the doping concentration is 1e15–1e20 atom / cm. 3 .

[0031] Preferably, the doping element of the amorphous layer is germanium.

[0032] As described above, this invention provides a finned transistor and its fabrication method. In this method, an amorphous layer is first formed by ion implantation on the surface of the fin, achieving an isolation effect. Subsequently, during the formation of the dielectric layer, the influence of internal stress on the fin is reduced, avoiding defects such as stacking faults and bending. Because the fin itself is a single-crystal material, its atoms are arranged in a periodic, ordered manner. Stress during dielectric layer deposition can easily extend along the crystal arrangement direction, causing significant crystal defects. In contrast, the amorphous layer has a significantly disordered atomic arrangement, thus dispersing stress and preventing it from extending deeply along certain directions, thereby avoiding crystal defects. Furthermore, high-temperature ion implantation is preferably used to form the amorphous layer, allowing it to recover to a single-crystal state during subsequent annealing processes (preferably peak annealing). Attached Figure Description

[0033] Figure 1 The diagram shows a schematic of the structure of a finned transistor in the prior art.

[0034] Figure 2 The image shown is an electron microscope image of crystal defects in a fin, as described in the prior art.

[0035] Figures 3-9 The diagram shows the manufacturing process of the fins in this invention.

[0036] Figure 10 The diagram shown illustrates the ion implantation of the fins in this invention.

[0037] Figure 11 The diagram shows a structural schematic of an amorphous layer forming on the surface of the fin.

[0038] Figure 12 The diagram shows a structure that forms a dielectric layer.

[0039] Figure 13 The images shown are electron microscope images of fins obtained by room temperature ion implantation combined with peak annealing and high temperature ion implantation combined with peak annealing.

[0040] Figure 14 The display shows a comparison of fin conductivity between room-temperature ion implantation combined with peak annealing and high-temperature ion implantation combined with peak annealing.

[0041] Component designation explanation

[0042] 11 Fins

[0043] 12 amorphous layers

[0044] 101 Semiconductor Substrate

[0045] 102 mandrels

[0046] 103 Side walls

[0047] 201 Dielectric Layer

[0048] 1011 Substrate Material Layer

[0049] 1021 Auxiliary Material Layer

[0050] 1031 Hard mask layer Detailed Implementation

[0051] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0052] In the detailed description of embodiments of the present invention, for ease of explanation, the cross-sectional views illustrating the device structure may be partially enlarged and not to scale. Furthermore, the schematic diagrams are merely examples and should not limit the scope of protection of the present invention. In actual fabrication, the three-dimensional spatial dimensions of length, width, and depth should be included.

[0053] For ease of description, spatial relation terms such as “below,” “under,” “lower than,” “below,” “above,” and “upper” may be used herein to describe the relationship between one element or feature shown in the accompanying drawings and other elements or features. It will be understood that these spatial relation terms are intended to include directions other than those depicted in the drawings for the device in use or operation. Furthermore, when a layer is referred to as being “between” two layers, it can be the only layer between the two layers, or there may be one or more layers in between. The phrase “between” as used herein includes both endpoint values.

[0054] In the context of this application, the structure described above the first feature may include embodiments in which the first and second features are formed in direct contact, or embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0055] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the illustrations only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0056] Example 1

[0057] like Figures 3-12 As shown, this embodiment provides a method for fabricating a finned transistor, specifically including the following steps:

[0058] S1: A semiconductor substrate is provided, on which fins are formed;

[0059] S2: Ion implantation is performed on the surface of the fin to achieve doping and form an amorphous layer;

[0060] S3: A dielectric layer is formed on the semiconductor substrate, and the dielectric layer fills the trench between the fins.

[0061] S4: Apply an annealing process to restore the amorphous layer to a single-crystal state.

[0062] Step S2 above involves doping the surface of the fin to form an amorphous layer, which effectively creates an isolation effect. This reduces the impact of internal stress on the fin during the subsequent formation of the dielectric layer, preventing defects such as stacking faults and bending. Because the fin itself is a single-crystal material with periodically ordered atomic arrangements, the stress during dielectric layer deposition easily extends along the crystal arrangement direction, causing significant crystal defects. In contrast, the amorphous layer exhibits significant atomic disorder, thus dispersing stress and preventing it from extending deeply along certain directions, thereby avoiding crystal defects.

[0063] The fabrication process of the semiconductor structure described in this invention will now be described in detail with reference to the accompanying drawings.

[0064] Specifically, the formation of the fin 11 in step S1 can be achieved through multiple patterning processes, such as dual patterning lithography (DPL) processes (including: photolithography-etch-photolithography-etch (LELE) process, self-aligned dual patterning (SADP) process, spacer-dielectric patterning (SIDP) process, other dual patterning processes, or combinations thereof), triple patterning processes (e.g., photolithography-etch-photolithography-etch-photolithography-etch (LELELE) process, self-aligned triple patterning (SATP) process, other triple patterning processes, or combinations thereof), other multiple patterning processes (e.g., self-aligned quadruple patterning (SAQP) process), or combinations thereof. Typically, multiple patterning processes combine photolithography and self-alignment processes, allowing the creation of patterns with smaller pitches, such as those achievable using a single direct photolithography process.

[0065] As one implementation method, taking the SADP process as an example, such as Figures 3-9 As shown, the method for forming the semiconductor substrate 101 with the fin 11 in step S1 is as follows:

[0066] S1-1: Provide a substrate material layer 1011, and form an auxiliary material layer 1021 on the substrate material layer 1011, such as... Figures 3-4 As shown;

[0067] S1-2: Etch the auxiliary material layer 1021 to form the mandrel 102, as shown. Figure 5 As shown;

[0068] S1-3: A hard mask layer 1031 is deposited on the surface of the substrate material layer 1011 and the surface and sidewalls of the mandrel 102, such as Figure 6 As shown;

[0069] S1-4: The hard mask layer 1031 located on the surface of the mandrel 102 and the substrate material layer 1011 is removed by etching, leaving the hard mask layer 1031 covering the sidewalls of the mandrel 102 to form sidewalls 103, such as... Figure 7 As shown;

[0070] S1-5: Remove the mandrel 102, and etch the substrate material layer 1011 using the sidewall 103 as a mask to form the semiconductor substrate 101 and the fins 11 located on the semiconductor substrate 101, such as Figures 8-9 As shown.

[0071] Specifically, the substrate material layer 1011 can be a single-layer or multi-layer structure, such as silicon, germanium, silicon-germanium, other suitable semiconductor materials, or combinations thereof. Depending on the design requirements of the fin transistor, the substrate material layer 1011 can include the same or different materials. Furthermore, the substrate material layer 1011 can also be a compound semiconductor, such as silicon carbide, silicon phosphide, gallium arsenide, or gallium phosphide; or it can be an alloy semiconductor, such as SiGe, SiPC, GaAsP, AlInAs, AlGaAs, GalnAs, GalnP, and / or GalnAsP. In this embodiment, the substrate material layer 1011 is preferably made of silicon.

[0072] The auxiliary material layer 1021 includes semiconductor and / or dielectric materials that achieve the desired etching selectivity, such as silicon, amorphous silicon, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, etc. The hard mask layer 1031 can be silicon nitride, silicon oxynitride, or silicon nitride. It should be understood that the auxiliary material layer 1021, the hard mask layer 1031, and the substrate material layer 1011 should be selected from different materials to achieve etching selectivity in the etching process. The auxiliary material layer 1021 and the hard mask layer 1031 can be formed by chemical vapor deposition (CVD), low-pressure CVD (LPCVD), plasma-enhanced CVD (PECVD), thermal nitriding, or other suitable processes. The deposition thickness of the hard mask layer 1031 in steps S1-3 determines the width of the sidewall 103, and thus the width of the sidewall 103 determines the final width of the fin 11. The formation density of the fin 11 can be controlled by the density of the mandrel 102. The size and density of the fin 11 can be adjusted according to actual needs, and no further restrictions are imposed here.

[0073] Furthermore, such as Figures 10-11As shown, in step S2, during the process of ion implantation to form an amorphous layer 12 on the surface of the fin 11, the angle between the ion implantation direction and the surface of the fin 11 is less than 30°; the doping concentration of the amorphous layer 12 is 1e15~1e20 atom / cm 3 The doping element is a group IV element such as Ge, which is in the same group as the substrate silicon material and can achieve better doping; the depth of ion implantation, i.e. the thickness of the amorphous layer 12, is 1 to 10 nm.

[0074] Specifically, ion implantation is a commonly used doping process in semiconductor device manufacturing, offering advantages such as precise control of impurity doping, good repeatability, and good uniformity. Charged ions, under the influence of electric and magnetic fields, enter the wafer with a certain amount of energy to achieve doping. After implantation, ions collide with silicon atoms, losing energy. Once depleted, the ions remain stationary at a specific location within the wafer. Through collisions with silicon atoms, the ions transfer energy to them, making silicon atoms new incident particles. These new incident ions then collide with other silicon atoms, creating a chain reaction. During ion implantation, the high-energy ion bombardment of the wafer surface can damage the crystal lattice structure, transforming a single-crystal structure into an amorphous state. Therefore, the implantation angle and depth must be controlled during ion implantation to avoid unnecessary lattice damage.

[0075] Furthermore, ion implantation in step S2 can be performed at room temperature (25–30°C) or at high temperature (180–500°C), preferably at high temperature, because the amorphous layer 12 formed at high temperature can be restored to a single-crystal state through the annealing process in step S4, preferably using a peak annealing process. Under peak annealing conditions, the amorphous layer can be brought back to a molten state, and the seed crystal therein can induce the amorphous layer to solidify in a single-crystal form again. This can also be understood as a high-temperature induced polycrystalline, i.e., mixed crystal, transformation to a high-temperature stable crystal form, similar to the process of heating and melting polycrystalline silicon and then solidifying it into a single-crystal silicon rod. During peak annealing, the wafer is heated to the set temperature at an extremely rapid heating rate, and then cooled at a relatively rapid cooling rate. Peak annealing can repair the lattice damage and defects caused by ion implantation, thereby restoring the amorphous layer to a single-crystal state.

[0076] like Figure 13As shown, this is a comparison of room-temperature ion implantation and high-temperature ion implantation, followed by peak annealing under the same conditions. It can be seen that room-temperature ion implantation combined with peak annealing does not effectively transform the amorphous layer into a single crystal (the single-crystal material layer of the fin is significantly thinner), while high-temperature ion implantation combined with peak annealing effectively restores the amorphous layer to a single-crystal state, and the conductivity is also significantly improved. Especially when the width of fin 11 is less than 20 nm, the conductivity of fin 11 after high-temperature ion implantation combined with peak annealing is about 5 times higher than that after room-temperature ion implantation combined with peak annealing, exhibiting better single-crystal doping characteristics. Figure 14 As shown in the figure, the horizontal axis represents the fin width, and the vertical axis represents the electrical conductivity. This is because room-temperature ion implantation causes greater damage to the crystal lattice compared to high-temperature ion implantation, making implantation defects more difficult to recover.

[0077] Furthermore, such as Figure 12 As shown, in step S3, the dielectric layer 201 fills the trenches between the fins 11 to form shallow trench isolation (STI), thereby electrically isolating the fins 11 from each other. The dielectric layer 201 includes an insulating material, such as silicon oxide, silicon nitride, or silicon oxynitride. The dielectric layer 201 is preferably silicon oxide. Preferably, the dielectric layer 201 is formed by flowable chemical vapor deposition (FCVD), using a flowable dielectric material to fill the trenches between the fins 11, avoiding voids.

[0078] In this embodiment, the preparation method first involves ion implantation on the surface of the fin to form an amorphous layer, thereby achieving an isolation effect. This reduces the impact of internal stress on the fin during the subsequent formation of the dielectric layer, preventing defects such as stacking faults and bending. Furthermore, high-temperature ion implantation is preferably used to form the amorphous layer, allowing it to be restored to a single-crystal state during the subsequent peak annealing process.

[0079] Example 2

[0080] This embodiment provides a finned transistor, such as Figure 12 As shown, the fin transistor can be formed by the fabrication method in Embodiment 1 above, but is not limited to the fabrication method in Embodiment 1 above. The fin transistor specifically includes:

[0081] Semiconductor substrate 101;

[0082] Fin 11, the fin 11 being located on the semiconductor substrate 101 and having an amorphous layer 12 formed on its surface;

[0083] Dielectric layer 201 is formed on the semiconductor substrate 101 and fills the trenches between the fins 11.

[0084] Specifically, the semiconductor substrate 101 and the fin 11 can be obtained by etching the substrate material layer 1011, for example by SADP process. The specific process can be referred to the relevant description in the above embodiment 1, and will not be elaborated here.

[0085] Furthermore, the amorphous layer 12 on the surface of the fin 11 is obtained by ion implantation. The angle between the direction of ion implantation and the surface of the fin 11 is less than 30°; the doping concentration of the amorphous layer 12 is 1e15~1e20 atom / cm. 3 The doping element is a group IV element such as Ge, which is in the same group as the substrate silicon material and can achieve better doping; the depth of ion implantation, i.e. the thickness of the amorphous layer 12, is 1 to 10 nm.

[0086] Specifically, ion implantation is a commonly used doping process in semiconductor device manufacturing, offering advantages such as precise control of impurity doping, good repeatability, and good uniformity. Charged ions, under the influence of electric and magnetic fields, enter the wafer with a certain amount of energy to achieve doping. After implantation, ions collide with silicon atoms, losing energy. Once depleted, the ions remain stationary at a specific location within the wafer. Through collisions with silicon atoms, the ions transfer energy to them, making silicon atoms new incident particles. These new incident ions then collide with other silicon atoms, creating a chain reaction. During ion implantation, the high-energy ion bombardment of the wafer surface can damage the crystal lattice structure, transforming a single-crystal structure into an amorphous state. Therefore, the implantation angle and depth must be controlled during ion implantation to avoid unnecessary lattice damage.

[0087] like Figure 13 As shown, this is a comparison of room-temperature ion implantation and high-temperature ion implantation followed by peak annealing under the same conditions. It can be seen that room-temperature ion implantation combined with peak annealing does not effectively transform the amorphous layer 12 into a single crystal, while high-temperature ion implantation combined with peak annealing effectively restores the amorphous layer 12 to a single-crystal state, and the conductivity is also significantly improved. Especially when the width of the fin 11 is less than 20 nm, the conductivity of the fin 11 after high-temperature ion implantation combined with peak annealing is about 5 times higher than that after room-temperature ion implantation combined with peak annealing, exhibiting better single-crystal doping characteristics. Figure 14 As shown. Compared to high-temperature ion implantation, room-temperature ion implantation causes greater damage to the crystal lattice, making implantation defects more difficult to recover.

[0088] Furthermore, the ion implantation process described above can be performed at room temperature (25–30°C) or at high temperature (180–500°C), preferably at high temperature, because the amorphous layer 12 formed at high temperature can be restored to a single-crystal state through subsequent peak annealing. Under peak annealing conditions, the amorphous layer 12 can be brought back to a molten state, and the seed crystal therein induces the amorphous layer 12 to solidify again in a single-crystal form. This can also be understood as a high-temperature induced transformation of polycrystalline, i.e., mixed crystal, into a high-temperature stable crystal form, similar to the process of heating and melting polycrystalline silicon and then solidifying it into a single-crystal silicon rod. During peak annealing, the wafer is heated to the set temperature at an extremely rapid rate and then cooled at a relatively rapid rate. Peak annealing can repair the lattice damage and defects caused by ion implantation, thereby restoring the amorphous layer 12 to a single-crystal state.

[0089] Furthermore, the dielectric layer 201 fills the trenches between the fins 11 to form shallow trench isolation (STI), thereby electrically isolating the fins 11 from each other. The dielectric layer 201 comprises an insulating material, such as silicon oxide, silicon nitride, or silicon oxynitride. The dielectric layer 201 is preferably silicon oxide. Preferably, the dielectric layer 201 is formed by fluid chemical vapor deposition (FCVD), using a flowable dielectric material to fill the trenches between the fins 11, avoiding voids.

[0090] The FinFET device described in this embodiment may be included in a microprocessor, memory, and / or other IC devices. In some embodiments, the FinFET device may be part of an IC chip, a system-on-a-chip (SoC), or a portion thereof, including various passive and active microelectronic devices such as resistors, capacitors, inductors, diodes, MOSFETs, CMOS transistors, bipolar junction transistors (BJTs), lateral diffused MOS transistors (LDMOS), high-voltage transistors, high-frequency transistors, etc.

[0091] In summary, this invention provides a finned transistor and its fabrication method. In this method, an amorphous layer is first formed by ion implantation on the surface of the fin, achieving an isolation effect. Subsequently, during the formation of the dielectric layer, the influence of internal stress on the fin is reduced, avoiding defects such as stacking faults and bending. Because the fin itself is a single-crystal material, its atoms are arranged in a periodic, ordered manner. Stress during dielectric layer deposition easily extends along the crystal arrangement direction, causing significant crystal defects. In contrast, the amorphous layer has a significantly disordered atomic arrangement, thus dispersing stress and preventing it from extending deeply along certain directions, thereby avoiding crystal defects. Furthermore, high-temperature ion implantation is preferably used to form the amorphous layer, allowing it to be restored to a single-crystal state during the subsequent peak annealing process.

[0092] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for fabricating a finned transistor, characterized in that, Includes the following steps: S1: A semiconductor substrate is provided, on which fins are formed; S2: Ion implantation is performed on the surface of the fin to form an amorphous layer; S3: A dielectric layer is formed on the semiconductor substrate, and the dielectric layer fills the trenches between the fins; the amorphous layer is used to form an isolation layer to reduce the stress effect on the fins when the dielectric layer is formed, and the ion implantation temperature is 180~500℃; S4: Apply an annealing process to restore the amorphous layer to a single-crystal state.

2. The preparation method according to claim 1, characterized in that, The method for forming the semiconductor substrate in step S1 includes the following steps: S1-1: Provide a substrate material layer, and form an auxiliary material layer on the substrate material layer; S1-2: Etch the auxiliary material layer to form a mandrel; S1-3: A hard mask layer is deposited on the surface of the substrate material layer, as well as on the surface and sidewalls of the mandrel; S1-4: The hard mask layer located on the surface of the mandrel and the surface of the substrate material layer is removed by etching, while the hard mask layer covering the sidewall of the mandrel is retained to form a sidewall; S1-5: Remove the mandrel, and etch the substrate material layer using the sidewall as a mask to form the semiconductor substrate and the fins located on the semiconductor substrate.

3. The preparation method according to claim 1, characterized in that, The thickness of the amorphous layer is 1~10 nm, and the doping concentration is 1e15~1e20 atom / cm². 3 .

4. The preparation method according to claim 1, characterized in that, The doping element of the amorphous layer is germanium.

5. The preparation method according to claim 1, characterized in that, During ion implantation, the angle between the direction of ion implantation and the surface of the fin is less than 30°.

6. The preparation method according to claim 1, characterized in that, The dielectric layer is formed by fluid chemical vapor deposition.

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