Dielectric Superjunction MIS Structure for Evaluating Superjunction Charge Balance and Testing Method

Abstract

The present invention discloses a dielectric superjunction MIS structure and a testing method for evaluating the charge balance of a superjunction, including an aluminum thin film on the back of a substrate, an N+-type silicon substrate, a superjunction N region, a superjunction P region, an insulating layer dielectric, a silicon oxide thin film, and a metal thin film, and comprising the steps of: (1) preparing a dielectric superjunction structure on an N+-type silicon substrate wafer, then growing a silicon oxide thin film on the surface of the superjunction structure, and then sputtering a metal thin film on the surface of the silicon oxide thin film and on the back of the N+-type substrate, so as to prepare a dielectric superjunction MIS structure device for electrical testing; (2) testing the forward bias and reverse bias C-V characteristic curves of the dielectric superjunction MIS structure under high-frequency conditions; (3) judging whether the superjunction structure maintains charge balance according to the tested C-V characteristic curves by comparing the magnitudes of the forward bias capacitance value and the reverse bias capacitance value. The present invention can judge the charge balance situation of the superjunction structure and the specific degree of imbalance of the N / P regions, and the judging method is simple and effective.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor technology, and in particular relates to a test structure and a test method for evaluating the charge balance of a superjunction. Background Art

[0002] National strategies such as "carbon peak", "carbon neutrality", and "new infrastructure" have put forward higher standards and more stringent requirements for the core of the new generation of power electronic devices - semiconductor power devices. The superjunction innovatively introduces a periodic charge balance mechanism into the traditional single-conducting resistive voltage withstand layer, turning it into a junction-type voltage withstand layer, breaking through the 2.5th power "silicon limit" relationship between the specific on-resistance and the breakdown voltage of traditional silicon unipolar power semiconductor devices, reducing it to a quasi-linear relationship of 1.32nd power or even 1.03rd power. Therefore, applying the superjunction technology to silicon power devices realizes the upgrade of silicon power devices, thus promoting the high-quality development of power devices from the bottom layer of the device.

[0003] The superjunction structure should satisfy the charge balance principle. For a superjunction with the same width of N / P regions, the concentrations of the N region and the P region should be equal. If the superjunction structure is in a charge non-equilibrium state, it will greatly affect its breakdown voltage, and the specific on-resistance will also be affected to a certain extent, making it difficult for the superjunction device to achieve excellent performance.

[0004] Therefore, when fabricating a superjunction device, it is extremely important to fully evaluate whether the superjunction region maintains charge balance, which is of great significance for the analysis, prediction of device performance, and improvement of the process.

[0005] During the fabrication process of a superjunction device, the charge balance of the superjunction structure is often evaluated by testing the breakdown voltage of the superjunction voltage withstand layer. However, this method has a rigid requirement, that is, the breakdown must occur in the cell region, so the terminal efficiency of the terminal region must be very high, which puts forward higher requirements for device designers and engineering experimenters. At the same time, even if the superjunction region is in charge non-equilibrium, this method cannot determine whether the concentration of the P region is too high or the concentration of the N region is too high, making it difficult to carry out the next device structure optimization and process optimization.

[0006] Therefore, exploring a simple and effective test structure and test method for evaluating the charge balance of the superjunction structure will be of great significance for the design and fabrication of superjunction power devices. Summary of the Invention

[0007] The purpose of the present invention is to propose a simple and effective test structure and test method for evaluating the charge balance of a superjunction, realizing the accurate evaluation of the charge balance of the N / P regions during the fabrication process of a superjunction device.

[0008] To achieve the above-mentioned invention purpose, the technical solution of the present invention is as follows:

[0009] A dielectric superjunction MIS structure for evaluating superjunction charge balance, comprising an aluminum thin film 7 on the back of the substrate, a silicon N+-type substrate 1 above the aluminum thin film 7 on the back of the substrate, alternately arranged superjunction N regions 2 and superjunction P regions 3 above the silicon N+-type substrate 1, an insulating layer dielectric 4 between the superjunction N regions 2 and the superjunction P regions 3, a silicon oxide thin film 5 above the superjunction N regions 2, the superjunction P regions 3, and the insulating layer dielectric 4, and a metal thin film 6 above the silicon oxide thin film 5.

[0010] As a preferred mode, the superjunction N region 2 and the superjunction P region 3 are one of a strip cell, a square cell, a hexagonal cell, and a grid cell.

[0011] As a preferred mode, the metal thin film 6 and the aluminum thin film 7 on the back of the substrate are aluminum foil films.

[0012] The present invention also provides a test method for a dielectric superjunction MIS structure for evaluating superjunction charge balance, comprising the following steps:

[0013] (1) Perform N-type epitaxy on an N+-type silicon wafer, etch trenches on the N-type epitaxy, then grow an insulating layer dielectric on the trenches, and then fill with P-type epitaxy to obtain a dielectric superjunction structure. Then grow a silicon oxide thin film on the surface of the superjunction structure, and then sputter a metal thin film on the surface of the silicon oxide thin film and the back of the N+-type substrate, thereby preparing a dielectric superjunction MIS structure device for electrical testing;

[0014] (2) Test the forward bias and reverse bias C-V characteristic curves of the dielectric superjunction MIS structure under high-frequency conditions;

[0015] (3) According to the measured C-V characteristic curves, when the forward bias reaches a certain value, the C-V curve remains horizontal and unchanged. Let the ratio of the measured capacitance to the silicon oxide capacitance of the insulating layer at this time be the forward bias capacitance value; when the reverse bias reaches a certain value, the C-V curve remains horizontal and unchanged. Let the ratio of the measured capacitance to the silicon oxide capacitance of the insulating layer at this time be the reverse bias capacitance value; by comparing the magnitudes of the forward bias capacitance value and the reverse bias capacitance value, the forward bias capacitance value is used to judge the doping situation of the P region, and the reverse bias capacitance value is used to judge the doping situation of the N region. If the two are equal, it means that the concentrations of the superjunction N region and the P region are equal, that is, the superjunction N / P region charge is balanced; if the forward bias capacitance value is greater than the reverse bias capacitance value, it means that the concentration of the P region is greater than that of the N region; if the reverse bias capacitance value is greater than the forward bias capacitance value, it means that the concentration of the N region is greater than that of the P region; if the charges in the N region and the P region are unbalanced, the specific degree of imbalance is deduced through the forward bias capacitance value and the reverse bias capacitance value formula.

[0016] As a preferred mode, in step (3), the forward bias capacitance value C + is obtained by the following formula:

[0017]

[0018] Negative bias capacitance value C - is obtained by the following formula:

[0019]

[0020] Silicon dioxide insulation layer capacitance C 0 is obtained by the following formula:

[0021]

[0022] where A is the area of the superjunction structure covered by the silicon dioxide insulation layer, C 0 is the silicon dioxide insulation layer capacitance, d 0 is the thickness of the silicon dioxide insulation layer; ε r0 is the relative dielectric constant of silicon dioxide, ε rs is the relative dielectric constant of silicon, ε 0 is the dielectric constant; N N is the doping concentration of the superjunction N region, N P is the doping concentration of the superjunction P region, A N is the area of the metal thin film covering the superjunction N region, A P is the area of the metal thin film covering the superjunction P region; q is the elementary charge, k 0 is the Boltzmann constant, T is the temperature, n i is the intrinsic carrier concentration.

[0023] As a preferred method, in step (1), the process for preparing the dielectric superjunction structure is trench etching - dielectric growth - epitaxial backfilling method.

[0024] As a preferred method, in step (1), the thickness of the insulation layer dielectric growth is 30 - 60 nm;

[0025] And / or the thickness of the silicon dioxide thin film is 20 - 40 nm;

[0026] And / or the thickness of the metal thin film is 50 - 100 nm.

[0027] As a preferred method, in step (1), the growth of the silicon dioxide thin film (5) is dry oxidation or wet oxidation;

[0028] And / or the growth of the metal thin film (6), the backside metal thin film (7) of the substrate is by magnetron sputtering method, electron beam evaporation method.

[0029] As a preferred method, in step (2), the frequency of the high frequency is 100 kHz.

[0030] As a preferred method, in step (2), the range of the positive bias voltage is between 0 - 20 V; the range of the negative bias voltage is between - 20 - 0 V.

[0031] The beneficial effects of the present invention are as follows: A test method for evaluating the charge balance of a superjunction structure based on a dielectric superjunction MIS structure is proposed, which realizes the accurate evaluation of the charge balance of the N / P regions during the preparation of superjunction devices, facilitating the next-step optimization of device structure and process. Compared with the method of judging whether the superjunction structure maintains charge balance by testing the breakdown voltage of the superjunction voltage-resistant layer, the test method proposed by the present invention requires a simple test structure preparation, has more accurate test results, and is convenient for popularization and use in the academic and industrial circles. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 is a schematic flow chart of the present invention;

[0033] Figure 2 is a dielectric superjunction MIS structure diagram of Embodiment 3;

[0034] Figure 3 is a high-frequency C-V curve of the dielectric superjunction MIS structure test of Embodiment 3;

[0035] Figure 4 is a decomposition diagram of the high-frequency C-V curve of the dielectric superjunction MIS structure test of Embodiment 3;

[0036] Figure 5 is a high-frequency C-V curve of the dielectric superjunction MIS structure of Embodiment 3 where the N-region concentration is equal to the P-region concentration;

[0037] Figure 6 is a high-frequency C-V curve of the dielectric superjunction MIS structure of Embodiment 3 where the P-region concentration is greater than the N-region concentration;

[0038] Figure 7 is a high-frequency C-V curve of the dielectric superjunction MIS structure of Embodiment 3 where the N-region concentration is greater than the P-region concentration.

[0039] 1 is a silicon N+-type substrate, 2 is a superjunction N-region, 3 is a superjunction P-region, 4 is an insulating layer dielectric, 5 is a silicon oxide film, 6 is a metal film, and 7 is a metal film on the back of the substrate. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0040] The present invention will be further described below in conjunction with the accompanying drawings of the specification and the specific embodiments.

[0041] Embodiment 1

[0042] This embodiment provides a dielectric superjunction MIS structure for evaluating superjunction charge balance, including an aluminum thin film 7 on the back of the substrate, a silicon N+-type substrate 1 above the metal thin film 7 on the back of the substrate, alternately arranged superjunction N regions 2 and superjunction P regions 3 above the silicon N+-type substrate 1, an insulating layer dielectric 4 between the superjunction N region 2 and the superjunction P region 3, a silicon oxide thin film 5 above the superjunction N region 2, the superjunction P region 3, and the insulating layer dielectric 4, and a metal thin film 6 above the silicon oxide thin film 5.

[0043] The superjunction N region 2 and the superjunction P region 3 are one of a strip-shaped cell, a square cell, a hexagonal cell, and a grid-shaped cell.

[0044] The metal thin film 6 and the metal thin film 7 on the back of the substrate are aluminum foil films.

[0045] Embodiment 2

[0046] This embodiment provides a test method for a dielectric superjunction MIS structure for evaluating superjunction charge balance, including the following steps:

[0047] (1) Perform N-type epitaxy on an N+-silicon substrate wafer, etch trenches on the N-type epitaxy, then grow an insulating layer dielectric on the trenches, and then fill with P-type epitaxy to obtain a dielectric superjunction structure. Then grow a silicon oxide thin film on the surface of the superjunction structure, and then sputter a metal thin film on the surface of the silicon oxide thin film and the back of the N+-substrate, thereby preparing a dielectric superjunction MIS structure device for electrical testing;

[0048] (2) Test the forward bias and reverse bias C-V characteristic curves of the dielectric superjunction MIS structure under high-frequency conditions;

[0049] (3) According to the measured C-V characteristic curves, when the forward bias reaches a certain value, the C-V curve remains horizontal and unchanged. Let the ratio of the measured capacitance to the insulating layer silicon oxide capacitance at this time be the forward bias capacitance value; when the reverse bias reaches a certain value, the C-V curve remains horizontal and unchanged. Let the ratio of the measured capacitance to the insulating layer silicon oxide capacitance at this time be the reverse bias capacitance value; by comparing the magnitudes of the forward bias capacitance value and the reverse bias capacitance value, the forward bias capacitance value is used to judge the doping situation of the P region, and the reverse bias capacitance value is used to judge the doping situation of the N region. If the two are equal, it means that the concentrations of the superjunction N region and the P region are equal, that is, the superjunction N / P region charge is balanced; if the forward bias capacitance value is greater than the reverse bias capacitance value, it means that the concentration of the P region is greater than that of the N region; if the reverse bias capacitance value is greater than the forward bias capacitance value, it means that the concentration of the N region is greater than that of the P region; if the charges in the N region and the P region are unbalanced, the specific degree of imbalance is deduced through the forward bias capacitance value and the reverse bias capacitance value formula.

[0050] In step (3), the forward bias capacitance value C + is obtained by the following formula:

[0051]

[0052] Negative bias capacitance value C - Is obtained by the following formula:

[0053]

[0054] Insulating layer silicon oxide capacitance C 0 Is obtained by the following formula:

[0055]

[0056] Wherein, A is the area of the superjunction structure covered by the insulating layer silicon oxide, C 0 Is the insulating layer silicon oxide capacitance, d 0 Is the thickness of the insulating layer silicon oxide; ε r0 Is the relative dielectric constant of silicon oxide, ε rs Is the relative dielectric constant of silicon, ε 0 Is the dielectric constant; N N Is the doping concentration of the superjunction N region, N P Is the doping concentration of the superjunction P region, A N Is the area of the metal thin film covering the superjunction N region, A P Is the area of the metal thin film covering the superjunction P region; q is the elementary charge, k 0 Is the Boltzmann constant, T is the temperature, n i Is the intrinsic carrier concentration.

[0057] In step (1), the process for preparing the dielectric superjunction structure is trench etching - dielectric growth - epitaxial backfilling method.

[0058] In step (1), the thickness of the insulating layer dielectric growth is 30 - 60 nm;

[0059] And / or the thickness of the silicon oxide thin film is 20 - 40 nm;

[0060] And / or the thickness of the metal thin film is 50 - 100 nm.

[0061] In step (1), the growth of the silicon oxide thin film 5 is dry oxygen oxidation or wet oxygen oxidation;

[0062] And / or the growth of the metal thin film 6 and the backside metal thin film 7 of the substrate is by magnetron sputtering method, electron beam evaporation method.

[0063] In step (2), the frequency of the high frequency is 100 kHz.

[0064] In step (2), the range of the positive bias voltage is between 0 - 20 V; the range of the negative bias voltage is between -20 - 0 V.

[0065] Example 3

[0066] This embodiment provides a test method for evaluating the charge balance of a dielectric superjunction MIS structure, including the following steps:

[0067] (1) Use the trench etching - dielectric growth - epitaxial backfilling method to prepare a dielectric superjunction structure on a silicon N+-type substrate 1. The superjunction cell structure is a strip cell. It is required that the widths of the superjunction N region 2 and the superjunction P region 3 are the same. For a structure with different widths of the superjunction N / P regions, its analysis method is similar to that of a structure with the same N / P width. The thickness of the grown dielectric 4 is 40 nm. Then, use the dry oxidation method to grow a 30-nm-thick silicon oxide film 5 on the surface of the prepared dielectric superjunction structure, and it is required that the number of superjunction N regions and P regions covered by the silicon oxide film is equal. Subsequently, use the magnetron sputtering method to sputter a 50-nm aluminum metal film 6 on the surface of the silicon oxide film and a 50-nm aluminum backside metal film 7 on the backside of the substrate, thereby preparing an aluminum - silicon oxide - silicon dielectric superjunction MIS structure, as Figure 2 shown.

[0068] (2) Conduct a high-frequency C-V characteristic curve test on the prepared dielectric superjunction MIS structure. The corresponding curve is as Figure 3 shown. The abscissa is the voltage, and the ordinate is the ratio of the measured capacitance C to the capacitance C 0 of the insulating layer silicon oxide. The positive half-axis of the abscissa is used to evaluate the concentration of the P region of the superjunction MIS structure, and the negative half-axis of the abscissa is used to evaluate the concentration of the N region of the superjunction MIS structure. Read the positive bias capacitance value and the negative bias capacitance value respectively. The overall C-V characteristic curve graph can be decomposed into the superposition of the C-V curves of all N regions of the dielectric superjunction MIS structure and the superposition of the C-V curves of all P regions of the dielectric superjunction MIS structure, as Figure 4 shown.

[0069] (3) According to the measured C-V characteristic curve, when the positive bias voltage reaches a certain value, the C-V curve remains horizontal and unchanged. Let the ratio of the measured capacitance to the capacitance of the insulating layer silicon oxide at this time be the positive bias capacitance value; when the negative bias voltage reaches a certain value, the C-V curve remains horizontal and unchanged. Let the ratio of the measured capacitance to the capacitance of the insulating layer silicon oxide at this time be the negative bias capacitance value. By comparing the magnitudes of the positive bias capacitance value and the negative bias capacitance value, the positive bias capacitance value is used to judge the doping situation of the P region, and the negative bias capacitance value is used to judge the doping situation of the N region. If the two are equal, it means that the concentrations of the superjunction N region and the P region are equal, that is, the superjunction N / P region charge is balanced, as Figure 5 shown; if the positive bias capacitance value is greater than the negative bias capacitance value, it means that the concentration of the P region is greater than that of the N region, as Figure 6 shown; if the negative bias capacitance value is greater than the positive bias capacitance value, it means that the concentration of the N region is greater than that of the P region, as Figure 7 shown; if the charges in the N region and the P region are unbalanced, the specific degree of imbalance is deduced through the positive bias capacitance value and the negative bias capacitance value formula.

[0070] In step (3), the positive bias capacitance value C + is obtained by the following formula:

[0071]

[0072] The negative bias capacitance value C - is obtained by the following formula:

[0073]

[0074] The insulating layer silicon oxide capacitance C 0 is obtained by the following formula:

[0075]

[0076] where A is the area of the superjunction structure covered by the insulating layer silicon oxide, C 0 is the insulating layer silicon oxide capacitance, d 0 is the thickness of the insulating layer silicon oxide; ε r0 is the relative dielectric constant of silicon oxide, ε rs is the relative dielectric constant of silicon, ε 0 is the permittivity; N N is the doping concentration of the superjunction N region, N P is the doping concentration of the superjunction P region, A N is the area of the metal thin film covering the superjunction N region, A P is the area of the metal thin film covering the superjunction P region; q is the elementary charge, k 0 is the Boltzmann constant, T is the temperature, n i is the intrinsic carrier concentration.

[0077] (4) If the N / P region charges are unbalanced, the concentration of the N region and the P region can be calculated by substituting the measured positive bias capacitance value and negative bias capacitance value into the positive bias capacitance value C + and the negative bias capacitance value C - formulas, so as to determine the specific degree of unbalance value.

[0078] The test structure and test method for evaluating the superjunction charge balance proposed by the present invention require simple preparation of the test structure, and the test results are more accurate, which is convenient for popularization and use in the academic and industrial circles.

[0079] The above description taking silicon as the semiconductor material is only the preferred embodiment of the present invention, and is not used to limit the present invention. Other mainstream semiconductor materials are still applicable. For those skilled in the art, the present invention can have various changes and modifications. Any modification made within the spirit and principle of the present invention is within the protection scope of the present invention.

Claims

1. A test method for evaluating the charge balance of a dielectric superjunction MIS structure of a superjunction, characterized in that, it includes the following steps: (1) Perform N-type epitaxy on an N+ silicon substrate wafer, etch trenches on the N-type epitaxy, then grow an insulating layer dielectric on the trenches, and then fill with P-type epitaxy to obtain a dielectric superjunction structure. Then grow a silicon oxide film on the surface of the superjunction structure, and then sputter a metal film on the surface of the silicon oxide film and the back of the N+ substrate, thereby preparing a dielectric superjunction MIS structure device for electrical testing; (2) Test the forward bias and reverse bias C-V characteristic curves of the dielectric superjunction MIS structure under high-frequency conditions; (3) According to the measured C-V characteristic curves, when the forward bias reaches a certain value, the C-V curve remains horizontal and unchanged. Let the ratio of the measured capacitance to the silicon oxide capacitance of the insulating layer at this time be the forward bias capacitance value; when the reverse bias reaches a certain value, the C-V curve remains horizontal and unchanged. Let the ratio of the measured capacitance to the silicon oxide capacitance of the insulating layer at this time be the reverse bias capacitance value; by comparing the magnitudes of the forward bias capacitance value and the reverse bias capacitance value, the forward bias capacitance value is used to judge the doping situation of the P region, and the reverse bias capacitance value is used to judge the doping situation of the N region. If the two are equal, it means that the concentrations of the superjunction N region and P region are equal, that is, the superjunction N / P region charge is balanced; if the forward bias capacitance value is greater than the reverse bias capacitance value, it means that the concentration of the P region is greater than that of the N region; if the reverse bias capacitance value is greater than the forward bias capacitance value, it means that the concentration of the N region is greater than that of the P region; if the N region and P region charges are unbalanced, the specific degree of imbalance is deduced through the forward bias capacitance value and reverse bias capacitance value formulas.

2. The test method for evaluating the charge balance of a dielectric superjunction MIS structure of a superjunction according to claim 1, characterized in that, In step (3), the positive bias capacitance value C + is obtained by the following formula: Negative bias capacitance value C - Obtained from the following formula: Insulating layer silicon oxide capacitor C 0 Obtained by the following formula: Among them, A is the area of the superjunction structure covered by the insulating layer of silicon oxide, C 0 is the capacitance of the insulating layer of silicon oxide, d 0 is the thickness of the insulating layer of silicon oxide; ε r0 is the relative permittivity of silicon oxide, ε rs is the relative permittivity of silicon, ε 0 is the permittivity; N N is the doping concentration of the superjunction N region, N P is the doping concentration of the superjunction P region, A N is the area of the metal thin film covering the superjunction N region, A P is the area of the metal thin film covering the superjunction P region; q is the elementary charge, k 0 is the Boltzmann constant, T is the temperature, n i is the intrinsic carrier concentration.

3. The test method for evaluating the charge balance of a dielectric superjunction MIS structure of a superjunction according to claim 1, characterized in that, in step (1), the process for preparing the dielectric superjunction structure is the trench etching-dielectric growth-epitaxial backfilling method.

4. The test method for evaluating the charge balance of a dielectric superjunction MIS structure of a superjunction according to claim 1, characterized in that, in step (1), the thickness of the insulating layer dielectric growth is 30 - 60 nm; and / or the thickness of the silicon oxide film is 20 - 40 nm; and / or the thickness of the metal film is 50 - 100 nm.

5. The test method for evaluating the charge balance of a dielectric superjunction MIS structure of a superjunction according to claim 1, characterized in that, in step (1), the growth of the silicon oxide film (5) is by dry oxidation or wet oxidation; and / or the growth of the metal film (6) and the back metal film of the substrate (7) is by magnetron sputtering method or electron beam evaporation method.

6. The test method for evaluating the charge balance of a dielectric superjunction MIS structure of a superjunction according to claim 1, characterized in that, in step (2), the frequency of the high frequency is 100 kHz.

7. The test method for evaluating the charge balance of a dielectric superjunction MIS structure of a superjunction according to claim 1, characterized in that, in step (2), the range of the forward bias is between 0 - 20 V; the range of the reverse bias is between -20 - 0 V.

8. The test method for evaluating the charge balance of a dielectric superjunction MIS structure of a superjunction according to claim 1, characterized in that: The dielectric superjunction MIS structure includes a metal thin film (7) on the back of the substrate, a silicon N+-type substrate (1) above the metal thin film (7) on the back of the substrate, an alternately arranged superjunction N region (2) and superjunction P region (3) above the silicon N+-type substrate (1), an insulating layer dielectric (4) between the superjunction N region (2) and the superjunction P region (3), a silicon oxide thin film (5) above the superjunction N region (2), the superjunction P region (3), and the insulating layer dielectric (4), and a metal thin film (6) above the silicon oxide thin film (5).

9. The test method for evaluating the charge balance of a dielectric superjunction MIS structure of a superjunction according to claim 8, characterized in that: The superjunction N region (2) and the superjunction P region (3) are one of a strip cell, a square cell, a hexagonal cell, and a grid cell.

10. The test method for evaluating the charge balance of a dielectric superjunction MIS structure of a superjunction according to claim 8, characterized in that: The metal thin film (6) and the metal thin film (7) on the back of the substrate are aluminum foil films.

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