Semiconductor device and method for forming the same

Abstract

This application discloses a semiconductor device and a method for forming the same. The method comprises: providing a substrate having a conductive plug disposed therein, the substrate including a plurality of protrusions, the conductive plug being located between two adjacent protrusions; forming a first metal layer covering at least the top corners of each protrusion; forming a second metal layer covering the top of the conductive plug; performing an annealing process so that the second metal layer on the top of the conductive plug reacts with the conductive plug to form a metal silicide; and removing the remaining first and second metal layers after the annealing process. This application can improve the conductivity of the conductive plug and the corresponding contact layer.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor device and a method for forming the same. Background Art

[0002] Conductive plugs are essential components of semiconductor structures, such as memory and / or transistors. They interconnect various layers within the semiconductor structure and ensure operational reliability. The inventors have discovered that in some semiconductor structures, conductive plugs exhibit poor electrical conductivity. Summary of the Invention

[0003] In view of this, the present application provides a semiconductor device and a method for forming the same to solve the problem of poor conductivity of contact plugs in some semiconductor structures.

[0004] The present application provides a method for forming a semiconductor device, comprising:

[0005] Providing a substrate, wherein a conductive plug is provided in the substrate, the substrate comprising a plurality of convex pillars, and the conductive plug is located between two adjacent convex pillars;

[0006] forming a first metal layer covering at least the top corners of each of the convex pillars;

[0007] forming a second metal layer covering a top portion of the conductive plug;

[0008] performing an annealing process so that the second metal layer on the top of the conductive plug reacts with the conductive plug to form a metal silicide;

[0009] The first metal layer and the second metal layer remaining after the annealing process are removed.

[0010] Optionally, the method of forming the first metal layer covering at least the top corners of each of the convex pillars further comprises: sputtering a first metal onto the top of the convex pillars to obtain the first metal layer covering the top surface and corners of the convex pillars.

[0011] Optionally, the thickness of the first metal layer is smaller than the thickness of the second metal layer.

[0012] Optionally, the thickness of the first metal layer ranges from 1 nm to 3 nm.

[0013] Optionally, the temperature at which the first metal layer is formed is lower than the temperature at which the second metal layer is formed.

[0014] Optionally, both sides of the convex column include a spacer layer, and an oxide layer is provided in the spacer layer.

[0015] Optionally, the first metal layer at least covers the top of the spacer layer along the protruding direction of the convex column.

[0016] Optionally, the oxide layer is exposed at a corner of the top of the convex column.

[0017] Optionally, the method of forming the second metal layer covering the top of the conductive plug further includes: depositing a second metal on the top of the conductive plug to obtain the second metal layer covering the conductive plug.

[0018] Optionally, after forming the first metal layer that at least covers the top corners of each of the convex pillars, the forming method further comprises: performing a pre-cleaning process on the substrate and the first metal layer by using a dry etching method.

[0019] Optionally, the material of the first metal layer includes at least one of cobalt, titanium, nickel and manganese; and / or the material of the second metal layer includes at least one of cobalt, titanium, nickel and manganese.

[0020] Optionally, the conductive plug is made of polysilicon or doped polysilicon.

[0021] Optionally, the method of performing the annealing process further includes: performing an annealing process to cause the top of the conductive plug to react with the second metal layer in contact therewith to obtain a reacted metal silicide.

[0022] The present application also provides a semiconductor device, comprising:

[0023] A substrate, wherein a conductive plug is provided in the substrate, the substrate includes a plurality of convex pillars, and the conductive plug is located between two adjacent convex pillars;

[0024] The interconnection contact layer is located on the surface of the conductive plug. After the corner of the top of the convex column is covered by the first metal layer, the interconnection contact layer is formed by the reaction of the second metal layer covering the top of the conductive plug with the conductive plug.

[0025] The semiconductor device and its formation method form a first metal layer on the surface of the protrusion of the substrate, covering at least the top corners of each protrusion, to isolate the oxide layer exposed at the corners of the protrusion and prevent the transfer of oxygen in the oxide layer during related processes; then form a second metal layer covering the top of the conductive plug, and perform an annealing process on the entire substrate to cause the second metal layer on the top of the conductive plug to react with the conductive plug to form a metal silicide. The second metal layer does not contact the oxygen in the oxide layer and is not oxidized by this oxygen, thereby reducing the resistivity of the resulting metal silicide and improving the conductivity of the resulting contact layer and the corresponding conductive plug. At this time, the first metal layer and the second metal layer remaining after the annealing process are removed, and the metal silicide is retained as the contact layer on the surface of the conductive plug. The contact layer has good conductivity and high stability, thereby optimizing the performance of the corresponding semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0027] Figure 1a 、 Figure 1b 、 Figure 1c and Figure 1d It is a schematic diagram of a conductive plug and related structures in a semiconductor device;

[0028] Figure 2 This is a flow chart of a method for forming a semiconductor device in one embodiment of the present application;

[0029] Figure 3a 、 Figure 3b 、 Figure 3c 、 Figure 3d 、 Figure 3e 、 Figure 3f 、 Figure 3g 、 Figure 3h and Figure 3i This is a schematic diagram of the structures obtained in each step of an embodiment of the present application. DETAILED DESCRIPTION

[0030] The inventors have found that in most semiconductor devices, the conductive plug is usually set in the groove of the semiconductor structure. Figure 1a As shown, the groove is located between two adjacent protrusions, and the protrusion may include an insulating sidewall layer. The surface of the conductive plug has a contact layer, which is connected to the interconnected object above through the contact layer to achieve the corresponding connection function. The inventor found that some solutions form a metal layer on the surface of the conductive plug. Figure 1bAs shown, the metal layer is subjected to annealing and other heat treatments to convert the metal layer into a corresponding metal silicide, which becomes the contact layer on the surface of the conductive plug. Figure 1c The inventors studied the process of forming the contact layer and found that in some semiconductor structures, such as Figure 1a As shown, the two sides of the column include a spacer layer, the middle of the spacer layer includes an oxide layer, and the oxide layer is exposed at the corner of the column. The corner of the column may be bombarded by corresponding ions during sputtering and / or cleaning processes, refer to Figure 1d As shown in the figure, when the oxide layer exposed at the corner of the protrusion is bombarded by ions, the oxygen element ( Figure 1d The Ox shown in FIG2 will be transferred to the surface of the conductive plug and react with the metal and other elements on the surface of the conductive plug to form metal oxides, which will increase the resistivity of the conductive plug and thus affect the conductive performance of the entire conductive plug.

[0031] To address the above-mentioned problem, the present application forms a first metal layer on the surface of the protrusion of the substrate, covering at least the top corners of each protrusion, so as to isolate the oxide layer exposed at the corners of the protrusion and prevent the oxygen elements in the oxide layer from being transferred during the relevant process; then forms a second metal layer covering the top of the conductive plug, and performs an annealing process on the substrate to cause the second metal layer on the top of the conductive plug to react with the conductive plug to form a metal silicide, wherein the second metal layer will not contact the oxygen elements in the oxide layer and will not be oxidized by this part of the oxygen elements, which can reduce the resistivity of the obtained metal silicide and improve the conductivity of the formed contact layer and the corresponding conductive plug.

[0032] The following, in conjunction with the accompanying drawings, clearly and completely describes the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of this application. In the absence of conflict, the following embodiments and their technical features can be combined with each other.

[0033] In a first aspect, the present application provides a method for forming a semiconductor device, referring to Figure 2 As shown, the forming method includes S110 to S150.

[0034] S110, reference Figure 3a As shown, a substrate 210 is provided, wherein a conductive plug 211 is disposed in the substrate 210 . The substrate 210 includes a plurality of protrusions 212 , and the conductive plug 211 is located between two adjacent protrusions 212 .

[0035] The above-mentioned convex pillars 212 can also be called insulating sidewall layers. There is a groove 213 between two adjacent convex pillars 212, and the conductive plug 211 is arranged in the groove 213. Optionally, a functional structure such as a gate can be provided inside the convex pillars 212, such as Figure 3a As shown, a spacer layer 214 is provided on both sides of the convex column 212. The spacer layer 214 may include a dielectric layer or other structure having an isolation function. Figure 3b As shown, an oxide layer 214a is provided in the spacer layer 214, and the oxide layer 214a is exposed at the corner 215 of the protrusion 212. The inventors found during the research process that the corner 215 of the protrusion 212 may be bombarded by corresponding ions during the sputtering and / or cleaning process. Figure 1d As shown, when the oxide layer 214 a exposed at the corner 215 is bombarded by ions, oxygen elements are easily transferred to the surface of the electrical plug 211 and react with metal elements and other elements on the surface of the conductive plug 211 to form metal oxides, thereby increasing the resistivity of the surface of the conductive plug 211 and affecting the conductive performance of the surface of the conductive plug 211, thereby affecting the conductive performance of the entire conductive plug 211.

[0036] Optionally, the substrate 210 may further include electrodes, bit lines and / or other functional areas that need to be interconnected with other devices (not shown in the figure). Figure 3c As shown, the substrate 210 may include an active area 215 and an isolation area 214. The active area 215 may form a corresponding functional area within the substrate 210. The isolation area 214 may be an STI (shallow trench) isolation structure. The isolation area 214 may isolate each active area. The conductive plug 211 contacts the active area 215 and the isolation area 214 respectively, so that the conductive plug 211 can independently contact the corresponding active area 215 and electrically lead the corresponding active area 215. Specifically, as Figure 3c As shown, adjacent conductive plugs 211 contact the isolation region 214 where they are close to each other, and contact the active region 215 where they are far away from each other, so that the arrangement of the active region 215 and the isolation region 214 is more regular, which can further ensure the stability of the corresponding interconnection characteristics.

[0037] Optionally, the conductive plug 211 may be formed by filling the groove 213 with a conductive material and / or a semiconductor material. The groove 213 may be in the shape of a long strip or a through-hole. The conductive plug 211 may also contact at least one interconnected object to provide an interconnection interface for the interconnected object in contact, so that other devices can be interconnected with the interconnected object through the conductive plug 211. The above-mentioned interconnected object may include a doped region (such as an active region 215) located in the substrate 210, and the conductive plug 211 may be formed on the surface of the doped region in the substrate 210 to electrically lead out the doped region.

[0038] Optionally, the conductive plug 211 is made of polysilicon, doped polysilicon, or other silicon-containing conductive materials. Optionally, the conductive plug 211 is made of polysilicon so that the conductive plug 211 has good conductivity and can react with the metal layer on top of it through an annealing process to obtain the desired metal silicide.

[0039] Optionally, refer to Figure 3d As shown, part of the side surface of the upper end of the conductive plug 211 is opposite to the protrusion 212 and contacts the protrusion 212 .

[0040] In one embodiment, after step S110 , the above-mentioned forming method may further include: cleaning the substrate 210 to remove impurities on the surface of the substrate 210 and improve the quality of the structure formed by subsequent processes.

[0041] S120, reference Figure 3e As shown, a first metal layer 221 is formed to cover at least the top corners 215 of each protrusion 212 .

[0042] Optionally, the first metal layer 221 covers at least the top portion of the spacer layer 214 along the protruding direction of the protrusion 212. Optionally, the oxide layer 214a is exposed at the corner 215 of the top of the protrusion 212. In this way, the first metal layer 221 can cover the oxide layer 214a exposed at the top corner 215 to isolate the oxide layer 214a and prevent the oxygen element in the oxide layer 214a from being transferred during related processes, thereby preventing the metal and other elements on the surface of the conductive plug 211 from being oxidized. This ensures or optimizes the conductive properties of the subsequently formed contact layer.

[0043] Optionally, step S120 can form the first metal layer 221 using a deposition or sputtering process. Optionally, when forming the first metal layer 221 using a deposition process, the first bias voltage used can be a relatively low bias voltage, resulting in a relatively slow formation rate. This allows the first metal layer 221 to cover only the top of the protrusion 212, simplifying the process and saving material while still covering the corner 215. Optionally, the first bias voltage can range from 0 to 5V (volts), for example, the first bias voltage can be 0V, 3V, or 5V. Optionally, step S120 can form the first metal layer 221 in a relatively low temperature environment to prevent the first metal layer 221 from reacting with related structures such as the semiconductor material in contact, ensuring the stability of related structures in the substrate 210 during the process. It can also reduce the environmental requirements for forming the first metal layer 221. For example, when forming the first metal layer 221, the surface temperature of the substrate 210 can be below 350°C (degrees Celsius), effectively preventing the first metal layer 221 from thermally reacting with materials such as polysilicon in contact.

[0044] Optionally, the material of the first metal layer 221 includes at least one of cobalt, titanium, nickel and manganese.

[0045] In one embodiment, the method of forming a first metal layer 221 that covers at least the top corners 215 of each boss 212 further includes: sputtering a first metal onto the top of the boss 212 to obtain a first metal layer 221 covering the top surface of the boss 212 and the corners 215, so that the first metal layer 221 can isolate the oxide layer 214a exposed at the corners 215, and prevent the oxygen element in the oxide layer 214a from being transferred during the related process.

[0046] Optionally, the thickness of the first metal layer 221 is relatively small, so as to simplify the corresponding formation process and save materials based on the oxide layer 214a exposed at the isolation corner 215. Optionally, the thickness of the first metal layer 221 ranges from 1 nm (nanometer) to 3 nm. For example, the thickness of the first metal layer 221 can be 1 nm, 2 nm, or 3 nm.

[0047] In one embodiment, after step S120 , the above formation method may further include: after forming the first metal layer 221 , cleaning the current semiconductor device to make the surface of the conductive plug 211 cleaner and further improve the quality of the contact layer formed subsequently.

[0048] In one embodiment, after step S120, the formation method further includes: pre-cleaning the substrate 210 and the first metal layer 221 using a dry etching method to further improve the cleanliness of the substrate 210 and the first metal layer 221, thereby improving the quality of the contact layer formed subsequently. Optionally, the dry etching method may include an ion sputtering method corresponding to an inert gas such as argon ion sputtering to ensure stability during the cleaning process.

[0049] S130, reference Figure 3f As shown, a second metal layer 222 is formed to cover the top of the conductive plug 211 .

[0050] The second metal layer 222 is used to thermally react with the conductive plug 211 in contact therewith to form a metal silicide, which forms a contact layer on top of the conductive plug 211. Optionally, the material of the second metal layer 22 includes at least one of cobalt, titanium, nickel, and manganese, so that the subsequently formed metal silicide has good conductivity and stability. Optionally, the first metal layer 221 and the second metal layer 222 are made of the same material, so that the corresponding structures are formed using the same material, which helps simplify the relevant process.

[0051] Optionally, the thickness of the first metal layer 221 is smaller than that of the second metal layer 222 , so as to control the thickness of the first metal layer 221 while ensuring the isolation effect provided by the first metal layer 221 , thereby reducing the difficulty of subsequent removal of the first metal layer 221 .

[0052] Optionally, the temperature at which the first metal layer 221 is formed is lower than the temperature at which the second metal layer 222 is formed, so that the quality of the obtained second metal layer 222 can be further optimized.

[0053] In one embodiment, the method for forming the second metal layer 222 covering the top of the conductive plug 211 further includes: depositing a second metal on the top of the conductive plug 211 to obtain the second metal layer 222 covering the conductive plug 211. Optionally, when forming the second metal layer 222 using a deposition process, the second bias voltage used can be a relatively large bias voltage, corresponding to a relatively fast formation rate, so that the second metal can be deposited on the top of the conductive plug 211 in the groove 213, thereby improving the quality of the deposited second metal layer 222 and enabling the second metal layer 222 to completely cover the top of the conductive plug 211. Optionally, the second bias voltage can range from 200 to 600 V, for example, the second bias voltage can be 200 V, 300 V, 500 V, or 600 V, etc.

[0054] S140, perform annealing process, refer to Figure 3g As shown, the second metal layer 222 on the top of the conductive plug 211 reacts with the conductive plug 211 to form a metal silicide 223. The metal silicide 223 is the contact layer on the top of the conductive plug 211 and can provide a contact surface with stable performance for the conductive plug 211.

[0055] In one embodiment, the method of performing an annealing process further includes: performing an annealing process to react the top of the conductive plug 211 with the second metal layer 222 in contact therewith, thereby obtaining a reacted metal silicide 223. Optionally, the temperature of the annealing process ranges from 350° C. to 700° C., for example, the annealing process temperature can be 350° C., 400° C., 500° C., 600° C., or 700° C., etc., to ensure that the second metal layer 222 on the top of the conductive plug 211 fully reacts with the conductive plug 211 in contact therewith, thereby improving the quality of the obtained metal silicide 223.

[0056] S150, removing the first metal layer 221 and the second metal layer 222 remaining after the annealing process, to obtain Figure 3h and Figure 3i The semiconductor structure shown in FIG. 1 is to retain the metal silicide 223 as the contact layer on the surface of the conductive plug 211. Figure 3iIn the embodiment, a portion of the side surface of the upper end of the conductive plug 211 is opposite to the protrusion 212 , and the conductive plug 211 is in contact with the protrusion 212 .

[0057] In the above method for forming a semiconductor device, a first metal layer 221 is formed on the surface of the protrusion 212 of the substrate 210, covering at least the top corners 215 of each protrusion 212, so as to isolate the oxide layer 214a exposed at the corners 215 of the protrusion 212 and prevent the oxygen element in the oxide layer 214a from being transferred during the relevant process; a second metal layer 222 is then formed to cover the top of the conductive plug 211, and the entire substrate 210 is annealed to react with the second metal layer 222 on the top of the conductive plug 211 to form a conductive plug. The metal silicide 223 is formed, wherein the second metal layer 222 will not contact the oxygen elements in the oxide layer 214a and will not be oxidized by this part of the oxygen elements, which can reduce the resistivity of the obtained metal silicide 223 and improve the conductivity of the formed contact layer and the corresponding conductive plug. At this time, the first metal layer 221 and the second metal layer 222 remaining after the annealing process are removed, and the metal silicide 223 is retained as the contact layer on the surface of the conductive plug 211. The contact layer has good conductivity and high stability, thereby optimizing the performance of the corresponding semiconductor structure.

[0058] In a second aspect, the present application provides a semiconductor device, comprising:

[0059] A substrate, wherein a conductive plug is provided in the substrate, the substrate includes a plurality of convex pillars, and the conductive plug is located between two adjacent convex pillars;

[0060] The interconnection contact layer is located on the surface of the conductive plug. After the corner of the top of the convex column is covered by the first metal layer, the interconnection contact layer is formed by the reaction of the second metal layer covering the top of the conductive plug with the conductive plug.

[0061] The above-mentioned semiconductor device can be formed by the method for forming a semiconductor device described in any of the above-mentioned embodiments, and has all the beneficial effects of the method for forming a semiconductor device described in any of the above-mentioned embodiments, which will not be described in detail here.

[0062] Although the present application has been shown and described with respect to one or more implementations, equivalent variations and modifications will occur to those skilled in the art based on reading and understanding this specification and the accompanying drawings. The present application includes all such modifications and variations and is limited only by the scope of the appended claims. In particular, with respect to the various functions performed by the above-mentioned components, the terms used to describe such components are intended to correspond to any component (unless otherwise indicated) that performs the specified function of the component (e.g., it is functionally equivalent), even if the structure is not necessarily equivalent to the disclosed structure that performs the function in the exemplary implementation of this specification shown herein.

[0063] That is, the above description is merely an embodiment of the present application and does not limit the patent scope of the present application. Any equivalent structural or equivalent process transformations made using the contents of the description and drawings of this application, such as the mutual combination of technical features between the various embodiments, or direct or indirect application in other related technical fields, are also included in the patent protection scope of the present application.

[0064] In addition, in the description of the present application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside" and the like indicate positions or positional relationships based on the positions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present application. In addition, for structural elements with the same or similar characteristics, the present application may use the same or different reference numerals to identify them. In addition, the terms "first" and "second" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the technical features indicated. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more features. In the description of the present application, "multiple" means two or more, unless otherwise clearly and specifically defined.

[0065] In this application, the word "exemplary" is used to mean "serving as an example, illustration or description". Any embodiment described in this application as "exemplary" is not necessarily to be construed as being more preferred or more advantageous than other embodiments. The above description is provided to enable any person skilled in the art to implement and use the present application. In the above description, various details are listed for the purpose of explanation. It should be understood that a person of ordinary skill in the art can recognize that the present application can be implemented without using these specific details. In other embodiments, well-known structures and processes will not be elaborated in detail to avoid obscuring the description of the present application with unnecessary details. Therefore, the present application is not intended to be limited to the embodiments shown, but is consistent with the widest scope consistent with the principles and features disclosed in this application.

Claims

1. A method for forming a semiconductor device, characterized in that: The forming method comprises: Providing a substrate, wherein a conductive plug is provided in the substrate, the substrate includes a plurality of protrusions, and the conductive plug is located between two adjacent protrusions; both sides of the protrusions include spacer layers, wherein an oxide layer is provided in the spacer layers, and the oxide layer is exposed at the corners of the tops of the protrusions; forming a first metal layer covering at least the top corners of each of the convex pillars; the first metal layer at least covers the top of the spacer layer along the protruding direction of the convex pillars; forming a second metal layer covering a top portion of the conductive plug; performing an annealing process so that the second metal layer on the top of the conductive plug reacts with the conductive plug to form a metal silicide; The first metal layer and the second metal layer remaining after the annealing process are removed.

2. The method for forming a semiconductor device according to claim 1, wherein: The method of forming a first metal layer covering at least the top corners of each of the convex pillars further comprises: A first metal is sputtered onto the top of the convex pillar to obtain a first metal layer covering the top surface and corners of the convex pillar.

3. The method for forming a semiconductor device according to claim 1, wherein: The thickness of the first metal layer is smaller than that of the second metal layer.

4. The method for forming a semiconductor device according to claim 1, wherein: The thickness of the first metal layer ranges from 1 nm to 3 nm.

5. The method for forming a semiconductor device according to claim 1, wherein: The temperature at which the first metal layer is formed is lower than the temperature at which the second metal layer is formed.

6. The method for forming a semiconductor device according to claim 1, wherein: The method of forming a second metal layer covering the top of the conductive plug further includes: A second metal is deposited on top of the conductive plug to obtain a second metal layer covering the conductive plug.

7. The method for forming a semiconductor device according to claim 1, wherein: After forming the first metal layer that at least covers the top corners of each of the convex pillars, the forming method further includes: The substrate and the first metal layer are pre-cleaned by using a dry etching method.

8. The method for forming a semiconductor device according to claim 1, wherein: The material of the first metal layer includes at least one of cobalt, titanium, nickel and manganese; and / or the material of the second metal layer includes at least one of cobalt, titanium, nickel and manganese.

9. The method for forming a semiconductor device according to claim 1, wherein: The conductive plug is made of polysilicon or doped polysilicon.

10. The method for forming a semiconductor device according to claim 1, wherein: The method for performing the annealing process further comprises: An annealing process is performed to allow the top of the conductive plug to react with the second metal layer in contact therewith, thereby obtaining a reacted metal silicide.

11. A semiconductor device, characterized in that: The semiconductor device is formed by the forming method according to any one of claims 1 to 10, comprising: A substrate, wherein a conductive plug is provided in the substrate, the substrate includes a plurality of convex pillars, and the conductive plug is located between two adjacent convex pillars; The interconnection contact layer is located on the surface of the conductive plug. After the corner of the top of the convex column is covered by the first metal layer, the interconnection contact layer is formed by the reaction of the second metal layer covering the top of the conductive plug with the conductive plug.

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