Semiconductor device package and method of forming the same

Abstract

Embodiments of the present disclosure provide a semiconductor device package and a method of forming the same. The semiconductor device package includes a package substrate having a first surface and a second surface opposite the first surface. A plurality of integrated devices are bonded to the first surface of the package substrate. A first underfill element is disposed over the first surface and around the integrated devices. A first molding layer is disposed over the first surface and around the integrated devices and the first underfill element. A semiconductor die is bonded to the second surface of the package substrate. A second underfill element is disposed over the second surface and around the semiconductor die. A second molding layer is disposed over the second surface and around the semiconductor die and the second underfill element. A plurality of conductive bumps are disposed over the second surface and adjacent to the second molding layer.

Description

Technical Field

[0001] This disclosure relates to a semiconductor manufacturing technology, and more particularly to a semiconductor device package including warp control and a method for forming the same. Background Technology

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Typically, semiconductor devices are manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor material layers on a semiconductor substrate, and then patterning these material layers using lithography to form circuit components and elements. Multiple integrated circuits are usually fabricated on a single semiconductor wafer, and the individual dies on the wafer are separated by sawing along scribe lines between the integrated circuits. Each die is typically individually packaged in, for example, multi-chip modules (MCMs) or other types of packages.

[0003] Packaging structures not only protect semiconductor devices from environmental contaminants but also provide connectivity interfaces for the semiconductor devices encapsulated within them. Smaller packaging structures with less area or lower height have been developed for encapsulating semiconductor devices.

[0004] While existing packaging structures and methods for manufacturing them are generally sufficient to meet their intended purposes, they are not entirely satisfactory in all respects. Summary of the Invention

[0005] This disclosure provides a semiconductor device package including a package substrate, a plurality of integrated devices, a first underfill element, a first molding layer, a semiconductor die, a second underfill element, a second molding layer, and a plurality of conductive bumps. The package substrate has a first surface and a second surface opposite to the first surface. The integrated devices are bonded to the first surface. The first underfill element is disposed on the first surface and surrounds the integrated devices. The first molding layer is disposed on the first surface and surrounds the integrated devices and the first underfill element, wherein the first molding layer has a different composition than the first underfill element. The semiconductor die is bonded to the second surface. The second underfill element is disposed on the second surface and surrounds the semiconductor die. The second molding layer is disposed on the second surface and surrounds the semiconductor die and the second underfill element, wherein the second molding layer has a different composition than the second underfill element. Conductive bumps are disposed on the second surface and adjacent to the second molding layer.

[0006] This disclosure provides a semiconductor device package including a package substrate, a plurality of integrated devices, a first underfill element, a first molding layer, a first semiconductor die, and a second underfill element. The package substrate has a first surface and a second surface opposite to the first surface. The integrated devices are bonded to the first surface, including a first integrated device and a second integrated device, wherein the thickness of the first integrated device is greater than that of the second integrated device. The first underfill element is disposed on the first surface and surrounds the integrated devices, wherein a first portion of the first underfill element in contact with the first integrated device is greater than a second portion of the first underfill element in contact with the second integrated device. The first molding layer is disposed on the first surface and seals the integrated devices and the first underfill element, wherein the first molding layer has a different composition than the first underfill element. The first semiconductor die is bonded to the second surface. The second underfill element is disposed on the second surface and surrounds the first semiconductor die.

[0007] This disclosure provides a method for forming a semiconductor device package. The method includes bonding a plurality of integrated devices to a first surface of a package substrate. The method further includes forming a first underfill element on the first surface to surround the integrated devices. The method also includes forming a first molding layer on the first surface to seal the integrated devices and the first underfill element, wherein the first molding layer has a different composition than the first underfill element. The method further includes bonding a semiconductor die to a second surface of the package substrate opposite to the first surface. The method also includes forming a second underfill element on the second surface to surround the semiconductor die. The method further includes forming a second molding layer on the second surface to seal the semiconductor die and the second underfill element, wherein the second molding layer has a different composition than the second underfill element. Furthermore, the method includes distributing a plurality of conductive bumps on the second surface adjacent to the second molding layer. Attached Figure Description

[0008] The following detailed description, along with the accompanying drawings, constitutes a complete disclosure. It should be emphasized that, in accordance with the general practice of this industry, the illustrations are not necessarily drawn to scale. In fact, the dimensions of components may be arbitrarily enlarged or reduced for clarity.

[0009] Figures 1A to 1G These are cross-sectional views of various stages of the process of forming a semiconductor device package according to some embodiments.

[0010] Figures 2A to 2G These are cross-sectional views of various stages of the process of forming a semiconductor device package according to some embodiments.

[0011] Figure 3 This is a cross-sectional view of a semiconductor device package according to some embodiments.

[0012] Figure 4 This is a cross-sectional view of a semiconductor device package according to some embodiments.

[0013] The reference numerals in the attached figures are explained as follows:

[0014] 100, 100': Carrier substrate

[0015] 102: Packaging substrate

[0016] 102A, 102B: Surface

[0017] 1021, 1022: Contact pads

[0018] 104, 104': Integrated device

[0019] 106, 106': Bottom padding element

[0020] 108, 108': Molded layer

[0021] 108A: Top surface

[0022] 110, 110': Semiconductor grains

[0023] 110A, 110A': Top surface

[0024] 112, 112': Conductive connectors

[0025] 112A, 112A': Metal pillars

[0026] 112B, 112B': Metal capping

[0027] 114, 114': Bottom padding element

[0028] 116, 116': Molded layer

[0029] 116A, 116A': Top surface

[0030] 116B: Open

[0031] 118, 118': Conductive bumps

[0032] 202: Packaging substrate

[0033] 202A, 202B: Surface

[0034] 204: Insulation layer

[0035] 206: Electrical conductivity characteristics

[0036] 206A, 206B: Contact pads

[0037] 208: Conductive post

[0038] 208A: Top surface

[0039] 310: Semiconductor die

[0040] 310A: Top surface

[0041] 312: Conductive connector

[0042] 312A: Metal Column

[0043] 312B: Metal capping layer

[0044] 320: Cover structure

[0045] 330: Thermal interface material

[0046] 410: Molded layer

[0047] 410A: Top surface

[0048] 420: Molded layer

[0049] 420A: Top surface

[0050] G: Cutting groove

[0051] P, P': Cutting tape

[0052] h1, h2, h3: Thickness

[0053] T1, T2, T3, T4, T6, T7, T8, T9: Thickness

[0054] T5: Combining thickness Detailed Implementation

[0055] The following disclosure provides many different embodiments or examples to implement different features of this application. Specific examples of components and their arrangements are described below to illustrate this disclosure. Of course, these embodiments are merely examples and should not be construed as limiting the scope of this disclosure. For example, the specification may describe a first feature formed on or above a second feature, which may include embodiments where the first and second features are in direct contact, or embodiments where an additional feature is formed between the first and second features, such that the first and second features may not be in direct contact. Furthermore, repeated reference numerals and / or designations may be used in different examples of this disclosure; this repetition is for simplification and clarity and is not intended to limit any specific relationship between the various embodiments and / or structures discussed.

[0056] Furthermore, spatial terms, such as "below," "lower," "above," "higher," and similar terms, are used to facilitate the description of the relationship between one element or feature and another element(s) in the diagram. In addition to the orientation shown in the diagram, these spatial terms are intended to encompass different orientations of the device in use or operation. The device may be rotated to different orientations (90 degrees or other orientations), and the spatial terms used here can be interpreted in the same way.

[0057] The use of the term "substantially" in the specification, such as "substantially flat" or "substantially coplanar," is understood by those skilled in the art. In some embodiments, the adjective "substantially" may be omitted. Where applicable, the term "substantially" may also include embodiments of "entirely," "completely," "all," etc. Where applicable, the term "substantially" may also refer to 90% or higher, such as 95% or higher, particularly 99% or higher, including 100%. Furthermore, terms such as "substantially parallel" or "substantially perpendicular" should be interpreted as not excluding minor deviations from a particular arrangement, and may include, for example, deviations of up to 10°. The term "substantially" does not exclude "completely," for example, a composition "substantially free" may be completely free of Y.

[0058] Terms used in conjunction with a specific distance or size, such as "about," should be interpreted as not excluding minor deviations relative to the specific distance or size, and may include, for example, deviations of up to 10%. The term "about" used with the numerical value x may mean x ± 5 or 10%.

[0059] According to various embodiments of this disclosure, a semiconductor device package (structure) including warpage control and a method for forming the same are provided. Intermediate stages of forming the semiconductor device package are illustrated according to some embodiments. Variations of some embodiments are also discussed. In the various views and illustrative embodiments, the same reference numerals are used to denote the same elements. According to some embodiments, a semiconductor device package includes underfill elements and molding layers located on both sides of a package substrate to reduce warpage and prevent delamination at the bonding interface between the package substrate and the device thereon. Therefore, the reliability of the semiconductor device package is improved.

[0060] This document describes embodiments within a specific context, namely, a system-in-package (SIP) comprising one or more functional semiconductor dies (also referred to as chips) and passive devices integrated on opposite sides of a package substrate. Other embodiments may also be contemplated for other applications, such as different package types or different configurations, which will readily conceive of those skilled in the art upon reading this disclosure. It should be noted that the embodiments discussed herein may not necessarily describe every component or feature that may be present in the structure. For example, multiple instances of a component may be omitted from the figures, such as when a discussion of one of the components is sufficient to convey various aspects of the embodiment. Furthermore, the method embodiments discussed herein may be performed in a particular order; however, other method embodiments may be performed in any logical order.

[0061] Figures 1A to 1G This diagram shows a cross-sectional view of an intermediate stage in the formation of a semiconductor device package according to some embodiments of the present disclosure. Figure 1A As shown, according to some embodiments, a carrier substrate 100 is provided. The carrier substrate 100 may be configured to provide temporary mechanical and structural support for the processing of building layers or structures during subsequent processing steps. In some embodiments, the carrier substrate 100 is made of materials including glass, silicon, silicon oxide, aluminum oxide, metals, combinations thereof, and / or other similar materials. In some other embodiments, the carrier substrate 100 includes a metal frame.

[0062] like Figure 1A As shown, according to some embodiments, a packaging substrate 102 is disposed on a carrier substrate 100. The packaging substrate 102 may be configured to provide electrical connections between a device packaged in a packaging structure and an external electronic device, such as a printed circuit board (PCB), which will be further described later. In some embodiments, the packaging substrate 102 is a core or core-less wiring substrate. The core layer (not shown) of the packaging substrate 102 may include or be made of fibrous materials, polymeric materials, semiconductor materials, glass materials, metallic materials, or other suitable materials. One or more interconnect structure layers may also be formed on one or both sides of the core layer to facilitate routing. In some embodiments, the packaging substrate 102 includes a printed circuit board (PCB), a ceramic substrate, or the like.

[0063] In some other embodiments, the packaging substrate 102 includes a semiconductor substrate, which may be a bulk semiconductor substrate, a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GOI) substrate, or the like. The semiconductor material of the substrate may include silicon, germanium, compound semiconductors (including silicon-germanium, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide), alloy semiconductors (including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP), or combinations thereof. Other substrates, such as multilayer or gradient substrates, may also be used. The packaging substrate 102 may be doped or undoped.

[0064] In some embodiments, the package substrate 102 is an interposer substrate without active devices (e.g., transistors and diodes) and passive devices (e.g., resistors, capacitors, inductors, etc.). In some alternative embodiments, the package substrate 102 is a device substrate that includes active and / or passive devices.

[0065] In some embodiments, the packaging substrate 102 has two opposing and parallel surfaces 102A and 102B, such as Figure 1A As shown. Surface 102B faces the carrier substrate 100. Contact pad 1021 is formed on or exposed from surface 102A and can be used for electrical connection to subsequently attached package components (described later). Contact pad 1022 is formed on or exposed from surface 102B and can be used for electrical connection to subsequently attached package components (described later). Although not shown, the package substrate 102 also includes conductive lines (e.g., vias and / or traces) therein to interconnect contact pads 1021 and 1022. The conductive lines and contact pads 1021 and 1022 may include or be made of a conductive material, such as a metal (e.g., copper, aluminum, or tungsten). The methods for forming the above-described package substrate 102 are well known in the art and will not be described further here.

[0066] like Figure 1AAs shown, according to some embodiments, several integrated devices 104 are stacked on surface 102A of package substrate 102. In some embodiments, integrated devices 104 are integrated passive devices (IPDs), such as resistors, capacitors, etc., or combinations thereof. In some embodiments, integrated devices 104 may be of different types and have different heights (or thicknesses). Integrated devices 104 can be placed on surface 102A using, for example, a pick-and-place tool (not shown). In some embodiments, integrated devices 104 are bonded (i.e., electrically interconnected) to surface 102A by solder elements (e.g., solder paste, not shown for simplicity). In some embodiments, solder elements may be formed on terminals of integrated devices 104, on contact pads 1021 exposed on surface 102, or on both, prior to the bonding process. A reflow process is then performed to melt the solder elements to form conductive contacts, thereby physically and electrically coupling integrated devices 104 to package substrate 102.

[0067] like Figure 1B As shown, according to some embodiments, an underfill element 106 is formed on the surface 102A of the encapsulation substrate 102 to surround and protect the integrated device 104 and the conductive contacts below it, and to enhance the connection between the integrated device 104 and the encapsulation substrate 102. The underfill element 106 may include or be made of an insulating material, such as an underfill material. The underfill material may include epoxy resin, resin, filler, stress release agent (SRA), adhesion promoter, other suitable materials, or combinations thereof. In some embodiments, liquid underfill material is dispensed into the gaps between each integrated device 104 and the encapsulation substrate 102 and / or the gaps between adjacent integrated devices 104 to strengthen the conductive contacts and even the overall encapsulation structure. According to some embodiments, after dispensing, the underfill material is cured (e.g., by heating or ultraviolet (UV) radiation) to form the underfill element 106.

[0068] In some embodiments, the thickness T1 of the bottom filler element 106 (e.g., from surface 102A to the top surface of the bottom filler element 106 in a direction perpendicular to surface 102A) is about 1 / 3 to about 1 / 2 of the thickness T2 of the integrated device 104 (e.g., from surface 102A to the top surface of the integrated device 104 in a direction perpendicular to surface 102A). Figure 1B As shown. However, other thickness values ​​or ranges can also be used.

[0069] In some embodiments, such as Figure 1B As shown, the thicker the integrated device 104, the thicker the portion of the underfill element 106 surrounding and contacting the integrated device 104 (e.g., thickness h1 > thickness h2 > thickness h3). For example, there may be a portion of the underfill element 106 between two integrated devices 104 of different thicknesses, wherein the thickness of the portion of the underfill element 106 in contact with the thicker integrated device 104 is greater than the thickness of the portion of the underfill element 106 in contact with the thinner integrated device 104. This can be achieved by precisely controlling the amount of underfill material dispensed, and this can improve the reliability of the package by increasing the adhesion of the integrated device 104 to the package substrate 102.

[0070] like Figure 1C As shown, according to some embodiments, a molding layer 108 is formed on surface 102A of the encapsulation substrate 102 to seal and protect the integrated device 104 and the underfill element 106. The molding layer 108 can be separated from the conductive contacts below the integrated device 104 by the underfill element 106. In some embodiments, the molding layer 108 comprises or is made of an insulating material, such as a molding material. The molding material may include a polymeric material, such as an epoxy resin in which fillers are dispersed. In some embodiments, the molding material (e.g., a liquid molding material) is dispensed onto the encapsulation substrate 102, the integrated device 104, and the underfill element 106 using, for example, injection molding. In some embodiments, a heat treatment is then used to solidify the liquid molding material and transform it into the molding layer 108. In some embodiments, the molding layer 108 extends laterally to the side edges of the encapsulation substrate 102.

[0071] Due to a mismatch in the coefficient of thermal expansion (CTE) between the package substrate 102 and the packaged components or other materials thereon, the package substrate 102 may warp during the molding process of the molding layer 108 (e.g., during thermal stress). Warping can lead to reliability issues, such as delamination at the junction or interface between the integrated device 104 and the package substrate 102. In some embodiments, the underfill element 106 can further alleviate thermal stress occurring in the form of stress or strain on the conductive junctions, thereby reducing warping of the package substrate 102 and preventing delamination at the interface (e.g., between the integrated device 104 and the conductive junctions and / or between the package substrate 102 and the conductive junctions).

[0072] In some embodiments, the underfill element 106 and the molding layer 108 have different thermal and mechanical properties, for example, by having different material compositions. Each of the underfill element 106 and the molding layer 108 can be modified, for example, by adjusting the ratio of filler to epoxy resin in the individual materials used to have specific mechanical and / or thermal properties. The filler may be an inorganic material, such as alumina, silica, etc.

[0073] In some embodiments, the bottom fill element 106 may be relatively compliant to alleviate thermal stress, for example by having a Young's modulus below about 15 GPa, and the molding layer 108 may have a high thermal conductivity to facilitate heat dissipation, for example by having a Young's modulus below about 25 x 10⁻⁶ GPa. -6 The coefficient of thermal expansion (CTE). For example, the underfill element 106 may have a higher coefficient of thermal expansion than the molding layer 108, while the molding layer 108 may have a higher Young's modulus than the underfill element 106. In a specific example, the underfill element 106 has a coefficient of thermal expansion of 1.73 x 10⁻⁶. -5 The coefficient of thermal expansion and Young's modulus of 12 GPa, and the molding layer 108 has a coefficient of 1.1 x 10⁻⁶. -5 The coefficient of thermal expansion and Young's modulus of 21 GPa. According to some embodiments, this can be achieved by having the molded layer 108 have a higher filler content than the underfill element 106. For example, the filler content of the underfill element 106 may be between about 20% and about 50%, and the filler content of the molded layer 108 may be between about 80% and about 90%. Those skilled in the art will understand that the above examples are provided for illustrative purposes, and other values ​​(or ranges) of the coefficient of thermal expansion, Young's modulus, and / or filler content of the underfill element 106 and the molded layer 108 may also be used.

[0074] In some embodiments, a planarization process is further applied to the molding layer 108 to partially remove the molding layer 108. This reduces the thickness T3 of the molding layer 108 (e.g., from surface 102A to the top surface 108A of the molding layer 108 in a direction perpendicular to surface 102A), resulting in a thinner overall package structure. Furthermore, a substantially flat top surface of the molding layer 108 is achieved, which is beneficial for subsequent processes. In some embodiments, such as Figure 1C As shown, after the planarization process, the integrated device 104 is buried or sealed in the molding layer 108. The planarization process may include a grinding process, a chemical mechanical polishing (CMP) process, an etching process, a dry polishing process, one or more other optional processes, or a combination thereof.

[0075] like Figure 1D As shown, according to some embodiments, Figure 1C The resulting structure is inverted such that the molding layer 108 is attached to a cutting tape P, and the carrier substrate 100 originally located on the surface 102B of the packaging substrate 102 is removed. Then, according to some embodiments, several semiconductor dies 110 (only one semiconductor die 110 is shown for simplicity) are stacked on the surface 102B of the packaging substrate 102. Semiconductor die 110 may include logic dies (e.g., central processing units, graphics processing units, field-programmable gate arrays (FPGAs), system-on-chip (SOC) dies, microcontrollers, etc.), memory dies (e.g., dynamic random access memory (DRAM) dies, static random access memory (SRAM) dies, etc.), power management dies (e.g., power management integrated circuit (PMIC) dies, radio frequency (RF) dies, sensor dies, micro-electro-mechanical system (MEMS) dies, signal processing dies (e.g., digital signal processing (DSP) dies), front-end dies (e.g., analog front-end (AFE) dies), etc., or combinations thereof. Semiconductor die 110 may be placed on surface 102B using, for example, a pick-and-place tool (not shown). In some embodiments, such as... Figure 1D As shown, the width of the semiconductor die 110 is greater than the width of each integrated device 104, and extends laterally across two or more integrated devices 104.

[0076] In some embodiments, such as Figure 1D As shown, each semiconductor die 110 is bonded to (i.e., electrically interconnected to) surface 102B via a plurality of conductive connectors 112. In some embodiments, each conductive connector 112 includes a metal pillar 112A and a metal capping layer (e.g., solder cap) 112B located above the metal pillar 112A. The conductive connector 112 including the metal pillar 112A and the metal capping layer 112B is sometimes referred to as a microbump. The conductive connector 112 may be formed on the active surface exposed to the semiconductor die 110 (e.g., ...) prior to the bonding process. Figure 1DThe exposed contact pad (not shown) is located on the lower surface shown in the diagram. The metal pillar 112A may comprise a conductive material, such as copper, aluminum, gold, nickel, palladium, or combinations thereof, and may be formed by sputtering, printing, electroplating, electroless plating, chemical vapor deposition (CVD), etc. The metal pillar 112A may be solderless and have substantially vertical sidewalls. In some embodiments, a metal capping layer 112B is formed on top of a metal pillar 112A. The metal capping layer 112B may comprise nickel, tin, tin-lead, gold, copper, silver, palladium, indium, nickel-palladium-gold, nickel-gold, etc., or combinations thereof, and may be formed by a plating process, such as an electroplating process. Those skilled in the art will understand that the above-described conductive connector 112 example is provided for illustrative purposes, and other conductive connectors 112 with different structures may also be used.

[0077] The bonding between the semiconductor die 110 and the package substrate 102 can be solder bonding or direct metal-to-metal (e.g., copper-to-copper) bonding. According to some embodiments, the semiconductor die 110 is bonded to the package substrate 102 via a reflow process. During the reflow process, conductive contacts (e.g., conductive connectors 112) contact the exposed contact pads (not shown) of the semiconductor die 110 and the exposed contact pads 1022 on the surface 102B of the package substrate 102, respectively, to physically and electrically couple the semiconductor die 110 to the package substrate 102.

[0078] like Figure 1D As shown, according to some embodiments, an underfill element 114 is formed on the surface 102B of the packaging substrate 102 to surround and protect the semiconductor die 110 and the conductive connectors 112 below it, and to enhance and protect the connection between the semiconductor die 110 and the packaging substrate 102. In some embodiments, a portion of the underfill element 114 is located between the surface 102B and the active surface of the semiconductor die 110 and fills the gap between adjacent conductive connectors 112 to strengthen the conductive connectors 112 and even the overall packaging structure. The material and formation method of the underfill element 114 can be compared with those of the packaging substrate 102. Figure 1B The materials and forming methods of the bottom filling element 106 shown are the same or similar, so they will not be described again here.

[0079] like Figure 1E As shown, according to some embodiments, a molding layer 116 is formed on the surface 102B of the packaging substrate 102 to seal and protect the semiconductor die 110 and the underfill element 114. The molding layer 116 can be separated from the conductive connector 112 below the semiconductor die 110 by the underfill element 114. The material and formation method of the molding layer 116 can be compared with those of the semiconductor die 110. Figure 1CThe materials and formation methods of the molding layer 108 shown are the same or similar, so they will not be described again here. In some embodiments, the molding layer 116 extends laterally to the side edge of the encapsulation substrate 102, and the side edges of the encapsulation substrate 102, the molding layer 108 and the molding layer 116 are aligned.

[0080] In some embodiments, the underfill element 114 and the molding layer 116 have different thermal and mechanical properties, for example, by having different material compositions. Each of the underfill element 114 and the molding layer 116 can be modified, for example, by adjusting the ratio of filler to epoxy resin in the individual materials used to have specific mechanical and / or thermal properties. The filler may be an inorganic material, such as alumina, silica, etc.

[0081] In some embodiments, the underfill element 114 may be relatively compliant to alleviate thermal stress, and the molding layer 116 may have a high thermal conductivity to facilitate heat dissipation. In some embodiments, the molding layer 116 has a lower coefficient of thermal expansion, a higher Young's modulus, a higher filler content percentage than the underfill element 114, or a combination thereof. In some cases, the values ​​of the coefficient of thermal expansion, Young's modulus, and filler content of the underfill element 114 and the molding layer 116 may be the same as or similar to the values ​​of the coefficient of thermal expansion, Young's modulus, and filler content of the underfill element 106 and the molding layer 108 described above, and will not be repeated here. However, other values ​​may also be used. In some embodiments, similar to the underfill element 106 discussed above, the underfill element 114 may further alleviate thermal stress, for example, that occurs in the form of stress or strain on conductive contacts (e.g., conductive connector 112) during the molding process of the molding layer 116. This reduces warping of the package substrate 102, prevents breakage of the semiconductor die 110, and avoids delamination at the bonding interface (e.g., between the semiconductor die 110 and the conductive connector 112 and / or between the package substrate 102 and the conductive connector 112).

[0082] In some embodiments, a planarization process is further applied to the molding layer 116 to partially remove the molding layer 116 until the top surface 110A of the semiconductor die 110 is exposed through the molding layer 116 (e.g., the top surface 110A is substantially flush with the top surface 116A of the molding layer 116, i.e., the thickness T4 of the molding layer 116 (e.g., from surface 102B to the top surface 116A of the molding layer 116 in a direction perpendicular to surface 102B) is substantially equal to the bonding thickness T5 of the semiconductor die 110 and the conductive interconnect 112 below it (e.g., from surface 102B to the top surface 110A of the semiconductor die 110 in a direction perpendicular to surface 102B)). Figure 1EAs shown. This facilitates the dissipation of heat generated from the semiconductor die 110 during operation. However, in some other embodiments, the semiconductor die 110 may also be buried or sealed in the molding layer 116 after the planarization process. The planarization process may include a polishing process, a chemical mechanical polishing (CMP) process, an etching process, a dry polishing process, one or more other optional processes, or a combination thereof.

[0083] like Figure 1F As shown, according to some embodiments, a patterning process is performed to form an opening 116B in the molding layer 116 to expose a contact pad 1022 on a surface 102B not occupied by the conductive connector 112. The patterning process may include photolithography, energy beam drilling (e.g., laser drilling, ion beam drilling, or electron beam drilling), etching, mechanical drilling, one or more other optional processes, or a combination thereof.

[0084] In some embodiments, the solder ball (or solder element) is then positioned (e.g., in direct contact) on the exposed contact pad 1022 in the opening 116B, such as... Figure 1F As shown. A reflow process is then performed to melt the solder balls to form conductive bumps 118. In some other embodiments, underbump metallization (UBM) components are formed on the exposed contact pads 1022 before the solder balls are placed. In some other embodiments, solder components are electroplated onto the exposed contact pads 1022. Afterward, a reflow process is used to melt the solder components to form conductive bumps 118. According to some embodiments, the exposed conductive bumps 118 (sometimes also referred to as ball grid arrays (BGAs)) allow the semiconductor package structure to bond and electrically connect to an external printed circuit board or other electronic device (not shown).

[0085] Subsequently, according to some embodiments, along Figure 1F The cutting groove G shown is used for a segmentation process (also known as a sawing process) to form multiple individual package structures. Figure 1F The image shows one of the encapsulation structures. Each encapsulation structure can be removed from the cutting tape P using, for example, a pick-and-place tool (not shown). Figure 1G It shows in Figures 1A to 1F The semiconductor device package obtained after the process shown. Figure 1GIn this process, bottom filler elements 106 and 114 are formed on both sides of the package substrate 102 to alleviate thermal stress generated during the molding process of molding layers 108 and 116, as described above. Therefore, warpage of the package substrate 102 and / or semiconductor die 110 can be reduced, and delamination at the interface between the package substrate 102 and the device packaged thereon can be avoided. As a result, the reliability of the entire package structure is improved.

[0086] Many variations and / or modifications can be made to the embodiments of this disclosure. Figures 2A to 2G These are cross-sectional views of various stages of the process of forming a semiconductor device package according to some embodiments.

[0087] like Figure 2A As shown, according to some embodiments, in a carrier substrate 100' (and Figure 1A An encapsulation substrate 202 is formed on the same carrier substrate 100 shown. The encapsulation substrate 202 can be configured to provide electrical connection between a device encapsulated in an encapsulation structure and an external electronic device, such as a printed circuit board (PCB), which will be described further later.

[0088] In some embodiments, the packaging substrate 202 is a redistributed substrate for routing, comprising a plurality of laminated insulating layers 204 and a plurality of conductive features 206 surrounded by the insulating layers 204, such as... Figure 2A As shown. Conductive feature 206 may include conductive lines providing electrical connection in the horizontal direction and conductive vias providing electrical connection in the vertical direction. Furthermore, as... Figure 2A As shown, conductive features 206 include contact pads 206A and 206B formed on or exposed from opposing surfaces 202A and 202B of the package substrate 202 to allow electrical connections between the package substrate 202 and subsequently attached package components (described later). Surface 202B faces the carrier substrate 100'.

[0089] The insulating layer 204 may include or be made of one or more polymeric materials. The polymeric materials may include polybenzoxazole (PBO), polyimide (PI), epoxy resins, one or more other suitable polymeric materials, or combinations thereof. In some embodiments, the polymeric material is photosensitive. Therefore, photolithography can be used to form openings with the desired pattern in the insulating layer 204.

[0090] In some other embodiments, part or all of the insulating layer 204 comprises or is made of a dielectric material other than a polymeric material. The dielectric material may include silicon oxide, silicon carbide, silicon nitride, silicon oxynitride, one or more other suitable materials, or combinations thereof.

[0091] The conductive feature 206 may include or be made of copper, aluminum, gold, cobalt, titanium, nickel, silver, graphene, one or more other suitable conductive materials, or combinations thereof. In some embodiments, the conductive feature 206 includes multiple sublayers. For example, each conductive feature 206 includes multiple sublayers, including Ti / Cu, Ti / Ni / Cu, Ti / Cu / Ti, Al / Ti / Ni / Ag, other suitable sublayers, or combinations thereof.

[0092] The formation of the aforementioned packaging substrate 202 may involve multiple deposition or coating processes, multiple patterning processes, and / or multiple planarization processes.

[0093] Deposition or coating processes can be used to form insulating and / or conductive layers. Deposition or coating processes may include spin coating, electroplating, electroless plating, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), one or more other optional processes, or combinations thereof.

[0094] Patterning processes can be used to pattern insulating layers and / or conductive layers. Patterning processes may include photolithography, energy beam drilling (e.g., laser drilling, ion beam drilling, or electron beam drilling), etching, mechanical drilling, one or more other optional processes, or combinations thereof.

[0095] Planarization processes can be used to provide a flat top surface for the formed insulating layer and / or conductive layer to facilitate subsequent processes. Planarization processes may include mechanical polishing processes, chemical mechanical polishing (CMP) processes, one or more other optional processes, or combinations thereof.

[0096] like Figure 2A As shown, according to some embodiments, after forming the package substrate 202, a plurality of integrated devices 104' are stacked on and bonded to the surface 202A of the package substrate 202. In some embodiments, the integrated devices 104' are integrated passive devices (IPDs), such as resistors, capacitors, etc., or combinations thereof. The bonding method of the integrated devices 104' can be... Figure 1A The joining method of the integrated device 104 shown is the same or similar, so it will not be described again here.

[0097] like Figure 2B As shown, according to some embodiments, similar to Figure 1BIn the illustrated embodiment, an underfill element 106' is formed on the surface 202A of the packaging substrate 202 to surround and protect the integrated device 104' and the conductive contacts below it, and to enhance the connection between the integrated device 104' and the packaging substrate 202. The material, structure, and formation method of the underfill element 106' can be compared with... Figure 1B The materials, structures and forming methods of the bottom filling element 106 shown are the same or similar, so they will not be described again here.

[0098] like Figure 2B As shown, according to some embodiments, similar to Figure 1C In the illustrated embodiment, a molding layer 108' is formed on surface 202A of the packaging substrate 202 to seal and protect the integrated device 104' and the underfill element 106'. The molding layer 108' can be separated from the conductive contacts below the integrated device 104' by the underfill element 106'. The material, structure, and formation method of the molding layer 108' can be compared with... Figure 1C The molding layer 108 shown is made of the same or similar material, structure and formation method, and will not be described again here. In some embodiments, the molding layer 108' extends laterally to the side edge of the encapsulation substrate 202.

[0099] In some embodiments, the underfill element 106' and the molding layer 108' have different thermal and mechanical properties, for example, by having different material compositions. Each of the underfill element 106' and the molding layer 108' can be modified, for example, by adjusting the ratio of filler to epoxy resin in the individual materials used to have specific mechanical and / or thermal properties. The filler can be an inorganic material, such as alumina, silica, etc.

[0100] In some embodiments, the underfill element 106' may be relatively flexible to alleviate thermal stress, and the molding layer 108' may have a high thermal conductivity to facilitate heat dissipation. In some embodiments, the molding layer 108' has a lower coefficient of thermal expansion than the underfill element 106', a higher Young's modulus than the underfill element 106', a higher filler content percentage than the underfill element 106', or a combination thereof. The values ​​of the coefficient of thermal expansion, Young's modulus, and filler content of the underfill element 106' and the molding layer 108' may be the same as or similar to the values ​​of the coefficient of thermal expansion, Young's modulus, and filler content of the underfill element 106' and the molding layer 108' described above, and will not be repeated here. However, other values ​​may also be used. In some embodiments, similar to the underfill element 106 discussed above, the underfill element 106' can further alleviate thermal stress occurring on the conductive contacts in the form of stress or strain, thereby reducing warpage of the package substrate 202 and avoiding delamination at the bonding interface (e.g., between the integrated device 104' and the conductive contacts and / or between the package substrate 202 and the conductive contacts).

[0101] In some embodiments, a planarization process is further applied to the molding layer 108' to thin the molding layer 108', similar to... Figure 1C The embodiment shown. In some embodiments, after the planarization process, the integrated device 104' is buried or sealed in the molding layer 108', such as Figure 2B As shown. Planarization processes may include grinding processes, chemical mechanical polishing (CMP) processes, etching processes, dry polishing processes, one or more other optional processes, or combinations thereof.

[0102] like Figure 2C As shown, according to some embodiments, Figure 2B The resulting structure is inverted, such that the molding layer 108' is attached to a cutting tape P', and the carrier substrate 100' originally located on the surface 202B of the encapsulation substrate 202 is removed. Then, according to some embodiments, conductive pillars 208 are formed on the surface 202B. Each conductive pillar 208 can be electrically connected to a contact pad 206B exposed on the surface 202B. In some embodiments, the conductive pillar 208 has vertical sidewalls. The direction of extension of the vertical sidewalls can be substantially perpendicular to the surface 202B.

[0103] The conductive post 208 may include or be made of copper, aluminum, gold, cobalt, titanium, tin, one or more other suitable materials, or combinations thereof. The conductive post 208 may be formed using electroplating, electroless plating, placement, printing, physical vapor deposition (PVD), chemical vapor deposition (CVD), one or more other optional processes, or combinations thereof.

[0104] like Figure 2DAs shown, according to some embodiments, several semiconductor dies 110' (only one semiconductor die 110' is shown for simplicity) are stacked on the surface 202B of the packaging substrate 202. The semiconductor die 110' can be coupled with... Figure 1D The semiconductor dies 110 shown are the same or similar, and therefore will not be described again here. The semiconductor die 110' can be placed on the surface 202B using, for example, a pick-and-place tool (not shown). In some embodiments, such as... Figure 2D As shown, the width of the semiconductor die 110' is greater than the width of each integrated device 104', and extends laterally across two or more integrated devices 104'. In some embodiments, the conductive posts 208 are arranged adjacent to the periphery of the semiconductor die 110'.

[0105] In some embodiments, each semiconductor die 110' is bonded (i.e., electrically interconnected) to a contact pad 206B exposed at surface 202B that is not occupied by conductive pillars 208 via a plurality of conductive connectors 112', such as Figure 2D As shown. In some embodiments, each conductive connector 112' includes a metal pillar 112A' and a metal capping layer (e.g., solder cap) 112B' located above the metal pillar 112A'. The conductive connector 112' including the metal pillar 112A' and the metal capping layer 112B' is sometimes referred to as a microbump. Before the bonding process, the conductive connector 112' may be formed on the active surface exposed to the semiconductor die 110' (e.g., Figure 2D On the exposed contact pad (not shown) at the lower surface shown. The material and forming method of the conductive connector 112' can be consistent with... Figure 1D The conductive connector 112 shown is made of the same or similar material and is formed by the same method, so it will not be described again here. Those skilled in the art will understand that the above-described conductive connector 112' example is provided for illustrative purposes, and other conductive connectors 112' with different structures can also be used.

[0106] The bonding between the semiconductor die 110' and the package substrate 202 can be solder bonding or direct metal-to-metal (e.g., copper-to-copper) bonding. According to some embodiments, the semiconductor die 110' is bonded to the package substrate 202 via a reflow process. During the reflow process, conductive contacts (e.g., conductive connectors 112') contact the exposed contact pads (not shown) of the semiconductor die 110' and the exposed contact pads 206B on the surface 202B of the package substrate 202, respectively, to physically and electrically couple the semiconductor die 110' to the package substrate 202.

[0107] like Figure 2DAs shown, according to some embodiments, an underfill element 114' is formed on the surface 202B of the packaging substrate 202 to surround and protect the semiconductor die 110' and the conductive connector 112' below it, and to enhance the connection between the semiconductor die 110' and the packaging substrate 102'. In some embodiments, a portion of the underfill element 114' is located between the surface 202B and the active surface of the semiconductor die 110' and fills the gap between adjacent conductive connectors 112' to strengthen the conductive connectors 112' and even the overall packaging structure. The material and formation method of the underfill element 114' can be related to... Figure 2B The bottom filling element 106' shown (and) Figure 1B The bottom filling element 106 shown is made of the same or similar material and is formed by the same or similar method, so it will not be described again here.

[0108] like Figure 2E As shown, according to some embodiments, a molding layer 116' is formed on the surface 202B of the packaging substrate 202 to seal and protect the semiconductor die 110' and the underfill element 114'. The molding layer 116' can be separated from the conductive connector 112' below the semiconductor die 110' by the underfill element 114'. In some embodiments, the molding layer 116' also surrounds and protects the conductive pillar 208. The material and formation method of the molding layer 116' can be compared with those of the semiconductor die 110'. Figure 2B The molded layer 108' shown (and Figure 1C The molding layer 108 shown is made of the same or similar material and is formed by the same method, so it will not be described again here. In some embodiments, the molding layer 116' extends laterally to the side edge of the encapsulation substrate 202, and the side edges of the encapsulation substrate 202, the molding layer 108' and the molding layer 116' are aligned.

[0109] In some embodiments, the underfill element 114' and the molding layer 116' have different thermal and mechanical properties, for example, by having different material compositions. Each of the underfill element 114' and the molding layer 116' can be modified, for example, by adjusting the ratio of filler to epoxy resin in the individual materials used to have specific mechanical and / or thermal properties. The filler can be an inorganic material, such as alumina, silica, etc.

[0110] In some embodiments, the underfill element 114' may be relatively compliant to alleviate thermal stress, and the molding layer 116' may have a high thermal conductivity to facilitate heat dissipation. In some embodiments, the molding layer 116' has a lower coefficient of thermal expansion, a higher Young's modulus, a higher filler content percentage, or a combination thereof than the underfill element 114'. In some cases, the values ​​of the coefficient of thermal expansion, Young's modulus, and filler content of the underfill element 114' and the molding layer 116' may be the same as or similar to the values ​​of the coefficient of thermal expansion, Young's modulus, and filler content of the underfill element 106 and the molding layer 108 described above, and will not be repeated here. However, other values ​​may also be used. In some embodiments, similar to the underfill element 106 discussed above, the underfill element 114' may further alleviate thermal stress, for example, that occurs in the form of stress or strain on conductive contacts (e.g., conductive connector 112') during the molding process of the molding layer 116'. This reduces warpage of the packaging substrate 202, prevents breakage of the semiconductor die 110', and avoids delamination at the bonding interface (e.g., between the semiconductor die 110' and the conductive connector 112' and / or between the packaging substrate 202 and the conductive connector 112').

[0111] In some embodiments, a planarization process is further applied to the molding layer 116' to partially remove the molding layer 116' until the top surface 110A' of the semiconductor die 110' is exposed through the molding layer 116' (e.g., the top surface 110A' is substantially flush with the top surface 116A' of the molding layer 116'). Figure 2E As shown. This facilitates the dissipation of heat generated from the semiconductor die 110' during operation. However, in some other embodiments, the semiconductor die 110' may also be buried or sealed in the molding layer 116' after the planarization process. In some embodiments, such as Figure 2E As shown, after the planarization process, the top surface 208A of the conductive pillar 208 is also exposed through the molding layer 116' (e.g., the top surface 208A is substantially flush with the top surface 116A' of the molding layer 116' and / or the top surface 110A' of the semiconductor die 110'). The planarization process may include a polishing process, a chemical mechanical polishing (CMP) process, an etching process, a dry polishing process, one or more other optional processes, or a combination thereof.

[0112] In some embodiments, solder balls (or solder elements) are then disposed (e.g., in direct contact) on the top surface 208A of the exposed conductive post 208 (see...). Figure 2E ) on, such as Figure 2FAs shown. A reflow process is then performed to melt the solder balls to form conductive bumps 118'. In some embodiments, conductive pillars 208 (sometimes also referred to as through molding vias (TMVs)) formed in and through the molding layer 116' electrically couple the conductive bumps 118' to the package substrate 202. According to some embodiments, exposed conductive bumps 118' (sometimes also referred to as ball grid array (BGA)) allow the semiconductor package structure to bond and electrically connect to an external printed circuit board or other electronic device (not shown).

[0113] Subsequently, according to some embodiments, along Figure 2F The cutting groove G shown is used for a segmentation process (also known as a sawing process) to form multiple individual package structures. Figure 2F The image shows one of the encapsulation structures. Each encapsulation structure can be removed from the cutting tape P' using, for example, a pick-and-place tool (not shown). Figure 2G It shows in Figures 2A to 2F The semiconductor device package obtained after the process shown. Figure 2G In this process, bottom filler elements 106' and 114' are formed on both sides of the package substrate 202 to alleviate thermal stress generated during the molding process of molding layers 108' and 116', as described above. Therefore, warpage of the package substrate 202 and / or semiconductor die 110' can be reduced, and delamination at the interface between the package substrate 202 and the device packaged thereon can be avoided. As a result, the reliability of the entire package structure is improved.

[0114] Many variations and / or modifications can be made to the embodiments of this disclosure. Figure 3 This is a cross-sectional view of a semiconductor device package according to some embodiments. It should be understood that... Figure 3 Most of the structures in it are related to Figure 1G Since the parts are the same as those in the original text, only the differences will be described here. Figure 3 In this embodiment, an additional semiconductor die 310 is mounted on surface 102A of the packaging substrate 102. In some embodiments, the semiconductor die 310 and the semiconductor die 110 on surface 102B of the packaging substrate 102 may be the same or different types of electronic components. For example, semiconductor die 110 may be a processor die and semiconductor die 310 may be a memory die, but other combinations may also be used.

[0115] In some embodiments, the semiconductor die 310 is bonded to (i.e., electrically interconnected to) the surface 102A via a plurality of conductive connectors 312, such as Figure 3 As shown. In some embodiments, each conductive connector 312 includes a metal post 312A and a metal capping layer (e.g., a solder cap) 312B located on the metal post 312A, similar to Figure 1D The structure of the conductive connector 112 shown is illustrated. Before forming the aforementioned underfill element 106 and molding layer 108, the semiconductor die 310 can be bonded to the package substrate 102 using the conductive connector 312. In some embodiments, such as... Figure 3 As shown, the formed underfill element 106 also surrounds and protects the semiconductor die 310 and the conductive connector 312 below it, and enhances the connection between the semiconductor die 310 and the package substrate 102. The formed molding layer 108 also seals and protects the semiconductor die 310, and can be separated from the conductive connector 312 below the semiconductor die 310 by the underfill element 106.

[0116] like Figure 3 As shown, according to some embodiments, in the planarization process (e.g.) Figure 1C (As shown in the diagram) After this, the semiconductor die 310 is exposed through the molding layer 108 (e.g., the top surface 310A of the semiconductor die 310 is substantially flush with the top surface 108A of the molding layer 108). Figure 3 According to some embodiments, the semiconductor device package further includes a cover structure 320, which may also be a heat sink, attached to the top surface 108A of the molding layer 108 and the top surface 310A of the semiconductor die 310 using a thermal interface material 330. The cover structure 320 in this embodiment is flat, but the embodiments of this disclosure are not limited thereto. In different embodiments, the cover structure 320 may be annular or other suitable structures. The material of the cover structure 320 may include copper, steel, stainless steel, or combinations thereof. The thermal interface material 330 may be a thermally conductive and electrically insulating material, such as epoxy resin, epoxy resin mixed with a metal (such as silver or gold), thermal grease, white grease, or combinations thereof. The thermal interface material 330 may be distributed on the top surface 108A of the molding layer 108 and the top surface 310A of the semiconductor die 310. The cover structure 320 can then be placed on the thermal interface material 330 using a pick-and-place tool (not shown) to attach the cover structure 320 to the remainder of the package. In some embodiments, the rigid cover structure 320 may further constrain the underlying package substrate 102 to mitigate warping of the package substrate 102 and / or the semiconductor die 310 thereon.

[0117] In some other embodiments, after the planarization process, the semiconductor die 310 is buried or sealed in the molding layer 108 (i.e., not exposed), and / or the cap structure 320 and the thermal interface material 330 may be omitted. It should be understood that the semiconductor die 310, cap structure 320, and thermal interface material 330 described herein can also be applied to the aforementioned... Figure 2G In the semiconductor device package disclosed in the embodiments.

[0118] Many variations and / or modifications can be made to the embodiments of this disclosure. Figure 4 This is a cross-sectional view of a semiconductor device package according to some embodiments. It should be understood that... Figure 4 Most of the structures in it are related to Figure 3 Since the parts are the same as those in the original text, only the differences will be described here. Figure 4 In the package substrate 102, there is an additional molding layer 410 on the surface 102A and an additional molding layer 420 on the surface 102B of the package substrate 102.

[0119] In some embodiments, the molding layer 410 is disposed between the molding layer 108 and the underfill element 106, and surrounds and protects the semiconductor die 310, the integrated device 104, and the underfill element 106, such as... Figure 4 As shown. Molding layer 410 can be applied to surface 102A using, for example, injection molding, and then cured. Subsequently, molding layer 108 can be applied to molding layer 410 using, for example, injection molding, and then cured. According to some embodiments, each of molding layer 410 and molding layer 108 extends laterally to a side edge of the encapsulation substrate 102, such that the individual sides of the encapsulation substrate 102, molding layer 410, and molding layer 108 are connected. In some embodiments, such as Figure 4 As shown, the thickness T6 of the molding layer 410 (e.g., from surface 102A to the top surface 410A of the molding layer 410 in a direction perpendicular to surface 102A) is less than the thickness T7 of the molding layer 108 (e.g., from the top surface 410A of the molding layer 410 to the top surface 108A of the molding layer 108 in a direction perpendicular to surface 102A). However, in different embodiments, the thickness T6 may also be equal to or greater than the thickness T7.

[0120] In some embodiments, molding layer 410 and molding layer 108 have different thermal and mechanical properties, for example, by having different material compositions. Each of molding layer 410 and molding layer 108 can be modified, for example, by adjusting the ratio of filler to epoxy resin in the individual molding compound used to have specific mechanical and / or thermal properties. The filler may be an inorganic material, such as alumina, silica, etc.

[0121] In some embodiments, the molding layer 410 may be relatively flexible to alleviate thermal stress, and the molding layer 108 may have a high thermal conductivity to facilitate heat dissipation. In some embodiments, the molding layer 108 has a lower coefficient of thermal expansion than the molding layer 410, a higher Young's modulus than the molding layer 410, a higher filler content percentage than the molding layer 410, or a combination thereof. For example, the coefficient of thermal expansion of the molding layer 410 is greater than that of the molding layer 108 and less than that of the bottom filler element 106, the Young's modulus of the molding layer 410 is less than that of the molding layer 108 and greater than that of the bottom filler element 106, and / or the filler content percentage of the molding layer 410 is lower than that of the molding layer 108 and higher than that of the bottom filler element 106. Therefore, in addition to controlling warpage through the bottom filling element 106 as described above, the molding layer 410 can also reduce the warpage of the package substrate 102 by reducing the mismatch in the coefficient of thermal expansion between the package substrate 102 and the components or other materials thereon.

[0122] In some embodiments, the molding layer 420 is disposed between the molding layer 116 and the underfill element 114, and surrounds and protects the semiconductor die 110 and the underfill element 114, such as Figure 4 As shown. Molding layer 420 can be applied to surface 102B using, for example, injection molding, and then cured. Subsequently, molding layer 116 can be applied to molding layer 420 using, for example, injection molding, and then cured. According to some embodiments, each of molding layer 420 and molding layer 116 extends laterally to a side edge of the encapsulation substrate 102, such that the individual sides of the encapsulation substrate 102, molding layer 420, and molding layer 116 are connected. In some embodiments, such as Figure 4 As shown, the thickness T8 of the molding layer 420 (e.g., from surface 102B to the top surface 420A of the molding layer 420 in a direction perpendicular to surface 102B) is less than the thickness T9 of the molding layer 116 (e.g., from the top surface 420A of the molding layer 420 to the top surface 116A of the molding layer 116 in a direction perpendicular to surface 102B). However, in different embodiments, the thickness T8 may be equal to or greater than the thickness T9.

[0123] In some embodiments, molding layer 420 and molding layer 116 have different thermal and mechanical properties, for example, by having different material compositions. Each of molding layer 420 and molding layer 116 can be modified, for example, by adjusting the ratio of filler to epoxy resin in the individual molding compound used to have specific mechanical and / or thermal properties. The filler may be an inorganic material, such as alumina, silica, etc.

[0124] In some embodiments, the molding layer 420 may be relatively flexible to alleviate thermal stress, and the molding layer 116 may have a high thermal conductivity to facilitate heat dissipation. In some embodiments, the molding layer 116 has a lower coefficient of thermal expansion than the molding layer 420, a higher Young's modulus than the molding layer 420, a higher filler content percentage than the molding layer 420, or a combination thereof. For example, the coefficient of thermal expansion of the molding layer 420 is greater than that of the molding layer 116 and less than that of the bottom filler element 114; the Young's modulus of the molding layer 420 is less than that of the molding layer 116 and greater than that of the bottom filler element 114; and / or the filler content percentage of the molding layer 420 is lower than that of the molding layer 116 and higher than that of the bottom filler element 114. Therefore, in addition to controlling warpage through the bottom filling element 114 as described above, the molding layer 420 can also reduce the warpage of the package substrate 102 by reducing the mismatch in the coefficient of thermal expansion between the package substrate 102 and the components or other materials thereon.

[0125] It should be understood that the additional molding layers 410 and 420 described herein can also be applied to the aforementioned Figure 1G and Figure 2G In the semiconductor device package disclosed in the embodiments.

[0126] Embodiments of this disclosure form a semiconductor device package including a package substrate (e.g., a wiring substrate or redistribution substrate), a plurality of integrated devices located on a first surface of the package substrate, a first molding layer located on the first surface and sealing the integrated devices, a semiconductor die located on a second surface of the package substrate, and a second molding layer located on the second surface and sealing the semiconductor die. According to some embodiments, the semiconductor device package further includes a first underfill element located on the first surface of the package substrate and surrounding a conductive contact between the integrated devices and the package substrate, and a second underfill element located on the second surface of the package substrate and surrounding a conductive contact between the semiconductor die and the package substrate. The underfill element can alleviate thermal stress occurring in the form of stress or strain at the conductive contact during a high-temperature molding process, thereby reducing warpage of the package substrate and preventing delamination at the interface between the packaged device and the package substrate. Therefore, the reliability of the semiconductor device package is improved.

[0127] According to some embodiments of this disclosure, a semiconductor device package is provided. The semiconductor device package includes a package substrate, a plurality of integrated devices, a first underfill element, a first molding layer, a semiconductor die, a second underfill element, a second molding layer, and a plurality of conductive bumps. The package substrate has a first surface and a second surface opposite to the first surface. The integrated devices are bonded to the first surface. The first underfill element is disposed on the first surface and surrounds the integrated devices. The first molding layer is disposed on the first surface and surrounds the integrated devices and the first underfill element, wherein the first molding layer has a different composition than the first underfill element. The semiconductor die is bonded to the second surface. The second underfill element is disposed on the second surface and surrounds the semiconductor die. The second molding layer is disposed on the second surface and surrounds the semiconductor die and the second underfill element, wherein the second molding layer has a different composition than the second underfill element. Conductive bumps are disposed on the second surface and adjacent to the second molding layer.

[0128] In some embodiments, a first underfill element has a higher coefficient of thermal expansion than a first molding layer, and a second underfill element has a higher coefficient of thermal expansion than a second molding layer. In some embodiments, a first molding layer has a higher Young's modulus than a first underfill element, and a second molding layer has a higher Young's modulus than a second underfill element. In some embodiments, a first molding layer has a higher filler content percentage than a first underfill element, and a second molding layer has a higher filler content percentage than a second underfill element. In some embodiments, a semiconductor die is bonded to a second surface via a plurality of conductive connectors, and a portion of the second underfill element is located between the second surface and a surface of the semiconductor die facing the second surface to surround the conductive connectors. In some embodiments, the semiconductor die is exposed from the second molding layer. In some embodiments, conductive bumps are in direct contact with the second surface and are exposed from the second molding layer. In some embodiments, conductive bumps are disposed on the second molding layer, and the semiconductor device package further includes a plurality of through-holes formed in and through the second molding layer to electrically connect the conductive bumps to a package substrate. In some embodiments, the integrated device includes an integrated passive device. In some embodiments, the semiconductor die extends across two or more integrated devices.

[0129] According to other embodiments of this disclosure, a semiconductor device package is provided. The semiconductor device package includes a package substrate, a plurality of integrated devices, a first underfill element, a first molding layer, a first semiconductor die, and a second underfill element. The package substrate has a first surface and a second surface opposite to the first surface. The integrated devices are bonded to the first surface, wherein the integrated devices include a first integrated device and a second integrated device, and the thickness of the first integrated device is greater than that of the second integrated device. The first underfill element is disposed on the first surface and surrounds the integrated devices, wherein a first portion of the first underfill element in contact with the first integrated device is greater than a second portion of the first underfill element in contact with the second integrated device. The first molding layer is disposed on the first surface and seals the integrated devices and the first underfill element, wherein the first molding layer has a different composition than the first underfill element. The first semiconductor die is bonded to the second surface. The second underfill element is disposed on the second surface and surrounds the first semiconductor die.

[0130] In some embodiments, the semiconductor device package further includes a second molding layer and a plurality of conductive bumps. The second molding layer is disposed on a second surface of the package substrate and seals a first semiconductor die and a second underfill element. The second molding layer has a different composition from the second underfill element, and the conductive bumps are disposed on the second surface and adjacent to the second molding layer. In some embodiments, the semiconductor device package further includes a second semiconductor die bonded to a first surface of the package substrate. The second semiconductor die is surrounded by a first underfill element and sealed by the first molding layer. In some embodiments, a surface of the second semiconductor die is exposed through the first molding layer, and the semiconductor device package further includes a thermal interface material and a cap structure. The thermal interface material is located on the surface of the second semiconductor die, and the cap structure is attached to the thermal interface material. In some embodiments, the semiconductor device package further includes a third molding layer disposed between the first molding layer and the first underfill element and surrounding the second semiconductor die, the integrated device, and the first underfill element. The third molding layer has a different composition from the first molding layer and the first underfill element.

[0131] According to other embodiments of this disclosure, a method for forming a semiconductor device package is provided. The method includes bonding a plurality of integrated devices to a first surface of a package substrate. The method further includes forming a first underfill element on the first surface to surround the integrated devices. The method further includes forming a first molding layer on the first surface to seal the integrated devices and the first underfill element, wherein the first molding layer has a different composition than the first underfill element. The method further includes bonding a semiconductor die to a second surface of the package substrate opposite to the first surface. The method further includes forming a second underfill element on the second surface to surround the semiconductor die. The method further includes forming a second molding layer on the second surface to seal the semiconductor die and the second underfill element, wherein the second molding layer has a different composition than the second underfill element. Furthermore, the method includes disposing a plurality of conductive bumps on the second surface and adjacent to the second molding layer.

[0132] In some embodiments, the first molding layer has a lower coefficient of thermal expansion than the first underfill element, a higher Young's modulus than the first underfill element, a higher filler content percentage than the first underfill element, or a combination thereof. In some embodiments, the second molding layer has a lower coefficient of thermal expansion than the second underfill element, a higher Young's modulus than the second underfill element, a higher filler content percentage than the second underfill element, or a combination thereof. In some embodiments, the method of forming a semiconductor device package further includes: bonding an additional semiconductor die to a first surface prior to forming the first underfill element and the first molding layer, wherein the formed first underfill element more surrounds the additional semiconductor die, the formed first molding layer more seals the additional semiconductor die, and a surface of the additional semiconductor die is exposed through the first molding layer; applying a thermal interface material to the surface of the additional semiconductor die; and attaching a cap structure to the thermal interface material. In some embodiments, the method of forming a semiconductor device package further includes: forming a third molding layer between a first molding layer and a first underfill element to surround an additional semiconductor die, an integrated device, and a first underfill element, wherein the third molding layer has a different composition from the first molding layer and the first underfill element; and / or forming a fourth molding layer between a second molding layer and a second underfill element to surround a semiconductor die and a second underfill element, wherein the fourth molding layer has a different composition from the second molding layer and the second underfill element.

[0133] The foregoing outlines features of numerous embodiments, enabling those skilled in the art to better understand this disclosure from various perspectives. Those skilled in the art will understand that other processes and structures can be readily designed or modified based on this disclosure to achieve the same objectives and / or the same advantages as the embodiments described herein. Those skilled in the art will also understand that these equivalent structures do not depart from the inventive spirit and scope of this disclosure. Various changes, substitutions, or modifications can be made to this disclosure without departing from its inventive spirit and scope.

Claims

1. A semiconductor device package, comprising: A packaging substrate has a first surface and a second surface opposite to the first surface; Multiple integrated devices are attached to the first surface; A first bottom filling element is disposed on the first surface and surrounds the integrated device; A first molding layer is disposed on the first surface and surrounds the integrated device and the first underfill element, wherein the first molding layer has a different composition from the first underfill element; A semiconductor die is bonded to the second surface; A second bottom filling element is disposed on the second surface and surrounds the semiconductor grain; A second molding layer is disposed on the second surface and surrounds the semiconductor die and the second bottom filler element, wherein the second molding layer has a different composition from the second bottom filler element; Multiple conductive bumps are disposed on the second surface and adjacent to the second molding layer; A third molding layer is disposed between the first molding layer and the first underfill element, surrounding the integrated device and the first underfill element and contacting the first surface, wherein the third molding layer has a different composition from the first molding layer and the first underfill element, and the coefficient of thermal expansion of the third molding layer is greater than the coefficient of thermal expansion of the first molding layer and less than the coefficient of thermal expansion of the first underfill element; as well as A fourth molding layer is disposed between the second molding layer and the second bottom filler element, surrounding the semiconductor die and the second bottom filler element and contacting the second surface, wherein the fourth molding layer has a different composition from the second molding layer and the second bottom filler element, and the coefficient of thermal expansion of the fourth molding layer is greater than the coefficient of thermal expansion of the second molding layer and less than the coefficient of thermal expansion of the second bottom filler element.

2. The semiconductor device package of claim 1, wherein the first molding layer has a higher Young's modulus than the third molding layer, the third molding layer has a higher Young's modulus than the first underfill element, the second molding layer has a higher Young's modulus than the fourth molding layer, and the fourth molding layer has a higher Young's modulus than the second underfill element.

3. The semiconductor device package of claim 1, wherein the first molding layer has a higher filler content percentage than the third molding layer, the third molding layer has a higher filler content percentage than the first bottom filler element, the second molding layer has a higher filler content percentage than the fourth molding layer, and the fourth molding layer has a higher filler content percentage than the second bottom filler element.

4. The semiconductor device package of claim 1, wherein the semiconductor die is bonded to the second surface via a plurality of conductive connectors, and a portion of the second bottom fill element is located between the second surface and a surface of the semiconductor die facing the second surface to surround the conductive connectors.

5. The semiconductor device package of claim 1, wherein the semiconductor die is exposed from the second molding layer.

6. The semiconductor device package of claim 1, wherein the conductive bumps pass through the second molding layer and the fourth molding layer, directly contact the second surface, and are exposed from the second molding layer.

7. The semiconductor device package of claim 1, wherein the conductive bump is disposed on the second molding layer, and the semiconductor device package further includes a plurality of through holes formed in and through the second molding layer to electrically connect the conductive bump to the package substrate.

8. The semiconductor device package of claim 1, wherein the integrated device includes an integrated passive device.

9. The semiconductor device package of claim 1, wherein the semiconductor die extends across two or more of the integrated devices.

10. A semiconductor device package, comprising: A packaging substrate has a first surface and a second surface opposite to the first surface; Multiple integrated devices are joined to the first surface, wherein the integrated devices include a first integrated device and a second integrated device, and the thickness of the first integrated device is greater than that of the second integrated device; A first bottom filler element is disposed on the first surface and surrounds the integrated device, wherein the thickness of a first portion of the first bottom filler element in contact with the first integrated device is greater than the thickness of a second portion of the first bottom filler element in contact with the second integrated device; A first molding layer is disposed on the first surface and seals the integrated device and the first underfill element, wherein the first molding layer has a different composition from the first underfill element; A first semiconductor die is bonded to the second surface; A second bottom filling element is disposed on the second surface and surrounds the first semiconductor grain; as well as A second molding layer is disposed between the first molding layer and the first underfill element, surrounding the integrated device and the first underfill element and contacting the first surface, wherein the second molding layer has a different composition from the first molding layer and the first underfill element, and the coefficient of thermal expansion of the second molding layer is greater than the coefficient of thermal expansion of the first molding layer and less than the coefficient of thermal expansion of the first underfill element.

11. The semiconductor device package of claim 10, further comprising: A third molding layer is disposed on the second surface of the packaging substrate and seals the first semiconductor die and the second underfill element, wherein the third molding layer has a different composition from the second underfill element; as well as Multiple conductive bumps are disposed on the second surface and adjacent to the third molding layer.

12. The semiconductor device package of claim 10, further comprising: A second semiconductor die is bonded to the first surface of the package substrate, wherein the second semiconductor die is surrounded by the first bottom filler element and the second molding layer and sealed by the first molding layer, wherein one surface of the second semiconductor die is higher than a top surface of the second molding layer.

13. The semiconductor device package of claim 12, wherein the surface of the second semiconductor die is exposed through the first molding layer, and the semiconductor device package further comprises: A thermal interface material is located on the surface of the second semiconductor grain; as well as A cover structure is attached to the thermal interface material.

14. A method for forming a semiconductor device package, comprising: Multiple integrated devices are bonded to a first surface of a packaging substrate; A first bottom filling element is formed on the first surface to surround the integrated device; A first molding layer is formed on the first surface to seal the integrated device and the first underfill element, wherein the first molding layer has a different composition from the first underfill element; A semiconductor die is bonded to a second surface of the packaging substrate that is opposite to the first surface; A second bottom filling element is formed on the second surface to surround the semiconductor grain; A second molding layer is formed on the second surface to seal the semiconductor die and the second underfill element, wherein the second molding layer has a different composition from the second underfill element; Multiple conductive bumps are disposed on the second surface and adjacent to the second molding layer; as well as A third molding layer is formed between the first molding layer and the first underfill element to surround the first underfill element of the integrated device and contact the first surface, wherein the third molding layer has a different composition from the first molding layer and the first underfill element, and the coefficient of thermal expansion of the third molding layer is greater than the coefficient of thermal expansion of the first molding layer and less than the coefficient of thermal expansion of the first underfill element.

15. The method of forming a semiconductor device package as claimed in claim 14, wherein the third molding layer has a higher Young's modulus than the first underfill element and a lower filler content percentage than the first molding layer, or a combination thereof.

16. The method of forming a semiconductor device package as claimed in claim 14, wherein the second molding layer has a lower coefficient of thermal expansion, a higher Young's modulus, a higher filler content percentage, or a combination thereof than the second underfill element.

17. The method of forming a semiconductor device package as claimed in claim 14, further comprising: Prior to forming the first underfill element, the third molding layer, and the first molding layer, an additional semiconductor die is bonded to the first surface, wherein the formed first underfill element and the third molding layer further surround the additional semiconductor die, the formed first molding layer further seals the additional semiconductor die, and one surface of the additional semiconductor die is exposed through the first molding layer. A thermal interface material is applied to the surface of the additional semiconductor grain; as well as A cover structure is attached to the thermal interface material.

18. The method of forming a semiconductor device package as claimed in claim 17, further comprising: A fourth molding layer is formed between the second molding layer and the second underfill element to surround the semiconductor die and the second underfill element and to contact the second surface, wherein the fourth molding layer has a different composition from the second molding layer and the second underfill element, and the coefficient of thermal expansion of the fourth molding layer is greater than the coefficient of thermal expansion of the second molding layer and less than the coefficient of thermal expansion of the second underfill element.

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