A variable gain power amplifier

Abstract

The present invention belongs to the field of wireless communication technology and discloses a variable gain power amplifier. The present invention comprises a differential common source with a neutralizing capacitor to improve a gain control circuit, and a differential common source with a neutralizing capacitor circuit to form a two-stage or multi-stage variable gain power amplifier. The two-stage or multi-stage variable gain power amplifier is formed by the differential common source with a neutralizing capacitor to improve the gain control circuit and the differential common source with a neutralizing capacitor circuit. The present invention solves the problems of existing variable gain power amplifiers, such as AM-PM distortion, complex layout structure, inability to achieve maximum output power matching, and low linearity.

Description

Technical Field

[0001] The present invention relates to the technical field of wireless communications, and in particular to a variable gain power amplifier. Background Art

[0002] A transmitter chip generally needs to perform multiple functions, including frequency conversion, phase conversion, amplitude conversion, and high-power output of the transmitted signal. The implementation of these multiple functions can affect each other. For example, a transmitter uses a power amplifier to achieve sufficient power output, but the AM-PM distortion of the power amplifier will affect the phase of the output signal. A general gain control unit (such as a variable gain amplifier or attenuator) will also cause the signal phase to change when controlling the link gain to achieve signal amplitude conversion. The phase changes of the above two signals are generally uncontrollable, and it is generally desired that the phase change of the signal be completed only by the phase shifter. Therefore, it is very important to achieve low phase fluctuations in the signal between the power amplifier and the gain control unit when the link gain state changes.

[0003] Nowadays, when considering achieving low phase fluctuation of the signal between the power amplifier and the gain control unit when the link gain state changes, two modules are generally designed separately, such as AM-PM distortion compensation for the power amplifier and low additive phase shift technology for the gain control unit. However, the above approach will degrade other performance of the link. For example, in the paper "M.Abdulaziz, HVHünerli, K.Buisman and C.Fager,"Improvement of AM–PM in a 33-GHz CMOS SOI Power Amplifier Using pMOS Neutralization," in IEEE Microwave and Wireless Components Letters, vol. 29, no. 12, pp. 798-801, Dec. 2019, doi: 10.1109 / LMWC.2019.2948763.", Figure 1As shown in the figure, this design uses PMOS transistors to compensate for AM-PM distortion. Although it achieves good AM-PM distortion performance, this technology sacrifices the gain and PAE of the power amplifier. However, if the gain control unit wants to achieve low additional phase shift, it will also have disadvantages such as complex circuit structure, large layout area, and low linearity. For example, in the paper "T.Wu, C.Zhao, H.Liu, Y.Wu, Y.Yu and K.Kang,"A 20~43GHz VGA with 21.5dB Gain Tuning Range and Low Phase Variation for 5G Communications in 65-nm CMOS," 2019 IEEE RadioFrequency Integrated Circuits Symposium (RFIC), 2019, pp.71-74, doi:10.1109 / RFIC.2019.8701807.", Figure 2 As shown in the figure, the structure uses a cross-coupling structure to offset the parasitic capacitance between the gate and drain of the transistor. Since the bias difference between the two transistors in the high gain state is large, a large difference in gate-source parasitic capacitance will be generated. Therefore, the asymmetric capacitor V a and V b Compensation is achieved to achieve low additional phase shift, but its layout structure is complex, and in order to achieve low additional phase shift, it cannot achieve maximum output power matching, its linearity is low, and it is not suitable for application in power amplifiers. Summary of the Invention

[0004] In view of the above-mentioned deficiencies in the prior art, the present invention provides a variable gain power amplifier that solves the problems of AM-PM distortion, complex layout structure, inability to achieve maximum output power matching and low linearity in the prior art variable gain power amplifier.

[0005] In order to achieve the above-mentioned object of the invention, the technical solution adopted by the present invention is: a variable gain power amplifier, comprising: a differential common source with a neutralizing capacitor to improve the gain control circuit, and a differential common source with a neutralizing capacitor circuit to form a two-stage or multi-stage variable gain power amplifier;

[0006] When forming a two-stage cascade, the invention comprises: a differential common source with a neutralizing capacitor to improve the gain control circuit and a differential common source with a neutralizing capacitor circuit;

[0007] The output end of the differential common source with neutralization capacitor improved gain control circuit is connected to the input end of the differential common source with neutralization capacitor circuit through a matching network, the input end of the differential common source with neutralization capacitor improved gain control circuit serves as the input end of the variable gain power amplifier, and the output end of the differential common source with neutralization capacitor circuit serves as the output end of the variable gain power amplifier;

[0008] When forming a multi-stage cascade, it includes: a differential common source with neutralizing capacitor improved gain control circuit and multiple differential common source with neutralizing capacitor circuits;

[0009] The plurality of differential common source strip neutralizing capacitor circuits are sequentially connected in series, and a matching network is connected between every two adjacent differential common source strip neutralizing capacitor circuits;

[0010] The input end of the differential common source with neutralization capacitor improved gain control circuit serves as the input end of the variable gain power amplifier, the output end of the differential common source with neutralization capacitor circuit is connected to the input end of the first differential common source with neutralization capacitor circuit through a matching network, the output end of the differential common source with neutralization capacitor circuit is connected to the input end of the adjacent differential common source with neutralization capacitor circuit through a matching network, and the output end of the last differential common source with neutralization capacitor circuit serves as the output end of the variable gain power amplifier.

[0011] Furthermore, the differential common source with neutralizing capacitor circuit includes: NMOS tube M1, NMOS tube M2, neutralizing capacitor C f1 and neutralizing capacitor C f2 ;

[0012] The gate of the NMOS tube M1 and the neutralizing capacitor C f1 One end is connected to the negative input terminal Vin- of the differential common source with neutralizing capacitor circuit, and its drain is connected to the neutralizing capacitor C f2 One end of the differential common source is connected to the positive output terminal Vout+ of the neutralizing capacitor circuit, and its source is connected to the source of the NMOS tube M2 and grounded;

[0013] The gate of the NMOS tube M2 and the neutralizing capacitor C f2 One end is connected to the positive input terminal Vin+ of the differential common source and capacitor circuit, and its drain is connected to the capacitor C f1 The other end is connected and serves as the negative output terminal Vout- of the differential common source and capacitor circuit.

[0014] Furthermore, the differential common source with neutralization capacitor improved gain control circuit includes: neutralization capacitor C f3 , neutralizing capacitor C f4 , NMOS tube M3, NMOS tube M4, NMOS tube M5, NMOS tube M6, resistor R1 and resistor R2;

[0015] The gate of the NMOS tube M3 is respectively connected to the neutralization capacitor C f3 One end of the NMOS tube M5 is connected to the drain, and serves as the positive input terminal Vin+ of the differential common source with neutralizing capacitor to improve the gain control circuit. Its drain is connected to the neutralizing capacitor C f4One end of the differential common source is connected to the negative output terminal Vout- of the neutralizing capacitor improved gain control circuit, and its source is connected to the source of the NMOS tube M4 and grounded;

[0016] The drain of the NMOS tube M4 and the capacitor C f3 The other end is connected and used as the positive output terminal Vout+ of the differential common source with neutralization capacitor to improve the gain control circuit, and its gate is connected to the neutralization capacitor C f4 The other end of the transistor is connected to the drain of the NMOS transistor M6 and serves as the negative input terminal Vin- of the differential common source with neutralization capacitor improved gain control circuit; the source of the NMOS transistor M5 is grounded, and the gate thereof is connected to one end of the resistor R1; the source of the NMOS transistor M6 is grounded, and the gate thereof is connected to one end of the resistor R2; the other end of the resistor R1 serves as the control voltage input terminal VC1 of the differential common source with neutralization capacitor improved gain control circuit; the other end of the resistor R2 serves as the control voltage input terminal VC2 of the differential common source with neutralization capacitor improved gain control circuit.

[0017] In summary, the beneficial effects of the present invention are:

[0018] 1. The differential common source with neutralizing capacitor improves the output signal of the gain control circuit in the present invention. When the control voltage VC decreases, the phase of the output signal increases. The differential common source with neutralizing capacitor circuit increases when the gate voltage V pa When the gain is reduced, the phase of the output signal decreases, and the phase increase of the front-stage circuit is compensated by the phase reduction of the rear-stage circuit, thereby improving the output signal phase fluctuation when the gain changes and solving the AM-PM distortion problem.

[0019] 2. Gain control typically uses active cross-coupling circuits to improve phase fluctuations. However, active cross-coupling circuits have high layout complexity, making them difficult to design. However, the two amplifier circuits used in this invention offer simple structures, flexible applications, and minimal circuit and layout complexity.

[0020] 3. Conventional gain control improves phase fluctuations, and its output matching is often conjugate matching. Therefore, it cannot achieve low phase fluctuations in the amplifier output signal while simultaneously outputting maximum power. Due to the different operating states of the cross-coupled transistors, its linearity is also low. However, the present invention improves phase fluctuations by using a two- or multi-stage cascade. This allows the gain control stage to achieve conjugate matching, while the other stages use maximum power matching. The linearity of the amplifier is dominated by the remaining amplifiers, excluding the gain control stage. Therefore, it is possible to achieve low phase fluctuations in the amplifier output signal while simultaneously outputting maximum power, thereby improving the amplifier's linearity. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 The circuit diagram of a power amplifier using PMOS for AM-PM distortion compensation.

[0022] Figure 2 This is a circuit diagram of an active cross-coupled variable gain amplifier.

[0023] Figure 3 The diagram shows a two-stage cascade connection consisting of a differential common source with neutralizing capacitor improved gain control circuit and a differential common source with neutralizing capacitor circuit.

[0024] Figure 4 The specific circuit diagram of the two-stage cascade;

[0025] Figure 5 Specific circuit diagram for multi-stage cascade;

[0026] Figure 6 This is the circuit diagram of the differential common source and capacitor circuit.

[0027] Figure 7 Circuit diagram of a gain control circuit improved with neutralizing capacitors for differential common source.

[0028] Figure 8 This is a small signal schematic diagram of a single-tube common-source amplifier.

[0029] Figure 9 This is a simplified small signal schematic diagram of a common-source transistor.

[0030] Figure 10 This is a simplified small signal schematic diagram of a parallel variable resistor common-source transistor.

[0031] Figure 11 Figure 2 shows the additional phase shift simulation results of the proposed two-stage cascade structure. DETAILED DESCRIPTION

[0032] The specific embodiments of the present invention are described below to facilitate understanding of the present invention by those skilled in the art. However, it should be clear that the present invention is not limited to the scope of the specific embodiments. For those skilled in the art, as long as various changes are within the spirit and scope of the present invention as defined and determined by the appended claims, these changes are obvious, and all inventions and creations utilizing the concepts of the present invention are protected.

[0033] like Figure 3 As shown, a variable gain power amplifier comprises: a differential common source with a neutralizing capacitor to improve the gain control circuit, and a differential common source with a neutralizing capacitor circuit to form a two-stage or multi-stage variable gain power amplifier;

[0034] like Figures 3-4 As shown, when forming a two-stage cascade, it includes: a differential common source with neutralizing capacitor improved gain control circuit and a differential common source with neutralizing capacitor circuit;

[0035] The output end of the differential common source with neutralization capacitor improved gain control circuit is connected to the input end of the differential common source with neutralization capacitor circuit through a matching network, the input end of the differential common source with neutralization capacitor improved gain control circuit serves as the input end of the variable gain power amplifier, and the output end of the differential common source with neutralization capacitor circuit serves as the output end of the variable gain power amplifier;

[0036] like Figure 5 As shown, when forming a multi-stage cascade, it includes: a differential common source with neutralizing capacitor improved gain control circuit and multiple differential common source with neutralizing capacitor circuits;

[0037] The plurality of differential common source strip neutralizing capacitor circuits are sequentially connected in series, and a matching network is connected between every two adjacent differential common source strip neutralizing capacitor circuits;

[0038] The input end of the differential common source with neutralization capacitor improved gain control circuit serves as the input end of the variable gain power amplifier, the output end of the differential common source with neutralization capacitor circuit is connected to the input end of the first differential common source with neutralization capacitor circuit through a matching network, the output end of the differential common source with neutralization capacitor circuit is connected to the input end of the adjacent differential common source with neutralization capacitor circuit through a matching network, and the output end of the last differential common source with neutralization capacitor circuit serves as the output end of the variable gain power amplifier.

[0039] like Figure 6 As shown, the differential common source with neutralizing capacitor circuit includes: NMOS tube M1, NMOS tube M2, and neutralizing capacitor C f1 and neutralizing capacitor C f2 ;

[0040] The gate of the NMOS tube M1 and the neutralizing capacitor C f1 One end is connected to the negative input terminal Vin- of the differential common source with neutralizing capacitor circuit, and its drain is connected to the neutralizing capacitor C f2 One end of the differential common source is connected to the positive output terminal Vout+ of the neutralizing capacitor circuit, and its source is connected to the source of the NMOS tube M2 and grounded;

[0041] The gate of the NMOS tube M2 and the neutralizing capacitor C f2 One end is connected to the positive input terminal Vin+ of the differential common source and capacitor circuit, and its drain is connected to the capacitor C f1 The other end is connected and serves as the negative output terminal Vout- of the differential common source and capacitor circuit.

[0042] like Figure 7 As shown, the differential common source with neutralizing capacitor improved gain control circuit includes: neutralizing capacitor C f3 , neutralizing capacitor C f4, NMOS tube M3, NMOS tube M4, NMOS tube M5, NMOS tube M6, resistor R1 and resistor R2;

[0043] The gate of the NMOS tube M3 is respectively connected to the neutralization capacitor C f3 One end of the NMOS tube M5 is connected to the drain, and serves as the positive input terminal Vin+ of the differential common source with neutralizing capacitor to improve the gain control circuit. Its drain is connected to the neutralizing capacitor C f4 One end of the differential common source is connected to the negative output terminal Vout- of the neutralizing capacitor improved gain control circuit, and its source is connected to the source of the NMOS tube M4 and grounded;

[0044] The drain of the NMOS tube M4 and the capacitor C f3 The other end is connected and used as the positive output terminal Vout+ of the differential common source with neutralization capacitor to improve the gain control circuit, and its gate is connected to the neutralization capacitor C f4 The other end of the transistor is connected to the drain of the NMOS transistor M6 and serves as the negative input terminal Vin- of the differential common source with neutralization capacitor improved gain control circuit; the source of the NMOS transistor M5 is grounded, and the gate thereof is connected to one end of the resistor R1; the source of the NMOS transistor M6 is grounded, and the gate thereof is connected to one end of the resistor R2; the other end of the resistor R1 serves as the control voltage input terminal VC1 of the differential common source with neutralization capacitor improved gain control circuit; the other end of the resistor R2 serves as the control voltage input terminal VC2 of the differential common source with neutralization capacitor improved gain control circuit.

[0045] When forming a two-stage cascade, the differential common source with a neutralizing capacitor improves the gain control circuit to form a gain control stage, and the differential common source with a neutralizing capacitor circuit serves as a power stage.

[0046] When forming a multi-stage cascade, the differential common source with neutralizing capacitor improves the gain control circuit to form a gain control stage, the differential common source with neutralizing capacitor circuit in the middle forms a driving stage, and the differential common source with neutralizing capacitor circuit at the end forms a power stage;

[0047] The input end of the gain control stage, the output end of the gain control stage, the input end of the driver stage, the output end of the driver stage, the input end of the power stage and the output end of the power stage all need to be connected to the matching network when in use, such as Figures 4-5 shown.

[0048] In this embodiment, the resistor R1 and the resistor R2 are large resistors of 10 kΩ.

[0049] In this embodiment, the matching network can be implemented by a transformer to isolate DC, pass AC, match input impedance, and match output impedance, and DC power supply and gate voltage setting can be implemented through transformer taps.

[0050] When working, the following voltages are provided to the variable gain power amplifier: The gate voltage of the differential common source neutralizing capacitor circuit is V pa In the differential common source with neutralization capacitor to improve the gain control circuit, the gate voltage of the common source tubes M3 and M4 is V vga , the differential common source with neutralization capacitor improves the gain control circuit. The NMOS tubes M5 and M6 are set to gate voltage V through large resistors R1 or R2. c . Simultaneously control Figure 6 The gate voltage V pa as well as Figure 7 The control voltage VC1 or VC2 of the circuit can achieve the effect of reducing the link gain of the cascade amplification link while reducing the output signal phase fluctuation.

[0051] Working principle of the present invention:

[0052] The small signal diagram of a single-tube common-source amplifier is as follows Figure 8 As shown. gd 、C gs 、C ds They are gate-drain parasitic capacitance, gate-source parasitic capacitance, and drain-source parasitic capacitance, respectively. gs is the gate-source small signal swing, r ds is the internal resistance, Z L is the load, v out is the output voltage, g m is the transconductance, and the current flowing through the capacitor C gd The current is I, the voltage of the gate node is V, and the following equation is obtained:

[0053]

[0054] Where r is the real part of the drain-source impedance, x is the imaginary part of the drain-source impedance, and ω is the angular frequency.

[0055] Capacitor C gs Rear input impedance Z in It can be expressed as formula (2):

[0056]

[0057] From this we can get Z in The real part Re(Z in ) is formula (3):

[0058]

[0059] Z in The imaginary part im(Z in) Formula (4):

[0060]

[0061] When using the neutralizing capacitor technique, the parasitic capacitance C gd The influence of Z in The real part Re(Z in ) and the imaginary part im(Z in ) is formula (5) and formula (6):

[0062]

[0063]

[0064] So the capacitor C gs The rear part is regarded as the equivalent resistance R eff Series equivalent capacitance C eff , its schematic diagram is as follows Figure 9 shown.

[0065] pass Figure 8 、 Figure 9 It is easy to see that formula (7) holds:

[0066] V out =-g m Z L v gs (7)

[0067] From formula (7), we can get formula (8):

[0068] ∠V out =-∠v gs (8)

[0069] Here, ∠ is the sign of the angle.

[0070] That is, to analyze the output signal phase, only the parasitic capacitance C needs to be analyzed. gs The signal phase on the

[0071] Let f be the frequency, ω=2πf, then Figure 9 We can get formula (9):

[0072]

[0073] Where i is the input current of the transistor.

[0074] Let the denominator of the above formula be

[0075]

[0076] Among them, a and b are intermediate variables.

[0077] At this point, it is easy to see that equation (11) and equation (2) hold true:

[0078]

[0079]

[0080] Formula (9) can be rewritten as formula (13):

[0081]

[0082] After separating the real and imaginary parts, we can get formula (14):

[0083]

[0084] Finally, the phase of the signal output from the amplifier to the load is obtained as formula (15):

[0085]

[0086] At this point, it is easy to know that since a and ω are greater than 0, when the static bias voltage decreases, the gain of the differential common source neutralization capacitor circuit decreases. At this time, the parasitic capacitance C gs As the capacitance decreases, the output signal phase at the load decreases.

[0087] For Figure 7 The differential common source with neutralization capacitance improves the gain control circuit shown. Since the drains of transistors M5 and M6 are connected to the ground, their parasitic capacitance is C gd Series C gs Then connect C in parallel ds , which has little effect on the signal phase and can be ignored during analysis, so transistors M5 and M6 can be equivalent to variable resistors, and the same Figure 9 Set up, parallel variable resistor R3, such as Figure 10 shown.

[0088] Its parasitic capacitance is C gs The voltage signal on , it is easy to get formula (16):

[0089]

[0090] Among them, R3 is the resistance value of the variable resistor R3 connected to the circuit.

[0091] Using the assumptions of formula (10), we can get formula (17):

[0092]

[0093] After separating the real and imaginary parts, we can get formula (18):

[0094]

[0095] Finally, the phase of the signal output from the amplifier to the load is obtained as formula (19):

[0096]

[0097] At this point, it is easy to know that since a is greater than 0, when designing (ωC gs -b) is less than 0, so when the control voltage VC increases (control voltage VC1 and control voltage VC2), the gain of the differential common source neutralizing capacitor improved gain control circuit decreases, at this time the resistance of the variable resistor R3 decreases, and the phase of the output signal on the load increases.

[0098] Figure 6 The differential common source with neutralizing capacitor circuit shown reduces the gate voltage V pa , its gain decreases, the phase of the output signal decreases, Figure 7 The differential common source with neutralizing capacitors improves the gain control circuit shown. As the control voltage VC decreases, the gain decreases and the phase of the output signal increases, achieving a two-stage compensation effect. This allows a two-stage amplifier cascade to achieve phase predistortion, thereby reducing output signal phase fluctuations when gain changes. Figure 11 The simulation results of the additional phase shift of the two-stage cascade structure show that the additional phase shift is less than 0.5° when the gain changes after adopting this structure.

[0099] The present invention includes the following beneficial effects:

[0100] 1. The differential common source with neutralizing capacitor improves the output signal of the gain control circuit in the present invention. When the control voltage VC decreases, the gain decreases and the phase of the output signal increases. The differential common source with neutralizing capacitor circuit increases when the gate voltage V pa When it decreases, the gain decreases and the output signal phase decreases. The phase increase of the previous circuit is compensated by the phase reduction of the subsequent circuit, thereby improving the output signal phase fluctuation when the gain changes.

[0101] 2. Gain control typically uses active cross-coupling circuits to improve phase fluctuations. However, active cross-coupling circuits have high layout complexity, making them difficult to design. However, the two amplifier circuits used in this invention offer simple structures, flexible applications, and minimal circuit and layout complexity.

[0102] 3. In order to improve phase fluctuation, the final amplifier generally adopts AM-PM cancellation technology. Generally, compared with the differential common source with neutralizing capacitor circuit, the above technology has lower gain. This will result in the amplifier using AM-PM cancellation technology having lower PAE when the amplifier outputs the same power. The power consumption of the final amplifier accounts for a large part of the link power consumption. Therefore, if the final amplifier does not adopt AM-PM cancellation technology, the PAE of the entire link will be significantly improved.

[0103] 4. Since two or more stages are used to prevent phase distortion, different gain states can be achieved by adjusting the gain states of the two-stage amplifiers separately. That is, a certain gain state of the link actually corresponds to a combination of the gain states of multiple amplifiers at each stage (for example, if the link desires a gain state that is 1dB lower than the maximum gain state, then for a two-stage cascade amplification structure, the final stage gain can be reduced by 0.7dB and the previous stage gain by 0.3dB, or the final stage gain can be reduced by 0.5dB and the previous stage gain by 0.5dB, so one gain state corresponds to multiple combinations). In specific implementation, the combination with the smallest link output signal phase fluctuation can be selected, thereby achieving lower output signal phase fluctuation for the entire link.

Claims

1. A variable gain power amplifier, characterized in that: include: A differential common source with a neutralizing capacitor to improve the gain control circuit, and a differential common source with a neutralizing capacitor circuit to form a two-stage or multi-stage variable gain power amplifier; When forming a two-stage cascade, the invention comprises: a differential common source with a neutralizing capacitor to improve the gain control circuit and a differential common source with a neutralizing capacitor circuit; The output end of the differential common source with neutralization capacitor improved gain control circuit is connected to the input end of the differential common source with neutralization capacitor circuit through a matching network, the input end of the differential common source with neutralization capacitor improved gain control circuit serves as the input end of the variable gain power amplifier, and the output end of the differential common source with neutralization capacitor circuit serves as the output end of the variable gain power amplifier; When forming a multi-stage cascade, it includes: a differential common source with neutralizing capacitor improved gain control circuit and multiple differential common source with neutralizing capacitor circuits; The plurality of differential common source strip neutralizing capacitor circuits are sequentially connected in series, and a matching network is connected between every two adjacent differential common source strip neutralizing capacitor circuits; The input end of the differential common source with neutralization capacitor improved gain control circuit serves as the input end of the variable gain power amplifier, the output end of the differential common source with neutralization capacitor circuit is connected to the input end of the first differential common source with neutralization capacitor circuit through a matching network, the output end of the differential common source with neutralization capacitor circuit is connected to the input end of the adjacent differential common source with neutralization capacitor circuit through a matching network, and the output end of the last differential common source with neutralization capacitor circuit serves as the output end of the variable gain power amplifier; The differential common source with neutralization capacitor improved gain control circuit includes: a neutralization capacitor C f3 , neutralizing capacitor C f4 , NMOS tube M3, NMOS tube M4, NMOS tube M5, NMOS tube M6, resistor R1 and resistor R2; The gate of the NMOS tube M3 is respectively connected to the neutralization capacitor C f3 One end of the NMOS tube M5 is connected to the drain, and serves as the positive input terminal Vin+ of the differential common source with neutralizing capacitor to improve the gain control circuit. Its drain is connected to the neutralizing capacitor C f4 One end of the differential common source is connected to the negative output terminal Vout- of the neutralizing capacitor improved gain control circuit, and its source is connected to the source of the NMOS tube M4 and grounded; The drain of the NMOS tube M4 and the capacitor C f3 The other end is connected and used as the positive output terminal Vout+ of the differential common source with neutralization capacitor to improve the gain control circuit, and its gate is connected to the neutralization capacitor C f4 The other end of the transistor is connected to the drain of the NMOS transistor M6 and serves as the negative input terminal Vin- of the differential common source with neutralization capacitor improved gain control circuit; the source of the NMOS transistor M5 is grounded, and the gate thereof is connected to one end of the resistor R1; the source of the NMOS transistor M6 is grounded, and the gate thereof is connected to one end of the resistor R2; the other end of the resistor R1 serves as the control voltage input terminal VC1 of the differential common source with neutralization capacitor improved gain control circuit; the other end of the resistor R2 serves as the control voltage input terminal VC2 of the differential common source with neutralization capacitor improved gain control circuit.

2. The variable gain power amplifier according to claim 1, wherein: The differential common source with neutralizing capacitor circuit includes: NMOS transistor M1, NMOS transistor M2, neutralizing capacitor C f1 and neutralizing capacitor C f2 ; The gate of the NMOS tube M1 and the neutralizing capacitor C f1 One end is connected and serves as the negative input terminal Vin- of the differential common source with neutralizing capacitor circuit, and its drain is connected to the neutralizing capacitor C f2 One end of the differential common source is connected to the positive output terminal Vout+ of the neutralizing capacitor circuit, and its source is connected to the source of the NMOS tube M2 and grounded; The gate of the NMOS tube M2 and the neutralizing capacitor C f2 The other end is connected to the positive input terminal Vin+ of the differential common source and capacitor circuit, and its drain is connected to the capacitor C f1 The other end is connected and serves as the negative output terminal Vout- of the differential common source and capacitor circuit.

Images