Signal extraction filtering method and system based on parallel filtering

Abstract

The present invention discloses a signal decimation filtering method and system based on parallel filtering. The system includes a result selector and at least two cascaded fully parallel 2-fold fast decimation filter modules. The method includes: obtaining first-class parallel data and setting an operating clock; decomposing the first-class parallel data into first input data and second input data, and respectively passing the first input data and the second input data through corresponding filters and then superimposing them to obtain second-class parallel data; if the current fully parallel 2-fold fast decimation filter module is not the first stage and the last stage, sending the second-class parallel data to a second FIFO to be converted into decimation result data and input into the result selector, and sending the second-class parallel data to a first FIFO to be converted into first-class parallel data and then input into the next-stage fully parallel 2-fold fast decimation filter module. The present invention improves the data throughput and the overall data processing speed of decimation filtering, and can select to output results with different decimation multiples.

Description

Technical Field

[0001] The present invention relates to the field of signal processing, and in particular to a signal multi-stage decimation method and system based on parallel filtering. Background Art

[0002] In the process of signal processing, decimation filtering is usually performed on high-sampling-rate data according to the actual signal bandwidth to reduce the amount of data processed by subsequent algorithms, improve the real-time performance of the system, enhance the processing ability, and reduce the system power consumption.

[0003] Currently, there are mainly two decimation filtering methods for signals. The first is a serial multi-stage decimation scheme, as Figure 1 shown. It consists of a first-order CIC filter, multiple HB half-band filters, and a compensation FIR filter. Its characteristics are that decimation is selectable, the configuration is flexible, and the generality is strong. The second is a parallel polyphase decimation scheme, as Figure 2 shown. Different phases of the sequence are input to the corresponding decimation filters. When the decimation factor is relatively high, the structure of the decimation filter can be transformed to realize the processing of parallel data, and a part of the computing resources can be saved. Its characteristics are reducing unnecessary operations, reducing power consumption, and being applicable to high-speed parallel data.

[0004] The disadvantage of the first-mentioned scheme is that it cannot process data in parallel. Given the limited clock rate of the hardware processing platform, in the case of high-speed data streams, multiple data channels need to be processed in parallel, and this scheme is not suitable. The disadvantage of the second-mentioned scheme is that the decimation factor is fixed. If multiple decimation factors are required simultaneously, multiple decimation filters with the same structure but different filters need to be designed, resulting in huge resource consumption. Summary of the Invention

[0005] The technical problem to be solved by the present invention is: aiming at the technical problems existing in the prior art, the present invention provides a signal decimation filtering method and system based on parallel filtering, which improves the data throughput and the overall data processing speed of decimation filtering, and can select to output results with different decimation factors.

[0006] To solve the above technical problems, the technical solution proposed by the present invention is:

[0007] A signal decimation filtering method based on parallel filtering is applied to a signal decimation system. The signal decimation system includes a result selector and at least two cascaded fully parallel 2-fold fast decimation filter modules. The first-stage fully parallel 2-fold fast decimation filter module is connected to a signal source, and each stage of the fully parallel 2-fold fast decimation filter module is connected to the result selector. A first FIFO is provided between adjacent fully parallel 2-fold fast decimation filter modules. Each stage of the fully parallel 2-fold fast decimation filter module from the second stage and later is connected to the result selector through a second FIFO. The method includes:

[0008] The current fully parallel 2-fold fast decimation filter module obtains the first type of parallel data, and sets the ratio of the operating clock of the current fully parallel 2-fold fast decimation filter module to the operating clock of the previous-level fully parallel 2-fold fast decimation filter module as a preset value;

[0009] The current fully parallel 2-fold fast decimation filter module decomposes the first type of parallel data into first input data and second input data according to the input data bits of the first type of parallel data;

[0010] The current fully parallel 2-fold fast decimation filter module superimposes the first input data and the second input data after passing through the corresponding filters respectively to obtain the second type of parallel data;

[0011] If the current fully parallel 2-fold fast decimation filter module is not the first level and the last level, the second type of parallel data is sent to the corresponding second FIFO to be converted into decimation result data and input to the result selector, and the second type of parallel data is sent to the corresponding first FIFO to be converted into the first type of parallel data and then input to the next-level fully parallel 2-fold fast decimation filter module. The clock rates of the decimation result data corresponding to each level of the fully parallel 2-fold fast decimation filter module are the same.

[0012] Further, after the current fully parallel 2-fold fast decimation filter module superimposes the first branch data and the second branch data after passing through the corresponding filters respectively to obtain the output data, it further includes: if the current fully parallel 2-fold fast decimation filter module is the first level, the second type of parallel data is sent to the result selector as the decimation result data, and the second type of parallel data is sent to the corresponding first FIFO to be converted into the first type of parallel data and then input to the next-level fully parallel 2-fold fast decimation filter module.

[0013] Further, the last-level fully parallel 2-fold fast decimation filter module is also connected through a FIR decimation filter and a result selector. After the current fully parallel 2-fold fast decimation filter module superimposes the first branch data and the second branch data after passing through the corresponding filters respectively to obtain the output data, it further includes: if the current fully parallel 2-fold fast decimation filter module is the last level, the second type of parallel data is sent to the corresponding second FIFO to be converted into decimation result data and then input to the result selector, and the decimation result data is sent to the FIR decimation filter for further decimation and then input to the result selector.

[0014] Further, the specific steps of superimposing the first input data and the second input data after passing through the corresponding filters respectively to obtain the second type of parallel data include:

[0015] Input the first input data into the corresponding filter to obtain the first branch parallel data;

[0016] The second input data is input into the corresponding filter to obtain second-branch parallel data;

[0017] Calculate the sum of each corresponding data bit of the first-branch parallel data and the second-branch parallel data to obtain the value of each data bit of the second type of parallel data.

[0018] Further, the first type of parallel data is 8-channel data (x0, x1, x2, x3, x4, x5, x6, x7), the first input data includes the even-numbered bits (x0, x2, x4, x6) of the input data of the first type of parallel data, the second input data includes the odd-numbered bits (x1, x3, x5, x7) of the input data of the first type of parallel data, and the data expression of each data bit of the first-branch parallel data is as follows:

[0019] Y00 = x0 * H0 + Z -4 (x6 * H1 + x4 * H2 + x2 * H3);

[0020] Y10 = x2 * H0 + x0 * H1 + Z -4 (x6 * H2 + x4 * H3);

[0021] Y20 = x4 * H0 + x2 * H1 + x0 * H2 + Z -4 (x6 * H3);

[0022] Y30 = x6 * H0 + x4 * H1 + x2 * H2 + x0 * H3;

[0023] The data expression of each data bit of the second-branch parallel data is as follows:

[0024] Y01 = am * x1;

[0025] Y11 = am * x3;

[0026] Y21 = am * x5;

[0027] Y31 = am * x7;

[0028] In the above formula, Z -4 represents the first type of parallel data cached for one beat, H0, H1, H2, and H3 are respectively preset filter coefficients, and am is a preset intermediate filter coefficient.

[0029] Optionally, the intermediate filter coefficient am is 0.5.

[0030] The present invention also provides a signal extraction system, which includes a result selector and at least two cascaded fully parallel 2-fold decimation filter modules. The first-stage fully parallel 2-fold decimation filter module is connected to a signal source, and each stage of the fully parallel 2-fold decimation filter module is connected to the result selector. A first FIFO is provided between adjacent fully parallel 2-fold decimation filter modules. Each stage of the fully parallel 2-fold decimation filter module starting from the second stage is connected to the result selector through a second FIFO. The fully parallel 2-fold decimation filter module is configured to perform:

[0031] Obtain first-class parallel data, and set the ratio of the operating clock of the current fully parallel 2-fold decimation filter module to the operating clock of the previous-stage fully parallel 2-fold decimation filter module as a preset value;

[0032] According to the input data bits of the first-class parallel data, decompose the first-class parallel data into first input data and second input data;

[0033] After the first input data and the second input data pass through corresponding filters respectively and are superimposed to obtain second-class parallel data;

[0034] If the current fully parallel 2-fold decimation filter module is not the first stage and the last stage, convert the second-class parallel data into decimation result data through the second FIFO and input it into the result selector, and convert the second-class parallel data into first-class parallel data through the first FIFO and then input it into the next-stage fully parallel 2-fold decimation filter module. The clock rates of the decimation result data corresponding to each stage of the fully parallel 2-fold decimation filter module are the same.

[0035] Further, the first-stage fully parallel 2-fold decimation filter module is configured to perform: after the first input data and the second input data pass through corresponding filters respectively and are superimposed to obtain second-class parallel data, send the second-class parallel data to the result selector as decimation result data, and send the second-class parallel data to the corresponding first FIFO to be converted into first-class parallel data and then input into the next-stage fully parallel 2-fold decimation filter module.

[0036] Further, the last-stage fully parallel 2-fold decimation filter module is also connected to the result selector through an FIR decimation filter. The last-stage fully parallel 2-fold decimation filter module is configured to perform: after the first input data and the second input data pass through corresponding filters respectively and are superimposed to obtain second-class parallel data, send the second-class parallel data to the corresponding second FIFO to be converted into decimation result data and then input into the result selector, and send the decimation result data to the FIR decimation filter for further decimation and then input into the result selector.

[0037] Further, when the first input data and the second input data are respectively passed through corresponding filters and then superimposed to obtain the second type of parallel data, the fully parallel 2-fold decimation filter module is configured to perform:

[0038] Pass the first input data through the corresponding filter to obtain the first-branch parallel data;

[0039] Pass the second input data through the corresponding filter to obtain the second-branch parallel data;

[0040] Calculate the sum of each corresponding data bit of the first-branch parallel data and the second-branch parallel data to obtain the value of each data bit of the second type of parallel data.

[0041] Compared with the prior art, the advantages of the present invention are as follows:

[0042] The present invention passes the input data through a multi-stage fully parallel 2-fold decimation filter to sequentially reduce the high-speed parallel data to low-speed serial data, and the decimation filtering results after each speed reduction can be selected; the data throughput and the overall data processing speed of the decimation filtering are improved, and the results of different decimation multiples can be selected through a selector. By combining the use of different clock speeds and FIFOs, the fully parallel 2-fold decimation filter modules with the same structure can be reused, reducing the design difficulty.

[0043] The present invention also optimizes the design of the fully parallel 2-fold decimation filter module according to the design rules of the half-band filter, reducing the resource usage and ensuring the real-time performance and parallelism of the output data. Brief Description of the Drawings

[0044] Figure 1 It is a schematic flow chart of the current serial multi-stage decimation scheme.

[0045] Figure 2 It is a schematic flow chart of the current polyphase decimation filtering scheme.

[0046] Figure 3 It is a schematic flow chart of the signal decimation method according to the embodiment of the present invention.

[0047] Figure 4 It is a schematic structural diagram of the fully parallel 2-fold decimation filter module according to the embodiment of the present invention. Detailed Embodiments

[0048] The following further describes the present invention in conjunction with the drawings in the specification and specific preferred embodiments, but does not limit the protection scope of the present invention thereby.

[0049] Embodiment 1

[0050] To solve the problem of signal decimation filtering under high-speed parallel data streams, making the data processing throughput higher, occupying fewer resources, and having a wider range of applications, such as Figure 3 As shown, this embodiment proposes a signal decimation system with variable decimation factors, including a result selector and at least two cascaded fully parallel 2-fold fast decimation filter modules. The first-stage fully parallel 2-fold fast decimation filter module is connected to a signal source, and each stage of the fully parallel 2-fold fast decimation filter module is connected to the result selector. FIFOs (first-in-first-out buffers, hereinafter uniformly referred to as the first FIFO for distinction) are provided between adjacent fully parallel 2-fold fast decimation filter modules. Each stage of the fully parallel 2-fold fast decimation filter module starting from the second stage is connected to the result selector through a FIFO (first-in-first-out buffer, hereinafter uniformly referred to as the second FIFO for distinction). The first FIFO and the second FIFO respectively play the functions of isolating different data clock rates and changing the number of parallel data paths.

[0051] By setting multiple stages of fully parallel 2-fold fast decimation filter modules, decimation by 2-fold, 4-fold, and 8-fold can be performed in stages. Usually, after 8-fold decimation, the data rate becomes lower. The last-stage fully parallel 2-fold fast decimation filter module is also connected to the result selector through a FIR decimation filter. At this time, a more flexible decimation factor selection can be achieved through this FIR decimation filter.

[0052] Since the fully parallel 2-fold fast decimation filter module performs 2-fold decimation, the number of output data paths becomes 1 / 2 of the input data paths. For example, 8-way parallel input data passing through the fully parallel 2-fold fast decimation filter module will become 4-way parallel data. To ensure pipelined operation, the first FIFO converts the 4-way parallel data into 8-way parallel data and then inputs it to the next-stage fully parallel 2-fold fast decimation filter module. However, the clock rate of the output data of the first FIFO will become 1 / 2 of the input data. To ensure that the clock rates of the data input from each stage of the fully parallel 2-fold fast decimation filter module to the result selector are the same, the second FIFO converts the output data of the corresponding fully parallel 2-fold fast decimation filter module into decimated data at the same clock rate and then inputs it to the result selector to ensure pipelined operation. The principles of converting the number of input data paths through the FIFO and then outputting, and converting the clock rate of the input data through the FIFO and then outputting are common knowledge in the art and will not be elaborated here.

[0053] Taking the signal source sending an 8-way parallel input sequence as an example, the working principle of the signal decimation system of this embodiment is described as follows:

[0054] 1. The signal source transmits 8-channel parallel data. After passing through the first-stage fully parallel 2-fold fast decimation filter module, 4-channel parallel data after 2-fold decimation filtering is output. At this time, the operating clock of the first-stage fully parallel 2-fold fast decimation filter module is the single-fold operating clock. Therefore, the 4-channel parallel data is directly output to the result selector;

[0055] 2. The 4-channel parallel data output by the first-stage fully parallel 2-fold fast decimation filter module passes through the first FIFO and becomes 8-channel parallel data. Its clock rate is 1 / 2 of the output data of the first-stage fully parallel 2-fold fast decimation filter module. After passing through the second-stage fully parallel 2-fold fast decimation filter module, 4-channel parallel data after 4-fold decimation filtering is output. At this time, the operating clock of the second-stage fully parallel 2-fold fast decimation filter module is 1 / 2-fold operating clock to match the clock rate of the input data. The 4-channel parallel data output by the second-stage fully parallel 2-fold fast decimation filter module is input to the second FIFO. Since the output data clock rate of the second-stage fully parallel 2-fold fast decimation filter module needs to be the same as that of the first-stage fully parallel 2-fold fast decimation filter module, the output of the second FIFO becomes two-channel parallel data, and the clock becomes twice that of the second-stage fully parallel 2-fold fast decimation filter module, that is, 2-channel parallel data after 4-fold decimation filtering at the rate of the single-fold operating clock, and is output to the result selector;

[0056] 3. The 4-channel parallel data output by the second-stage fully parallel 2-fold fast decimation filter module passes through the first FIFO and becomes 8-channel parallel data. Its clock rate is 1 / 2 of the output data of the second-stage fully parallel 2-fold fast decimation filter module, that is, 1 / 4 of the output data of the first-stage fully parallel 2-fold fast decimation filter module. After passing through the third-stage fully parallel 2-fold fast decimation filter module, 4-channel parallel data after 8-fold decimation filtering is output. At this time, the operating clock of the third-stage fully parallel 2-fold fast decimation filter module is 1 / 4-fold operating clock to match the clock rate of the input data. The 4-channel parallel data output by the third-stage fully parallel 2-fold fast decimation filter module is input to the second FIFO. Since the output data clock rate of the third-stage fully parallel 2-fold fast decimation filter module needs to be the same as that of the first-stage fully parallel 2-fold fast decimation filter module, the output of the second FIFO becomes one-channel data, and the clock becomes four times that of the third-stage fully parallel 2-fold fast decimation filter module, that is, 1-channel data after 8-fold decimation filtering at the rate of the single-fold operating clock, and is output to the result selector;

[0057] 4. The single-channel serial data output from the previous step is decimated by M times through a FIR decimation filter. Among them, the FIR filter parameters are set to multiple groups of parameters with the same order. Different FIR decimation filters can be selected by the value of the decimation factor M. Then, every M data is decimated from the output of the FIR filter, that is, the variable M-fold decimation process is completed, so as to control the selection of different decimation factors. Finally, the decimation result of the single-channel 8*M times is output to the result selector.

[0058] 5. The result selector selects the output results of 2 times, 4 times, 8 times, and 8*M times according to the required decimation factor.

[0059] As Figure 4 shown, the full-parallel 2-fold fast decimation filter module of this embodiment can polyphase decompose the input data into two groups of input data, namely the first input data and the second input data, according to the input data bits, and corresponding filters are configured for these two groups of input data. After the first input data and the second input data pass through the corresponding filters respectively and then are superimposed, the parallel data after decimation filtering output is obtained.

[0060] Therefore, the full-parallel 2-fold fast decimation filter module of this embodiment is configured to execute:

[0061] Obtain the first type of parallel data, that is, the parallel data from the signal source or the previous full-parallel 2-fold fast decimation filter module, and set the ratio of the operating clock of the current full-parallel 2-fold fast decimation filter module to the operating clock of the previous full-parallel 2-fold fast decimation filter module to a preset value. The preset value in this embodiment is 1 / 2, that is, the operating clock of the subsequent full-parallel 2-fold fast decimation filter module is one-half of the operating clock of the previous full-parallel 2-fold fast decimation filter module, so as to match the clock rate after the parallel data from the previous full-parallel 2-fold fast decimation filter module is converted by the corresponding first FIFO;

[0062] Decompose the first type of parallel data into the first input data and the second input data according to the input data bits of the first type of parallel data. For example, the first type of parallel data is 8-channel parallel data, (x0, x1, x2, x3, x4, x5, x6, x7), the first input data includes the even input data bits (x0, x2, x4, x6) of the first type of parallel data, and the second input data includes the odd input data bits (x1, x3, x5, x7) of the first type of parallel data;

[0063] Superimpose the first input data and the second input data after passing through the corresponding filters respectively to obtain the second type of parallel data. Specifically:

[0064] After inputting the first input data into the corresponding filter, the first-branch parallel data is obtained. The data expression of each data bit in the first-branch parallel data is as follows:

[0065] Y00 = x0 * H0 + Z -4 (x6 * H1 + x4 * H2 + x2 * H3);

[0066] Y10 = x2 * H0 + x0 * H1 + Z -4 (x6 * H2 + x4 * H3);

[0067] Y20 = x4 * H0 + x2 * H1 + x0 * H2 + Z -4 (x6 * H3);

[0068] Y30 = x6 * H0 + x4 * H1 + x2 * H2 + x0 * H3;

[0069] In the above formula, Z -4 represents the 8-way parallel data cached for one clock cycle. H0, H1, H2, and H3 are respectively preset filter coefficients, and these filter coefficients are obtained according to the half-band filter design rules;

[0070] After inputting the second input data into the corresponding filter, the second-branch parallel data is obtained. The data expression of each data bit in the first-branch parallel data is as follows:

[0071] Y01 = am * x1;

[0072] Y11 = am * x3;

[0073] Y21 = am * x5;

[0074] Y31 = am * x7;

[0075] In the above formula, am is a preset intermediate filter coefficient, specifically 0.5;

[0076] Calculate the sum of each corresponding data bit of the first-branch parallel data and the second-branch parallel data to obtain the second type of parallel data, that is, the value of each data bit of the 4-way parallel data after decimation filtering. The results are as follows:

[0077] y0 = Y00 + Y01 = x0 * H0 + Z -4 (x6 * H1 + x4 * H2 + x2 * H3) + 0.5 * x1;

[0078] y1 = Y10 + Y11 = x2 * H0 + x0 * H1 + Z -4 (x6 * H2 + x4 * H3) + 0.5 * x3;

[0079] y2 = Y20 + Y21 = x4 * H0 + x2 * H1 + x0 * H2 + Z -4 (x6 * H3) + 0.5 * x5;

[0080] y3 = Y30 + Y31 = x6 * H0 + x4 * H1 + x2 * H2 + x0 * H3 + 0.5 * x7;

[0081] If the current fully parallel 2 - fold fast decimation filter module is the first stage, send the second - type parallel data to the result selector as the decimation result data, and send the second - type parallel data to the corresponding first FIFO to be converted into the first - type parallel data and then input to the next - level fully parallel 2 - fold fast decimation filter module;

[0082] If the current fully parallel 2 - fold fast decimation filter module is neither the first stage nor the last stage, send the second - type parallel data to the corresponding second FIFO to be converted into the decimation result data and input to the result selector, and send the second - type parallel data to the corresponding first FIFO to be converted into the first - type parallel data and then input to the next - level fully parallel 2 - fold fast decimation filter module. The clock rates of the decimation result data corresponding to each level of the fully parallel 2 - fold fast decimation filter module are the same;

[0083] If the current fully parallel 2 - fold fast decimation filter module is the last stage, send the second - type parallel data to the corresponding second FIFO to be converted into the decimation result data and then input to the result selector, and send the decimation result data to the FIR decimation filter for further decimation and then input to the result selector.

[0084] In summary, the signal decimation system of this embodiment adopts a combined structure of parallel 2 - fold fast decimation filter modules, reducing the resource utilization rate, effectively realizing high - speed real - time data parallelization, and adopting an optimized and ingenious implementation structure to reuse this module, reducing the design complexity. Combining decimation grading and the configurable filter coefficient structure in the final stage realizes multi - level selection of the decimation ratio, so that the application range is wider and the universality of the scheme is stronger.

[0085] Embodiment 2

[0086] This embodiment proposes a signal decimation filtering method based on parallel filtering, which is applied to the signal decimation system of Embodiment 1 and includes the following steps:

[0087] The current fully parallel 2 - fold fast decimation filter module obtains the first - type parallel data, and sets the ratio of the operating clock of the current fully parallel 2 - fold fast decimation filter module to the operating clock of the previous - level fully parallel 2 - fold fast decimation filter module as a preset value;

[0088] The current fully parallel 2-fold fast decimation filter module decomposes the first type of parallel data into first input data and second input data according to the input data bits of the first type of parallel data;

[0089] The current fully parallel 2-fold fast decimation filter module superimposes the first input data and the second input data after passing through the corresponding filters respectively to obtain the second type of parallel data;

[0090] If the current fully parallel 2-fold fast decimation filter module is the first stage, it sends the second type of parallel data to the result selector as decimation result data, and sends the second type of parallel data to the corresponding first FIFO to be converted into the first type of parallel data and then input to the next-stage fully parallel 2-fold fast decimation filter module;

[0091] If the current fully parallel 2-fold fast decimation filter module is neither the first stage nor the last stage, it sends the second type of parallel data to the corresponding second FIFO to be converted into decimation result data and input to the result selector, and sends the second type of parallel data to the corresponding first FIFO to be converted into the first type of parallel data and then input to the next-stage fully parallel 2-fold fast decimation filter module. The clock rates of the decimation result data corresponding to each stage of the fully parallel 2-fold fast decimation filter module are the same;

[0092] If the current fully parallel 2-fold fast decimation filter module is the last stage, it sends the second type of parallel data to the corresponding second FIFO to be converted into decimation result data and then input to the result selector, and sends the decimation result data to the FIR decimation filter for further decimation and then input to the result selector;

[0093] The result selector selects the corresponding decimation result data according to actual needs and outputs it.

[0094] In this embodiment, the specific steps of superimposing the first input data and the second input data after passing through the corresponding filters respectively to obtain the second type of parallel data include:

[0095] Input the first input data into the corresponding filter to obtain the first-branch parallel data;

[0096] Input the second input data into the corresponding filter to obtain the second-branch parallel data;

[0097] Calculate the sum of each corresponding data bit of the first-branch parallel data and the second-branch parallel data to obtain the value of each data bit of the second type of parallel data.

[0098] In this embodiment, the first type of parallel data is 8-channel data (x0, x1, x2, x3, x4, x5, x6, x7). The first input data includes the even-numbered bits of the input data of the first type of parallel data (x0, x2, x4, x6), and the second input data includes the odd-numbered bits of the input data of the first type of parallel data (x1, x3, x5, x7). The data expression of each data bit of the first branch parallel data is as follows:

[0099] Y00 = x0 * H0 + Z -4 (x6 * H1 + x4 * H2 + x2 * H3);

[0100] Y10 = x2 * H0 + x0 * H1 + Z -4 (x6 * H2 + x4 * H3);

[0101] Y20 = x4 * H0 + x2 * H1 + x0 * H2 + Z -4 (x6 * H3);

[0102] Y30 = x6 * H0 + x4 * H1 + x2 * H2 + x0 * H3;

[0103] The data expression of each data bit of the second branch parallel data is as follows:

[0104] Y01 = am * x1;

[0105] Y11 = am * x3;

[0106] Y21 = am * x5;

[0107] Y31 = am * x7;

[0108] In the above formula, Z -4 represents the first type of parallel data cached for one clock cycle. H0, H1, H2, and H3 are respectively preset filter coefficients, and am is a preset intermediate filter coefficient, specifically 0.5.

[0109] As can be seen from the above, in this embodiment, by using the combination of a clock and a FIFO, the combined structure of the fully parallel 2-fold decimation filter module can be reused, reducing the design difficulty, reducing the resource usage, and ensuring the real-time performance and parallelism of the algorithm.

[0110] The above is only a preferred embodiment of the present invention and does not impose any form of limitation on the present invention. Although the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present invention without departing from the technical solution of the present invention shall fall within the scope of protection of the technical solution of the present invention.

Claims

1. A signal extraction filtering method based on parallel filtering, characterized in that, Applied to a signal extraction system, the signal extraction system includes a result selector and at least two cascaded fully parallel 2-fold decimation filter modules. The first-stage fully parallel 2-fold decimation filter module is connected to a signal source, and each stage of the fully parallel 2-fold decimation filter module is connected to the result selector. A first FIFO is provided between adjacent fully parallel 2-fold decimation filter modules. Each stage of the fully parallel 2-fold decimation filter module from the second stage and later is connected to the result selector through a second FIFO. The last-stage fully parallel 2-fold decimation filter module is also connected to the result selector through a FIR decimation filter. The method includes: The current fully parallel 2-fold decimation filter module obtains first-class parallel data, and sets the ratio of the operating clock of the current fully parallel 2-fold decimation filter module to the operating clock of the previous-stage fully parallel 2-fold decimation filter module as a preset value; The current fully parallel 2-fold decimation filter module decomposes the first-class parallel data into first input data and second input data according to the input data bits of the first-class parallel data; The current fully parallel 2-fold decimation filter module superimposes the first input data and the second input data after passing through the corresponding filters respectively to obtain second-class parallel data; If the current fully parallel 2-fold decimation filter module is not the first stage and the last stage, the second-class parallel data is sent to the corresponding second FIFO to be converted into decimation result data and input into the result selector, and the second-class parallel data is sent to the corresponding first FIFO to be converted into first-class parallel data and then input into the next-stage fully parallel 2-fold decimation filter module. The clock rates of the decimation result data corresponding to each stage of the fully parallel 2-fold decimation filter module are the same; If the current fully parallel 2-fold decimation filter module is the last stage, the second-class parallel data is sent to the corresponding second FIFO to be converted into decimation result data and then input into the result selector, and the decimation result data is sent to the FIR decimation filter to be further decimated and then input into the result selector.

2. The signal decimation filtering method based on parallel filtering according to claim 1, wherein After the current fully parallel 2-fold decimation filter module superimposes the first branch data and the second branch data after passing through the corresponding filters respectively to obtain second-class parallel data, it further includes: If the current fully parallel 2-fold decimation filter module is the first stage, the second-class parallel data is sent to the result selector as decimation result data, and the second-class parallel data is sent to the corresponding first FIFO to be converted into first-class parallel data and then input into the next-stage fully parallel 2-fold decimation filter module.

3. The signal decimation filtering method based on parallel filtering according to claim 1, wherein The specific steps of superimposing the first input data and the second input data after passing through the corresponding filters respectively to obtain second-class parallel data include: Input the first input data into the corresponding filter to obtain first branch parallel data; Input the second input data into the corresponding filter to obtain second branch parallel data; Calculate the sum of each corresponding data bit of the first branch parallel data and the second branch parallel data to obtain the value of each data bit of the second-class parallel data.

4. The signal decimation filtering method based on parallel filtering according to claim 3, wherein, The first type of parallel data is 8-channel data (x0, x1, x2, x3, x4, x5, x6, x7). The first input data includes the even-numbered bits of the input data of the first type of parallel data (x0, x2, x4, x6), and the second input data includes the odd-numbered bits of the input data of the first type of parallel data (x1, x3, x5, x7). The data expression of each data bit of the first branch parallel data is as follows: Y00 = x0*H0 + Z -4 (x6*H1 + x4*H2 + x2*H3); Y10 = x2*H0 + x0*H1 + Z -4 (x6*H2 + x4*H3); Y20 = x4*H0 + x2*H1 + x0*H2 + Z -4 (x6*H3); Y30 = x6*H0 + x4*H1 + x2*H2 + x0*H3; The data expression of each data bit of the second branch parallel data is as follows: Y01 = am*x1; Y11 = am *x3; Y21 = am *x5; Y31 = am *x7; In the above formula, Z -4 represents the first type of parallel data cached for one clock cycle. H0, H1, H2, and H3 are respectively preset filter coefficients, and am is a preset intermediate filter coefficient.

5. The signal decimation filtering method based on parallel filtering according to claim 4, wherein The intermediate filter coefficient am is 0.

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6. A signal extraction system, characterized in that, The signal decimation system includes a result selector and at least two cascaded fully parallel 2-fold fast decimation filter modules. The first-stage fully parallel 2-fold fast decimation filter module is connected to the signal source, and each stage of the fully parallel 2-fold fast decimation filter module is connected to the result selector. A first FIFO is provided between adjacent fully parallel 2-fold fast decimation filter modules. Each stage of the fully parallel 2-fold fast decimation filter module from the second stage and later is connected to the result selector through a second FIFO. The last-stage fully parallel 2-fold fast decimation filter module is also connected to the result selector through a FIR decimation filter. The fully parallel 2-fold fast decimation filter module is configured to perform: Obtain the first type of parallel data, and set the ratio of the operating clock of the current fully parallel 2-fold fast decimation filter module to the operating clock of the previous-stage fully parallel 2-fold fast decimation filter module as a preset value; Decompose the first type of parallel data into first input data and second input data according to the input data bits of the first type of parallel data; Superimpose the first input data and the second input data after passing through the corresponding filters to obtain the second type of parallel data; If the current fully parallel 2-fold fast decimation filter module is not the first stage and the last stage, convert the second type of parallel data into decimation result data through the second FIFO and input it into the result selector, and convert the second type of parallel data into the first type of parallel data through the first FIFO and input it into the next-stage fully parallel 2-fold fast decimation filter module. The clock rates of the decimation result data corresponding to each stage of the fully parallel 2-fold fast decimation filter module are the same; If the current fully parallel 2-fold fast decimation filter module is the last stage, send the second type of parallel data to the corresponding second FIFO to be converted into decimation result data and input it into the result selector, and send the decimation result data to the FIR decimation filter for further decimation and then input it into the result selector.

7. The signal extraction system according to claim 6, wherein The first - stage fully - parallel 2 - fold decimation filter module is configured to perform: after the first input data and the second input data pass through the corresponding filters respectively and are superimposed to obtain the second - type parallel data, sending the second - type parallel data to the result selector as decimation result data, and sending the second - type parallel data to the corresponding first FIFO to be converted into the first - type parallel data and then input to the next - stage fully - parallel 2 - fold decimation filter module.

8. The signal extraction system according to claim 6, wherein When the first input data and the second input data pass through the corresponding filters respectively and are superimposed to obtain the second - type parallel data, the fully - parallel 2 - fold decimation filter module is configured to perform: Obtaining the first - branch parallel data after the first input data passes through the corresponding filter; Obtaining the second - branch parallel data after the second input data passes through the corresponding filter; Calculating the sum of each corresponding data bit of the first - branch parallel data and the second - branch parallel data to obtain the value of each data bit of the second - type parallel data.

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