Digital-to-analog conversion device and method with signal correction mechanism

Abstract

A digital-to-analog conversion device with a signal correction mechanism. A digital-to-analog conversion circuit converts an input digital signal having an input code word to generate an output analog signal. An echo transmission circuit processes the output analog signal to generate an echo signal. A correction circuit maps from a code word deviation table to generate a deviation signal based on the input code word. An echo cancellation circuit processes the deviation signal based on an echo cancellation coefficient to generate an echo cancellation signal. An error calculation circuit subtracts the echo cancellation signal from the echo signal to generate an error signal. An inverse error calculation circuit calculates an inverse error value after inverting the echo cancellation coefficient and subtracting the error signal. A deviation update circuit updates a correspondence of the code word deviation table based on path delays of the echo cancellation circuit and the inverse error calculation circuit.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to a digital-to-analog conversion technique, and particularly relates to a digital-to-analog conversion device and method with a signal correction mechanism. BACKGROUND

[0002] A digital-to-analog conversion circuit is an important element for converting a signal from a digital form to an analog form. The digital-to-analog conversion circuit can multiply a corresponding conversion gain value according to different code words, and thus generate analog signals of different sizes.

[0003] However, for a current output type digital-to-analog conversion circuit, process variation will cause non-ideal deviation of the output amplitude and shape. The deviation in amplitude will seriously affect the system performance. SUMMARY

[0004] Based on the problems existing in the prior art, one purpose of the present disclosure is to provide a digital-to-analog conversion device and method with a signal correction mechanism to improve the prior art.

[0005] The present disclosure includes a digital-to-analog conversion device with a signal correction mechanism, which includes a digital-to-analog conversion circuit, an echo transmission circuit, a correction circuit, an echo cancellation circuit, an error calculation circuit, an inverse error calculation circuit, and a bias update circuit. The digital-to-analog conversion circuit is configured to receive an input digital signal with an input code word from a signal source, and perform digital-to-analog conversion to generate an output analog signal. The echo transmission circuit is configured to process the output analog signal to generate an echo signal. The correction circuit is configured to receive the input digital signal, and generate a bias signal from a code word bias table according to the input code word, wherein the code word bias table includes a plurality of corresponding relationships, each corresponding relationship corresponding a code word to a bias value. The echo cancellation circuit is configured to process the bias signal according to a set of echo cancellation coefficients to generate an echo cancellation signal. The error calculation circuit is configured to subtract the echo signal from the echo cancellation signal to generate an error signal. The inverse error calculation circuit is configured to calculate an inverse error value after one-dimensional inversion of the echo cancellation coefficients and the error signal. The bias update circuit is configured to update the bias value of one corresponding relationship in the code word bias table according to the path delay of the echo cancellation circuit and the inverse error calculation circuit with the inverse error value.

[0006] The present application also includes a digital-to-analog conversion method with a signal correction mechanism, which comprises: receiving, by a digital-to-analog conversion circuit, an input digital signal with an input code word from a signal source, performing digital-to-analog conversion to generate an output analog signal; processing, by an echo transmission circuit, the output analog signal to generate an echo signal; receiving, by a correction circuit, the input digital signal, and generating a deviation signal according to the input code word from a code word deviation table, wherein the code word deviation table comprises a plurality of corresponding relationships, each corresponding relationship corresponding a code word to a deviation value; processing, by an echo cancellation circuit, the deviation signal according to a set of echo cancellation coefficients to generate an echo cancellation signal; subtracting, by an error calculation circuit, the echo signal from the echo cancellation signal to generate an error signal; performing, by an inverse error calculation circuit, one-dimensional inversion on the echo cancellation coefficients, and then calculating the inverse error value with the error signal; and updating, by a deviation update circuit, the deviation value of one corresponding relationship in the code word deviation table according to the path delay of the echo cancellation circuit and the inverse error calculation circuit with the inverse error value.

[0007] The features, embodiments and effects of the present application will be described in detail below with reference to the preferred embodiments and the accompanying drawings. BRIEF DESCRIPTION OF DRAWINGS

[0008] Figure 1 is a module diagram of a digital-to-analog conversion device with a signal correction mechanism according to an embodiment of the present application; and

[0009] Figure 2 is a flowchart of a digital-to-analog conversion method with a signal correction mechanism according to an embodiment of the present application. DETAILED DESCRIPTION

[0010] An object of the present application is to provide a digital-to-analog conversion device with a signal correction mechanism to correct the deviation of different code words and avoid errors caused by the deviation of the output signal level.

[0011] Please refer to Figure 1 . Figure 1 is a module diagram of a digital-to-analog conversion device 100 with a signal correction mechanism according to an embodiment of the present application. The digital-to-analog conversion device 100 comprises a digital-to-analog conversion circuit 110, an echo transmission circuit 120, a correction circuit 130, an echo cancellation circuit 140, an error calculation circuit 150, an inverse error calculation circuit 160, a deviation update circuit 170, and an auxiliary digital-to-analog conversion circuit 180.

[0012] The digital-to-analog conversion circuit 110 is configured to receive an input digital signal IS having an input code word from a signal source SS. In an embodiment, the signal source SS is exemplified as a transmission circuit (TX) in a communication system, but is not limited thereto. In an embodiment, the digital-to-analog conversion apparatus 100 can be provided with a filter (not shown) between the signal source SS and the digital-to-analog conversion circuit 110 for filtering the input digital signal IS before being transmitted to the digital-to-analog conversion circuit 110, for example, in a form of a square wave, but is not limited thereto.

[0013] In an embodiment, the input code word of the input digital signal IS can be in a form of 12 bits, but is not limited thereto, for covering a range of 4096 steps (2 12 ) from -2048 to 2047. The digital-to-analog conversion circuit 110 is configured to perform digital-to-analog conversion on the input code word of the input digital signal IS by multiplying a corresponding conversion gain value to generate an output analog signal OAS. However, due to process variation, the digital-to-analog conversion circuit 110 can generate a deviation corresponding to different code words when performing digital-to-analog conversion.

[0014] wherein the deviation corresponding to different code words can be quantified as a deviation value. For example, when the input code word is 2046, the corresponding conversion gain value is GA, and the size of the original output analog signal OAS should be 2046 x GA. However, under the influence of the deviation value DV, the size of the actual output analog signal OAS is (2046 + DV) x GA.

[0015] The echo transmission circuit 120 is configured to process the output analog signal OAS to generate an echo signal ES.

[0016] In an embodiment, the echo transmission circuit 120 includes an echo response circuit 190 and an analog-to-digital conversion circuit 195. The echo response circuit 190 is configured to perform echo response processing on the output analog signal OAS, and the analog-to-digital conversion circuit 195 is further configured to perform analog-to-digital conversion processing to generate the echo signal ES. In an embodiment, the echo transmission circuit 120 can optionally include a digital low-pass filter or other digital signal processing circuit (not shown), but is not limited thereto, for further digital processing of the echo signal ES.

[0017] The correction circuit 130 is configured to receive the input digital signal IS and generate a deviation signal DS from the code word deviation table TB according to the input code word of the input digital signal IS.

[0018] In one embodiment, the code word bias table TB can be stored in a storage circuit (not shown) included in the digital-to-analog conversion device 100. The code word bias table TB includes a plurality of correspondences, each of which corresponds a code word to a bias value. Taking the 12-bit example above, the code word bias table TB will have 4096 correspondences to correspond the code words from -2048 to 2047 to 4096 bias values, respectively. In one embodiment, in the initial state, the bias values corresponding to all code words are preset to 0.

[0019] The echo cancellation circuit 140 is configured to process the bias signal DS according to a set of echo cancellation coefficients CC to generate an echo-canceled signal ECS. It is noted that in one embodiment, the echo cancellation circuit 140 can be shared with a receive circuit (RX) in a communication system to cancel the echo fed into the receive circuit by a transmit circuit.

[0020] The error calculation circuit 150 is configured to subtract the echo signal ES from the echo-canceled signal ECS to generate an error signal DIS.

[0021] In the initial state, the echo cancellation circuit 140 will perform a training procedure on the echo cancellation coefficients CC according to the error signal DIS to make the echo cancellation coefficients CC converge. In one embodiment, the training procedure is a least mean square root training procedure.

[0022] After the training procedure of the echo cancellation coefficients CC is finished, the converged echo cancellation coefficients CC will apply a response process to the bias signal DS. The response process will approximate the path response of the input digital signal IS from the signal source SS via the path including the digital-to-analog conversion circuit 110 and the echo response circuit 190.

[0023] Next, the inverse error calculation circuit 160 is configured to perform a one-dimensional inversion on the echo cancellation coefficients CC and then calculate an inverse error value FD with the error signal DIS.

[0024] In one embodiment, the inverse error calculation circuit 160 can only select the coefficients with the most concentrated energy to perform the one-dimensional inversion. For example, the echo cancellation coefficients CC can have 256 coefficients, and the inverse error calculation circuit 160 selects the 32 coefficients with the most concentrated energy to perform the one-dimensional inversion. In one embodiment, since most of the signal bounces off the near end, the coefficients with the most concentrated energy are the first 32 coefficients among the 256 coefficients.

[0025] It is noted that the above embodiment is only an example. In other embodiments, the number of echo cancellation coefficients CC and the number of selected coefficients to perform the one-dimensional inversion can be different according to requirements.

[0026] For example, with 32 coefficients, after one-dimensional inversion, the first coefficient and the 32nd coefficient are swapped, the second coefficient and the 31st coefficient are swapped, and so on. The inversion error calculation circuit 160 multiplies the error signal DIS by each of the coefficients and then adds the results to generate an inversion error value FD.

[0027] In one embodiment, the inversion error calculation circuit 160 further simplifies the echo cancellation coefficients CC to be one-dimensional inverted.

[0028] In more detail, in one embodiment, the inversion error calculation circuit 160 is further configured to simplify the echo cancellation coefficients CC according to the maximum energy distribution, so that one or two coefficients corresponding to the maximum energy are selected from the echo cancellation coefficients CC, and the other coefficients are set to zero. Thus, the echo cancellation coefficients CC to be one-dimensional inverted include only two or fewer non-zero coefficients, so that the calculation of the inversion error calculation circuit 160 is simplified.

[0029] In another embodiment, when the digital-to-analog conversion device 100 only desires to perform foreground correction, the inversion error calculation circuit 160 is further configured to control the sampling phase of the analog-to-digital conversion circuit 195 by selecting the sampling phase of the analog-to-digital conversion circuit 195 to simplify the echo cancellation coefficients CC, so that the echo cancellation coefficients CC include only one non-zero coefficient and the other coefficients are set to zero, thereby simplifying the calculation of the inversion error calculation circuit 160.

[0030] For example, since the digital coefficients can be considered as a reduction in sampling of the analog coefficients, different digital coefficients can be selected by changing the sampling phase of the analog-to-digital conversion circuit 195. If the sampling phase is such that the echo cancellation coefficients CC are close in form to having only one sampling result (i.e., the other coefficients are much smaller than one of the coefficients), then the one non-zero coefficient can be considered, so that the calculation process is simplified when performing the inversion operation.

[0031] It should be noted that the above embodiments are only examples. In other embodiments, the echo cancellation coefficients CC can be simplified in other ways.

[0032] Further, the bias update circuit 170 is configured to update the bias value of a corresponding relationship in the code word bias table TB according to the path delay DL of the echo cancellation circuit 140 and the inversion error calculation circuit 160 based on the inversion error value FD. In one embodiment, the path delay DL is known information.

[0033] For example, when the echo cancellation coefficient CC is 0010, the reversed result will be 0100. In this case, the path delay DL will be 3 periods (3T). Therefore, the deviation update circuit 170 will update the deviation value corresponding to the input code word 3 periods ago in the code word deviation table TB according to the path delay DL.

[0034] The updating procedure of the code word deviation table TB will be performed continuously as the signal source SS feeds in input digital signals IS with various input code words to update the corresponding deviation values of all possible input code words.

[0035] After the deviation values are updated to a stable level, the auxiliary digital-to-analog conversion circuit 180 is configured to receive the input digital signal IS and generate a deviation correction analog signal CAS from the updated code word deviation table TB according to the input code word. The absolute value of the deviation correction analog signal CAS is equivalent to the absolute value of the deviation value corresponding to the input code word. The digital-to-analog conversion device 100 can further include a superimposition circuit 185 configured to superimpose the deviation correction analog signal CAS with the output analog signal OAS to offset the deviation value corresponding to the input code word and output an actual output analog signal AAS.

[0036] It is noted that the deviation value can be positive or negative. When the deviation value is positive, the deviation correction analog signal CAS can be negative. When the deviation value is negative, the deviation correction analog signal CAS can be positive.

[0037] In an embodiment, since the auxiliary digital-to-analog conversion circuit 180 can also have process errors, the echo transmission circuit 120 can also be configured to process the actual output analog signal AAS to generate an echo signal ES so that the deviation update circuit 170 updates the deviation value of one corresponding relationship in the code word deviation table TB accordingly. The output level of the actual output analog signal AAS will be more accurate.

[0038] Therefore, the digital-to-analog conversion device of the present application can correct the deviation of different code words to avoid errors caused by the deviation of the output signal level. Moreover, since the echo cancellation circuit used for deviation correction is shared with the receiving circuit in the communication system, there will be no additional cost for hardware.

[0039] Please refer to Figure 2 . Figure 2 is a flow chart of a digital-to-analog conversion method 200 with a signal correction mechanism according to an embodiment of the present application.

[0040] In addition to the aforementioned device, the present application also discloses a digital-to-analog conversion method 200 applied in the digital-to-analog conversion device 100 as shown in Figure 1 but not limited to. An embodiment of the digital-to-analog conversion method 200 is shown inFigure 2 as shown, comprising the following steps.

[0041] Step S210: receiving, by the digital-to-analog conversion circuit 110, an input digital signal IS having an input code word from a signal source SS, and performing digital-to-analog conversion to generate an output analog signal OAS.

[0042] Step S220: processing, by the echo transmission circuit 120, the output analog signal OAS to generate an echo signal ES.

[0043] Step S230: receiving, by the correction circuit 130, the input digital signal IS, and generating a deviation signal DS from the input code word according to a code word deviation table TB, wherein the code word deviation table TB comprises a plurality of corresponding relationships, each corresponding relationship corresponding a code word to a deviation value.

[0044] Step S240: processing, by the echo cancellation circuit 140, the deviation signal DS according to a set of echo cancellation coefficients CC to generate an echo cancellation signal ECS.

[0045] Step S250: subtracting, by the error calculation circuit 150, the echo cancellation signal ECS from the echo signal ES to generate an error signal DIS.

[0046] Step S260: performing one-dimensional inversion on the echo cancellation coefficients CC, and then calculating, by the inverse error calculation circuit 160, an inverse error value FD from the error signal DIS.

[0047] Step S270: updating, by the deviation update circuit 170, the deviation value of one corresponding relationship in the code word deviation table TB according to the path delay of the echo cancellation circuit and the inverse error calculation circuit, with the inverse error value FD.

[0048] It is noted that the above-mentioned embodiments are only examples. In other embodiments, those skilled in the art can make modifications without departing from the spirit of the present application.

[0049] In summary, the digital-to-analog conversion device and method with signal correction mechanism in the present application can correct the deviation of different code words to avoid errors caused by the deviation of the output signal level. Moreover, since the echo cancellation circuit used for deviation correction is shared with the receiving circuit in the communication system, there is no additional cost for hardware.

[0050] Although the embodiments of the present application are described above, these embodiments are not intended to limit the present application, and any person skilled in the art can make modifications to the technical features of the present application according to the content explicitly or implicitly disclosed in the present application, and these modifications all fall within the scope of the patent protection of the present application. In other words, the scope of the patent protection of the present application should be defined according to the claims of the present application.

[0051] Reference Signs List:

[0052] 100: digital-to-analog conversion device

[0053] 110: digital-to-analog conversion circuit

[0054] 120: echo transmission circuit

[0055] 130: correction circuit

[0056] 140: echo cancellation circuit

[0057] 150: error calculation circuit

[0058] 160: inverted error calculation circuit

[0059] 170: deviation update circuit

[0060] 180: auxiliary digital-to-analog conversion circuit

[0061] 185: superimposition circuit

[0062] 190: echo response circuit

[0063] 195: analog-to-digital conversion circuit

[0064] 200: digital-to-analog conversion method

[0065] S210 to S270: steps

[0066] AAS: actual output analog signal

[0067] CAS: deviation correction analog signal

[0068] CC: echo cancellation coefficient

[0069] DL: path delay

[0070] DIS: error signal

[0071] DS: deviation signal

[0072] ECS: echo cancellation signal

[0073] ES: echo signal

[0074] FD: inverted error value

[0075] IS: input digital signal

[0076] OAS: output analog signal

[0077] TB: code word deviation table

Claims

1. A digital-to-analog conversion apparatus having a signal correction mechanism, comprising: a digital-to-analog conversion circuit configured to receive an input digital signal having an input code word from a signal source, and to perform digital-to-analog conversion to generate an output analog signal; an echo transmission circuit configured to process the output analog signal to generate an echo signal; a correction circuit configured to receive the input digital signal, and to generate a deviation signal according to the input code word from a code word deviation table, wherein the code word deviation table comprises a plurality of correspondences, each of which corresponds a code word to a deviation value; an echo cancellation circuit configured to process the deviation signal according to a set of echo cancellation coefficients to generate an echo cancellation signal; an error calculation circuit configured to subtract the echo cancellation signal from the echo signal to generate an error signal; an inverted error calculation circuit configured to calculate the set of echo cancellation coefficients with the error signal after performing one-dimensional inversion to generate an inverted error value; and a deviation update circuit configured to update the deviation value of one of the correspondences in the code word deviation table according to a path delay of the echo cancellation circuit and the inverted error calculation circuit with the inverted error value. further comprising an auxiliary digital-to-analog conversion circuit configured to receive the input digital signal, and to generate a deviation correction analog signal according to the input code word from the code word deviation table, and to superimpose the deviation correction analog signal with the output analog signal to offset the deviation value corresponding to the input code word, and to output as an actual output analog signal. the echo transmission circuit is further configured to process the actual output analog signal to generate the echo signal, so that the deviation update circuit updates the deviation value of one of the correspondences in the code word deviation table accordingly. before the deviation update circuit starts to update the code word deviation table, the echo cancellation circuit is configured to perform a training procedure on the set of echo cancellation coefficients according to the error signal, so that the set of echo cancellation coefficients converges. the training procedure is a least mean square root training procedure. the inverted error calculation circuit is further configured to simplify the set of echo cancellation coefficients according to a maximum energy distribution, so that the set of echo cancellation coefficients only includes two or fewer non-zero coefficients. the echo transmission circuit comprises an echo response circuit and an analog-to-digital conversion circuit, which are respectively configured to perform echo response processing and analog-to-digital conversion processing on the output analog signal to generate the echo signal; wherein the inverted error calculation circuit is further configured to simplify the set of echo cancellation coefficients by controlling a sampling phase of the analog-to-digital conversion circuit, so that the set of echo cancellation coefficients only includes one non-zero coefficient. 8.A digital-to-analog conversion method having a signal correction mechanism, comprising: receiving, by a digital-to-analog conversion circuit, an input digital signal having an input code word from a signal source, and performing digital-to-analog conversion to generate an output analog signal; processing, by an echo transmission circuit, the output analog signal to generate an echo signal; ​ ​ ​ ​ ​ ​ ​ 2. The digital-to-analog conversion device of claim 1, wherein, ​ 3. The digital-to-analog conversion apparatus of claim 2, wherein ​ 4. The digital-to-analog conversion device of claim 1, wherein, ​ 5. The digital-to-analog conversion apparatus of claim 4, wherein ​ 6. The digital-to-analog conversion device of claim 1, wherein, ​ 7. The digital-to-analog conversion device of claim 1, wherein, ​ ​ ​ ​ ​ receiving the input digital signal by a correction circuit, and generating a deviation signal from a code word deviation table according to the input code word, wherein the code word deviation table comprises a plurality of correspondences, each of the correspondences corresponds a code word to a deviation value; processing the deviation signal by an echo cancellation circuit according to a set of echo cancellation coefficients to generate an echo cancellation signal; subtracting the echo signal from the echo cancellation signal by an error calculation circuit to generate an error signal; calculating an inverted error value from the error signal after one-dimensional inversion of the set of echo cancellation coefficients by an inverted error calculation circuit; and updating the deviation value of one of the correspondences in the code word deviation table according to a path delay of the echo cancellation circuit and the inverted error calculation circuit by an deviation update circuit with the inverted error value.

9. The digital-to-analog conversion method of claim 8, wherein, Further comprising: receiving the input digital signal by an auxiliary digital-to-analog conversion circuit, and generating a deviation correction analog signal from the code word deviation table according to the input code word, and superimposing the deviation correction analog signal to the output analog signal to offset the deviation value corresponding to the input code word, and outputting as an actual output analog signal.

10. The digital-to-analog conversion method of claim 9, wherein, Further comprising: processing the actual output analog signal by the echo transmission circuit to generate the echo signal, so that the deviation update circuit updates the deviation value of one of the correspondences in the code word deviation table accordingly.

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