Semiconductor device

Abstract

The present application provides a new semiconductor device suitable for high voltage without a drift layer. The semiconductor device of the present application is characterized by having: a first semiconductor layer of a first conductivity type, formed into either of a p-type and an n-type; a source portion, disposed in contact with the first semiconductor layer, and formed into a semiconductor portion of a second conductivity type different from the first conductivity type; a source electrode, disposed in ohmic contact with the source portion; a gate electrode, disposed on either face of the first semiconductor layer via a gate insulating film, and capable of forming an inversion layer in a region near a contact face of the first semiconductor layer with the gate insulating film by applying an electric field; a second semiconductor layer of the first conductivity type, disposed in contact with the inversion layer; and a drain electrode, disposed separately from the inversion layer and in Schottky contact with the second semiconductor layer.

Description

Technical Field

[0001] This invention relates to a semiconductor device without a drift layer suitable for high voltage resistance. Background Technology

[0002] Currently, IGBTs (Insulated Gate Bipolar Transistors), which have low on-resistance and high withstand voltage, are used as switching elements suitable for high power applications.

[0003] However, since the IGBT is a bipolar device that operates with minority carriers participating in conduction, it has a problem that its switching speed is worse than that of unipolar devices.

[0004] On the other hand, regarding unipolar operating devices such as MOSFETs (Metal-Oxide-Semiconductor Field Effect Transistors), there is a problem that the relationship between on-resistance and withstand voltage is a trade-off: when seeking low on-resistance, the withstand voltage decreases, and when seeking high withstand voltage, the on-resistance increases (see Non-Patent Literature 1-3). This problem will be explained in detail below.

[0005] Figure 1 The diagram shows a representative example of the element construction of an existing MOSFET element for power devices.

[0006] Such as Figure 1 As shown, in the MOSFET element 100, a second conductivity type (p) semiconductor layer 101 is formed within the first conductivity type (n-type) semiconductor layer 101. + The source region 102 and drain region 103 are of type p. Furthermore, a second conductivity type (p-type) with a lower impurity concentration is formed around the drain region 103. - Drift layer 104 (type).

[0007] In addition, source electrode 105 and drain electrode 106, which are in ohmic contact with these regions, are formed on source region 102 and drain region 103, respectively.

[0008] Furthermore, on the semiconductor layer 101, a gate electrode 108 is disposed between the source region 102 and the drain region 103 by a gate insulating film 107. In the MOSFET element 100, as a voltage is applied to the gate electrode 108, a polarity-reversing inversion layer (channel region) 109 can be formed in the semiconductor layer 101 directly below the gate electrode 108 in such a way that it is erected between the source region 102 and the drift layer 104.

[0009] In this MOSFET device 100, although the drift layer 104 can be used to improve the breakdown voltage, the on-resistance becomes high due to the low impurity concentration in the drift layer 104. Furthermore, sometimes the drift layer 104 is formed to increase the breakdown voltage, but this also contributes to a longer carrier movement path, leading to a higher on-resistance. These factors contributing to the increased on-resistance originate from the drift resistance of the drift layer 104. On the other hand, if the impurity concentration in the drift layer 104 is increased, reducing the drift resistance, the applied electric field strength will increase, thereby lowering the breakdown voltage.

[0010] Therefore, in existing MOSFET devices with a drift layer, there is always a problem that the relationship between the on-resistance from the drift resistor and the breakdown voltage is always a trade-off: when seeking low on-resistance, the breakdown voltage decreases, and when seeking high breakdown voltage, the on-resistance increases.

[0011] Therefore, in order to break the status quo, it is necessary to develop a new semiconductor device that does not have the aforementioned drift layer and is suitable for high voltage resistance.

[0012] Furthermore, the withstand voltage referred to here is the limit of voltage that will not cause malfunction or damage to the component.

[0013] Existing technical documents

[0014] Non-patent literature

[0015] Non-patent literature 1: SMSze, "Physics of Semiconductor Devices", Wiley, 3rd Edition (2007).

[0016] Non-Patent Literature 2: "At the forefront of device development for next-generation power semiconductors - an energy-saving society", NTS, ISBN-10:4860432622, (2009).

[0017] Non-patent literature 3: Kazuo Arai and Sadao Yoshida, “Fundamentals and Applications of SiC Devices”, (2003), ohmsha, Ltd. Summary of the Invention

[0018] [The problem the invention aims to solve]

[0019] The objective of this invention is to solve the aforementioned problems in the prior art and provide a novel semiconductor device suitable for high voltage resistance without a drift layer.

[0020] [Technical means to solve the problem]

[0021] As a means to solve the aforementioned problem, it is described below. That is,

[0022] <1> A semiconductor device, characterized by comprising: a first semiconductor layer of a first conductivity type, formed of either p-type or n-type conductivity; a source portion disposed in connection with the first semiconductor layer and formed of a second conductivity type different from the first conductivity type; a source electrode disposed in ohmic contact with the source portion; a gate electrode disposed on any surface of the first semiconductor layer through a gate insulating film, and capable of forming an inversion layer in the region near the contact surface with the gate insulating film in the first semiconductor layer by applying an electric field; a second semiconductor layer of the first conductivity type disposed in connection with the inversion layer; and a drain electrode disposed separately from the inversion layer and in Schottky contact with the second semiconductor layer.

[0023] <2> According to the semiconductor device described in <1>, the distance L, which is the shortest distance between the inversion layer and the drain electrode, is... dg The following condition (1) must be met.

[0024] [Number 1]

[0025]

[0026] In equation (1), ε represents the dielectric constant of the second semiconductor layer, and φ bi The built-in potential generated between the second semiconductor layer and the drain electrode of the Schottky contact is represented by q, which represents the electron charge, and N. d This indicates the impurity concentration in the second semiconductor layer.

[0027] <3> The semiconductor device described in any one of <1> to <2>, wherein the impurity concentration in the source portion is one order of magnitude higher than the impurity concentration in the first semiconductor layer.

[0028] <4> A semiconductor device according to any one of <1> to <3>, wherein the source portion is formed as any one of a layer buried from one side of the first semiconductor layer toward a side opposite to the one side and a layer stacked on the one side, the gate electrode is disposed on the one side of the first semiconductor layer through a gate insulating film, the second semiconductor layer is formed at a position opposite to the source portion through the gate electrode and the inversion layer as any one of a layer buried from one side of the first semiconductor layer toward a side opposite to the one side and a layer stacked on the one side, and the drain electrode is disposed on the second semiconductor layer.

[0029] <5> A semiconductor device according to any one of <1> to <3>, wherein the source portion is formed as a layer on one surface where a source electrode is disposed, a first semiconductor layer is deposited on the surface of the layer opposite to the one surface and is formed in such a way as having a through hole, the through hole extending from the deposited surface of the first semiconductor layer and the layer to the surface opposite to the deposited surface, a second semiconductor layer and a drain electrode are sequentially disposed on the surface opposite to the first semiconductor layer, and a gate electrode is disposed in the through hole in such a way that the contact surface with the first semiconductor layer and the layer is covered by a gate insulating film.

[0030] <6> A semiconductor device according to any one of <1> to <5>, wherein the first semiconductor layer and the second semiconductor layer are formed into a single layer with the same semiconductor material and impurity concentration.

[0031] <7> The semiconductor device according to any one of <1> to <6>, wherein at least one of the first semiconductor layer, the second semiconductor layer and the source portion is formed of a wide bandgap semiconductor forming material having a bandgap larger than that of silicon.

[0032] <8> In the semiconductor device described in <7>, the wide bandgap semiconductor forming material is diamond.

[0033] <9> According to the semiconductor device described in <8>, the source electrode is formed of diamond and has hopping conductivity.

[0034] [The effects of the invention]

[0035] According to the present invention, the aforementioned problems in the prior art can be solved, and a new semiconductor device suitable for high voltage resistance can be provided without the drift layer. Attached Figure Description

[0036] Figure 1 This is a cross-sectional view showing a representative example of the component construction of existing MOSFET elements used in power devices.

[0037] Figure 2(a) is a cross-sectional view showing the state of a planar MOSFET device when it is turned off.

[0038] Figure 2(b) is a cross-sectional view showing the state of a planar MOSFET device when it is turned on.

[0039] Figure 3(a) is a diagram showing the energy band diagram of a MOSFET device in thermal equilibrium when the drain-source electrode is disconnected.

[0040] Figure 3(b) is a diagram showing the energy band diagram of a MOSFET device in thermal equilibrium when the drain-source electrode is connected.

[0041] Figure 4 This is an explanatory diagram used to compare the on-resistance of a conventional MOSFET with that of the MOSFET of the present invention.

[0042] Figure 5 This is an explanatory diagram used to compare the slope of the characteristic represented linearly on a double logarithmic graph of the on-resistance and withstand voltage of a MOSFET with a drift layer with the slope of the characteristic of the MOSFET of the present invention.

[0043] Figure 6 This is a cross-sectional view showing the component structure of a vertical MOSFET element.

[0044] Figure 7 This is a cross-sectional view showing the device structure of a planar MOSFET device formed using diamond semiconductor.

[0045] Figure 8 This is a diagram showing an optical microscope image obtained from the upper surface of the semiconductor device of Example 1, and a magnified representation of a portion of the optical microscope image.

[0046] Figure 9 This is a graph showing the results obtained from measuring the device characteristics of the semiconductor device in Example 1.

[0047] Figure 10 It represents the distance L related to equation (1). dg A graph showing the relationship between the concentration of impurities in the second semiconductor layer and the concentration of impurities in the second semiconductor layer.

[0048] Figure 11 This is a graph showing the drain current-drain voltage characteristics of the semiconductor device in Example 2.

[0049] Figure 12(a) is a graph showing the drain current-drain voltage characteristics of the semiconductor device of Example 3.

[0050] Figure 12(b) is a graph showing the drain current-drain voltage characteristics of the semiconductor device of Example 4. Detailed Implementation

[0051] (Semiconductor devices)

[0052] The semiconductor device of the present invention is configured having a first semiconductor layer, a source portion, a source electrode, a second semiconductor layer, a drain electrode, and a gate electrode.

[0053] In the semiconductor device, the drain region 103 (see reference 100) is absent. Figure 1It operates on a different principle. Furthermore, the semiconductor device does not have the drift layer 104 found in the conventional MOSFET element 100 (see reference 104). Figure 1 Therefore, the switching resistance is not affected by the drift resistance.

[0054] Hereinafter, the various parts of the semiconductor device will be described first, and then the operating principle and implementation method of the semiconductor device will be explained in detail with reference to the accompanying drawings.

[0055] <First Semiconductor Layer>

[0056] The first semiconductor layer is formed as a semiconductor layer of a first conductivity type, which is either p-type or n-type. The first semiconductor layer is formed as the first conductivity type by introducing either a p-type impurity or an n-type impurity.

[0057] There are no particular limitations on the p-type impurity substance; any known impurity substance can be used, with boron being a representative example. Similarly, there are no particular limitations on the n-type impurity substance; any known impurity substance can be used, with phosphorus or nitrogen being representative examples.

[0058] There are no particular limitations on the impurity concentration in the first semiconductor layer, but 1×10⁻⁶ is preferred. 11 cm -3 ~1×10 18 cm -3 about.

[0059] There are no particular limitations on the forming material of the first semiconductor layer, and known semiconductor materials including silicon and germanium can be cited as examples. However, from the viewpoint of application to power devices, a semiconductor forming material with a wide bandgap that is larger than that of silicon is preferred. That is, in the semiconductor device, the on-resistance is not affected by the drift resistance, and the semiconductor material can be selected with particular consideration of the withstand voltage. Therefore, it is suitable for power devices utilizing the wide bandgap semiconductor.

[0060] There are no particular limitations on the wide bandgap semiconductor forming material, and it can be appropriately selected according to the purpose. Examples include silicon carbide (SiC), gallium nitride (GaN), diamond, etc. Among them, diamond is preferred because it has excellent melting point, thermal conductivity, resistance to insulation damage, carrier velocity limit, hardness, elastic constant, chemical stability and radiation resistance, in addition to its excellent wide bandgap characteristics.

[0061] There are no particular limitations on the first semiconductor layer, and it can be made of a known semiconductor substrate or the like.

[0062] Furthermore, there are no particular limitations on the method for forming the first semiconductor layer, and it can be appropriately selected from known formation methods depending on the forming material. Moreover, when the first semiconductor layer is diamond, the method described in Japanese Patent Application Publication No. 2018-006572, which involves forming the layer on a diamond substrate using plasma vapor deposition, is preferred.

[0063] Furthermore, when the via is formed in the first semiconductor layer, there are no particular limitations on the method for forming the via, and well-known photolithography methods can be cited as examples.

[0064] <Source Section>

[0065] The source portion is formed as a semiconductor portion of a second conductivity type that is disposed in connection with the first semiconductor layer and whose conductivity type is different from the first conductivity type.

[0066] As the forming material of the source portion, the same forming material as the forming material of the first semiconductor layer can be used. Alternatively, as the impurity substance in the source portion, an impurity substance with a polarity opposite to that of the first semiconductor layer can be used.

[0067] There is no particular limitation on the impurity concentration in the source region, but it is preferably one order of magnitude higher than the impurity concentration in the first semiconductor layer. Specifically, 1 × 10⁻⁶ is preferred. 19 cm -3 ~1×10 22 cm -3 Left and right. If the impurity concentration in the source region is higher than that in the first semiconductor layer, the resistance of the source region can be reduced.

[0068] There are no particular limitations on the method for forming the source electrode, and it can be appropriately selected from known forming methods depending on the forming material.

[0069] As a representative formation method, the well-known ion implantation method can be cited. That is, the source region can be formed in the same way as the well-known source region, as a layer buried from one side of the first semiconductor layer toward the side opposite to the one side.

[0070] Alternatively, in the case where the material is difficult to form using ion implantation (such as diamond), the layer can be formed as a layer deposited on one surface of the first semiconductor layer. In this case, the plasma vapor deposition method or photolithography method described in Japanese Patent Application Publication No. 2018-006572 can be used to form the layer.

[0071] Furthermore, regardless of the material used to form the source portion, it can be shaped in a layered manner according to the element structure of the semiconductor device.

[0072] Furthermore, when the source portion is formed of diamond, it is preferable to have hopping conductivity from the viewpoint of reducing the resistance of the source portion. This hopping conductivity is achieved by ensuring that the impurity concentration in the source portion formed of diamond is 1 × 10⁻⁶. 19 cm -3 This is illustrated above.

[0073] <Source Electrode>

[0074] The source electrode is configured to make ohmic contact with the source portion.

[0075] There are no particular limitations on the material used to form the source electrode, and examples include known electrode materials such as titanium, aluminum, nickel, molybdenum, tungsten, tantalum, platinum, gold, alloys containing these elements, carbides, nitrides, and silicides of these elements. When the source electrode is formed of diamond, titanium, platinum, gold, and laminates of these metals are preferred.

[0076] There are no particular limitations on the method for forming the source electrode, and well-known methods such as vacuum evaporation, CVD (Chemical Vapor Deposition), and ALD (Atomic Layer Deposition) can be cited as examples.

[0077] Furthermore, as for the method of forming the source portion and the source electrode when the source portion is formed from the diamond, a known forming method can be appropriately selected, for example, the method described in Japanese Patent No. 6341477.

[0078] <Gate electrode>

[0079] The gate electrode is disposed on any surface of the first semiconductor layer through a gate insulating film, and an inversion layer can be formed in the region near the contact surface with the gate insulating film in the first semiconductor layer by applying an electric field.

[0080] There are no particular limitations on the forming material of the gate insulating film, and it can be appropriately selected according to the purpose. For example, known forming materials such as SiO2, HfO2, Al2O3, and ZrO2 can be cited. In particular, when the first semiconductor layer is formed of diamond, Al2O3 is preferred. If Al2O3 is used, the interfacial energy level density, which is the defect energy level, can be reduced between Al2O3 and the diamond, and the inversion layer can be appropriately excited for the first semiconductor layer (for example, see Japanese Patent Application Publication No. 2018-006572, hereinafter referred to as Reference 1).

[0081] Furthermore, there are no particular limitations on the method for forming the gate insulating film, and it can be appropriately selected according to the purpose. For example, the ALD method, sputtering method, CVD method, etc., which use the forming material can be cited.

[0082] Reference 1: T.Matsumoto et.al., "Inversion channel diamond metal oxide-semiconductor field-effect transistor with normally off characteristics", Scientific Reports, 6, 31585 (2016).

[0083] There are no particular limitations on the material used to form the gate electrode, and examples include known electrode materials such as titanium, aluminum, nickel, molybdenum, tungsten, tantalum, platinum, gold, alloys containing these elements, carbides, nitrides and silicides of these elements.

[0084] Furthermore, there are no particular limitations on the method for forming the gate electrode, and it can be appropriately selected according to the purpose. For example, sputtering and CVD methods can be cited.

[0085] <Second Semiconductor Layer>

[0086] The second semiconductor layer is formed as a semiconductor layer of the first conductivity type configured in connection with the inversion layer.

[0087] There are no particular limitations on the impurity concentration in the second semiconductor layer, but similarly to the first semiconductor layer, it is preferably from 1 × 10⁻⁶. 11 cm -3 ~1×10 18 cm -3 The impurity concentration is selected within a range of left and right. In the second semiconductor layer, if the impurity concentration is too low, the width of the depletion layer formed from the drain electrode at the Schottky contact to the second semiconductor layer may become wider, leading to a larger device. If the impurity concentration is too high, the width of the depletion layer may become narrower, making it difficult to process. Furthermore, the depletion layer will be described below together with the description of the first embodiment with reference to the accompanying drawings.

[0088] As the forming material of the second semiconductor layer, the same forming material as the forming material of the first semiconductor layer can be used as an example.

[0089] The second semiconductor layer is a layer whose impurity concentration can be set independently of the first semiconductor layer of the same conductivity type. However, in the manufacturing process, it is preferable that the impurity concentration is common to a region within the first semiconductor layer. That is, it is preferable that the first semiconductor layer and the second semiconductor layer are formed into a single layer using the same semiconductor material and impurity concentration. When formed in this way, the first semiconductor layer itself can also serve as the second semiconductor layer, thus omitting the manufacturing process of forming the second semiconductor layer into a semiconductor layer different from the first semiconductor layer.

[0090] There are no particular limitations on the formation method for forming the second semiconductor layer as a semiconductor layer different from the first semiconductor layer, and known semiconductor layer formation methods and known photolithography methods can be applied.

[0091] <Drain Electrode>

[0092] The drain electrode is separated from the inversion layer and is configured to contact the second semiconductor layer in a Schottky contact.

[0093] In the semiconductor device, by making the contact between the source portion and the source electrode an ohmic contact, and making the contact between the second semiconductor layer (or the first semiconductor layer if the second semiconductor layer is formed from the first semiconductor layer itself) and the drain electrode a Schottky contact, a method is used that is similar to existing MOSFET devices (e.g., see reference). Figure 1 They operate based on different principles.

[0094] There are no particular limitations on the material used to form the drain electrode, and examples include known electrode materials such as titanium, aluminum, nickel, molybdenum, tungsten, tantalum, platinum, gold, alloys containing these elements, carbides, nitrides, and silicides of these elements. When the source electrode is formed of diamond, titanium, platinum, gold, and laminates of these metals are preferred.

[0095] Furthermore, there are no particular limitations on the method for forming the drain electrode, and well-known methods such as vacuum evaporation, CVD, and ALD can be cited as examples.

[0096] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. Furthermore, the technical concept of the present invention is not limited to these embodiments, and can be widely applied to unipolar transistors and the like formed from wide-bandgap semiconductors.

[0097] [First Implementation]

[0098] Figures 2(a) and (b) show the semiconductor device of the first embodiment. This semiconductor device of the first embodiment is shown as a configuration example as a planar MOSFET element. Furthermore, Figure 2(a) is a cross-sectional view showing the planar MOSFET element in the off state, and Figure 2(b) is a cross-sectional view showing the planar MOSFET element in the on state.

[0099] As shown in Figures 2(a) and (b), the MOSFET element 10 has a first semiconductor layer 11 with an n-type conductivity, and a device with a p-type conductivity is disposed in connection with the first semiconductor layer 11. + The first semiconductor layer 11 has a source portion 12, a source electrode 15 disposed in ohmic contact with the source portion 12, a gate electrode 18 disposed on one surface of the first semiconductor layer 11 through a gate insulating film 17, and a drain electrode 16 disposed in Schottky contact with the second semiconductor layer 13.

[0100] The source portion 12 is formed as a layer buried from one surface of the first semiconductor layer 11 toward a surface opposite to that surface, and the impurity concentration is set to be higher than that of the first semiconductor layer 11 (p). + The inversion layer 19 is formed in such a way that it achieves ohmic contact with the source electrode 15. In addition, the source portion 12 is formed at a position that can contact the inversion layer 19.

[0101] On the other hand, the drain electrode 16 of the Schottky contact is configured separately from the inversion layer 19 formed in the first semiconductor layer 11 directly below the gate electrode 18 (see Figure 2(b)). Furthermore, the “L” in the figure... dg "" indicates the shortest distance between the inversion layer 19 and the drain electrode 16, where the drain electrode 16 is separated from the inversion layer 19 by a distance L. dg .

[0102] The distance L dg Essentially, this can be considered as the distance between the first contact position and the opposing position of the inversion layer 19, which is closest to the second contact position. The first contact position is the contact position between the drain electrode 16 on the side opposite to the gate electrode 18 and the second semiconductor layer 13 (first semiconductor layer 11). At this time, the second contact position is the contact position between the gate electrode 18 on the side opposite to the drain electrode 16 and the gate insulating film 17. That is, it can be considered as the distance between the drain electrode 16 and the gate electrode 18. In design, the distance L can also be... dg The distance between the drain electrode 16 and the gate electrode 18 is determined.

[0103] The second semiconductor layer 13 is formed as a region of the first semiconductor layer 11 itself, and is formed as a layer with the same semiconductor material and impurity concentration as the first semiconductor layer 11. As this second semiconductor layer 13, it corresponds to a region of the first semiconductor layer 11 whose main region is the region along the shortest path from the inversion layer 19 formed in the first semiconductor layer 11 directly below the gate electrode 18 to the drain electrode 16, and the drain electrode 16 is disposed in this region (see Figure 2(b)).

[0104] according to Figure 1 Compared with Figures 2(a) and (b), it can be understood that the difference between MOSFET element 10 and the existing MOSFET element 100 is that: a portion corresponding to the drain region 103 and the drift layer 104 is not formed. In addition, the source electrode 15 with ohmic contact and the drain electrode 16 with Schottky contact have electrodes with different contact characteristics.

[0105] This difference is based on the fact that the MOSFET element 10 operates on a different operating principle than the existing MOSFET element 100. Hereinafter, the operating principle of the MOSFET element 10 will be explained with reference to FIG3(a) and (b).

[0106] Figure 3(a) is a diagram showing the energy band diagram of the MOSFET element 10 when the drain electrode 16 and the source electrode 15 are disconnected in thermal equilibrium.

[0107] As shown in the figure, when disconnected, a first depletion layer is formed due to the Schottky junction between the drain electrode 16 and the second semiconductor layer 13 (the first semiconductor layer 11). Additionally, a second depletion layer is formed on the first semiconductor layer 11 due to the pn junction between the source portion 12 and the first semiconductor layer 11. These first and second depletion layers are not connected to each other and are separated by the neutral region of the first semiconductor layer 11.

[0108] When no voltage is applied to the gate electrode 18, the downward bandgap formed by the neutral region blocks the movement of holes (indicated by "+" in the figure) in the source portion 12, resulting in a non-current-flowing, open state. Even assuming a forward voltage is applied to the drain electrode 16, the p-channel voltage of the source portion 12... + Holes present in the valence band of the first semiconductor layer 11 will flow into the nth layer and recombine with electrons (represented by "-" in the figure) before disappearing.

[0109] Therefore, the holes in the source portion 12 cannot reach the drain electrode 16, and as a result, the first semiconductor layer 11 acts as an insulator relative to the holes, which are the majority carriers.

[0110] Figure 3(b) is a diagram showing the energy band diagram of the MOSFET element 10 when the drain electrode 16 and source electrode 15 are connected in thermal equilibrium.

[0111] As shown in the figure, if a voltage is applied to the gate electrode 18 to make it turn on, an inversion layer 19 is formed directly below the gate insulating layer 17 in the first semiconductor layer 11, and the neutral region disappears.

[0112] At this time, if a forward voltage is applied to the drain electrode 16, the holes present in the valence band of the source portion 12 will flow into the second semiconductor layer 13 through the inversion layer 19, and reach the drain electrode 16 using the internal electric field of the second semiconductor layer 13. That is, drain current flows.

[0113] Additionally, at this time, through the Schottky contact of the drain electrode 16, the first depletion layer formed on the second semiconductor layer 13 will be connected to the inversion layer 19, as the distance L between the drain electrode 16 and the gate electrode 18. dg From the viewpoint that the drain current flows through the inversion layer 19 and the drain electrode 16 via the second semiconductor layer 13 (the formation region of the first depletion layer), it is preferable to satisfy the following condition (1).

[0114] Furthermore, when the condition of the following formula (1) is met, the first depletion layer is completely depleted, and the second semiconductor layer 13, which is the formation region of the first depletion layer, becomes a good conductor relative to holes, and the switching resistance is significantly reduced.

[0115] [Number 2]

[0116]

[0117] In equation (1), ε represents the dielectric constant of the second semiconductor layer 13 (the first semiconductor layer 11), and φ bi The built-in potential generated between the second semiconductor layer 13 (the first semiconductor layer 11) and the Schottky contact drain electrode 16 is represented by q, which represents the electron charge, and N. d This indicates the impurity concentration in the second semiconductor layer 13 (the first semiconductor layer 11).

[0118] As described above, the MOSFET element 10 of the semiconductor device according to the first embodiment of the present invention does not have the drift layer 104 (see reference) found in the conventional MOSFET element 100. Figure 1 The on-resistance is formed as a drift-free resistance.

[0119] Therefore, as Figure 4 As shown, the MOSFET element 10 of the semiconductor device according to the first embodiment of the present invention can significantly reduce the on-resistance. Furthermore, Figure 4 This is an explanatory diagram used to compare the on-resistance of a conventional MOSFET with that of the MOSFET of the present invention.

[0120] Furthermore, in the MOSFET element 10 of the semiconductor device according to the first embodiment of the present invention, since the on-resistance depends on the channel resistance (resistance of the inversion layer 19), the slope of the characteristic represented linearly on the double logarithmic curve of on-resistance versus breakdown voltage is gentler than the slope of the characteristic of the MOSFET element in the present case where the on-resistance depends on the drift resistance.

[0121] Therefore, as Figure 5 As shown, according to the element structure of the MOSFET element 10 of the semiconductor device as the first embodiment of the present invention, regardless of whether the semiconductor material is Si, 4H-SiC, GaN, Ga2O3, or diamond, it is possible to achieve low on-resistance and high withstand voltage of the semiconductor device formed from the same semiconductor material. Furthermore, Figure 5 This is an explanatory diagram used to compare the slope of the characteristic represented linearly on a double logarithmic graph of the on-resistance and withstand voltage of a MOSFET with a drift layer with the slope of the characteristic of the MOSFET of the present invention.

[0122] Furthermore, in order to change the component configuration of the p-channel MOSFET element 10 to enable n-channel operation, the conductivity type of the first semiconductor layer 11 is changed from n-type to p-type, and the conductivity type of the source portion 12 is changed from p-type to n-type, thus becoming n-channel MOSFET 10. + The semiconductor layer is of the n-channel type, which reverses the polarity of the applied voltage relative to the p-channel type operation. The MOSFET device configured in this way can operate on the same operating principle as that described using Figures 3(a) and (b), except that the majority carriers are converted from holes to electrons.

[0123] Furthermore, the operating principle illustrated in Figures 3(a) and (b) can be applied to semiconductor devices formed from semiconductor materials (e.g., diamond) where the energy levels (donor and acceptor levels) of the conductive impurities in the first semiconductor layer of the semiconductor material (e.g., diamond) are located at a sufficiently deep position compared to the thermal excitation energy corresponding to the operating temperature of the semiconductor device. However, for semiconductor devices formed from semiconductor materials (e.g., silicon) that have shallower impurity energy levels at room temperature, operation can also be achieved by operating them at a sufficiently low temperature where the thermal excitation energy becomes sufficiently low.

[0124] [Second Implementation]

[0125] Next, Figure 6The semiconductor device of the second embodiment is shown. This semiconductor device of the second embodiment is illustrated as a configuration example of a vertically oriented MOSFET element. Furthermore, Figure 6 This is a cross-sectional view showing the component structure of a vertical MOSFET element.

[0126] like Figure 6 As shown, the MOSFET element 20 has a first semiconductor layer 21 with an n-type conductivity, a source portion 22 of a source semiconductor layer with a p-type conductivity and disposed in connection with the first semiconductor layer 21, a source electrode 25 disposed in ohmic contact with the source portion 22, a gate electrode 28 disposed on one surface of the first semiconductor layer 21 through a gate insulating film 27, and drain electrodes 26a and b disposed in Schottky contact with the second semiconductor layers 23a and 23b.

[0127] The second semiconductor layers 23a and 23b are formed as a region of the first semiconductor layer 21 itself, and are formed as a layer with the same semiconductor material and impurity concentration as the first semiconductor layer 21. As the second semiconductor layers 23a and 23b, they are equivalent to a region of the first semiconductor layer 21 whose main region is the area along the shortest path from the inversion layer 29a formed near the contact surface with the gate insulating film 27 in the first semiconductor layer 21 to the drain electrode 26a, and another region of the first semiconductor layer 21 whose main region is the area along the shortest path from the inversion layer 29b to the drain electrode 26b, and the drain electrodes 26a and 26b are disposed on these regions.

[0128] In the MOSFET element 20, the source portion 22 is formed as a layer on one surface where a source electrode 25 is disposed. A first semiconductor layer 21 is deposited on the surface of the source portion 22 opposite to the one surface and is formed in such a way as to have a through hole. The through hole extends from the deposited surface of the first semiconductor layer 21 and the source portion 22 to the surface opposite to the deposited surface.

[0129] Furthermore, drain electrodes 26a and 26b are disposed on the opposite side of the first semiconductor layer 21. In this example, as described above, the first semiconductor layer 21 itself also serves as the second semiconductor layer 23a (23b). The second semiconductor layer 23a (23b) corresponds to a region of the first semiconductor layer 21 whose main region is the area along the shortest path from the inversion layer 29a (29b) to the drain electrode 26a (26b). Therefore, it is essentially configured such that the second semiconductor layer 23a (23b) and the drain electrode 26a (26b) are disposed sequentially on the first semiconductor layer 21 at the upper end of the inversion layer 29a (29b).

[0130] In addition, the gate electrode 28 is disposed in the through hole such that the contact surface with the first semiconductor layer 21 and the source portion 22 is covered by the gate insulating film 27.

[0131] In the MOSFET element 20 of the semiconductor device of the second embodiment of the present invention, which is configured in this way, the operating principle of the MOSFET element 10 described in FIG3(a) and (b) can be applied by simply replacing the positional relationship between the p-type region and the n-type region in the longitudinal direction. Therefore, it is possible to form the semiconductor device suitable for high voltage with no drift resistance.

[0132] Furthermore, while the MOSFET element 20 has been described as operating in a p-channel mode, it is also possible to reverse the relationship between the p-type and n-type in the MOSFET element 20 to form a semiconductor device operating in an n-channel mode.

[0133] [Third Implementation]

[0134] Next, Figure 7 The semiconductor device of the third embodiment is shown in the figure. This semiconductor device of the third embodiment is illustrated as a configuration example of a planar MOSFET element formed using diamond semiconductor. Furthermore, Figure 7 This is a cross-sectional view showing the device structure of a planar MOSFET device formed using diamond semiconductor.

[0135] like Figure 7 As shown, the MOSFET element 30 has a first semiconductor layer 31 of a first conductivity type, a source portion 32 of a second conductivity type disposed in connection with the first semiconductor layer 31, a source electrode 35 disposed in ohmic contact with the source portion 32, a gate electrode 38 disposed on one surface of the first semiconductor layer 31 through a gate insulating film 37, and a drain electrode 36 disposed in Schottky contact with the second semiconductor layer 33.

[0136] The second semiconductor layer 33 is formed as a region of the first semiconductor layer 31 itself, and is formed as a layer with the same semiconductor material and impurity concentration as the first semiconductor layer 31. As this second semiconductor layer 33, it corresponds to a region of the first semiconductor layer 31 whose main region is the area along the shortest path from the inversion layer 39 formed in the first semiconductor layer 31 directly below the gate electrode 38 to the drain electrode 36, and the drain electrode 36 is disposed in this region.

[0137] In the MOSFET element 30, the first semiconductor layer 31 (including the second semiconductor layer 33) and the source portion 32 are composed of a semiconductor layer (diamond semiconductor layer) formed of diamond.

[0138] Furthermore, unlike the MOSFET 10 (see Figures 2(a) and (b)) where the source portion 32 is formed as a buried layer, in the MOSFET element 30, the source portion 32 is formed as a layer deposited on the surface of the first semiconductor layer 31. The source portion 32 formed as this layer can be formed using known methods such as plasma vapor deposition or photolithography.

[0139] Other matters may apply to the matters described for MOSFET element 10 (see Figure 2(a), (b)).

[0140] The MOSFET elements in the first to third embodiments described above are examples used to illustrate the general outline of the present invention. Appropriate modifications can be made to these examples as long as they do not impair the effects of the present invention.

[0141] Furthermore, the following describes embodiments of the present invention, but the technical concept of the present invention is not limited to these embodiments.

[0142] Example

[0143] (Example 1)

[0144] Using the diamond as the semiconductor forming material, the semiconductor device (planar MOSFET device) of Example 1 is manufactured by the manufacturing method shown below. This semiconductor device of Example 1 is based on... Figure 7 The planar MOSFET element 30 shown is manufactured using the configuration shown.

[0145] First, a nitrogen-doped n-type diamond substrate (manufactured by the Russian National Institute of Technology for Superhard and New Carbon Materials (TISNCM), Ib-type substrate) with a slightly tilted deviation angle and a main surface of {111} is prepared, and this substrate is set as the first semiconductor layer.

[0146] Next, a p-type semiconductor layer that will become the source portion is formed on the surface of the first semiconductor layer (the surface with the {111} plane as its main surface) using a selective growth method with a metal mask. This will be explained in detail below.

[0147] First, the surface of the first semiconductor layer is boiled using a mixture of sulfuric acid and nitric acid to clean it. Then, a resist is applied to the first semiconductor layer using spin coating, and a resist pattern is formed using a mask. After development, a metal mask material (a gold and titanium stack) is deposited onto the first semiconductor layer with the resist pattern. Finally, the resist pattern is removed using a stripping process, thereby forming a metal mask pattern on the first semiconductor layer.

[0148] Next, the first semiconductor layer (substrate) with the metal mask pattern is introduced into a plasma vapor deposition apparatus (Seki Technotron Corp / now: CORNES Technologies Limited, AX5010-1-S), so that the source portion (p-type diamond semiconductor layer) is grown in the area on the surface of the first semiconductor layer where the metal mask pattern is not formed.

[0149] The growth conditions used hydrogen, methane, and trimethylboron gas, which imparts p-type conductivity, as raw materials. The flow rate of the hydrogen was set to 399 sccm, the flow rate of the methane was set to 0.8 sccm, and the flow rate of the hydrogen-diluted trimethylboron gas (containing 1% by volume of trimethylboron) was set to 0.8 sccm. These were then introduced into the plasma vapor deposition apparatus. The film formation conditions of the plasma vapor deposition apparatus were set as follows: plasma input power was set to 1,200 W, pressure was set to 50 Torr, and film formation time was set to 0.16 hours.

[0150] Next, the first semiconductor layer on which the source portion is formed is acid-washed to remove the metal mask pattern.

[0151] Next, the first semiconductor layer in this state is heated at 500°C for 1 hour in an aqueous environment, causing OH groups to bond to a dangling bond of a carbon atom protruding outward from the {111} face of the first semiconductor layer, thereby performing an end-capping treatment on the carbon atoms located on the outermost surface of the first semiconductor layer using OH groups. This end-capping treatment is performed using a tubular electric furnace (manufactured by Koyo Thermo Systems, a small tube furnace), and the aqueous environment is achieved by using high-purity nitrogen to bubble ultrapure water.

[0152] Next, using an atomic layer deposition apparatus (Oxford Instruments Ltd., FlexAL), an Al2O3 insulating film is formed on the surface of the first semiconductor layer as the gate insulating film. Furthermore, the formation conditions for the gate insulating film using the atomic layer deposition apparatus are set as follows: film deposition temperature is 300°C, and thickness is 50 nm.

[0153] During the formation of this gate insulating film, the H atoms in the OH groups of the carbon atoms, bonded by the end-capping treatment, are replaced by Al atoms in the gate insulating film (the Al2O3 insulating film), thereby forming stable bonds between the carbon atoms and the gate insulating film. Thus, a gate insulating film is formed on the surface of the first semiconductor layer with fewer defects.

[0154] Next, resist is applied to the Al2O3 insulating film by spin coating, and a mask is used to form a resist pattern that does not cover the formation areas of the source and drain electrodes to be formed in subsequent processes. After development, the gate insulating film in the areas not covered by the resist pattern is removed by immersion in a diluted hydrofluoric acid solution, and then excess resist is removed by immersion in a resist removal solution.

[0155] Thus, the formation regions of the source electrode and the drain electrode are exposed, and the first semiconductor layer is covered by the gate insulating film.

[0156] Next, for the first semiconductor layer in this state, a resist is applied by spin coating, and a mask is used to form a resist pattern that does not cover the formation regions of the source electrode and the drain electrode, as well as the gate electrode formation region on the gate insulating film. After development, a gold (100nm) / platinum (30nm) / titanium (30nm) multilayer electrode is deposited using a vacuum evaporation apparatus (manufactured by Eiko Engineering, electron beam evaporator), and then the resist pattern is removed by stripping.

[0157] Thus, the source electrode, the drain electrode, and the gate electrode that form the multilayer electrode are formed on each formation region.

[0158] The semiconductor device of Example 1 is manufactured as the planar MOSFET element formed from the diamond semiconductor in the above manner.

[0159] <Characteristics>

[0160] Next, the operation of the MOSFET in the semiconductor device of Example 1 will be confirmed. Figure 8 The image shows the semiconductor device of Embodiment 1 as viewed from its top surface. Furthermore, Figure 8 This is a diagram showing an optical microscope image obtained from the upper surface of the semiconductor device of Example 1, and a magnified representation of a portion of the optical microscope image.

[0161] like Figure 8 As shown in the optical microscope image, in the semiconductor device of Embodiment 1, the linewidth of the gate electrode, which is linearly arranged between the source electrode and the drain electrode, is set as the gate length L. g The wiring length of the gate electrode at the position sandwiched between the source electrode and the drain electrode is defined as the gate width W. g At that time, the gate length L g The gate width is 10μm. gThe length is 100 μm. Furthermore, in the semiconductor device of Example 1, a gate length L is also provided. g The gate widths are 5μm and 15μm, respectively, and the gate width is W. g The component structures are 50μm and 150μm in size. Additionally, the distance L... dg The distance between the drain electrode and the gate electrode is 5 μm.

[0162] Figure 9 The results shown are those obtained by measuring the device characteristics of the semiconductor device of Example 1 using a semiconductor parameter analyzer device (manufactured by KEITHLEY, 4200-SCS). Figure 9 The diagram shows the drain voltage between the source and drain electrodes on the horizontal axis and the drain current flowing between the source and drain electrodes on the vertical axis, with the voltage V applied to the gate electrode as the reference. g Drain current-drain voltage characteristics as the voltage changes from 0V to -12V on a -2V scale.

[0163] Such as Figure 9 As shown, it was confirmed that the gate voltage V was... g The characteristic of drain current flow when the value increases from the normally off state (towards the negative direction) enables the semiconductor device of Example 1 to perform MOSFET operation.

[0164] Additionally, the voltage V applied to the gate electrode will be... g The drain voltage at 0V is applied at a value greater than -200V, but without causing insulation failure.

[0165] The conditions of formula (1), which are described as suitable conditions for obtaining the semiconductor device of the present invention, are investigated.

[0166] [Number 3]

[0167]

[0168] In equation (1), ε represents the dielectric constant of the second semiconductor layer, and φ bi The built-in potential generated between the second semiconductor layer and the drain electrode of the Schottky contact is represented by q, which represents the electron charge, and N. d This indicates the impurity concentration in the second semiconductor layer.

[0169] Figure 10 The figure shows the distance L, which is equivalent to the length of the depletion layer generated in the second semiconductor layer from the drain electrode to the inversion layer when a reverse voltage of 1V is applied to the drain electrode. dg The relationship with the impurity concentration in the second semiconductor layer. Figure 10 It represents the distance L associated with equation (1). dg A graph showing the relationship between the concentration of impurities in the second semiconductor layer and the condition. In the graph, the gray areas represent regions that satisfy the condition of equation (1), and the white areas represent regions that do not satisfy the condition of equation (1).

[0170] The impurity concentration in the second semiconductor layer (the first semiconductor layer itself) of the semiconductor device in Example 1 is 1 × 10⁻⁶. 14 cm -3 Distance L dg It is 5μm.

[0171] The setting conditions of the semiconductor device in this embodiment 1 related to the above formula (1) are equivalent to Figure 10 The conditions drawn within the gray area (represented by “□” in the figure) satisfy the conditions of equation (1).

[0172] On the other hand, besides reducing the impurity concentration in the second semiconductor layer (the first semiconductor layer itself) of the semiconductor device of Example 1 from 1×10 14 cm -3 Change to 2×10 15 cm -3 The semiconductor device of the reference example is manufactured under otherwise identical conditions, the setting conditions of the semiconductor device of the reference example relating to the aforementioned formula (1) being equivalent to Figure 10 The conditions drawn within the white area (represented by "■" in the figure) do not satisfy the conditions of equation (1).

[0173] Regarding the semiconductor device of Example 1, it was confirmed that... Figure 9 The operating conditions (gate voltage, drain voltage) are shown, but for the semiconductor device in the reference example, it was confirmed that it did not operate under these conditions. Figure 9 The operating conditions (gate voltage, drain voltage) are shown. To operate the semiconductor device of the reference example, the voltage application conditions need to be changed to larger values. Conversely, the semiconductor device of Example 1 can be evaluated as being able to operate with smaller voltage application conditions.

[0174] As described above, in order for the semiconductor device of the present invention to perform the MOSFET operation appropriately, the condition of equation (1) needs to be satisfied.

[0175] (Example 2)

[0176] In addition to using masks of different sizes to reduce the distance L between the drain electrode and the gate electrode dg The semiconductor device of Example 2 was manufactured in the same manner as in Example 1, except that the size was changed from 5μm to 2μm.

[0177] (Example 3)

[0178] The first semiconductor layer is a nitrogen-doped diamond substrate with a phosphorus-doped layer, instead of the n-type diamond substrate (manufactured by the Russian National Institute of Technology for Superhard and New Carbon Materials (TISNCM), Ib-type substrate), and masks of different sizes are used to reduce the distance L between the drain electrode and the gate electrode. dg The gate length L was changed from 5μm to 2μm. g The gate width W was changed from 10μm to 5μm. g The size of the semiconductor element in Example 3 was changed from 100μm to 150μm, but otherwise the semiconductor element was manufactured in the same manner as in Example 1.

[0179] The nitrogen-doped Ib-type substrate with the phosphorus-doped layer is formed by introducing a nitrogen-doped diamond substrate (manufactured by the Russian National Institute of Superhard and New Carbon Materials Technology (TISNCM), Ib-type substrate) into the plasma vapor deposition apparatus (manufactured by SekiTechnotron Corp / now CORNES Technologies Limited, AX5010-1-S), and growing the phosphorus-doped layer, which is the first semiconductor layer, on the substrate.

[0180] The phosphorus-doped layer is formed using hydrogen, methane, and phosphine gas (which imparts n-type conductivity) as raw materials. The flow rate of hydrogen is set to 996 sccm, the flow rate of methane is set to 4 sccm, and the flow rate of hydrogen-diluted phosphine gas (phosphine content: 1,000 ppm) is set to 1 sccm. These are introduced into the plasma vapor deposition apparatus and formed under the following growth conditions: the plasma input power of the plasma vapor deposition apparatus is set to 3,600 W, the pressure is set to 150 Torr, and the film formation time is set to 1 hour.

[0181] (Example 4)

[0182] The following hydrogen sealing process is performed as a pretreatment for the sealing of the OH group, and masks of different sizes are used to separate the distance L between the drain electrode and the gate electrode. dg The gate length L was changed from 2μm to 5μm. g The size of the semiconductor element in Example 4 was changed from 5μm to 15μm, but otherwise the semiconductor element was manufactured in the same manner as in Example 3.

[0183] The hydrogen end-capping process is performed after the formation of the source portion by introducing the first semiconductor layer (and the nitrogen-doped diamond substrate) after the metal mask pattern has been removed by acid washing into a plasma vapor deposition apparatus (manufactured by ARIOS INC., DCVD-901K), introducing hydrogen gas into the plasma vapor deposition apparatus at a flow rate of 100 sccm, setting the plasma input power of the plasma vapor deposition apparatus to 600 W, setting the pressure condition to 30 kPa, and setting the processing time to 10 minutes. This causes hydrogen to bond to a dangling bond of a carbon atom protruding outward from the {111} face of the first semiconductor layer, thereby performing hydrogen end-capping on the carbon atom located on the outermost surface of the semiconductor layer.

[0184] In the subsequent end-capping process of the OH group, the hydrogen is replaced by the OH group. Due to the atomic-level roughness of the surface, the hydrogen that is not replaced by the OH group remains directly, thus ending the dangling bond and helping to reduce the interfacial energy level density.

[0185] The drain current-drain voltage characteristics of each semiconductor device in Examples 2 to 4 were measured using the semiconductor parameter analyzer device (manufactured by KEITHLEY, 4200-SCS). Figure 11 Figure 12(a) shows the on-current-on-voltage characteristics of the semiconductor device of Embodiment 2. Figure 12(b) shows the drain current-drain voltage characteristics of the semiconductor device of Embodiment 3. Furthermore, in these figures, the horizontal axis represents the voltage between the source electrode and the drain electrode as the drain voltage, and the vertical axis represents the current density of the current flowing between the source electrode and the drain electrode as the drain current. The voltage V applied to the gate electrode is... g Characteristics as the voltage changes from 0V to -15V using a -3V scale.

[0186] like Figure 11 As shown, in the semiconductor device of Embodiment 2, a device similar to a conventional MOSFET element (see reference 1) is obtained. Figure 1 Equal to the maximum drain current density of 1.5 mA / mm.

[0187] The result can be interpreted as follows.

[0188] That is, this result implies that in the drain region of existing MOSFET devices (refer to...) Figure 1 The drain region 103(p) + The resistance of the low-resistance region and the distance L dg A region of 2 μm (reference) Figure 7There is no resistance difference in the second semiconductor layer 33. This also means that, through the connection with the drain electrode (refer to...) Figure 7 The Schottky junction of the drain electrode 36 in the middle extends to the inversion layer (see reference). Figure 7 The depletion layer of the inversion layer 39) at a distance L dg An internal electric field is generated in a 2μm region, which is used to extract carriers from the inversion layer directly below the gate, thereby making the originally high resistance of the distance L negligible. dg The state of resistance in a region of 2μm.

[0189] That is, in the semiconductor device of the present invention, since a drift layer with high on-resistance is not configured (see reference 1), Figure 1 The drift layer 104 in the middle can operate with low on-resistance, so it is not constrained by the trade-off between on-resistance and voltage rating of existing MOSFET devices, and can achieve both low on-resistance and high voltage rating.

[0190] Furthermore, based on the comparison of Figures 12(a) and (b), it can be understood that if the distance L between the drain electrode and the gate electrode is made... dg Reducing the drain diameter from 5μm to 2μm will lower the turn-on voltage. At a distance L dg In the measurement results of Figure 12(a) (Example 3) with a diameter of 2 μm, a saturation region of drain current-drain voltage characteristics appears in the range of turn-on voltage from 0 V to -30 V, which means that sufficient voltage is applied.

[0191] The results shown in Figures 12(a) and (b) can be interpreted as follows.

[0192] That is, if the distance L dg It is relative to the drain electrode (refer to) Figure 7 The drain electrode 36 in the middle is oriented toward the inversion layer (refer to the reference layer). Figure 7 If the length of the depletion layer (39) extending from the inversion layer is too long, the drain voltage used to turn on will become higher, and the drain current will become drastically lower. In addition, the voltage reaching the saturation region will also become higher.

[0193] Therefore, it can be interpreted as, at a distance L dg In the measurement results of Figure 12(b) (Example 4) with a focal length of 5 μm, no saturation region was observed within the range of 0V to -30V turn-on voltage.

[0194] [Explanation of Symbols]

[0195] 10, 20, 30, 100 MOSFET devices

[0196] 11,21,31 First semiconductor layer

[0197] 12,22,32 Source poles

[0198] 15, 25, 35, 105 Source electrodes

[0199] 16, 26a, 26b, 36, 106 Drain electrodes

[0200] 17,27,37,107 Gate insulating film

[0201] 18, 28, 38, 108 gate electrodes

[0202] 19,29a,29b,39,109 Inverted layers

[0203] 102 Source Region

[0204] 103 Drain Region

[0205] 104 Drift layer.

Claims

1. A semiconductor device, characterized in that... have: The first semiconductor layer of the first conductivity type is formed as either p-type or n-type conductivity type; The source portion is configured to be connected to the first semiconductor layer and is formed as a semiconductor portion of a second conductivity type, which is different from the first conductivity type. The source electrode is configured to be in ohmic contact with the source portion; A gate electrode is disposed on any surface of the first semiconductor layer, separated by a gate insulating film, and an inversion layer can be formed in the region near the contact surface with the gate insulating film in the first semiconductor layer by applying an electric field; The second semiconductor layer of the first conductivity type is configured to be connected to the inversion layer; as well as The drain electrode is disposed separately from the inversion layer and in Schottky contact with the second semiconductor layer; and The distance L, which is the shortest distance between the inversion layer and the drain electrode. dg The following condition (1) must be satisfied. [Equation (1)] In equation (1), ε represents the dielectric constant of the second semiconductor layer, and φ bi The built-in potential generated between the second semiconductor layer and the drain electrode of the Schottky contact is represented by q, which represents the electron charge, and N. d This indicates the impurity concentration in the second semiconductor layer.

2. The semiconductor device according to claim 1, wherein the impurity concentration in the source portion is one order of magnitude higher than the impurity concentration in the first semiconductor layer.

3. The semiconductor device according to claim 1, wherein the source portion is formed as either a layer buried from one surface of the first semiconductor layer toward a surface opposite to said one surface, or a layer stacked on said one surface. The gate electrode is disposed on one surface of the first semiconductor layer, separated by a gate insulating film. The second semiconductor layer is formed at a position opposite to the source portion, separated by the gate electrode and the inversion layer, as either a layer buried from one surface of the first semiconductor layer toward a surface opposite to that one surface, or a layer deposited on that one surface. The drain electrode is disposed on the second semiconductor layer.

4. The semiconductor device according to claim 1, wherein the source portion is formed as a layer on one surface in which a source electrode is disposed. A first semiconductor layer is deposited on the surface of the layer opposite to the first semiconductor layer and is formed with a through-hole, the through-hole extending from the first semiconductor layer and the deposited surface to the surface opposite to the deposited surface. A second semiconductor layer and a drain electrode are sequentially disposed on the opposite side of the first semiconductor layer, and The gate electrode is disposed within the through-hole such that the contact surface with the first semiconductor layer and the layer is covered by a gate insulating film.

5. The semiconductor device of claim 1, wherein the first semiconductor layer and the second semiconductor layer are formed as a single layer with the same semiconductor material and impurity concentration.

6. The semiconductor device according to claim 1, wherein at least one of the first semiconductor layer, the second semiconductor layer, and the source portion is formed of a wide bandgap semiconductor forming material having a bandgap larger than that of silicon.

7. The semiconductor device of claim 6, wherein the wide bandgap semiconductor forming material is diamond.

8. The semiconductor device of claim 7, wherein the source portion is formed of diamond and has hopping conductivity.

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