System and method for motor cycle measurement and controlled signal path fault detection

Abstract

Systems and methods for motor period measurement and controlled signal path fault detection. A method for motor period measurement based on phase voltage includes: generating a commanded phase voltage; and applying the commanded phase voltage to a first phase voltage input of the motor, a second phase voltage input of the motor, and a third phase voltage input of the motor. The method also includes measuring a first period of the phase voltage associated with the first phase voltage input and the second phase voltage input, and comparing the first period of the phase voltage associated with the first phase voltage input and the second phase voltage input to a frequency of the commanded phase voltage. The method also includes: identifying a fault associated with a first integrated circuit or a signal path in response to determining that the first period of the phase voltage associated with the first phase voltage input and the second phase voltage input is outside a frequency range associated with the commanded phase voltage.

Description

Technical Field

[0001] The present disclosure relates to vehicle circuits, and more particularly, to systems and methods for phase voltage-based motor cycle measurement and controlled signal path fault detection. Background Art

[0002] Vehicles, such as cars, trucks, sport utility vehicles, off-road vehicles, minivans, or other suitable vehicles, often include various electric motors, such as permanent magnet motors or other suitable electric motors. Such electric motors may be used for various aspects of vehicle control or operation, such as vehicle propulsion or other suitable aspects of vehicle control or operation.

[0003] In a typical electric motor, the application of torque requires knowledge (e.g., by a vehicle controller) of the motor position. However, when the circuitry used to determine the motor position fails, the system associated with the motor is placed in a safe operating state. Typically, this may include a controller or other suitable component determining a specific safe operating state in which to place the system associated with the motor. To determine this specific safe state, the controller or other suitable component typically measures the speed of the motor. The controller or other suitable component can then use the measured motor speed to determine the specific safe operating state. Summary of the Invention

[0004] The present disclosure relates generally to electric motor control.

[0005] One aspect of the disclosed embodiment includes a method for phase voltage-based motor period measurement (e.g., where the period is inversely proportional to speed). The method includes generating a commanded phase voltage and applying the commanded phase voltage to a first phase voltage input of a motor, a second phase voltage input of the motor, and a third phase voltage input of the motor. The first phase voltage input and the second phase voltage input can be connected to a first differential capacitive coupling interface of a first integrated circuit, and the second phase voltage input and the third phase voltage input can be connected to a second differential capacitive coupling interface of a second integrated circuit. The method also includes measuring a first period of the phase voltage associated with the first phase voltage input and the second phase voltage input at an integrated analog comparator of the first integrated circuit, and comparing the first period of the phase voltage associated with the first phase voltage input and the second phase voltage input to a frequency associated with the commanded phase voltage. The method also includes identifying a fault associated with the first integrated circuit and / or a corresponding signal path in response to determining that the first period of the phase voltage associated with the first phase voltage input and the second phase voltage input is outside a frequency range associated with the commanded phase voltage.

[0006] Another aspect of the disclosed embodiment includes a system for phase voltage-based motor cycle measurement. The system includes a processor and a memory. The memory includes instructions that, when executed by the processor, cause the processor to: command a phase voltage having a defined period (e.g., frequency) during a self-test operation command; apply the commanded phase voltage to a first phase voltage input of a motor, a second phase voltage input of the motor, and a third phase voltage input of the motor, the first phase voltage input and the second phase voltage input being connected to a first differential capacitive coupling interface of a first integrated circuit, and the second phase voltage input and the third phase voltage input being connected to a second differential capacitive coupling interface of a second integrated circuit; measure a first period of the phase voltage associated with the first phase voltage input and the second phase voltage input at an integrated analog comparator of the first integrated circuit; compare the first period of the phase voltage associated with the first phase voltage input and the second phase voltage input to a frequency associated with the commanded phase voltage; and in response to determining that the first period of the phase voltage associated with the first phase voltage input and the second phase voltage input is outside a frequency range associated with the commanded phase voltage, identify a fault associated with at least one of the first integrated circuit and the corresponding signal path.

[0007] Another aspect of the disclosed embodiment includes an apparatus for motor cycle measurement based on phase voltage. The apparatus includes a processor and a memory. The memory includes instructions that, when executed by the processor, cause the processor to perform the following operations: commanding generation of a phase voltage having a defined period (e.g., frequency) during a power-up / initialization self-test operation; applying the commanded phase voltage to a first phase voltage input of the motor, a second phase voltage input of the motor, and a third phase voltage input of the motor, the first phase voltage input and the second phase voltage input being connected to a first differential capacitive coupling interface of a first integrated circuit, and the second phase voltage input and the third phase voltage input being connected to a second differential capacitive coupling interface of a second integrated circuit; measuring a first period of the phase voltage associated with the first phase voltage input and the second phase voltage input at an integrated analog comparator of the first integrated circuit; and comparing the first period of the phase voltage associated with the first phase voltage input and the second phase voltage input to the commanded phase voltage. the frequency associated with the commanded phase voltage; in response to determining that the first cycle of the phase voltage associated with the first phase voltage input and the second phase voltage input is outside the frequency range associated with the commanded phase voltage, identifying a fault associated with at least one of the first integrated circuit and the corresponding signal path; measuring the second cycle of the phase voltage associated with the second phase voltage input and the third phase voltage input at the integrated analog comparator of the second integrated circuit; comparing the second cycle of the phase voltage associated with the second phase voltage input and the third phase voltage input with the frequency associated with the commanded phase voltage; and in response to determining that the second cycle of the phase voltage associated with the second phase voltage input and the third phase voltage input is outside the frequency range associated with the commanded phase voltage, identifying a fault associated with the second integrated circuit and at least one of the corresponding signal paths.

[0008] These and other aspects of the disclosure are provided in the following description of the embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The present disclosure will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It is emphasized that, according to common practice, the various features of the drawings are not to scale. Instead, the dimensions of the various features have been arbitrarily expanded or reduced for clarity.

[0010] Figure 1 A vehicle according to the principles of the present disclosure is generally shown.

[0011] Figure 2 A controller according to the principles of the present disclosure is generally shown.

[0012] Figure 3A and Figure 3BA phase voltage based motor period measurement system according to the principles of the present disclosure is generally shown.

[0013] Figure 4 is a flow chart generally illustrating a method for motor period measurement based on phase voltage according to the principles of the present disclosure. DETAILED DESCRIPTION

[0014] The following discussion relates to various embodiments of the present invention. Although one or more of these embodiments may be preferred, the disclosed embodiments should not be interpreted or otherwise used to limit the scope of the present disclosure. In addition, it will be understood by those skilled in the art that the following description has broad application, and the discussion of any embodiment is merely an example of that embodiment and is not intended to imply that the scope of the present disclosure is limited to that embodiment.

[0015] As mentioned above, vehicles such as cars, trucks, sport utility vehicles, off-road vehicles, minivans, or other suitable vehicles typically include various electric motors, such as permanent magnet electric motors or other suitable electric motors. Such electric motors may be used for various aspects of vehicle control or operation, such as vehicle propulsion or other suitable aspects of vehicle control or operation.

[0016] In a typical electric motor, the application of torque requires knowledge (e.g., by a controller of the vehicle) of the motor position. However, when the circuit used to obtain the motor position fails, the systems associated with the motor are placed in a safe operating state. Typically, this may include the controller determining a particular safe operating state in which to place the systems associated with the motor. When the vehicle is moving, placing the systems associated with the motor in the safe operating state is typically accomplished by the controller commanding all six switches (which may include insulated gate bipolar transistor (IGBT) switches or other suitable switches) to open (e.g., which is referred to as six switch open (6SO)) or by the controller commanding three upper / lower switches of the six IGBT switches to close (e.g., which may be referred to as 3-phase short circuit upper / lower (3PSU / 3PSL) switches).

[0017] To determine which safe operating state (e.g., 6SO or 3PS) to place the systems associated with the electric motor, the controller typically measures the speed of the electric motor. The controller or other suitable component can then use the measured motor speed to determine a specific safe operating state. To operate the vehicle according to a corresponding risk classification scheme (e.g., Automotive Safety Integrity Level (ASIL) D or other suitable risk classification scheme), the vehicle can include circuitry to measure the speed of the electric motor for safe state operational control of the systems associated with the electric motor, and can include the ability to test the circuitry with good coverage.

[0018] Typically, solutions for providing a safe operating state for systems associated with an electric motor may include using a high voltage (HV) isolation amplifier with a HV resistor divider network to transmit a single-phase voltage on the HV interface and using an auxiliary microprocessor or controller to support motor speed measurement, which can be relatively resource intensive and consume a large amount of printed circuit board (PCB) area (real state). In addition, such solutions generally do not address the lack of fault coverage diagnostics for ASIL D compliant systems. For example, such solutions: do not support testing for faults in the IGBT control and feedback paths before torque is enabled; use single-phase voltage feedback to monitor speed during 6SO (e.g., but do not test the continuity and integrity of the full control and feedback paths of all six IGBTs during power-up / initialization self-test); monitor single-phase voltage only after entering torque / mission mode, and use single-phase voltage feedback.

[0019] In response to a fault in a single feedback path, such a solution may result in a loss of visibility of the phase voltage input signal. Additionally or alternatively, such a solution may not be able to measure speed in the 6SO operating mode and therefore may not be able to maintain the systems associated with the motor in an appropriate safe operating state.

[0020] Therefore, systems and methods such as those described herein that are configured to provide phase voltage-based motor cycle measurement and controlled signal path fault detection may be desirable. In some embodiments, the systems and methods described herein can be configured to provide a phase voltage-based cycle measurement differential interface that includes HV isolation with relatively high immunity to coupled noise without using (relatively expensive) components. The systems and methods described herein can be configured to provide a functional safety testing method that uses a controller and an application-specific integrated circuit (ASIC) state machine to verify the continuity and integrity of the complete IGBT control and feedback path.

[0021] In some embodiments, the systems and methods described herein can be configured to use a differential capacitive coupling interface that is biased to an intermediate power supply and compared to each other. The systems and methods described herein can be configured to bias and appropriately filter (e.g., using corresponding filter circuits) systems associated with the motor to reject high-frequency interconnect transients and support rejection of high-voltage to low-voltage domain ground interference.

[0022] In some embodiments, the systems and methods described herein can be configured to provide relatively high tolerance to single point failures (SPFs). The systems and methods described herein can be configured to use phase redundancy for cycle measurement by routing the three phases to two ASICs. The systems and methods described herein can be configured to use the motor cycle detection block of the corresponding ASIC. The systems and methods described herein can be configured to use the controller to command alternating 3-phase shorted upper (3PSU) and 3-phase shorted lower (3PSL) patterns with a predetermined cycle. The systems and methods described herein can be configured to compare the patterns with the measured cycle from the ASIC.

[0023] In some embodiments, the systems and methods described herein can be configured to use the controller to control the switching of external IGBTs and measure the period within the ASIC to verify that: the six IGBT gate drive supplies are functioning properly; the IGBT gate drive supplies are functioning properly; the six connections of the IGBTs to the paths are connected correctly; the period measurements are relayed correctly to the controller; the six IGBTs are switched according to controller commands; passive components are correctly connected between the IGBTs and the phase voltage feedback paths; and the phase voltage-based motor period detection block is functioning properly.

[0024] In some embodiments, the systems and methods described herein can be configured to provide a system test of an electric motor that is relatively easy to perform and provides a relatively fast (e.g., 10 milliseconds or other suitable time period) test response (e.g., test response of the entire path and all IGBTs), which can enable relatively rapid entry into mission mode operation. The systems and methods described herein can be configured to enable cycle measurement and fault detection (e.g., using a differential interface topology and redundant phase voltage inputs in conjunction with a controller and ASIC-controlled test sequence) while supporting ASIL D functional safety requirements.

[0025] In some embodiments, the systems and methods described herein can be configured to provide a solution that reduces PCB area and cost. The systems and methods described herein can be configured to accommodate ground domain differential voltages (AC and DC) without the need for isolation amplifiers. The systems and methods described herein can be configured to eliminate the use of HV resistor divider networks and auxiliary microprocessors for cycle measurements. The systems and methods described herein can be configured to provide a controller and ASIC controlled test strategy where the complete IGBT control and feedback paths are controlled, which can provide comprehensive fault coverage before enabling torque.

[0026] In some embodiments, the systems and methods described herein can be configured to generate a commanded phase voltage (e.g., generate a phase voltage by command). The systems and methods described herein can be configured to command the generation of a phase voltage during a command of a self-test operation or during any suitable operation or at any suitable time. The commanded phase voltage may include a three-phase short circuit upper mode and a three-phase short circuit lower mode or other suitable modes. The systems and methods described herein can be configured to apply the commanded phase voltage to a first phase voltage input of the motor, a second phase voltage input of the motor, and a third phase voltage input of the motor. The motor can be associated with a vehicle. However, it should be understood that the motor can be associated with any other suitable application in addition to or in lieu of a vehicle, and the principles of the present invention apply accordingly. The first phase voltage input and the second phase voltage input can be connected to a first differential capacitive coupling interface of a first integrated circuit, and the second phase voltage input and the third phase voltage input can be connected to a second differential capacitive coupling interface of a second integrated circuit. The first integrated circuit can include a first ASIC, and the second integrated circuit can include a second ASIC.

[0027] In some embodiments, the first differential capacitive coupling interface can be biased to an intermediate power supply and can be configured to provide a differential phase voltage input signal to the first integrated circuit based on the first phase voltage input and the second phase voltage input. Additionally or alternatively, the first differential capacitive coupling interface can be configured to reject high-frequency interconnect transients and reject ground interference from the high voltage to the low voltage domain.

[0028] In some embodiments, the second differential capacitive coupling interface can be biased to an intermediate power supply and can be configured to provide a differential phase voltage input signal to the second integrated circuit based on the second phase voltage input and the third voltage input. Additionally or alternatively, the second differential capacitive coupling interface can be configured to reject high-frequency interconnect transients and reject ground interference from the high voltage to the low voltage domain.

[0029] The systems and methods described herein can be configured to measure a first period of a phase voltage associated with a first phase voltage input and a second phase voltage input at an integrated analog comparator of a first integrated circuit. The systems and methods described herein can be configured to compare the first period of the phase voltage associated with the first phase voltage input and the second phase voltage input to a frequency associated with a commanded phase voltage. The systems and methods described herein can be configured to identify a fault associated with at least one of the first integrated circuit and the corresponding signal path in response to determining that the first period of the phase voltage associated with the first phase voltage input and the second phase voltage input is outside a frequency range associated with the commanded phase voltage.

[0030] In some embodiments, the systems and methods described herein can be configured to measure a second period of the phase voltage associated with the second and third phase voltage inputs at an integrated analog comparator of the second integrated circuit. The systems and methods described herein can be configured to compare the second period of the phase voltage associated with the second and third phase voltage inputs to a frequency associated with a commanded phase voltage. The systems and methods described herein can be configured to identify a fault associated with at least one of the second integrated circuit and the corresponding signal path in response to determining that the second period of the phase voltage associated with the second and third phase voltage inputs is outside a frequency range associated with the commanded phase voltage.

[0031] Figure 1 A vehicle 10 in accordance with the principles of the present disclosure is generally shown. The vehicle 10 may include any suitable vehicle, such as a car, a truck, a sport utility vehicle, a minivan, an off-road vehicle, any other passenger vehicle, any suitable commercial vehicle, or any other suitable vehicle. Although the vehicle 10 is shown as a passenger vehicle having wheels and for use on roads, the principles of the present disclosure may be applied to other vehicles, such as aircraft, ships, trains, drones, or other suitable vehicles. The vehicle 10 includes a body 12 and a hood 14. A portion of the body 12 defines a passenger compartment 18. Another portion of the body 12 defines an engine compartment 20. The hood 14 may be movably connected to a portion of the body 12 such that when the hood 14 is in a first or open position, the hood 14 provides access to the engine compartment 20, and when the hood 14 is in a second or closed position, the hood 14 covers the engine compartment 20.

[0032] A passenger compartment 18 is disposed rearward of an engine compartment 20. Vehicle 10 may include any suitable propulsion system, including an internal combustion engine, one or more electric motors (e.g., an electric vehicle), one or more fuel cells, a hybrid propulsion system (e.g., a hybrid vehicle) including a combination of an internal combustion engine, one or more electric motors, and / or any other suitable propulsion system. In some embodiments, vehicle 10 may include a gasoline or gasoline-fueled engine, such as a spark-ignition engine. In some embodiments, vehicle 10 may include a diesel-fueled engine, such as a compression-ignition engine. Engine compartment 20 houses and / or contains at least some components of the propulsion system of vehicle 10. Additionally or alternatively, propulsion controls such as an accelerator actuator (e.g., an accelerator pedal), a brake actuator (e.g., a brake pedal), a steering wheel, and other such components are disposed within the vehicle's passenger compartment 18. The propulsion controls may be actuated or controlled by the driver of vehicle 10 and may each be directly connected to a corresponding component of the propulsion system, such as a throttle, brakes, axles, vehicle transmission, etc. In some embodiments, the propulsion control may transmit signals to a vehicle computer (eg, via ride-by-wire), which in turn may control corresponding propulsion components of the propulsion system.

[0033] In one embodiment, the vehicle 10 includes a transmission that is connected to the crankshaft via a flywheel, a clutch, or a fluid coupling. In some embodiments, the transmission includes a manual transmission. In some embodiments, the transmission includes an automatic transmission. In the case of an internal combustion engine or a hybrid vehicle, the vehicle 10 may include one or more pistons that work in conjunction with the crankshaft to generate force that is transmitted through the transmission to one or more shafts that rotate the wheels 22. When the vehicle 10 includes one or more electric motors, the vehicle battery and / or fuel cell supplies energy to the electric motors to rotate the wheels 22. In the case where the vehicle 10 includes a vehicle battery to provide energy to the one or more electric motors, if the battery is depleted, the battery can be connected to the power grid (e.g., using a wall outlet) to charge the battery cells. Additionally or alternatively, the vehicle 10 can employ regenerative braking, which uses one or more electric motors of the vehicle 10 as a generator to convert kinetic energy lost due to deceleration back into stored energy in the battery.

[0034] Vehicle 10 may include an automatic vehicle propulsion system, such as cruise control, adaptive cruise control, automatic braking control, other automatic vehicle propulsion systems, or combinations thereof. Vehicle 10 may be an autonomous or semi-autonomous driving vehicle, or other suitable type of vehicle. Vehicle 10 may include more or fewer features than generally shown and / or disclosed herein.

[0035] In some embodiments, the vehicle 10 may include a controller, such as controller 100, as shown in FIG. Figure 2. The controller 100 may include any suitable controller, such as an electronic control unit or other suitable controller. The controller 100 may be configured to control various functions of the steering system and / or various functions of the vehicle 10, for example. The controller 100 may include a processor 102 and a memory 104. The processor 102 may include any suitable processor, such as those described herein. Additionally or alternatively, the controller 100 may include any suitable number of processors in addition to the processor 102. The memory 104 may include a single disk or multiple disks (e.g., a hard drive) and include a storage management module that manages one or more partitions within the memory 104. In some embodiments, the memory 104 may include flash memory, semiconductor (solid-state) memory, etc. The memory 104 may include random access memory (RAM), read-only memory (ROM), or a combination thereof. The memory 104 may include instructions that, when executed by the processor 102, cause the processor 102 to control at least various aspects of the vehicle 10.

[0036] In some embodiments, the controller 100 can be configured to provide phase voltage-based motor cycle measurement and controlled signal path fault detection. For the inspector, the controller 100 can interact with the circuit 200 and / or control various aspects of the circuit 200. The circuit 200 may include a first differential capacitive coupling interface 202 (e.g., may be referred to herein as the first interface 202) and a second differential capacitive coupling interface 204 (e.g., may be referred to herein as the second interface 204). The first interface 202 may be biased to an intermediate power supply. The first interface 202 may include internal and / or external filtering blocks. The second interface 204 may be biased to an intermediate power supply. The second interface 204 may include internal and / or external filtering blocks. Each of the first interface 202 and the second interface 204 may include various electrical components, such as capacitors, resistors, inductors, etc. The first interface 202 and the second interface 204 may be in electrical communication with one or more power supplies. The controller 100 may utilize one or more power supplies.

[0037] In some embodiments, the first interface 202 can be configured to provide a differential phase voltage input signal to the first integrated circuit 206. Additionally or alternatively, the second interface 204 can be configured to provide a differential phase voltage input signal to the second integrated circuit 208. The differential phase voltage input signal interface can provide relatively high noise immunity.

[0038] In some embodiments, the circuit 200 can include an inverter system that routes phase voltage inputs of the motor 210 to the first integrated circuit 206 and the second integrated circuit 208, respectively. For example, the inverter system can route a first phase voltage input (e.g., illustrated as VOL_PH1) and a second phase voltage input (e.g., illustrated as VOL_PH2_1) to the first integrated circuit 206. Additionally or alternatively, the inverter system can route a second phase voltage input (e.g., illustrated as VOL_PH2_2) and a third phase voltage input (e.g., illustrated as VOL_PH3) to the second integrated circuit 208. It should be understood that the inverter can route any combination of the first phase voltage input, the second phase voltage input, and the third phase voltage input to either the first integrated circuit 206 or the second integrated circuit 208.

[0039] In some embodiments, each of the first integrated circuit 206 and the second integrated circuit 208 may use a different pair of phase voltage inputs to ensure redundancy in period measurement of the motor 210 during 6SO, which may provide enhanced tolerance to single point failures.

[0040] In some embodiments, the controller 100 and / or circuit 200 can be configured to test and verify the complete IGBT control (eg, including all six IGBT switches 220) and feedback signal paths (eg, Figure 3A and Figure 3B ) are connected and function according to various operating specifications. For example, during a power-up / initialization self-test operation (e.g., or other suitable operation), the controller 100 can command the 3PSU and 3PSL at a predetermined frequency. The frequency can include any suitable frequency, including but not limited to a frequency up to 20 kHz. In some embodiments, the frequency can include a 10 kHz frequency or other suitable frequency.

[0041] In some embodiments, the integrated analog comparator and self-test block 212 of the first integrated circuit 206 can alternately monitor one of the phase voltage inputs (e.g., the first phase voltage input and the second phase voltage input) and compare the monitored phase voltage input to the intermediate power supply. The digital block 214 can measure the period associated with the monitored phase voltage input. Additionally or alternatively, the integrated analog comparator and self-test block 216 of the second integrated circuit 208 can alternately monitor one of the phase voltage inputs (e.g., the second phase voltage input and the third phase voltage input) and compare the monitored phase voltage input to the intermediate power supply. The digital block 218 can measure the period associated with the monitored phase voltage input. This can provide testability of two phase voltage signal paths for each of the first integrated circuit 206 and the second integrated circuit 208 (e.g., all three phase voltage input signal paths in the circuit 200) by performing a single test.

[0042] In some embodiments, the controller 100 can read the measured period via a serial peripheral interface (SPI) or other suitable interface.The controller 100 can compare the measured period to a frequency associated with the commanded frequency.

[0043] In some embodiments, a state machine associated with the circuit 200 can manage the testing process. In some embodiments, the controller 100 and / or the circuit 200 can support rejection of high-voltage to low-voltage domain ground interference. The controller 100 and / or the circuit 200 can increase fault coverage for the phases of the motor 210 (e.g., the first integrated circuit 206 and the second integrated circuit 208 cover all three phases).

[0044] In some embodiments, the first integrated circuit 206 may include an integrated auxiliary cycle counter and averaging block 226 that provides a measurement of the average motor cycle for a user-selectable number of readings. The controller 100 may use the average motor cycle as a measured period to compare with the commanded frequency to identify a fault in the first integrated circuit 206.

[0045] In some embodiments, the second integrated circuit 208 can include an integrated auxiliary cycle counter and averaging block 228 that provides a measurement of the average motor cycle for a user-selectable number of readings. The controller 100 can use the average motor cycle as a measured period to compare with the commanded frequency to identify a fault in the second integrated circuit 208.

[0046] In some embodiments, the controller 100 can be configured to command the generation of phase voltages. The controller 100 can generate the commanded phase voltages during a power-up / initialization self-test operation of the circuit 200 or other appropriate components of the vehicle 10. Additionally or alternatively, the controller 100 can generate the commanded phase voltages during any appropriate operation or at any appropriate time. The commanded phase voltages can include a three-phase short-circuit upper mode and a three-phase short-circuit lower mode, or other suitable modes.

[0047] The controller 100 may apply the commanded phase voltages to a first phase voltage input of the electric motor 210 (e.g., may be referred to as a motor), a second phase voltage input of the electric motor 210, and a third phase voltage input of the electric motor 210. As described above, the electric motor 210 may be associated with the vehicle 10. However, it should be understood that the electric motor 210 may be associated with any other suitable application in addition to or in lieu of the vehicle 10, and the principles of the present disclosure apply accordingly.

[0048] As described above, the first phase voltage input and the second phase voltage input can be connected to the first interface 202, and the second phase voltage input and the third phase voltage input can be connected to the second interface 204. The first interface 202 can be biased to an intermediate power supply and can be configured to provide a differential phase voltage input signal based on the first phase voltage input and the second phase voltage input to the first integrated circuit 206. Additionally or alternatively, the first interface 202 can be configured to reject high-frequency interconnect transients and reject ground interference from the high voltage to the low voltage domain.

[0049] In some embodiments, the second interface 204 can be biased to an intermediate power supply and can be configured to provide a differential phase voltage input signal based on the second phase voltage input and the third voltage input to the second integrated circuit 208. Additionally or alternatively, the second interface 204 can be configured to reject high-frequency interconnect transients and reject ground interference from the high voltage to the low voltage domain.

[0050] The controller 100 can measure a first period of the phase voltage associated with the first and second phase voltage inputs at the integrated analog comparator and self-test block 212 of the first integrated circuit 206. The controller 100 can compare the first period of the phase voltage associated with the first and second phase voltage inputs to a frequency associated with the commanded phase voltage. The controller 100 can determine whether the first period is within a range of the commanded frequency. The range can be any suitable range, such as plus or minus 1%, plus or minus one unit of the commanded frequency, or other suitable range.

[0051] If the controller 100 determines that the first period is outside the range of the commanded frequency, the controller 100 can identify a fault associated with the first integrated circuit 206 and / or the corresponding signal path. For example, the controller 100 can determine that the fault occurs in the first integrated circuit 206 and can identify the fault or faulty component based on a comparison of the first period and the commanded frequency. The controller 100 can place the circuit 200 in a safe operating state, such as any of the safe operating states described herein, in response to determining that a fault has occurred in the first integrated circuit 206. Alternatively, if the controller 100 determines that the first period is within the range of the commanded frequency, the controller 100 determines that the first integrated circuit 206 is not faulty.

[0052] In some embodiments, the controller 100 can measure a second period of the phase voltage associated with the second and third phase voltage inputs at the integrated analog comparator and self-test block 216 of the second integrated circuit 208. The controller 100 can compare the second period of the phase voltage associated with the second and third phase voltage inputs to a frequency associated with the commanded phase voltage. The controller 100 can determine whether the second period is within the range of the commanded frequency.

[0053] If the controller 100 determines that the second period is outside the range of the commanded frequency, the controller 100 can identify a fault associated with the second integrated circuit 208 and / or the corresponding signal path. For example, the controller 100 can determine that a fault has occurred in the second integrated circuit 208 and can identify the fault or faulty component based on a comparison between the second period and the commanded frequency. In response to determining that a fault has occurred in the second integrated circuit 208, the controller 100 can place the circuit 200 in a safe operating state, such as any of the safe operating states described herein. Alternatively, if the controller 100 determines that the second period is within the range of the commanded frequency, the controller 100 determines that the second integrated circuit 208 and / or the corresponding signal path are not faulty.

[0054] In some embodiments, the controller 100 and / or circuit 200 can perform the methods described herein. However, the methods described herein as being performed by the controller 100 and / or circuit 200 are not meant to be limiting, and any type of software executed on a controller or processor can perform the methods described herein without departing from the scope of the present disclosure. For example, a controller such as a processor executing software within a computing device can perform the methods described herein.

[0055] Figure 4 4 is a flow chart generally illustrating a method 400 for motor period measurement based on phase voltage according to the principles of the present disclosure. At 402, the method 400 generates a commanded phase voltage. For example, the controller 100 may generate the commanded phase voltage.

[0056] At 404, method 400 applies the commanded phase voltage to a first phase voltage input of the motor, a second phase voltage input of the motor, and a third phase voltage input of the motor. The first phase voltage input and the second phase voltage input can be connected to a first differential capacitive coupling interface of a first integrated circuit, and the second phase voltage input and the third phase voltage input can be connected to a second differential capacitive coupling interface of a second integrated circuit. For example, controller 100 can apply the commanded phase voltage to the first phase voltage input, the second phase voltage input, and the third phase voltage input.

[0057] At 406 , method 400 measures a first period of a phase voltage associated with the first and second phase voltage inputs at an integrated analog comparator of the first integrated circuit. For example, the integrated analog comparator and self-test block 212 of the first integrated circuit 206 can measure the first period.

[0058] At 408 , the method 400 compares a first period of the phase voltage associated with the first and second phase voltage inputs to a frequency associated with the commanded phase voltage. For example, the controller 100 may compare the first period to the commanded frequency.

[0059] At 410, in response to determining that a first cycle of a phase voltage associated with the first phase voltage input and the second phase voltage input is outside a frequency range associated with the commanded phase voltage, the method 400 identifies a fault associated with the first integrated circuit. For example, in response to determining that the first cycle is outside a commanded frequency range, the controller identifies a fault in the first integrated circuit 206 and / or a corresponding signal path. As described above, the controller 100 can identify a fault in the second integrated circuit 208 and / or a corresponding signal path.

[0060] In some embodiments, a method for phase voltage-based motor period measurement includes generating a commanded phase voltage and applying the commanded phase voltage to a first phase voltage input of a motor, a second phase voltage input of the motor, and a third phase voltage input of the motor. The first phase voltage input and the second phase voltage input can be connected to a first differential capacitive coupling interface of a first integrated circuit, and the second phase voltage input and the third phase voltage input can be connected to a second differential capacitive coupling interface of a second integrated circuit. The method also includes measuring a first period of the phase voltage associated with the first phase voltage input and the second phase voltage input at an integrated analog comparator of the first integrated circuit, and comparing the first period of the phase voltage associated with the first phase voltage input and the second phase voltage input to a frequency associated with the commanded phase voltage. The method also includes identifying a fault associated with at least one of the first integrated circuit and the corresponding signal path in response to determining that the first period of the phase voltage associated with the first phase voltage input and the second phase voltage input is outside a frequency range associated with the commanded phase voltage.

[0061] In some embodiments, the method further includes measuring, at an integrated analog comparator of the second integrated circuit, a second period of the phase voltage associated with the second and third phase voltage inputs, comparing the second period of the phase voltage associated with the second and third phase voltage inputs to a frequency associated with the commanded phase voltage, and identifying a fault associated with at least one of the second integrated circuit and the corresponding signal path in response to determining that the second period of the phase voltage associated with the second and third phase voltage inputs is outside a frequency range associated with the commanded phase voltage. In some embodiments, the first differential capacitive coupling interface is biased to an intermediate power supply and configured to provide a differential phase voltage input signal to the first integrated circuit based on the first and second phase voltage inputs. In some embodiments, the first differential capacitive coupling interface is further configured to reject high-frequency interconnect transients and reject ground interference from a high voltage to a low voltage domain. In some embodiments, the second differential capacitive coupling interface is biased to an intermediate power supply and configured to provide a differential phase voltage input signal to the second integrated circuit based on the second and third phase voltage inputs. In some embodiments, the second differential capacitive coupling interface is further configured to reject high-frequency interconnect transients and reject ground interference from the high voltage to the low voltage domain. In some embodiments, the electric motor is associated with a vehicle. In some embodiments, generating the commanded phase voltages includes generating the commanded phase voltages during a commanded self-test operation. In some embodiments, the commanded phase voltages include a three-phase short-circuit upper mode and a three-phase short-circuit lower mode. In some embodiments, the first integrated circuit includes a first application-specific integrated circuit, and the second integrated circuit includes a second application-specific integrated circuit.

[0062] In some embodiments, a system for phase voltage-based motor period measurement includes a processor and a memory. The memory includes instructions that, when executed by the processor, cause the processor to: generate a commanded phase voltage; apply the commanded phase voltage to a first phase voltage input of a motor, a second phase voltage input of the motor, and a third phase voltage input of the motor, the first phase voltage input and the second phase voltage input being connected to a first differential capacitive coupling interface of a first integrated circuit, and the second phase voltage input and the third phase voltage input being connected to a second differential capacitive coupling interface of a second integrated circuit; measure a first period of the phase voltage associated with the first phase voltage input and the second phase voltage input at an integrated analog comparator of the first integrated circuit; compare the first period of the phase voltage associated with the first phase voltage input and the second phase voltage input to a frequency associated with the commanded phase voltage; and in response to determining that the first period of the phase voltage associated with the first phase voltage input and the second phase voltage input is outside a frequency range associated with the commanded phase voltage, identify a fault associated with at least one of the first integrated circuit and a corresponding signal path.

[0063] In some embodiments, the instructions further cause the processor to measure, at an integrated analog comparator of the second integrated circuit, a second period of the phase voltage associated with the second and third phase voltage inputs, compare the second period of the phase voltage associated with the second and third phase voltage inputs to a frequency associated with a commanded phase voltage, and, in response to determining that the second period of the phase voltage associated with the second and third phase voltage inputs is outside a frequency range associated with the commanded phase voltage, identify a fault associated with at least one of the second integrated circuit and the corresponding signal path. In some embodiments, the first differential capacitive coupling interface is biased to an intermediate power supply, and wherein the first differential capacitive coupling interface is configured to provide a differential phase voltage input signal to the first integrated circuit based on the first and second phase voltage inputs. In some embodiments, the first differential capacitive coupling interface is further configured to reject high-frequency interconnect transients and reject high-voltage to low-voltage domain ground interference. In some embodiments, the second differential capacitive coupling interface is biased to an intermediate power supply, and wherein the second differential capacitive coupling interface is configured to provide a differential phase voltage input signal to the second integrated circuit based on the second and third phase voltage inputs. In some embodiments, the second differential capacitive coupling interface is further configured to reject high-frequency interconnect transients and reject ground interference from the high voltage to the low voltage domain. In some embodiments, the electric motor is associated with a vehicle. In some embodiments, the instructions further cause the processor to generate commanded phase voltages during a commanded self-test operation. In some embodiments, the commanded phase voltages include a three-phase short-circuit upper mode and a three-phase short-circuit lower mode.

[0064] In some embodiments, a device for motor cycle measurement based on phase voltage. The device includes a processor and a memory. The memory includes instructions that, when executed by the processor, cause the processor to perform the following operations: generate a commanded phase voltage during a command of a self-test operation; apply the commanded phase voltage to a first phase voltage input of the motor, a second phase voltage input of the motor, and a third phase voltage input of the motor, the first phase voltage input and the second phase voltage input being connected to a first differential capacitive coupling interface of a first integrated circuit, and the second phase voltage input and the third phase voltage input being connected to a second differential capacitive coupling interface of a second integrated circuit; measure a first cycle of the phase voltage associated with the first phase voltage input and the second phase voltage input at an integrated analog comparator of the first integrated circuit; compare the first cycle of the phase voltage associated with the first phase voltage input and the second phase voltage input with a frequency associated with the commanded phase voltage; row comparison; in response to determining that the first cycle of the phase voltage associated with the first phase voltage input and the second phase voltage input is outside the frequency range associated with the commanded phase voltage, identifying a fault associated with at least one of the first integrated circuit and the corresponding signal path; measuring the second cycle of the phase voltage associated with the second phase voltage input and the third phase voltage input at the integrated analog comparator of the second integrated circuit; comparing the second cycle of the phase voltage associated with the second phase voltage input and the third phase voltage input with the frequency associated with the commanded phase voltage; and in response to determining that the second cycle of the phase voltage associated with the second phase voltage input and the third phase voltage input is outside the frequency range associated with the commanded phase voltage, identifying a fault associated with the second integrated circuit and at least one of the corresponding signal path.

[0065] The above discussion is intended to illustrate the principles and various embodiments of the present disclosure. Once the above disclosure is fully understood, many changes and modifications will become apparent to those skilled in the art.

[0066] The word "example" is used herein to mean serving as an example, instance, or illustration. Any aspect or design described herein as an "example" is not necessarily to be construed as being preferred or advantageous over other aspects or designs. On the contrary, the use of the word "example" is intended to present concepts in a concrete manner. As used in this application, the term "or" is intended to mean an inclusive "or" rather than an exclusive "or." That is, unless otherwise stated or clear from the context, "X includes A or B" is intended to mean any natural inclusive permutation. That is, if X includes A; X includes B; or X includes both A and B, then "X includes A or B" satisfies any of the foregoing circumstances. In addition, the articles "a" and "an" used in this application should generally be interpreted to mean "one or more" unless otherwise stated or clear from the context to indicate a singular form. In addition, the use of the terms "implementation" or "an implementation" throughout the text is not intended to mean the same embodiment or implementation unless described as such.

[0067] Implementations of the systems, algorithms, methods, instructions, and the like described herein may be implemented using hardware, software, or any combination thereof. The hardware may include, for example, a computer, an intellectual property (IP) core, an application specific integrated circuit (ASIC), a programmable logic array, an optical processor, a programmable logic controller, microcode, a microcontroller, a server, a microprocessor, a digital signal processor, or any other suitable circuitry. The term "processor" should be understood to include any of the foregoing hardware, either individually or in combination. The terms "signal" and "data" may be used interchangeably.

[0068] As used herein, the term module can include a packaged functional hardware unit designed for use with other components, a set of instructions executable by a controller (e.g., a processor executing software or firmware), processing circuitry configured to perform specific functions, and independent hardware or software components that interface with a larger system. For example, a module can include an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), an electrical circuit, a digital logic circuit, an analog circuit, a combination of discrete circuits, gates, and other types of hardware, or a combination thereof. In other embodiments, a module can include a memory that stores instructions that can be executed by a controller to implement the features of the module.

[0069] Furthermore, in one aspect, for example, a general-purpose computer or general-purpose processor with a computer program that, when executed, performs any of the corresponding methods, algorithms, and / or instructions described herein can be used to implement the systems described herein. Additionally or alternatively, for example, a special-purpose computer / processor can be used, which can include other hardware for executing any method, algorithm, or instruction described herein.

[0070] Furthermore, all or part of the implementation of the present disclosure may take the form of a computer program product accessible from, for example, a computer-usable or computer-readable medium. A computer-usable or computer-readable medium can be any device capable of, for example, tangibly containing, storing, communicating, or transmitting a program for use by or in conjunction with any processor. The medium can be, for example, an electronic, magnetic, optical, electromagnetic, or semiconductor device. Other suitable media are also possible.

[0071] The above embodiments, implementations, and aspects have been described to allow easy understanding of the present disclosure without limiting the present disclosure. On the contrary, the present disclosure is intended to cover various modifications and equivalent arrangements, the scope of which is consistent with the broadest interpretation to include all such modifications and equivalent structures permitted by law.

Claims

1. A method for measuring a motor cycle based on phase voltage, the method comprising the following steps: Generate commanded phase voltage; applying the commanded phase voltage to a first phase voltage input of a motor, a second phase voltage input of the motor, and a third phase voltage input of the motor, the first phase voltage input and the second phase voltage input being connected to a first differential capacitive coupling interface of a first integrated circuit, and the second phase voltage input and the third phase voltage input being connected to a second differential capacitive coupling interface of a second integrated circuit; measuring, at an integrated analog comparator of the first integrated circuit, a first cycle of a phase voltage associated with the first phase voltage input and the second phase voltage input; comparing the first period of the phase voltage associated with the first phase voltage input and the second phase voltage input to a frequency associated with the commanded phase voltage; identifying a fault associated with at least one of the first integrated circuit and a corresponding signal path in response to determining that the first cycle of the phase voltage associated with the first and second phase voltage inputs is outside a frequency range associated with a commanded phase voltage, measuring, at an integrated analog comparator of the second integrated circuit, a second cycle of a phase voltage associated with the second phase voltage input and the third phase voltage input; comparing the second period of the phase voltage associated with the second phase voltage input and the third phase voltage input to a frequency associated with the commanded phase voltage; as well as In response to determining that the second cycle of the phase voltage associated with the second and third phase voltage inputs is outside a frequency range associated with the commanded phase voltage, a fault associated with at least one of the second integrated circuit and the corresponding signal path is identified.

2. The method according to claim 1, wherein The first differential capacitive coupling interface is biased to an intermediate power supply, and wherein the first differential capacitive coupling interface is configured to provide a differential phase voltage input signal to the first integrated circuit based on the first phase voltage input and the second phase voltage input.

3. The method according to claim 2, wherein: The first differential capacitive coupling interface is further configured as: Rejection of high-frequency interconnect transients; and Reject high voltage to low voltage domain ground interference.

4. The method according to claim 1, wherein The second differential capacitive coupling interface is biased to an intermediate power supply, and wherein the second differential capacitive coupling interface is configured to provide a differential phase voltage input signal to the second integrated circuit based on the second phase voltage input and the third phase voltage input.

5. The method according to claim 4, wherein The second differential capacitive coupling interface is further configured as: Rejection of high-frequency interconnect transients; and Reject high voltage to low voltage domain ground interference.

6. The method according to claim 1, wherein The electric motor is associated with a vehicle.

7. The method according to claim 1, wherein Generating the commanded phase voltages includes generating the commanded phase voltages during a commanded self-test operation.

8. The method according to claim 1, wherein The commanded phase voltages include a three-phase short circuit upper mode and a three-phase short circuit lower mode.

9. The method according to claim 1, wherein The first integrated circuit comprises a first application specific integrated circuit, and wherein the second integrated circuit comprises a second application specific integrated circuit.

10. A system for motor period measurement based on phase voltage, the system comprising: processor; as well as a memory comprising instructions that, when executed by the processor, cause the processor to: Generate commanded phase voltage; applying the commanded phase voltage to a first phase voltage input of a motor, a second phase voltage input of the motor, and a third phase voltage input of the motor, the first phase voltage input and the second phase voltage input being connected to a first differential capacitive coupling interface of a first integrated circuit, and the second phase voltage input and the third phase voltage input being connected to a second differential capacitive coupling interface of a second integrated circuit; measuring, at an integrated analog comparator of the first integrated circuit, a first cycle of a phase voltage associated with the first phase voltage input and the second phase voltage input; comparing the first period of the phase voltage associated with the first phase voltage input and the second phase voltage input to a frequency associated with the commanded phase voltage; identifying a fault associated with at least one of the first integrated circuit and a corresponding signal path in response to determining that the first cycle of the phase voltage associated with the first and second phase voltage inputs is outside a frequency range associated with a commanded phase voltage, measuring, at an integrated analog comparator of the second integrated circuit, a second cycle of a phase voltage associated with the second phase voltage input and the third phase voltage input; comparing the second period of the phase voltage associated with the second phase voltage input and the third phase voltage input to a frequency associated with the commanded phase voltage; as well as In response to determining that the second cycle of the phase voltage associated with the second and third phase voltage inputs is outside a frequency range associated with the commanded phase voltage, a fault associated with at least one of the second integrated circuit and the corresponding signal path is identified.

11. The system according to claim 10, wherein: The first differential capacitive coupling interface is biased to an intermediate power supply, and wherein the first differential capacitive coupling interface is configured to provide a differential phase voltage input signal to the first integrated circuit based on the first phase voltage input and the second phase voltage input.

12. The system according to claim 11, wherein The first differential capacitive coupling interface is further configured to: Rejection of high-frequency interconnect transients; and Reject high voltage to low voltage domain ground interference.

13. The system according to claim 10, wherein: The second differential capacitive coupling interface is biased to an intermediate power supply, and wherein the second differential capacitive coupling interface is configured to provide a differential phase voltage input signal to the second integrated circuit based on the second phase voltage input and the third phase voltage input.

14. The system according to claim 13, wherein: The second differential capacitive coupling interface is further configured to: Rejection of high-frequency interconnect transients; and Reject high voltage to low voltage domain ground interference.

15. The system according to claim 10, wherein: The electric motor is associated with a vehicle.

16. The system according to claim 10, wherein: The instructions further cause the processor to generate the commanded phase voltages during the command of the self-test operation.

17. The system according to claim 10, wherein: The commanded phase voltages include a three-phase short circuit upper mode and a three-phase short circuit lower mode.

18. A device for motor cycle measurement based on phase voltage, the device comprising: processor; as well as a memory comprising instructions that, when executed by the processor, cause the processor to: generating a commanded phase voltage during a command of a self-test operation; applying the commanded phase voltage to a first phase voltage input of a motor, a second phase voltage input of the motor, and a third phase voltage input of the motor, the first phase voltage input and the second phase voltage input being connected to a first differential capacitive coupling interface of a first integrated circuit, and the second phase voltage input and the third phase voltage input being connected to a second differential capacitive coupling interface of a second integrated circuit; measuring, at an integrated analog comparator of the first integrated circuit, a first cycle of a phase voltage associated with the first phase voltage input and the second phase voltage input; comparing the first period of the phase voltage associated with the first phase voltage input and the second phase voltage input to a frequency associated with the commanded phase voltage; identifying a fault associated with at least one of the first integrated circuit and a corresponding signal path in response to determining that the first cycle of the phase voltage associated with the first and second phase voltage inputs is outside a frequency range associated with a commanded phase voltage; measuring, at an integrated analog comparator of the second integrated circuit, a second cycle of a phase voltage associated with the second phase voltage input and the third phase voltage input; comparing the second period of the phase voltage associated with the second phase voltage input and the third phase voltage input to a frequency associated with the commanded phase voltage; as well as In response to determining that the second cycle of the phase voltage associated with the second and third phase voltage inputs is outside a frequency range associated with the commanded phase voltage, a fault associated with at least one of the second integrated circuit and the corresponding signal path is identified.

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