Computing devices, methods of operation, and machine readable storage media

Abstract

This invention provides a computing device, an operating method, and a machine-readable storage medium. In an embodiment of the invention, the operating method includes: checking data type information carried by a current instruction, wherein the data type information indicates the data type of the target operand corresponding to the current instruction; when the data type information indicates that the data type of the target operand is an adaptive data type, reading metadata corresponding to the target operand to obtain the actual data type of the target operand from the metadata; and executing the current instruction to process the target operand based on the actual data type of the target operand recorded in the metadata.

Description

Technical Field

[0001] This invention relates to an instruction set, and more particularly to a computing device, a method of operation, and a machine-readable storage medium. Background Technology

[0002] Generally, when writing a computational program, the writer knows the data type of the operands. Therefore, the writer can include instructions with "specified (fixed) data type" information in the program, and then use a compiler to compile the program. For example, a computational program might include a load instruction with the information "32-bit floating-point number" (fixed data type) to load an operand of data type "32-bit floating-point number" from memory into the computational core (e.g., a tensor core). Alternatively, a computational program might include matrix multiplication and accumulation (MMA) instructions with the information "32-bit floating-point number" (fixed data type) to allow the computational core to perform matrix multiplication on two loaded "32-bit floating-point number" operands. However, in some cases, the data type of the operands may be undefined at compile time (data type unknown). For example, the data type of the computation result of the hidden layer in a Convolutional Neural Network (CNN) algorithm may be dynamically determined only after the actual computation is performed. However, current instruction sets do not support "uncertain data types". Summary of the Invention

[0003] This invention provides a computing device and its operating method, as well as a machine-readable storage medium to support adaptive data types. Adaptive data types mean that the data type is unknown at compile time.

[0004] In an embodiment of the present invention, the operation method includes: checking the data type information carried by the current instruction, wherein the data type information indicates the data type of the target operand corresponding to the current instruction; when the data type information indicates that the data type of the target operand is an adaptive data type, reading the metadata corresponding to the target operand to obtain the actual data type of the target operand from the metadata, or directly obtaining the actual data type of the target operand; and executing the current instruction to process the target operand based on the actual data type of the target operand recorded in the metadata.

[0005] In an embodiment of the invention, the machine-readable storage medium is used to store non-transitory machine-readable instructions. When the non-transitory machine-readable instructions are executed by a computer, the operation method of the computing device can be implemented.

[0006] In an embodiment of the present invention, the computing device includes memory and a processing core. The memory stores target operands. The processing core is coupled to the memory. The processing core checks the data type information carried by the current instruction, wherein the data type information indicates the data type of the target operand corresponding to the current instruction. When the data type information indicates that the data type of the target operand is an adaptive data type, the processing core reads the metadata corresponding to the target operand to obtain the actual data type of the target operand from the metadata, or directly obtains the actual data type of the target operand. Based on the actual data type of the target operand recorded in the metadata, the processing core executes the current instruction to process the target operand.

[0007] Based on the above, the arithmetic core can check the data type information inherent in the current instruction to determine whether the data type of the target operand corresponding to the current instruction is a fixed (specified) data type or an adaptive data type. A fixed data type means that the data type of the target operand is known at compile time. An adaptive data type means that the data type of the target operand is unknown at compile time but is dynamically determined during program execution. During program execution, the actual data type of the target operand is recorded in the metadata corresponding to the target operand. Before executing the current instruction, the arithmetic core checks the data type of the target operand of the current instruction. When the data type of the target operand is an adaptive data type, the arithmetic core can obtain the actual data type of the target operand from the metadata corresponding to the target operand, or directly obtain the actual data type of the target operand. Based on the actual data type of the target operand recorded in the metadata, the arithmetic core can correctly execute the current instruction to process the target operand. Attached Figure Description

[0008] Figure 1 This is a schematic diagram of a circuit block of a computing device according to an embodiment of the present invention.

[0009] Figure 2 This is a flowchart illustrating an operation method of a computing device according to an embodiment of the present invention.

[0010] Figure 3 This is a circuit block diagram of the computation core, drawn according to an embodiment of the present invention.

[0011] Figure 4 This is a circuit block diagram of the computation core, drawn according to another embodiment of the present invention.

[0012] Explanation of reference numerals in the attached figures

[0013] 100: Computing device

[0014] 110: Memory

[0015] 120: Processing core

[0016] 121: Operational Circuit

[0017] 122, 126: Operand buffers

[0018] 123: Conversion Unit

[0019] 124: Loading Unit

[0020] 125: Status Register

[0021] Dconv: Operand

[0022] Dm: Metadata

[0023] Dorig: Calculation Results

[0024] S210~S250: Steps

[0025] ST: Statistical Results Detailed Implementation

[0026] Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same component reference numerals are used in the drawings and description to denote the same or similar parts.

[0027] The term "coupled (or connected)" as used throughout this specification (including the claims) may refer to any direct or indirect means of connection. For example, if the text describes a first device coupled (or connected) to a second device, it should be interpreted as the first device being directly connected to the second device, or the first device being indirectly connected to the second device through other devices or some means of connection. The terms "first," "second," etc., used throughout this specification (including the claims) are used to name components, and are not intended to limit the upper or lower limit of the number of components, nor to limit the order of components. Furthermore, wherever possible, components / components / steps using the same reference numerals in the drawings and embodiments represent the same or similar parts. Components / components / steps using the same reference numerals or the same terms in different embodiments may be referred to mutually in the relevant descriptions.

[0028] Figure 1 This is a schematic diagram of a circuit block of a computing device 100 according to an embodiment of the present invention. Figure 1The computing device 100 shown includes a memory 110 and a processing core 120. The memory 110 is used to store operands. This embodiment does not limit the specific data structure of the operands. For example, in neural network applications, operands can be vectors, tensors, or other data. Depending on the actual design, an operand can be a matrix or any one of multiple blocks of a matrix. The size of the matrix and the size of the block can be determined according to the actual design. For example, in some applications, the size of a block (operand) can be 32*32, 64*64, or other sizes.

[0029] The computation core 120 is coupled to memory 110. In different application examples, the computation core 120 includes a tensor core, a general matrix multiply (GEMM) core, an arithmetic logic unit (ALU), and / or other computation units. Depending on different design requirements, in some embodiments, the computation core 120 can be implemented as hardware circuitry. In other embodiments, the computation core 120 can be implemented as firmware, software (i.e., a program), or a combination of both. In still other embodiments, the computation core 120 can be implemented as a combination of hardware, firmware, and software.

[0030] In hardware terms, the aforementioned processing core 120 can be implemented as logic circuits on an integrated circuit. For example, the functions of the processing core 120 can be implemented as various logic blocks, modules, and circuits in one or more controllers, microcontrollers, microprocessors, application-specific integrated circuits (ASICs), digital signal processors (DSPs), field-programmable gate arrays (FPGAs), and / or other processing units. The functions of the processing core 120 can be implemented as hardware circuits, such as various logic blocks, modules, and circuits in an integrated circuit, using hardware description languages ​​(such as Verilog HDL or VHDL) or other suitable programming languages.

[0031] In software and / or firmware form, the functions of the aforementioned processing core 120 can be implemented as programming codes. For example, the processing core 120 can be implemented using general programming languages ​​(such as C, C++, or assembly language) or other suitable programming languages. The programming code can be recorded / stored in a non-transitory machine-readable storage medium. In some embodiments, the machine-readable storage medium includes, for example, semiconductor memory and / or a storage device. The semiconductor memory includes a memory card, read-only memory (ROM), flash memory, programmable logic circuitry, or other semiconductor memory. The storage device includes a tape, disk, hard disk drive (HDD), solid-state drive (SSD), or other storage device. An electronic device (e.g., a computer, central processing unit (CPU), controller, microcontroller, or microprocessor) can read and execute the programming code from the machine-readable storage medium to implement the functions of the processing core 120. Alternatively, the programming code may be provided to the electronic device via any transmission medium (such as a communication network or broadcast radio waves). The communication network may be, for example, the Internet, a wired communication network, a wireless communication network, or other communication media.

[0032] Figure 2 This is a flowchart illustrating an operation method of a computing device according to an embodiment of the present invention. In some embodiments, Figure 2 The operation of the computing device shown can be implemented in firmware or software (i.e., programs). For example, Figure 2 The operations of the illustrated computing device can be implemented as non-transitory machine-readable instructions (programming code or program), which can be stored in a machine-readable storage medium. When the non-transitory machine-readable instructions are executed by a computer, they can be implemented... Figure 2 The illustrated method of operating the computing device. In other embodiments, Figure 2 The operation method of the computing device shown can be implemented in hardware, for example, implemented in... Figure 1 The computing device 100 shown.

[0033] The processing core 120 can fetch instructions (hereinafter referred to as the current instruction) from memory 110. For example, the processing core 120 can fetch load instructions, matrix multiply and accumulation (MMA) instructions, or other instructions from memory 110. Generally, assuming the current instruction is used to process one or more operands, this current instruction carries the data type information of the one or more operands. The data type information indicates the data type of the target operand corresponding to the current instruction. Assuming the data type is known at compile time, the data type information represents any "fixed (specified) data type". For example, depending on the specific application, the fixed data type can be a 4-bit signed integer (s4), an 8-bit signed integer (s8), an 8-bit unsigned integer (u8), an 8-bit floating-point number (f8), an 8-bit brain float (bf8), a 16-bit signed integer (s16), a standard 16-bit floating-point number (f16), a 16-bit brain float (bf16), a standard 32-bit floating-point number (f32), a 32-bit fast floating-point number (ff32), or a floating-point number of more than 32 bits (f32+). Furthermore, depending on the specific application, the operand can be a scalar, vector, matrix, tensor, or other operands. For example, in neural network applications, based on the actual design, the operand can be any one of multiple blocks obtained by partitioning a matrix. The size of the matrix and the size of the block can be determined according to the actual design. For example, in some applications, the size of a block (operand) can be 32*32, 64*64, or other sizes.

[0034] In some cases, the data type of the target operand corresponding to the instruction may be uncertain at compile time (the data type is temporarily unknown). For example, the data type of the computation result of the hidden layer in a Convolutional Neural Network (CNN) program may be dynamically determined only after the actual computation is performed. The instruction set of this embodiment can support "uncertain data types," that is, adaptive data types. The adaptive data type means that the data type of the target operand is unknown (uncertain) at compile time, but is dynamically determined at actual execution.

[0035] Please refer to Figure 1 and Figure 2In step S210, the computation core 120 can check the data type information inherent in the current instruction. When the data type information indicates that the data type of all target operands of the current instruction is a fixed data type (the judgment result of step S220 is "No"), the computation core 120 can execute the current instruction to process the target operands based on the fixed data type (step S230). According to actual design, in some embodiments, step S230 can be a well-known practice, so it will not be described in detail here.

[0036] The specific content of the data type information can be determined according to the actual design. For example (but not limited to), the data type information may include 4 bits of encoding. When the 4 bits of encoding (data type information) are a first value (e.g., 0), it indicates that the fixed data type is a 4-bit signed integer s4. When the data type information is a second value (e.g., 1), it indicates that the fixed data type is an 8-bit signed integer s8. When the data type information is a third value (e.g., 2), it indicates that the fixed data type is an 8-bit unsigned integer u8. When the data type information is a fourth value (e.g., 3), it indicates that the fixed data type is a standard 16-bit floating-point number f16. When the data type information is a fifth value (e.g., 4), it indicates that the fixed data type is a standard 32-bit floating-point number f32. When the data type information is a sixth value (e.g., 5), it indicates that the fixed data type is a 16-bit floating-point number bf16. When the data type information is a seventh value (e.g., 9), it indicates that the fixed data type is an 8-bit floating-point number f8 with a 4-bit exponent. When the data type information is the eighth value (e.g., 10), it indicates that the fixed data type is an 8-bit floating-point number bf8 with a 5-bit exponent. When the data type information is the ninth value (e.g., 15), it indicates that the data type of the target operand is an adaptive data type.

[0037] When the data type information indicates that the data type of any target operand of the current instruction is an adaptive data type (the judgment result of step S220 is "yes"), the operation core 120 can read the metadata corresponding to the target operand to obtain the actual data type of the target operand from the metadata, or directly obtain the actual data type of the target operand (step S240). The specific content of the metadata can be determined according to the actual design. For example (but not limited to), the metadata may include an actual data type field to record the actual data type of the target operand corresponding to the metadata. As one of many examples, the actual data type recorded in the actual data type field includes an 8-bit floating-point number with a first structure, an 8-bit floating-point number with a second structure, or a 16-bit floating-point number with a third structure. For example, suppose the actual data type field includes a 2-bit encoded number. When the encoded number is 0, it indicates that the actual data type of the target operand is an 8-bit floating-point number with "1 sign, 5 exponents, and 2 mantissas" (first structure). The sign is used to represent positive or negative signs. When the code number is 1, it indicates that the actual data type of the target operand is an 8-bit floating-point number with "1 sign bit, 4 exponent bits, and 3 mantissa bits" (second structure). When the code number is 2, it indicates that the actual data type of the target operand is a 16-bit floating-point number with "1 sign bit, 5 exponent bits, and 10 mantissa bits" (third structure).

[0038] In some embodiments, the metadata may further include a scaling factor field to record the offset of the exponent of the target operand. The computation core 120 can convert long-format data into short-format data based on the range of exponent values ​​for each element in the target operand (e.g., a block). For example, assuming the range of exponent values ​​for all elements in a block (target operand) is 10–20, the computation core 120 can shift the exponent value range from 10–20 to the exponent value range of 0–10, and record the offset "-10" in the scaling factor field of the metadata. Therefore, when the computation core 120 executes the current instruction, it can restore the range of exponent values ​​for all elements in the target operand from "0–10" to "10–20" based on the offset "-10" in the scaling factor field of the metadata.

[0039] Based on the actual data type of the target operand recorded in the metadata, the processing core 120 can execute the current instruction to process the target operand (step S250). For example, suppose the current instruction includes a load instruction. When the data type information carried by the load instruction indicates that the data type of the target operand is an adaptive data type, the processing core 120 can read the metadata corresponding to the target operand from memory 110 to obtain the actual data type of the target operand from the metadata (step S240), and then record the metadata and the actual data type in a register inside the processing core 120, such as a state register or other registers. Therefore, based on the actual data type of the target operand recorded in the metadata, the processing core 120 can execute the load instruction (current instruction) to load the target operand from memory 110 into the processing core 120. Also suppose the current instruction includes a matrix multiplication and accumulation (MMA) instruction. When the data type information carried by the MMA instruction indicates that the data type of the target operand is an adaptive data type, the processing core 120 can directly obtain the actual data type of the target operand from its own internal registers (step S240).

[0040] Figure 3 This is a circuit block diagram of the computation core 120 according to an embodiment of the present invention. Figure 3 The illustrated processing core 120 includes a processing circuit 121, an operand buffer 122, and a conversion unit 123. After completing the previous layer's calculation, the processing circuit 121 generates a calculation result and stores the result, Dorig, in the operand buffer 122. Depending on the actual design, in different embodiments, the operand buffer 122 can be configured inside or outside the processing circuit 121, in a reduction buffer, or in thread local registers. Furthermore, the processing circuit 121 can statistically analyze the numerical characteristics of the calculation result, Dorig, and generate a statistical result ST for the conversion unit 123.

[0041] Operand buffer 122 can provide the computation result Dorig to conversion unit 123. Conversion unit 123, based on statistical result ST, converts the computation result Dorig into an operand Dconv (target operand) with a data type suitable for the next layer of computation, and corresponding metadata Dm. In actual execution, conversion unit 123 dynamically determines the data type of the operand Dconv. Therefore, conversion unit 123 records the actual data type of the operand Dconv in the metadata Dm corresponding to the operand Dconv, and then stores the operand Dconv and metadata Dm in memory 110.

[0042] Figure 4 This is a circuit block diagram of the computation core 120 according to another embodiment of the present invention. Figure 4 The illustrated processing core 120 includes a processing circuit 121, a load unit 124, a state register 125, and an operand buffer 126. The load unit 124 is coupled to memory 110. The state register 125 is coupled between the load unit 124 and the processing circuit 121. The operand buffer 126 is coupled between the load unit 124 and the processing circuit 121. Depending on the actual design, in different embodiments, the processing circuit 121 may include a tensor core, a generalized matrix multiplication (GEMM) core, an arithmetic logic unit (ALU), and / or other processing units.

[0043] As an illustrative example, assume the current instructions include a load instruction. When the data type information included in the load instruction indicates that the target operand's data type is an adaptive data type, the load unit 124 can read the metadata corresponding to the target operand from memory 110 to determine the actual data type of the target operand. The load unit 124 stores the metadata in the status register 125 for use by the arithmetic circuit 121. Furthermore, the load unit 124 can read the target operand from memory 110 based on the "actual data type of the target operand" recorded in the metadata. The load unit 124 stores the target operand in the operand buffer 126 for use by the arithmetic circuit 121.

[0044] As another illustrative example, suppose the current instruction includes a matrix multiplication and accumulation (MMA) instruction, and the target operands (first operand and second operand) corresponding to this MMA instruction have been loaded into the operand buffer 126 by a previously executed load instruction. Furthermore, the first operand corresponds to first metadata, and the second operand corresponds to second metadata. By analogy from the preceding description, the previously executed load instruction can store the first metadata and the actual data type recorded in the first metadata (the actual data type of the first operand) and the second metadata and the actual data type recorded in the second metadata (the actual data type of the first operand) in the status register 125. When the data type information inherent in the MMA instruction indicates that the data type of the first operand is an adaptive data type, the arithmetic circuit 121 can directly obtain the actual data type of the first operand from the status register 125. When the data type information inherent in the MMA instruction indicates that the data type of the second operand is an adaptive data type, the arithmetic circuit 121 can directly obtain the actual data type of the second operand from the status register 125. Based on the actual data types of the first operand and the second operand, the arithmetic circuit 121 can correctly read the first operand and the second operand from the operand buffer 126, and perform matrix multiplication on the first operand and the second operand.

[0045] In summary, the computation core 120 can check the data type information inherent in the current instruction to determine whether the data type of the target operand corresponding to the current instruction is a fixed (specified) data type or an adaptive data type. A fixed data type means that the data type of the target operand is known at compile time. An adaptive data type means that the data type of the target operand is unknown at compile time but is dynamically determined during program execution. During actual program execution, the actual data type of the target operand is recorded in the metadata corresponding to the target operand. Before executing the current instruction, the computation core 120 can check the data type of the target operand corresponding to the current instruction. When the data type of the target operand is an adaptive data type, the computation core 120 can obtain the actual data type of the target operand from the metadata corresponding to the target operand. Based on the actual data type of the target operand recorded in the metadata, the computation core 120 can correctly execute the current instruction to process the target operand.

[0046] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. An operating method of a computing device, characterized by, The operation method comprises: checking, by the operation core, data type information carried by a current instruction, wherein the data type information indicates a data type of a target operand corresponding to the current instruction; when the data type information indicates that the data type of the target operand is an adaptive data type, reading, by the operation core, metadata corresponding to the target operand from a memory, to obtain an actual data type of the target operand from the metadata, or directly obtaining the actual data type of the target operand from a register inside the operation core; and based on the actual data type of the target operand recorded in the metadata, executing, by the operation core, the current instruction to process the target operand, wherein the adaptive data type indicates that the data type of the target operand is unknown at a compilation time and is dynamically determined at an execution time.

2. The method of claim 1, wherein, The operation method further comprises: when the data type information indicates that the data type of the target operand is a fixed data type, executing, based on the fixed data type, the current instruction to process the target operand.

3. The method of claim 2, wherein, The fixed data type comprises a 4-bit signed integer, an 8-bit signed integer, an 8-bit unsigned integer, an 8-bit floating point number, an 8-bit brain floating point number, a 16-bit signed integer, a standard 16-bit floating point number, a 16-bit brain floating point number, a standard 32-bit floating point number, a 32-bit fast floating point number, or a 32-bit floating point number or above.

4. The method of claim 3, wherein, When the data type information is a first value, the fixed data type is a 4-bit signed integer s4; when the data type information is a second value, the fixed data type is an 8-bit signed integer s8; when the data type information is a third value, the fixed data type is an 8-bit unsigned integer u8; when the data type information is a fourth value, the fixed data type is a standard 16-bit floating point number f16; when the data type information is a fifth value, the fixed data type is a standard 32-bit floating point number f32; when the data type information is a sixth value, the fixed data type is a 16-bit brain floating point number bf16; when the data type information is a seventh value, the fixed data type is an 8-bit floating point number f8 with a 4-bit exponent; when the data type information is an eighth value, the fixed data type is an 8-bit brain floating point number bf8 with a 5-bit exponent; and when the data type information is a ninth value, the data type of the target operand is the adaptive data type.

5. The operating method according to claim 1, characterized in that, The current instruction comprises a load instruction, and the operation method further comprises: when the data type information carried by the load instruction indicates that the data type of the target operand is the adaptive data type, reading, from the memory, the metadata corresponding to the target operand to obtain the actual data type of the target operand from the metadata; storing the metadata and the actual data type recorded in the metadata in a state register of the operation core; based on the actual data type of the target operand recorded in the metadata, reading, from the memory, the target operand; and storing the target operand in an operand buffer of the operation core.

6. The operating method according to claim 1, characterized in that, The operation core includes a tensor core, a general matrix multiplication core, or an arithmetic logic unit.

7. The operating method according to claim 1, characterized in that, The current instruction includes a matrix multiplication and accumulation instruction, the target operand includes a first operand and a second operand, the metadata includes first metadata and second metadata, the first metadata corresponds to the first operand, the second metadata corresponds to the second operand, and the operation method further includes: when the data type information carried by the matrix multiplication and accumulation instruction indicates that the data type of the first operand is the adaptive data type, directly obtaining the actual data type of the first operand from a state register of the operation core; when the data type information carried by the matrix multiplication and accumulation instruction indicates that the data type of the second operand is the adaptive data type, directly obtaining the actual data type of the second operand from the state register of the operation core; based on the actual data type of the first operand and the actual data type of the second operand, reading the first operand and the second operand from an operand buffer of the operation core; and performing matrix multiplication calculation on the first operand and the second operand.

8. The operating method according to claim 1, characterized in that, The metadata includes an actual data type field used to record the actual data type of the target operand corresponding to the metadata.

9. The method of claim 8, wherein, The actual data type recorded by the actual data type field includes an 8-bit floating point number with a first structure, an 8-bit floating point number with a second structure, or a 16-bit floating point number with a third structure.

10. The method of claim 9, wherein, The first structure is "1-bit sign, 5-bit exponent, and 2-bit mantissa", the second structure is "1-bit sign, 4-bit exponent, and 3-bit mantissa", and the third structure is "1-bit sign, 5-bit exponent, and 10-bit mantissa".

11. The operating method according to claim 8, characterized in that, The metadata further includes a scaling factor field used to record the movement amount of the exponent of the target operand.

12. The operating method according to claim 1, characterized in that, The operation method further includes: generating a calculation result by the operation core; generating a statistical result by the operation core by counting the numerical characteristics of the calculation result; converting the calculation result into the target operand and the metadata based on the statistical result by the operation core; and storing the target operand and the metadata in the memory.

13. A machine readable storage medium for storing non-transitory machine readable instructions, which when executed by a computer can implement the operation method of the computing device of any one of claims 1-12.

14. A computing device, comprising: The computing device includes: a memory used to store a target operand; and an operation core coupled to the memory, wherein the operation core checks data type information carried by a current instruction, the data type information indicating the data type of the target operand corresponding to the current instruction; when the data type information carried by the matrix multiplication and accumulation instruction indicates that the data type of the first operand is the adaptive data type, directly obtaining the actual data type of the first operand from a state register of the operation core; when the data type information carried by the matrix multiplication and accumulation instruction indicates that the data type of the second operand is the adaptive data type, directly obtaining the actual data type of the second operand from the state register of the operation core; based on the actual data type of the first operand and the actual data type of the second operand, reading the first operand and the second operand from an operand buffer of the operation core; and performing matrix multiplication calculation on the first operand and the second operand. The metadata includes an actual data type field used to record the actual data type of the target operand corresponding to the metadata. The actual data type recorded by the actual data type field includes an 8-bit floating point number with a first structure, an 8-bit floating point number with a second structure, or a 16-bit floating point number with a third structure. The first structure is "1-bit sign, 5-bit exponent, and 2-bit mantissa", the second structure is "1-bit sign, 4-bit exponent, and 3-bit mantissa", and the third structure is "1-bit sign, 5-bit exponent, and 10-bit mantissa". The metadata further includes a scaling factor field used to record the movement amount of the exponent of the target operand. The operation method further includes: generating a calculation result by the operation core; generating a statistical result by the operation core by counting the numerical characteristics of the calculation result; converting the calculation result into the target operand and the metadata based on the statistical result by the operation core; and storing the target operand and the metadata in the memory.

13. A machine readable storage medium for storing non-transitory machine readable instructions, which when executed by a computer can implement the operation method of the computing device of any one of claims 1-12. The computing device includes: a memory used to store a target operand; and an operation core coupled to the memory, wherein the operation core checks data type information carried by a current instruction, the data type information indicating the data type of the target operand corresponding to the current instruction; When the data type information indicates that the data type of the target operand is an adaptive data type, the operation core reads metadata corresponding to the target operand from the memory to learn the actual data type of the target operand from the metadata, or directly obtains the actual data type of the target operand from a register inside the operation core; and The operation core executes the current instruction to process the target operand based on the actual data type of the target operand recorded in the metadata, Wherein, the adaptive data type indicates that the data type of the target operand is unknown at the time of compilation and is dynamically determined at the time of execution.

15. The computing device of claim 14, wherein, When the data type information indicates that the data type of the target operand is a fixed data type, the operation core executes the current instruction to process the target operand based on the fixed data type.

16. The computing device of claim 15, wherein, The fixed data type includes a 4-bit signed integer, an 8-bit signed integer, an 8-bit unsigned integer, an 8-bit floating point number, an 8-bit brain floating point number, a 16-bit signed integer, a standard 16-bit floating point number, a 16-bit brain floating point number, a standard 32-bit floating point number, a 32-bit fast floating point number, or a 32-bit floating point number or above.

17. The computing device of claim 16, wherein, When the data type information is a first value, it indicates that the fixed data type is a 4-bit signed integer s4, when the data type information is a second value, it indicates that the fixed data type is an 8-bit signed integer s8, when the data type information is a third value, it indicates that the fixed data type is an 8-bit unsigned integer u8, when the data type information is a fourth value, it indicates that the fixed data type is a standard 16-bit floating point number f16, when the data type information is a fifth value, it indicates that the fixed data type is a standard 32-bit floating point number f32, when the data type information is a sixth value, it indicates that the fixed data type is a 16-bit brain floating point number bf16, when the data type information is a seventh value, it indicates that the fixed data type is an 8-bit floating point number f8 with a 4-bit exponent, when the data type information is an eighth value, it indicates that the fixed data type is an 8-bit brain floating point number bf8 with a 5-bit exponent, and when the data type information is a ninth value, it indicates that the data type of the target operand is the adaptive data type.

18. The computing device of claim 14, wherein, The current instruction includes a load instruction, and the operation core includes: a load unit coupled to the memory, wherein when the data type information carried by the load instruction indicates that the data type of the target operand is the adaptive data type, the load unit reads the metadata corresponding to the target operand from the memory to learn the actual data type of the target operand from the metadata, and the load unit reads the target operand from the memory based on the actual data type of the target operand recorded in the metadata; a state register coupled to the load unit, wherein the load unit stores the metadata and the actual data type recorded in the metadata in the state register; and a state register coupled to the load unit, wherein the load unit stores the metadata and the actual data type recorded in the metadata in the state register; and An operand buffer coupled to the load unit, wherein the load unit stores the target operands in the operand buffer.

19. The computing device of claim 18, wherein, The operation core further includes: An operation circuit coupled to the state register and the operand buffer, wherein the operation circuit includes a tensor core, a general matrix multiplication core, or an arithmetic logic unit.

20. The computing device of claim 14, wherein, The current instruction includes a matrix multiplication and accumulation instruction, and the operation core includes: An operand buffer to store the target operands, wherein the target operands include a first operand and a second operand; A state register to store the metadata and the actual data type recorded by the metadata, wherein the metadata includes a first metadata and a second metadata, the first metadata corresponds to the first operand, and the second metadata corresponds to the second operand; and An operation circuit coupled to the state register and the operand buffer, wherein When the data type information carried by the matrix multiplication and accumulation instruction indicates that the data type of the first operand is the adaptive data type, the operation circuit directly obtains the actual data type of the first operand from the state register; When the data type information carried by the matrix multiplication and accumulation instruction indicates that the data type of the second operand is the adaptive data type, the operation circuit directly obtains the actual data type of the second operand from the state register; Based on the actual data type of the first operand and the actual data type of the second operand, the operation circuit reads the first operand and the second operand from the operand buffer; and The operation circuit performs matrix multiplication calculation on the first operand and the second operand.

21. The computing device of claim 14, wherein, The metadata includes an actual data type field to record the actual data type of the target operand corresponding to the metadata.

22. The computing device of claim 21, wherein, The actual data type recorded by the actual data type field includes an 8-bit floating point number with a first structure, an 8-bit floating point number with a second structure, or a 16-bit floating point number with a third structure.

23. The computing device of claim 22, wherein, The first structure is "1-bit sign, 5-bit exponent, and 2-bit mantissa", the second structure is "1-bit sign, 4-bit exponent, and 3-bit mantissa", and the third structure is "1-bit sign, 5-bit exponent, and 10-bit mantissa".

24. The computing device of claim 21, wherein, The metadata further includes a scaling factor field to record the movement amount of the exponent of the target operand.

25. The computing device of claim 14, wherein, The operation core generates a calculation result, the operation core generates a statistical result by counting the numerical characteristics of the calculation result, the operation core converts the calculation result into the target operand and the metadata based on the statistical result, and the operation core stores the target operand and the metadata in the memory.

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