Display panel and driving method thereof, and display device

Abstract

The embodiment of the present invention provides a display panel and a driving method thereof, and a display device, which relate to the field of display technology and are used to avoid the problem of screen flashing when the display panel is turned on, and to ensure the reliability of the display panel. The display panel includes an emission driving circuit, which includes a plurality of cascaded emission driving units; the emission driving unit includes a control module, which includes a control transistor; the control transistor responds to a signal at a first control signal end, and provides a signal at an adjustment signal end to a first node, so that the first output module is turned off; and the cross voltage between any two of the control electrode, the first electrode, and the second electrode of the control transistor is less than or equal to a preset threshold, and / or the continuous duration of the cross voltage between any two of the control electrode, the first electrode, and the second electrode of the control transistor being greater than the preset threshold is less than or equal to the preset duration.

Description

[Technical field]

[0001] The present invention relates to the field of display technology, and in particular to a display panel and a driving method thereof, and a display device. [Background technology]

[0002] With the continuous development of display technology, consumers' requirements for display screens are constantly increasing. At present, various types of displays, including liquid crystal displays and organic light-emitting displays, are emerging in an endless stream and have been developing rapidly. On this basis, display technologies such as 3D display, touch display technology, curved display, ultra-high resolution display and anti-peep display are also emerging.

[0003] Currently, display panels have screen flickering issues when they are turned on or off, which affects the display quality. [Summary of the invention]

[0004] In view of this, an embodiment of the present invention provides a display panel and a driving method thereof, and a display device, so as to solve the problem of screen flickering when the display panel is turned on or off.

[0005] In one aspect, an embodiment of the present invention provides a display panel, including an emission driving circuit, wherein the emission driving circuit includes a plurality of cascaded emission driving units; the emission driving unit includes:

[0006] A processing module, electrically connected to the input terminal, the first clock signal terminal, the second clock signal terminal, the first level signal terminal, the second level signal terminal, the first node and the second node, and the processing module is used to respond to the signals of the first clock signal terminal and the second clock signal terminal to provide signals to the first node and the second node;

[0007] A first output module, electrically connected to the first node, the second level signal terminal and the output terminal, the first output module is used to provide the signal of the second level signal terminal to the output terminal in response to the signal of the first node;

[0008] The control module includes a control transistor, a control electrode of which is electrically connected to a first control signal terminal, a first electrode of which is electrically connected to an adjustment signal terminal, and a second electrode of which is electrically connected to a first node; the control transistor responds to a signal at the first control signal terminal and provides a signal at the adjustment signal terminal to the first node to shut down the first output module; and

[0009] The voltage across any two of the control electrode, the first electrode and the second electrode of the control transistor is less than or equal to a preset threshold, and / or the continuous time for which the voltage across any two of the control electrode, the first electrode and the second electrode of the control transistor is greater than the preset threshold is less than or equal to a preset time.

[0010] On the other hand, an embodiment of the present invention provides a driving method applied to the above-mentioned display panel, wherein the working process of the display panel includes a first stage and a second stage, and the driving method includes:

[0011] In the first stage, the control transistor is controlled to be turned on, and the signal of the adjustment signal terminal is provided to the first node;

[0012] In the second phase, the control transistor is turned off.

[0013] In yet another aspect, an embodiment of the present invention provides a display device, comprising the above-mentioned display panel.

[0014] The display panel and its driving method and display device provided by the embodiment of the present invention can adjust the working state of the first output module by setting a control module in the emission driving unit. For example, when the machine is turned on and before the first frame of the picture is displayed, or after the machine is turned off, the control module can respond to the signal of the first control signal end to provide the signal of the adjustment signal end to the first node. The signal of the adjustment signal end can shut down the first output module, thereby avoiding the signal of the second level signal end electrically connected to the first output module from being output to the pixel driving circuit, and avoiding the sub-pixel from emitting light. That is, the display panel provided by the embodiment of the present invention can effectively avoid the problem of screen flashing when the display panel is turned on and off, and improve the display effect of the display panel.

[0015] Moreover, the embodiment of the present invention designs the control transistor in the control module, and makes the voltage across any two of the control electrode, the first electrode and the second electrode of the control transistor less than or equal to a preset threshold value, and / or makes the continuous time length that the voltage across any two of the control electrode, the first electrode and the second electrode of the control transistor is greater than the preset threshold value less than or equal to a preset time length, thereby avoiding the control transistor from being in a long-term high bias state, which is beneficial to ensuring the stability of the control transistor.

Brief Description of the Drawings

[0016] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0017] Figure 1 A schematic diagram of a display panel provided by an embodiment of the present invention;

[0018] Figure 2 A schematic diagram of an equivalent circuit of a sub-pixel provided by an embodiment of the present invention;

[0019] Figure 3 for Figure 2 A working timing diagram of the pixel driving circuit shown;

[0020] Figure 4 A schematic diagram of a transmission drive circuit provided by an embodiment of the present invention;

[0021] Figure 5 A circuit diagram of a transmission drive unit provided by an embodiment of the present invention;

[0022] Figure 6 A working timing diagram of a transmission drive circuit provided by an embodiment of the present invention;

[0023] Figure 7 for Figure 5 The shown transmission drive unit is a working timing diagram in the second stage;

[0024] Figure 8 A schematic diagram of another transmission drive circuit provided by an embodiment of the present invention;

[0025] Fig. 9 Another working timing diagram of a transmission driving circuit provided by an embodiment of the present invention;

[0026] Fig.10 Another working timing diagram of a transmission driving circuit provided by an embodiment of the present invention;

[0027] Fig.11 A schematic diagram of another transmission driving circuit provided by an embodiment of the present invention;

[0028] Fig.12 A schematic diagram of another transmission driving circuit provided by an embodiment of the present invention;

[0029] Fig.13 A circuit diagram of another transmitting driving unit provided by an embodiment of the present invention;

[0030] Fig.14 A schematic diagram of another transmission driving circuit provided by an embodiment of the present invention;

[0031] Fig.15 A cross-sectional schematic diagram of a first control signal line and a second control signal line provided in an embodiment of the present invention;

[0032] Fig.16 A cross-sectional schematic diagram of another first control signal line and a second control signal line provided in an embodiment of the present invention;

[0033] Fig.17 A cross-sectional schematic diagram of a first control signal line and a second control signal line provided in another embodiment of the present invention;

[0034] Fig.18A circuit diagram of another transmitting driving unit provided by an embodiment of the present invention;

[0035] Fig.19 A circuit diagram of another transmitting driving unit provided by an embodiment of the present invention;

[0036] Fig. 20 A schematic diagram of a display device provided by an embodiment of the present invention. [Specific implementation method]

[0037] In order to better understand the technical solution of the present invention, the embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0038] It should be clear that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0039] The terms used in the embodiments of the present invention are only for the purpose of describing specific embodiments, and are not intended to limit the present invention. The singular forms "a", "said" and "the" used in the embodiments of the present invention and the appended claims are also intended to include plural forms, unless the context clearly indicates other meanings.

[0040] It should be understood that the term "and / or" used in this article is only a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.

[0041] It should be understood that although the terms first, second, third, etc. may be used to describe transistors in embodiments of the present invention, these transistors should not be limited to these terms. These terms are only used to distinguish the transistors from each other. For example, without departing from the scope of embodiments of the present invention, the first transistor may also be referred to as the second transistor, and similarly, the second transistor may also be referred to as the first transistor.

[0042] An embodiment of the present invention provides a display panel, such as Figure 1 As shown, Figure 1A schematic diagram of a display panel 100 provided in an embodiment of the present invention, the display panel 100 includes an emission drive circuit 1, a scan drive circuit 2, a data drive circuit 3 and a plurality of sub-pixels 4. The display panel 100 also includes a first scan line Scan1, a second scan line Scan2, a light-emitting control signal line Emit and a data line Data. The emission drive circuit 1 is electrically connected to the sub-pixel 4 through the light-emitting control signal line Emit. The emission drive circuit 1 is used to output a light-emitting control signal to the sub-pixel 4 to control the light-emitting state of the sub-pixel 4. The scan drive circuit 2 is electrically connected to the sub-pixel 4 through the first scan line Scan1 and the second scan line Scan2. The data drive circuit 3 is electrically connected to the sub-pixel 4 through the data line Data.

[0043] For example, Figure 2 As shown, Figure 2 The equivalent circuit diagram of a sub-pixel 4 provided in an embodiment of the present invention is shown in FIG. 4 , wherein the sub-pixel 4 includes a pixel driving circuit 41 and a light-emitting element D electrically connected to each other. Exemplarily, the light-emitting element D includes any one of an organic light-emitting diode, an inorganic light-emitting diode, and a quantum dot light-emitting diode. Figure 2 As shown, the pixel driving circuit 41 includes a storage capacitor C and a first transistor T1 to a seventh transistor T7. Alternatively, the pixel driving circuit 41 in the sub-pixel 4 may also be configured to include other numbers of transistors in the embodiment of the present invention, which is not limited in the embodiment of the present invention.

[0044] When the pixel driving circuit 41 is working, Figure 3 As shown, Figure 3 for Figure 2 A working timing diagram of the pixel driving circuit 41 shown in the figure, in the initialization period t11, the first scanning driving signal provided by the first scanning line Scan1 is at a low level, the second scanning driving signal provided by the second scanning line Scan2 and the light-emitting control signal provided by the light-emitting control signal line Emit are respectively at high levels, and the reference voltage signal provided by the reference voltage line Vref resets the voltage of the control electrode of the third transistor T3 via the turned-on fifth transistor T5, and resets the anode of the light-emitting element D via the turned-on seventh transistor T7.

[0045] During the charging period t12, the second scanning drive signal provided by the second scanning line Scan2 is at a low level, the first scanning drive signal provided by the first scanning line Scan1 and the light-emitting control signal provided by the light-emitting control signal line Emit are respectively at high levels, and the data signal provided by the data line Data is written into the control electrode of the third transistor T3 via the turned-on second transistor T2, the third transistor T3 and the fourth transistor T4.

[0046] In the light-emitting period t13, the light-emitting control signal provided by the light-emitting control signal line Emit is at a low level, the first scanning drive signal provided by the first scanning line Scan1 and the second scanning drive signal provided by the second scanning line Scan2 are respectively at a high level, the first transistor T1, the third transistor T3 and the sixth transistor T6 are turned on, and a driving current is generated from the first power supply voltage terminal PVDD to the second power supply voltage terminal PVEE, and the light-emitting element D emits light under the action of the driving current.

[0047] like Figure 4 As shown, Figure 4 It is a schematic diagram of a transmit driving circuit 1 provided in an embodiment of the present invention. The transmit driving circuit 1 includes a plurality of cascaded transmit driving units 10 . Figure 4 The first-stage emission driving unit 10_1, the second-stage emission driving unit 10_2, the third-stage emission driving unit 10_3 and the fourth-stage emission driving unit 10_4 in the emission driving circuit 1 are used as an example. Each level of the emission driving unit 10 includes an input terminal IN, an output terminal OUT, a first clock signal terminal XCK, a second clock signal terminal CK, a first level signal terminal VGH and a second level signal terminal VGL. The emission driving unit 10 responds to the signals of the input terminal IN, the first clock signal terminal XCK, the second clock signal terminal CK, the first level signal terminal VGH and the second level signal terminal VGL, and provides a light-emitting control signal to the pixel driving circuit through the output terminal OUT.

[0048] like Figure 4 As shown, the display panel further includes a first clock signal line LK1, a second clock signal line LK2, a second level signal line LL, a first level signal line LH and a start signal line STV. The first clock signal line LK1 is electrically connected to the first clock signal terminal XCK of the odd-numbered emission driving unit 10 and the second clock signal terminal CK of the even-numbered emission driving unit 10 in the emission driving circuit 1, respectively. The second clock signal line LK2 is electrically connected to the second clock signal terminal CK of the odd-numbered emission driving unit 10 and the first clock signal terminal XCK of the even-numbered emission driving unit 10 in the emission driving circuit 1, respectively.

[0049] The first level signal line LH is electrically connected to the first level signal terminal VGH of each level of the emission driving unit 10 in the emission driving circuit 1, and the second level signal line LL is electrically connected to the second level signal terminal VGL of each level of the emission driving unit 10 in the emission driving circuit 1. The voltage transmitted by the second level signal line LL is lower than the voltage transmitted by the first level signal line LH.

[0050] The input terminal IN of the first stage emission driving unit 10 is electrically connected to the start signal line STV, and the input terminals IN of other stages emission driving units 10 are electrically connected to the output terminal OUT or the carry signal terminal of the previous stage emission driving unit 10. Here, the electrical connection with the output terminal OUT is used as an example for description.

[0051] For example, Figure 5 As shown, Figure 5 The circuit diagram of a transmission driving unit 10 provided in an embodiment of the present invention includes a processing module 5, a first output module 61, a second output module 62 and a control module 7. The processing module 5 is electrically connected to the input terminal IN, the first clock signal terminal XCK, the second clock signal terminal CK, the first level signal terminal VGH, the second level signal terminal VGL, the first node N1 and the second node N2. The processing module 5 is used to provide a signal to the first node N1 and the second node N2 in response to the signal of the first clock signal terminal XCK and the second clock signal terminal CK. The first output module 61 is electrically connected to the first node N1, the second level signal terminal VGL and the output terminal OUT. The first output module 61 is used to provide the signal of the second level signal terminal VGL to the output terminal OUT in response to the signal of the first node N1. The output terminal OUT is electrically connected to the above-mentioned light emitting control signal line Emit. The second output module 62 is electrically connected to the second node N2, the first level signal terminal VGH and the output terminal OUT of the transmission driving unit 10. The second output module 62 provides the signal of the first level signal terminal VGH to the output terminal OUT in response to the signal of the second node N2.

[0052] like Figure 5 As shown, the control module 7 includes a control transistor Mc, whose control electrode is electrically connected to the first control signal terminal C1, whose first electrode is electrically connected to the adjustment signal terminal D, and whose second electrode is electrically connected to the first node N1. In response to the signal of the first control signal terminal C1, the control transistor Mc provides the signal of the adjustment signal terminal D to the first node N1, so that the first output module 61 is turned off, so as to prevent the residual charge of the N1 node from causing the signal of the second level signal terminal VGL to be output to the output terminal OUT of the emission driving unit 10 through the first output module 61, thereby causing the problem of screen flickering when the device is turned on.

[0053] Exemplary, combined Figure 6 As shown, Figure 6 This is a working timing diagram of an emission driving circuit 1 provided by an embodiment of the present invention. The working process of the emission driving circuit 1 includes a first stage S1 and a second stage S2.

[0054] In the first stage S1, the first control signal terminal C1 provides a signal V to turn on the control transistor Mc. C1 , adjust the signal terminal D to provide a signal V that turns off the first output module 61S2 In the first stage S1, the control transistor Mc is turned on to adjust the signal V provided by the signal terminal D. S2 The first output module 61 is controlled to be cut off, thereby preventing the low level signal provided by the second level signal terminal VGL from being provided to the corresponding sub-pixel 4 through the first output module 61, thereby preventing the sub-pixel 4 from emitting light in the first stage S1, thereby avoiding screen flickering.

[0055] Exemplary, combined Figure 6 As shown, the working process of the emission driving circuit 1 also includes a second stage S2. In the second stage S2, the first control signal terminal C1 provides a signal V to turn off the control transistor Mc. C2 , so as to avoid the signal of the adjustment signal terminal D from being written into the first node N1 in the second stage S2, so that the signal of the first node N1 is independent of the signal of the adjustment signal terminal D in the second stage S2. In the second stage S2, the emission driving unit 10 can provide a pulse signal including a valid level and a non-valid level to the light emitting control signal line Emit through the output terminal OUT under the action of the input terminal IN, the first clock signal terminal XCK, the second clock signal terminal CK, the first level signal terminal VGH and the second level signal terminal VGL. Among them, combined with Figure 3 It can be seen that during the period when the emission driving unit 10 outputs a non-effective level, the corresponding pixel driving circuit 41 can perform a reset and charging operation. During the period when the emission driving unit 10 outputs an effective level, the corresponding pixel driving circuit 41 can perform a light-emitting operation. This arrangement enables the corresponding sub-pixel 4 to be lit at a target brightness, so that the display panel displays an image.

[0056] Exemplarily, the first stage S1 includes a power-on stage and / or a power-off stage of the display panel 100 , and the second stage S2 includes a normal display stage of the display panel 100 .

[0057] In an embodiment of the present invention, the voltage across any two of the control electrode, the first electrode and the second electrode of the control transistor Mc is less than or equal to a preset threshold, and / or the continuous duration of the voltage across any two of the control electrode, the first electrode and the second electrode of the control transistor Mc being greater than the preset threshold is less than or equal to the preset duration. Exemplarily, in the first stage S1 and the second stage S2, the voltage across any two of the control electrode, the first electrode and the second electrode of the control transistor Mc is less than or equal to the preset threshold. And / or, in the first stage S1 and the second stage S2, the continuous duration of the voltage across any two of the control electrode, the first electrode and the second electrode of the control transistor Mc being greater than the preset threshold is less than or equal to the preset duration.

[0058] In the embodiment of the present invention, the first control signal terminal C1 is configured to receive a global control signal. In the second stage S2, in order not to affect the normal operation of the emission driving unit 10, the control transistor Mc needs to be continuously turned off. In the second stage S2, when a fixed voltage is continuously applied to the first control signal terminal C1 to turn off the control transistor Mc, the threshold voltage of the control transistor Mc will drift because the control transistor Mc is under a high bias for a long time, resulting in an unexpected turn-on or leakage of the control transistor Mc, affecting the circuit operation stability of the emission driving unit 10.

[0059] The embodiments of the present invention make the voltage between any two of the control electrode, the first electrode and the second electrode of the control transistor Mc less than or equal to a preset threshold value, and / or make the continuous time that the voltage between any two of the control electrode, the first electrode and the second electrode of the control transistor Mc is greater than the preset threshold value less than or equal to a preset time. While improving the problem of screen flickering during startup, the control transistor Mc can be prevented from being in a large bias state for a long time, which is beneficial to improving the stability of the control transistor Mc, thereby ensuring the stable operation of the display panel.

[0060] The display panel provided by the embodiment of the present invention can adjust the working state of the first output module 61 by setting the control module 7 in the emission driving unit 10. For example, when the machine is turned on and before the first frame of the picture is displayed, or after the machine is turned off, the control module 7 can respond to the signal of the first control signal terminal C1 to provide the signal of the adjustment signal terminal D to the first node N1. The signal of the adjustment signal terminal D can turn off the first output module 61, thereby avoiding the signal of the second level signal terminal VGL electrically connected to the first output module 61 from being output to the pixel driving circuit, and avoiding the sub-pixel 4 from emitting light. That is, the display panel provided by the embodiment of the present invention can effectively avoid the problem of screen flickering when the display panel is turned on and off, and improve the display effect of the display panel.

[0061] Moreover, the embodiment of the present invention designs the control transistor Mc in the control module 7 so that the voltage across the control electrode, the first electrode and any two electrodes of the control transistor Mc is less than or equal to a preset threshold value, and / or the continuous time for which the voltage across the control electrode, the first electrode and any two electrodes of the control transistor Mc is greater than the preset threshold value is less than or equal to a preset time length, thereby avoiding the control transistor Mc from being in a long-term high bias state, which is beneficial to ensuring the stability of the control transistor Mc.

[0062] Exemplarily, each level of the emission driving unit 10 in the emission driving circuit 1 includes the above-mentioned control module 7, and the first control signal terminal C1 of each level of the emission driving unit 10 can be connected to the same first control signal line, and the adjustment signal terminal D of each level of the emission driving unit 10 can be connected to the same adjustment signal line, so that in the first stage S1, as Figure 6 As shown, each level of emission driving unit 10 can output a signal that makes the corresponding sub-pixel 4 not emit light, so as to realize the whole screen black state in the first stage S1, and avoid the situation where the high-level emission control signal cannot complete the transmission of the whole screen in the first stage S1, resulting in some pixels in the display panel still being lit.

[0063] For example, Figure 5 As shown, the processing module 5 includes a first processing unit 51 electrically connected to the first node N1. The first processing unit 51 is electrically connected to the input terminal IN, the second clock signal terminal CK and the first node N1. The first processing unit 51 is used to provide the signal of the input terminal IN to the first node N1 in response to the signal of the second clock signal terminal CK.

[0064] like Figure 5 As shown, the processing module 5 further includes a pull-down unit 53 and a pull-up unit 54. The pull-down unit 53 is electrically connected to the first level signal terminal VGH, the third node N3, the first clock signal terminal XCK and the first node N1. The pull-down unit 53 is used to provide the signal of the first level signal terminal VGH to the first node N1 in response to the signal of the first clock signal terminal XCK and the third node N3. The pull-up unit 54 is electrically connected to the first node N1, the second node N2, the third node N3, the first level signal terminal VGH, the first clock signal terminal XCK and the second clock signal terminal CK, and is used to transmit a voltage signal to the second node N2 in response to the signal of the second clock signal terminal CK, the first node N1, the third node N3 and the first clock signal terminal XCK.

[0065] For example, Figure 5 As shown, the first processing unit 51 includes a first transistor M1. A control electrode of the first transistor M1 is electrically connected to the second clock signal terminal CK, a first electrode of the first transistor M1 is electrically connected to the input terminal IN, and a second electrode of the first transistor M1 is electrically connected to the first node N1.

[0066] The pull-down unit 53 includes a fourth transistor M4 and a fifth transistor M5. The control electrode of the fourth transistor M4 is electrically connected to the third node N3, the first electrode of the fourth transistor M4 is electrically connected to the first level signal terminal VGH, the second electrode of the fourth transistor M4 is electrically connected to the first electrode of the fifth transistor M5; the control electrode of the fifth transistor M5 is electrically connected to the first clock signal terminal XCK, and the second electrode of the fifth transistor M5 is electrically connected to the first node N1.

[0067] The pull-up unit 54 includes a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, and a tenth transistor M10. The control electrode of the sixth transistor M6 is electrically connected to the second clock signal terminal CK, the first electrode of the sixth transistor M6 is electrically connected to the second level signal terminal VGL, and the second electrode of the sixth transistor M6 is electrically connected to the third node N3; the control electrode of the seventh transistor M7 is electrically connected to the first node N1, the first electrode of the seventh transistor M7 is electrically connected to the second clock signal terminal CK, and the second electrode of the seventh transistor M7 is electrically connected to the third node N3; the control electrode of the eighth transistor M8 is electrically connected to the third node N3, and the first electrode of the eighth transistor M8 is electrically connected to the first clock signal terminal XCK; the control electrode of the ninth transistor M9 is electrically connected to the first clock signal terminal XCK, the first electrode of the ninth transistor M9 is electrically connected to the second electrode of the eighth transistor M8, that is, the fourth node N4, and the second electrode of the ninth transistor M9 is electrically connected to the second node N2; the control electrode of the tenth transistor M10 is electrically connected to the first node N1, the first electrode of the tenth transistor M10 is electrically connected to the first level signal terminal VGH, and the second electrode of the tenth transistor M10 is electrically connected to the second node N2.

[0068] As shown in 5, the first output module 61 includes an eleventh transistor M11, the control electrode of the eleventh transistor M11 is electrically connected to the first node N1, the first electrode of the eleventh transistor M11 is electrically connected to the second level signal terminal VGL, and the second electrode of the eleventh transistor M11 is electrically connected to the output terminal OUT; the second output module 62 includes a twelfth transistor M12, the control electrode of the twelfth transistor M12 is electrically connected to the second node N2, the first electrode of the twelfth transistor M12 is electrically connected to the first level signal terminal VGH, and the second electrode of the twelfth transistor M12 is electrically connected to the output terminal OUT.

[0069] like Figure 5 As shown, the transmitting driving unit 10 further includes a first capacitor Cst1, a second capacitor Cst2 and a third capacitor Cst3. The first plate of the first capacitor Cst1 is electrically connected to the first node N1, and the second plate of the first capacitor Cst1 is electrically connected to the first clock signal terminal XCK. The first plate of the second capacitor Cst2 is electrically connected to the third node N3, and the second plate of the second capacitor Cst2 is electrically connected to the second electrode of the eighth transistor M8; the first plate of the third capacitor Cst3 is electrically connected to the first level signal terminal VGH, and the second plate of the third capacitor Cst3 is electrically connected to the second node N2.

[0070] In the second stage S2, each level of the emission driving unit 10 in the emission driving circuit 1 sequentially outputs a valid level signal in cooperation with each signal connected thereto. Figure 5 The emission drive unit 10 shown in the figure is a first-stage emission drive unit electrically connected to the start signal line STV as an example. Figure 5 and Figure 7 , Figure 7 for Figure 5 The working timing diagram of the transmitting driving unit 10 in the second stage S2 shown in the figure describes the working process of the transmitting driving unit 10 in the second stage S2. In the second stage S2, the working process of the transmitting driving unit 10 includes a first sub-period t21, a second sub-period t22, a third sub-period t23, a fourth sub-period t24, a fifth sub-period t25, a sixth sub-period t26, a seventh sub-period t27 and an eighth sub-period t28.

[0071] In the first sub-period t21, the second clock signal terminal CK provides a low level, the first clock signal terminal XCK provides a high level, and the start signal line STV provides a low level. The first transistor M1 and the sixth transistor M6 are turned on, and the low level signal provided by the start signal line STV writes the first node N1 low through the turned-on first transistor M1, and the seventh transistor M7, the tenth transistor M10 and the eleventh transistor M11 are turned on. The high level signal provided by the first level signal terminal VGH writes the second node N2 high through the turned-on tenth transistor M10, and the twelfth transistor M12 is turned off. The low level signal provided by the second level signal terminal VGL writes the output terminal OUT low through the turned-on eleventh transistor M11. The low level signal provided by the second clock signal terminal CK writes the third node N3 low through the turned-on seventh transistor M7, and the low level signal provided by the second level signal terminal VGL writes the third node N3 low through the turned-on sixth transistor M6, the fourth transistor M4 and the eighth transistor M8 are turned on, and the high level signal provided by the first clock signal terminal XCK writes the fourth node N4 high through the turned-on eighth transistor M8.

[0072] In the second sub-period t22, the second clock signal terminal CK provides a high level, the first clock signal terminal XCK provides a low level, and the start signal line STV provides a low level. The first transistor M1 and the sixth transistor M6 are turned off, the first node N1 maintains the low level of the first sub-period t21, the seventh transistor M7, the tenth transistor M10 and the eleventh transistor M11 are turned on, the second clock signal terminal CK writes the third node N3 high through the turned-on seventh transistor M7, and the fourth transistor M4 and the eighth transistor M8 are turned off. The first level signal terminal VGH writes the second node N2 high through the turned-on tenth transistor M10. When the first clock signal terminal XCK jumps from a high level to a low level, the potential of the first node N1 changes from a low level to a third level smaller than the low level under the action of the first capacitor Cst1, and the eleventh transistor M11 can be stably turned on to provide the low level signal of the second level signal terminal VGL to the output terminal OUT.

[0073] In the third sub-period t23, the second clock signal terminal CK provides a low level, the first clock signal terminal XCK provides a high level, and the start signal line STV provides a high level. The first transistor M1 and the sixth transistor M6 are turned on, and the high level signal provided by the start signal line STV writes the first node N1 high through the turned-on first transistor M1, and the seventh transistor M7, the tenth transistor M10 and the eleventh transistor M11 are turned off. The low level signal provided by the second level signal terminal VGL writes the third node N3 low through the turned-on sixth transistor M6, and the fourth transistor M4 and the eighth transistor M8 are turned on. The high level signal provided by the first clock signal terminal XCK writes the fourth node N4 high through the turned-on eighth transistor M8. The ninth transistor M9 is turned off under the action of the first clock signal terminal XCK, the second node N2 maintains the high level of the second sub-period t2, the twelfth transistor M12 is turned off, and the output terminal OUT maintains the low level of the second sub-period t22.

[0074] In the fourth sub-period t24, the second clock signal terminal CK provides a high level, the first clock signal terminal XCK provides a low level, and the start signal line STV provides a high level. The first transistor M1 and the sixth transistor M6 are turned off, the first node N1 maintains the high level of the third sub-period t23, the seventh transistor M7, the tenth transistor M10 and the eleventh transistor M11 are turned off, the third node N3 maintains the low level of the third sub-period t23, and the fourth transistor M4 and the eighth transistor M8 are turned on. When the first clock signal terminal XCK jumps from a high level to a low level, the low level signal provided by the first clock signal terminal XCK writes the fourth node N4 low through the turned-on eighth transistor M8. The third node N3 is pulled lower under the action of the second capacitor Cst2, so that the eighth transistor M8 remains in a turned-on state stably. Under the action of the low level provided by the first clock signal terminal XCK, the fifth transistor M5 and the ninth transistor M9 are turned on, and the high level signal provided by the first level signal terminal VGH writes the first node N1 high through the turned-on fourth transistor M4 and the fifth transistor M5. The low potential of the fourth node N4 writes the second node N2 low through the turned-on ninth transistor M9, and the twelfth transistor M12 is turned on. The first level signal terminal VGH writes the output terminal OUT high through the turned-on twelfth transistor M12.

[0075] In the fifth sub-period t25, the second clock signal terminal CK provides a low level, the first clock signal terminal XCK provides a high level, and the start signal line STV provides a high level. The first transistor M1 and the sixth transistor M6 are turned on. The high level signal provided by the start signal line STV writes the first node N1 high through the first transistor M1, and the seventh transistor M7, the tenth transistor M10 and the eleventh transistor M11 are turned off. The low level signal provided by the second level signal terminal VGL writes the third node N3 low through the turned-on sixth transistor M6, the fourth transistor M4 and the eighth transistor M8 are turned on, and the high level signal provided by the first clock signal terminal XCK writes the fourth node N4 high through the turned-on eighth transistor M8. The ninth transistor M9 is turned off. The second node N2 maintains the low level state of the fourth sub-period t4, and the twelfth transistor M12 is turned on. The first level signal terminal VGH writes the output terminal OUT high through the turned-on twelfth transistor M12.

[0076] In the sixth sub-period t26, the second clock signal terminal CK provides a high level, the first clock signal terminal XCK provides a low level, and the start signal line STV provides a low level. The first transistor M1 and the sixth transistor M6 are turned off, the first node N1 maintains the high level of the fifth sub-period t25, and the seventh transistor M7, the tenth transistor M10 and the eleventh transistor M11 are turned off. The third node N3 maintains the low level of the fifth sub-period t25, the fourth transistor M4 and the eighth transistor M8 are turned on, and the first level signal terminal VGH writes the first node N1 high through the turned-on fourth transistor M4 and the fifth transistor M5. When the first clock signal terminal XCK jumps from a high level to a low level, the low level writes the fourth node N4 low through the turned-on eighth transistor M8, and the potential of the third node N3 is further pulled down under the action of the third capacitor Cst3, and the eighth transistor M8 stably maintains the turned-on state. At the same time, the ninth transistor M9 is turned on, the low level signal of the fourth node N4 writes the second node N2 low through the turned-on ninth transistor M9, the twelfth transistor M12 is turned on, and the high level signal provided by the first level signal terminal VGH writes the output terminal OUT high through the turned-on twelfth transistor M12.

[0077] In the seventh sub-period t27, the second clock signal terminal CK provides a low level, the first clock signal terminal XCK provides a high level, and the start signal line STV provides a low level. The first transistor M1 and the sixth transistor M6 are turned on. The low level signal provided by the start signal line STV writes the first node N1 low through the first transistor M1, and the seventh transistor M7, the tenth transistor M10 and the eleventh transistor M11 are turned on. The low level signal provided by the second level signal terminal VGL writes the third node N3 low through the turned-on sixth transistor M6, the fourth transistor M4 and the eighth transistor M8 are turned on, and the high level signal provided by the first clock signal terminal XCK writes the fourth node N4 high through the turned-on eighth transistor M8. The ninth transistor M9 is turned off. The low level signal of the second level signal terminal VGL is provided to the output terminal OUT through the turned-on eleventh transistor M11. The high level signal provided by the first level signal terminal VGH writes the second node N2 high through the turned-on twelfth transistor M12, and the twelfth transistor M12 is turned off.

[0078] In the eighth sub-period t28, the second clock signal terminal CK provides a high level, the first clock signal terminal XCK provides a low level, and the start signal line STV provides a low level. The first transistor M1 and the sixth transistor M6 are turned off, the first node N1 maintains the low level of the seventh sub-period t27, the seventh transistor M7, the tenth transistor M10 and the eleventh transistor M11 are turned on, the second clock signal terminal CK writes the third node N3 high through the turned-on seventh transistor M7, and the fourth transistor M4 and the eighth transistor M8 are turned off. The first level signal terminal VGH writes the second node N2 high through the turned-on tenth transistor M10. When the first clock signal terminal XCK jumps from a high level to a low level, the potential of the first node N1 changes from a low level to a third level smaller than the low level under the action of the first capacitor Cst1, and the eleventh transistor M11 can be stably turned on to provide the low level signal of the second level signal terminal VGL to the output terminal OUT.

[0079] For example, Figure 6 As shown, the adjustment signal terminal D is used to transmit a pulse signal including a first level V1, wherein the first level V1 is a signal capable of controlling the first output module 61 to shut down. For example, when the first output module 61 includes a P-type transistor, the first level V1 may be equal to the level provided by the first level signal terminal VGH.

[0080] like Figure 6As shown, the embodiment of the present invention can make the adjustment signal terminal D constantly transmit the first level V1 in the first stage S1, and transmit the pulse signal including the first level V1 in the second stage S2. With this setting, on the one hand, the adjustment signal terminal D can stably write the first level V1 for controlling the first output module 61 to be turned off to the first node N1 in the first stage S1, so as to ensure that the emission driving unit 10 can output a signal that makes the sub-pixel 4 not emit light. On the other hand, by setting the signal transmitted by the adjustment signal terminal D as a pulse signal in the second stage S2, the embodiment of the present invention can also avoid the first electrode of the control transistor Mc electrically connected to the adjustment signal terminal D being at the first level V1 for a long time while ensuring that the first output module 61 is turned off in the first stage S1.

[0081] As mentioned above, in the second stage S2, when the output terminal OUT of the emission driving unit 10 outputs the effective level that causes the sub-pixel 4 to emit light, the first node N1 of the emission driving unit 10 is at an effective level that causes the first output module 61 to be turned on. Since the second electrode of the control transistor Mc is electrically connected to the first node N1, if the first electrode of the control transistor Mc is continuously at an ineffective level that causes the first output module 61 to be turned off, the first electrode and the second electrode of the control transistor Mc will be continuously subjected to a large cross-voltage. In the embodiment of the present invention, by setting the signal transmitted by the adjustment signal terminal D as a pulse signal, the continuous time that the adjustment signal terminal D transmits the first level V1 can be shortened, thereby facilitating shortening the continuous time that the first electrode and the second electrode of the control transistor Mc are subjected to a large cross-voltage, and improving the stability of the control transistor Mc.

[0082] Exemplary, combined Figure 5 , Figure 6 and Figure 8 As shown, Figure 8 Schematic diagram of another emission driving circuit provided by an embodiment of the present invention. When the adjustment signal terminal D receives a pulse signal, the embodiment of the present invention can make the adjustment signal terminal D of each level of emission driving unit 10 electrically connected to the start signal line STV, that is, make the adjustment signal terminal D of each level of emission driving unit 10 and the input terminal IN of the first level emission driving unit 10 receive the same signal. Figure 6As shown, in the first stage S1, the embodiment of the present invention can make the start signal line STV constantly transmit the first level V1 that turns off the first output module 61, and in the second stage S2, make the start signal line STV periodically output a pulse signal. The embodiment of the present invention makes the first electrode of the control transistor Mc electrically connected to the start signal line STV, shortens the continuous time between the first electrode and the second electrode of the control transistor Mc under a large cross voltage, improves the stability of the control transistor Mc, and can also avoid introducing too many wirings in the display panel 100, which can reduce the area of ​​the non-display area occupied by the emission drive circuit 1 and each signal line, which is conducive to simplifying the structure of the display panel 100 and improving the screen ratio of the display panel 100.

[0083] Optional, such as Fig. 9 As shown, Fig. 9 Another working timing diagram of an emission driving circuit provided by an embodiment of the present invention, the embodiment of the present invention can make the adjustment signal terminal D constantly transmit the first level V1 in the first stage S1, and constantly transmit the second level V2 in the second stage, wherein the first level V1 is a non-effective level for controlling the first output module 61 to be turned off, and the second level V2 is an effective level for controlling the first output module 61 to be turned on. For example, when the first output module 61 includes a P-type transistor, the first level V1 can be equal to the level provided by the first level signal terminal VGH. The second level V2 can be equal to the level provided by the second level signal terminal VGL. In this way, the cross-voltage between the first and second electrodes of the control transistor Mc can be reduced in the second stage S2, which is conducive to improving the stability of the control transistor Mc.

[0084] For example, Figure 6 and Fig. 9 As shown, the potential of the effective voltage transmitted by the first control signal terminal C1 is V C1 , the potential of the non-effective voltage is V C2 ; Adjust the potential of the ineffective voltage transmitted by the signal terminal D to V S2 ; The ineffective voltage transmitted by the regulating signal terminal D is used to turn off the first output module 61. Exemplarily, V S2 It can be equal to the first level V1 used to control the first output module 61 to be turned off. In the embodiment of the present invention, |V C2| ≥|V S2 Such a configuration can reduce the risk of the control transistor Mc being mistakenly turned on in the second stage S2.

[0085] Exemplarily, the embodiment of the present invention can also make the above-mentioned adjustment signal terminal D transmit a constant signal. Fig.10 As shown, Fig.10Another working timing diagram of the emission driving circuit provided by the embodiment of the present invention, in the first stage S1 and the second stage S2, the adjustment signal terminal D transmits the first level V1. The first level V1 is used to control the first output module 61 to turn off. For example, when the first output module 61 includes a P-type transistor, the first level V1 can be equal to the level provided by the first level signal terminal VGH.

[0086] Optional, such as Fig.11 As shown, Fig.11 A schematic diagram of another emission drive circuit provided by an embodiment of the present invention, in which the first level signal line LH can be electrically connected to the first level signal terminal VGH and the adjustment signal terminal D of each level of emission drive unit 10, respectively. That is, the adjustment signal terminal D of each level of emission drive unit 10 and the first level signal terminal VGH of each level of emission drive unit 10 receive the same signal. Such a configuration can, on the one hand, reduce the power consumption of the display panel. On the other hand, it can also avoid introducing too many wirings in the display panel 100, and can reduce the area of ​​the non-display area occupied by the emission drive circuit 1 and each signal line, which is conducive to simplifying the structure of the display panel 100 and improving the screen-to-body ratio of the display panel 100.

[0087] Exemplarily, after the display panel enters the second stage S2, the display panel enters the frame picture display stage. Taking the refresh frequency of the frame picture as F as an example, during the display time of the frame picture with the frequency F, the output signal of the emission driving unit 10 includes at least N pulses, N*F≥240Hz. Where N is an integer greater than or equal to 1. That is, the embodiment of the present invention can make the frequency of the signal output by the emission driving unit 10 greater than or equal to 240Hz. In this way, the signal output by the emission driving unit 10 can be switched between the effective level and the ineffective level at a relatively high frequency, that is, the output terminal OUT of the emission driving unit 10 can be prevented from continuously outputting the effective level for a long time. When the emission driving unit 10 outputs the effective level, the first node N1 of the emission driving unit 10 is in the effective level state that turns on the first output module 31. When the adjustment signal terminal D connected to the first pole of the control transistor Mc constantly transmits the ineffective level that turns off the first output module 31, this setting method can shorten the continuous time that the first pole and the second pole of the control transistor Mc are subjected to a large cross-voltage, which is conducive to improving the stability of the control transistor Mc.

[0088] Exemplarily, the embodiment of the present invention can set the frequency of the output signal of the transmission driving unit 10 to be greater than or equal to 1440 Hz. Further, the embodiment of the present invention can set the frequency of the output signal of the transmission driving unit 10 to be greater than or equal to 1920 Hz.

[0089] Exemplarily, during the display time of a frame picture with a frequency of F, an embodiment of the present invention can make the signal transmitted by the start signal line STV include at least N pulses, N*F≥240, so that the emission driving unit 10 outputs the above N pulses within the display period of a frame picture, so as to shorten the continuous length of time that the control transistor Mc is subjected to a large cross-voltage. Exemplarily, an embodiment of the present invention can make the refresh frequency of the frame picture F=120Hz, and make N≥2. Or, make the refresh frequency of the frame picture F=60Hz, and make N≥4.

[0090] Exemplarily, the embodiment of the present invention can set the frequency of the signal transmitted by the start signal line STV to be greater than or equal to 1440 Hz. Further, the embodiment of the present invention can set the frequency of the signal transmitted by the start signal line STV to be greater than or equal to 1920 Hz.

[0091] Optionally, the embodiment of the present invention can make the effective level duty ratio of the output signal of the emission driving unit 10 less than or equal to the first preset value. Under the action of the effective level, the corresponding sub-pixel can emit light. In this way, the continuous duration of the emission driving unit 10 outputting the effective level can be less than or equal to the preset duration, which can shorten the continuous time that the first and second electrodes of the control transistor Mc are subjected to a large cross-voltage, which is conducive to improving the stability of the control transistor Mc.

[0092] Exemplarily, the first preset value is less than or equal to 99%.

[0093] Optionally, the transmitting driving unit 10 further includes a bootstrap module, one electrode of the bootstrap module is connected to the first node N1, and the other electrode of the bootstrap module is electrically connected to the first clock signal terminal XCK. In the embodiment of the present invention, the duty cycle of the effective level transmitted by the first clock signal terminal XCK is less than or equal to the second preset value.

[0094] For example, Figure 5 As shown, the bootstrap module 8 includes a first capacitor Cst1.

[0095] Optional, such as Fig.12 As shown, Fig.12 A circuit diagram of another transmitting driving unit provided by an embodiment of the present invention, wherein the bootstrap module 8 includes a fourth capacitor Cst4, a fourteenth transistor M14 and a fifteenth transistor M15, wherein the first plate of the fourth capacitor Cst4 is electrically connected to the first node N1, the second plate of the fourth capacitor Cst4 is electrically connected to the first clock signal terminal XCK through the fifteenth transistor M15, and the second plate of the fourth capacitor Cst4 is also electrically connected to the first level signal terminal VGH through the fourteenth transistor M14. The control electrode of the fourteenth transistor M14 is electrically connected to the third node N3, and the control electrode of the fifteenth transistor M15 is electrically connected to the first node N1. Fig.12 In, with Figure 5 The same elements are indicated by the same reference numerals, and their connection relationship and working process are as described above. Figure 5 The description will not be repeated here.

[0096] As mentioned above, when the transmitting drive unit 10 is working, Figure 7 In the first sub-period t21 shown, the first node N1 is at a low level, which is equivalent to the second level provided by the second level signal terminal VGL. After entering the second sub-period t22, when the signal provided by the first clock signal terminal XCK switches from a high level to a low level, under the bootstrap effect of the bootstrap module 8, the potential of the first node N1 will be pulled to a third level lower than the second level provided by the second level signal terminal VGL, until the signal provided by the first clock signal terminal XCK switches from a low level to a high level, the potential of the first node N1 will be pulled up from the third level to the second level. When the first node N1 is at the third level, if the voltage of the first electrode of the control transistor Mc is large, the control transistor Mc will be subjected to a large cross-pressure. The embodiment of the present invention can shorten the continuous time that the potential of the first node N1 is at the third level by shortening the continuous time that the first clock signal terminal XCK is at a low level, thereby shortening the continuous time that the second electrode of the control transistor Mc electrically connected to the first node N1 is at the third level, which is conducive to improving the stability of the control transistor Mc.

[0097] Optionally, the second preset value is less than or equal to 40%.

[0098] Optional, such as Fig.12 and Fig.13 As shown, Fig.13 A circuit diagram of another transmitting driving unit provided by an embodiment of the present invention, in Fig.13 In, with Figure 5 The same elements are indicated by the same reference numerals, and their connection relationship and working process are as described above. Figure 5 The description of the thirteenth transistor M13 is omitted here. The emission driving unit 10 also includes a thirteenth transistor M13, whose control electrode is electrically connected to the second level signal terminal VGL, whose first electrode is electrically connected to the second electrode of the control transistor Mc, and whose second electrode is electrically connected to the first node N1. When the emission driving unit 10 is working, when the first node N1 is in the third level state lower than the low level, the setting of the thirteenth transistor M13 can raise the potential of the second electrode of the control transistor Mc, which is conducive to reducing the cross voltage between the first electrode and the second electrode of the control transistor Mc, and reducing the cross voltage between the control electrode and the second electrode of the control transistor Mc, thereby improving the stability of the control transistor Mc.

[0099] Optional, such as Fig.13As shown, the transmitting driving unit 10 further includes a protection module 9, a first end of the protection module 9 is electrically connected to the control transistor Mc, a second end of the protection module 9 is electrically connected to the first node N1, and the protection module 9 is responsive to a signal of the second clock signal terminal CK, electrically connecting the first node N1 and the control transistor Mc. When the potential of the first node N1 is pulled to a third level lower than the second level under the action of the bootstrap module 8, the setting of the protection module 9 can raise the potential of the second electrode of the control transistor Mc, thereby facilitating the reduction of the cross voltage between the first electrode and the second electrode of the control transistor Mc, and reducing the cross voltage between the control electrode and the second electrode of the control transistor, which is conducive to improving the reliability of the control transistor Mc.

[0100] For example, Fig.13 As shown, the protection module 9 includes a second transistor M2, a control electrode of which is electrically connected to the second clock signal terminal CK, a first electrode of which is electrically connected to the control transistor Mc, and a second electrode of which is electrically connected to the first node N1.

[0101] For example, Fig.13 As shown, the processing module 5 further includes a second processing unit 52, a first end of the second processing unit 52 is electrically connected to the input end IN, a second end of the second processing unit 52 is electrically connected to the first end of the protection module 9, and the second processing unit 52 responds to the signal of the second control signal end C2 to provide the signal of the input end IN to the protection module 9. In the embodiment of the present invention, the second processing unit 52 and the control module 7 work in time-sharing. In the first stage S1, the first control signal end C1 controls the control module 7 to be turned on, and the second control signal end C2 controls the second processing unit 52 to be turned off, so as to provide the signal provided by the adjustment signal end D to the protection module 9. In the second stage S2, the first control signal end C1 controls the control module 7 to be turned off, and the second control signal end C2 controls the second processing unit 52 to be turned on, so as to provide the signal of the input end IN to the protection module 6. As shown in FIG. Fig.14 As shown, the second processing unit 52 includes a third transistor M3 , a control electrode of which is electrically connected to the second control signal terminal C2 , a first electrode of which is electrically connected to the input terminal IN, and a second electrode of which is electrically connected to the protection module 6 .

[0102] For example, Fig.14 As shown, Fig.14 A schematic diagram of another emission driving circuit provided in an embodiment of the present invention, wherein the display panel further includes a first control signal line LC1, a second control signal line LC2 and an adjustment signal line LD; a first control terminal C1 of each emission driving unit 10 is electrically connected to the first control signal line LC1, a second control terminal C2 is electrically connected to the second control signal line LC2, and a first electrode of the control transistor Mc is electrically connected to the adjustment signal line LD.

[0103] For example, Fig.15 As shown, Fig.15 A cross-sectional schematic diagram of a first control signal line LC1 and a second control signal line LC2 provided in an embodiment of the present invention, wherein the first control signal line LC1 and the second control signal line LC2 are arranged in different layers, and the first control signal line LC1 and the second control signal line LC2 do not overlap along a direction perpendicular to the plane where the display panel is located. Fig.15 As shown, along the direction perpendicular to the plane where the display panel is located, an insulating layer 200 is included between the first control signal line LC1 and the second control signal line LC2. Such an arrangement is conducive to reducing the coupling between the first control signal line LC1 and the second control signal line LC2.

[0104] Or, if Fig.16 As shown, Fig.16 Another cross-sectional schematic diagram of a first control signal line LC1 and a second control signal line LC2 is provided for an embodiment of the present invention. The embodiment of the present invention can also make the first control signal line LC1 and the second control signal line LC2 be arranged on the same layer; and make the spacing d between the first control signal line LC1 and the second control signal line LC2 greater than 3μm to reduce the coupling between the first control signal line LC1 and the second control signal line LC2.

[0105] Or, if Fig.17 As shown, Fig.17 A cross-sectional schematic diagram of another first control signal line LC1 and a second control signal line LC2 provided in an embodiment of the present invention, when the first control signal line LC1 and the second control signal line LC2 are arranged in the same layer, as shown in FIG. Fig.17 As shown, in the embodiment of the present invention, a shielding line LP may be provided between the two. Exemplarily, the shielding line LP may be used to receive the first level signal VGH or the second level signal VGL to reduce the coupling between the first control signal line LC1 and the second control signal line LC2.

[0106] Optionally, the first control signal line LC1 has a first parasitic capacitance, the start signal line STV has a second parasitic capacitance, and the first parasitic capacitance is smaller than the second parasitic capacitance, so that in the first stage S1, the first control signal transmitted by the first control signal line LC1 can be quickly transmitted to each level of the emission driving unit 10, so that in the first stage S1, each row of sub-pixels electrically connected to each level of the emission driving unit 10 can be quickly placed in a non-luminous state to avoid the problem of screen flickering.

[0107] Optionally, in the embodiment of the present invention, one of the control transistor Mc and the third transistor M3 may include a P-type transistor, and the other may include an N-type transistor; and the first control signal terminal C1 and the second control signal terminal C2 may be electrically connected. Fig.18 As shown, Fig.18A circuit diagram of another emission driving unit 10 provided in an embodiment of the present invention, wherein the control transistor Mc includes a P-type transistor, the third transistor M3 includes an N-type transistor, and the control electrodes of the two are electrically connected. Such an arrangement can reduce the number of signal lines in the display panel while ensuring that the control transistor Mc and the third transistor M3 are turned on in a time-sharing manner.

[0108] For example, the embodiment of the present invention can make the width-to-length ratio of the channel of the control transistor Mc greater than or equal to the width-to-length ratio of the channel of the first transistor M1. This configuration can make the control transistor Mc have a faster turn-on speed, and when the display panel enters the first stage S1, the control transistor Mc can be turned on quickly to avoid the problem of screen flickering.

[0109] For example, Fig.19 As shown, Fig.19 A circuit diagram of another emission driving unit 10 provided in an embodiment of the present invention is shown, in which the control transistor Mc includes a dual-gate transistor to improve the stability of the control transistor Mc and reduce the risk of failure.

[0110] The embodiment of the present invention further provides a driving method applied to the above display panel, Figure 4 , Figure 5 and Figure 6 As shown, the working process of the display panel includes a first stage S1 and a second stage S2, and the driving method includes: in the first stage S1, controlling the control transistor Mc to be turned on, providing the signal of the adjustment signal terminal D to the first node N1 of the emission driving unit 10, so as to cut off the first output module 61, thereby preventing the emission driving unit 10 from outputting an effective level for controlling the sub-pixel 4 to emit light.

[0111] In the second phase S2 , the control transistor Mc is turned off.

[0112] The driving method for a display panel provided in an embodiment of the present invention can avoid the problem of screen flickering by controlling the first output module 61 to be turned off in the first stage S1, which is conducive to ensuring the display effect of the display panel. Moreover, by turning off the control transistor Mc in the second stage S2, the embodiment of the present invention can avoid the signal of the adjustment signal terminal D from being written into the first node N1 in the second stage S2, so that the signal of the first node N1 can be made independent of the signal of the adjustment signal terminal D in the second stage S2. In the second stage S2, the emission driving unit 10 can provide a pulse signal including an effective level and an ineffective level to the light emitting control signal line Emit through the output terminal OUT under the action of the input terminal IN, the first clock signal terminal XCK, the second clock signal terminal CK, the first level signal terminal VGH and the second level signal terminal VGL, so that the corresponding sub-pixel 4 can be lit at the target brightness, so that the display panel displays an image.

[0113] Optionally, the adjustment signal terminal D is used to transmit a pulse signal including a first level V1, and the first level V1 is used to control the first output module 61 to be turned off; the driving method provided by the embodiment of the present invention also includes:

[0114] During the display time of the frame picture with a frequency of F, the signal transmitted by the control start signal line STV includes at least N pulses, N*F≥240, so that the output signal of the emission driving unit includes N pulses during the display time of the frame picture with a frequency of F, so that the signal output by the emission driving unit 10 switches between the effective level and the ineffective level at a relatively high frequency, so as to avoid the output terminal OUT of the emission driving unit 10 continuously outputting the effective level for a long time. When the emission driving unit 10 outputs the effective level, the first node N1 of the emission driving unit 10 is at the effective level that turns on the first output module 31. When the adjustment signal terminal D connected to the first electrode of the control transistor Mc constantly transmits the ineffective level that turns off the first output module 31, this setting method can shorten the continuous time that the first electrode and the second electrode of the control transistor Mc are subjected to a large cross-voltage, which is conducive to improving the stability of the control transistor Mc.

[0115] Exemplarily, the driving method further includes: controlling the effective level duty cycle of the output signal of the emission driving unit 10 to be less than or equal to a first preset value. Under the action of the effective level, the corresponding sub-pixel 4 emits light. In this way, the continuous duration of the emission driving unit 10 outputting the effective level can be less than or equal to the preset duration, which can shorten the continuous time that the first and second electrodes of the control transistor Mc are subjected to a large cross-voltage, which is conducive to improving the stability of the control transistor Mc.

[0116] Exemplary, combined Figure 5 As shown, the transmitting driving unit 10 further includes a bootstrap module 8, one end of the bootstrap module 8 is electrically connected to the first node N1, and the other end of the bootstrap module 8 is electrically connected to the first clock signal terminal XCK. The driving method provided by the embodiment of the present invention further includes: controlling the duty cycle of the effective level transmitted by the first clock signal terminal XCK to be less than or equal to a second preset value. For example, Figure 5 As shown, the bootstrap module 8 includes a first capacitor Cst1. As mentioned above, when the transmitting driving unit 10 is working, Figure 7In the first sub-period t21 shown, the first node N1 is at a low level, and the low level is equivalent to the signal provided by the second level signal terminal VGL. After entering the second sub-period t22, when the signal provided by the first clock signal terminal XCK switches from a high level to a low level, under the bootstrap action of the bootstrap module 8, the potential of the first node N1 will be pulled to a third level lower than the second level, until the signal provided by the first clock signal terminal XCK switches from a low level to a high level, the potential of the first node N1 will be pulled up from the third level to the second level. When the first node N1 is at the third level, if the voltage of the first electrode of the control transistor Mc is large, the control transistor Mc will be subjected to a large cross-pressure. The embodiment of the present invention can shorten the duration of the potential of the first node N1 at the third level by shortening the continuous duration of the first clock signal terminal XCK being at a low level, thereby shortening the continuous duration of the second electrode of the control transistor Mc electrically connected to the first node N1 being at the third level, which is conducive to improving the reliability of the control transistor Mc.

[0117] The embodiment of the present invention further provides a display device, such as Fig. 20 As shown, Fig. 20 Schematic diagram of a display device provided in an embodiment of the present invention, the display device includes the above-mentioned display panel 100. The specific structure of the display panel 100 has been described in detail in the above-mentioned embodiment, and will not be repeated here. Fig. 20 The display device shown is for illustration only, and the display device may be any electronic device with a display function, such as a mobile phone, a tablet computer, a laptop computer, an e-reader or a television.

[0118] The display device provided by the embodiment of the present invention can adjust the working state of the first output module by setting a control module in the emission driving unit of the display panel. For example, when the machine is turned on and before the first frame of the picture is displayed, or after the machine is turned off, the control module can respond to the signal of the first control signal end to provide the signal of the adjustment signal end to the first node. The signal of the adjustment signal end can turn off the first output module, thereby avoiding the signal of the second level signal end electrically connected to the first output module from being output to the pixel driving circuit, and avoiding the sub-pixel from emitting light. That is, the display panel provided by the embodiment of the present invention can effectively avoid the problem of screen flickering when the display panel is turned on and off, and improve the display effect of the display panel.

[0119] Moreover, the embodiment of the present invention designs the control transistor in the control module, and makes the voltage across any two of the control electrode, the first electrode and the second electrode of the control transistor less than or equal to a preset threshold value, and / or makes the continuous time length that the voltage across any two of the control electrode, the first electrode and the second electrode of the control transistor is greater than the preset threshold value less than or equal to a preset time length, thereby avoiding the control transistor from being in a long-term high bias state, which is beneficial to ensuring the stability of the control transistor.

[0120] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A display panel, characterized in that: A transmitting driving circuit is included, wherein the transmitting driving circuit includes a plurality of cascaded transmitting driving units; The transmitting driving unit comprises: a processing module, electrically connected to the input terminal, the first clock signal terminal, the second clock signal terminal, the first level signal terminal, the second level signal terminal, the first node and the second node, the processing module being used to provide signals to the first node and the second node in response to signals at the first clock signal terminal and the second clock signal terminal; A first output module, electrically connected to the first node, the second level signal terminal and an output terminal, the first output module being used for providing a signal from the second level signal terminal to the output terminal in response to a signal from the first node; A control module includes a control transistor, a control electrode of which is electrically connected to a first control signal terminal, a first electrode of which is electrically connected to an adjustment signal terminal, and a second electrode of which is electrically connected to the first node; the control transistor responds to a signal at the first control signal terminal and provides a signal at the adjustment signal terminal to the first node to turn off the first output module; and The voltage across the control electrode of the control transistor, any two of the first electrode and the second electrode is less than or equal to a preset threshold, and / or the continuous duration for which the voltage across the control electrode of the control transistor, any two of the first electrode and the second electrode is greater than the preset threshold is less than or equal to a preset duration.

2. The display panel according to claim 1, characterized in that: The regulating signal terminal is used to transmit a pulse signal including a first level, and the first level is used to control the first output module to shut down.

3. The display panel according to claim 2, characterized in that: The emission driving circuit further includes a start signal line, which is electrically connected to the input terminal of the first-stage emission driving unit; the start signal line is also electrically connected to the adjustment signal terminal.

4. The display panel according to claim 1, characterized in that: The regulating signal terminal is used to transmit a constant signal, and the constant signal is used to control the first output module to shut down.

5. The display panel according to claim 1, characterized in that: During the display time of a frame picture with a frequency of F, the output signal of the emission driving unit includes at least N pulses, where N*F≥240.

6. The display panel according to claim 5, characterized in that: The emission driving circuit also includes a start signal line, which is electrically connected to the input end of the first-level emission driving unit; within the display time of a frame picture with a frequency of F, the signal transmitted by the start signal line includes at least N pulses, N*F≥240.

7. The display panel according to claim 1, characterized in that: The effective level duty ratio of the output signal of the transmitting driving unit is less than or equal to a first preset value.

8. The display panel according to claim 7, characterized in that: The first preset value is less than or equal to 99%.

9. The display panel according to claim 1, characterized in that: The transmitting driving unit also includes a bootstrap module, one pole of the bootstrap module is connected to the first node, the other pole of the bootstrap module is electrically connected to the first clock signal end, and the duty cycle of the effective level transmitted by the first clock signal end is less than or equal to a second preset value.

10. The display panel according to claim 9, characterized in that: The second preset value is less than or equal to 40%.

11. The display panel according to claim 1, characterized in that: The potential of the non-effective voltage transmitted by the first control signal terminal is V C2 The potential of the ineffective voltage transmitted by the adjustment signal terminal is V S2 ; The ineffective voltage transmitted by the adjustment signal terminal is used to shut down the first output module; | V C2| ≥|V S2 |.

12. The display panel according to claim 1, characterized in that: The processing module includes a first processing unit electrically connected to the first node, the first processing unit includes a first transistor, a control electrode of which is electrically connected to the second clock signal terminal, a first electrode of which is electrically connected to the input terminal, and a second electrode of which is electrically connected to the first node; The width-to-length ratio of the channel of the control transistor is greater than or equal to the width-to-length ratio of the channel of the first transistor.

13. The display panel according to claim 1, characterized in that: The control transistor comprises a dual-gate transistor.

14. The display panel according to claim 1, characterized in that: The emission driving unit also includes a protection module, a first end of the protection module is electrically connected to the control transistor, a second end of the protection module is electrically connected to the first node, and the protection module electrically connects the first node and the control transistor in response to a signal at the second clock signal end.

15. The display panel according to claim 14, characterized in that: The protection module includes a second transistor, a control electrode of which is electrically connected to the second clock signal terminal, a first electrode of which is electrically connected to the control transistor, and a second electrode of which is electrically connected to the first node.

16. The display panel according to claim 14, characterized in that: The processing module also includes a second processing unit, a first end of the second processing unit is electrically connected to the input end, a second end of the second processing unit is electrically connected to the first end of the protection module, and the second processing unit provides the signal of the input end to the protection module in response to a signal of a second control signal end.

17. The display panel according to claim 16, characterized in that: The display panel further includes a first control signal line, a second control signal line and an adjustment signal line; The control electrode of the control transistor is electrically connected to the first control signal line, and the first electrode of the control transistor is electrically connected to the adjustment signal line; The second processing unit includes a third transistor, a control electrode of which is electrically connected to the second control signal line, a first electrode of which is electrically connected to the input end, and a second electrode of which is electrically connected to the protection module.

18. The display panel according to claim 17, characterized in that: The first control signal line and the second control signal line are arranged in different layers, and along a direction perpendicular to the plane where the display panel is located, the first control signal line and the second control signal line do not overlap; or, The first control signal line and the second control signal line are arranged on the same layer; The interval between the first control signal line and the second control signal line is greater than 3 μm, or a shielding line is included between the first control signal line and the second control signal line.

19. The display panel according to claim 17, characterized in that: The emission driving circuit further includes a start signal line, wherein the start signal line is electrically connected to the input end of the first-stage emission driving unit; The first control signal line has a first parasitic capacitance, the start signal line has a second parasitic capacitance, and the first parasitic capacitance is smaller than the second parasitic capacitance.

20. The display panel according to claim 16, characterized in that: The second processing unit includes a third transistor, a control electrode of which is electrically connected to the second control signal terminal, a first electrode of which is electrically connected to the input terminal, and a second electrode of which is electrically connected to the protection module; One of the control transistor and the third transistor includes a P-type transistor, and the other includes an N-type transistor; the first control signal terminal and the second control signal terminal are electrically connected.

21. The display panel according to claim 1, characterized in that: The processing module also includes: a pull-down unit, electrically connected to the first level signal terminal, the third node, the first clock signal terminal and the first node, the pull-down unit being used to provide the signal of the first level signal terminal to the first node in response to the signal of the first clock signal terminal and the third node; a pull-up unit, electrically connected to the first node, the second node, the third node, the first level signal terminal, the first clock signal terminal, the second clock signal terminal and the third node, and configured to transmit a voltage signal to the second node in response to signals of the second clock signal terminal, the first node, the third node and the first clock signal terminal; The transmitting driving unit also includes: The second output module is electrically connected to the second node, the first level signal terminal and the output terminal of the emission driving unit. The second output module electrically connects the first level signal terminal and the output terminal in response to the signal of the second node.

22. The display panel according to claim 21, characterized in that: The pull-down unit includes a fourth transistor and a fifth transistor; The control electrode of the fourth transistor is electrically connected to the third node, the first electrode of the fourth transistor is electrically connected to the first level signal terminal, and the second electrode of the fourth transistor is electrically connected to the first electrode of the fifth transistor; the control electrode of the fifth transistor is electrically connected to the first clock signal terminal, and the second electrode of the fifth transistor is electrically connected to the first node; The pull-up unit comprises: a sixth transistor, wherein a control electrode of the sixth transistor is electrically connected to the second clock signal terminal, a first electrode of the sixth transistor is electrically connected to the second level signal terminal, and a second electrode of the sixth transistor is electrically connected to the third node; a seventh transistor, wherein a control electrode of the seventh transistor is electrically connected to the first node, a first electrode of the seventh transistor is electrically connected to the second clock signal terminal, and a second electrode of the seventh transistor is electrically connected to the third node; an eighth transistor, wherein a control electrode of the eighth transistor is electrically connected to the third node, and a first electrode of the eighth transistor is electrically connected to the first clock signal terminal; a ninth transistor, wherein a control electrode of the ninth transistor is electrically connected to the first clock signal terminal, a first electrode of the ninth transistor is electrically connected to the second electrode of the eighth transistor, and a second electrode of the ninth transistor is electrically connected to the second node; a tenth transistor, wherein a control electrode of the tenth transistor is electrically connected to the first node, a first electrode of the tenth transistor is electrically connected to the first level signal terminal, and a second electrode of the tenth transistor is electrically connected to the second node; The first output module comprises: an eleventh transistor, a control electrode of the eleventh transistor is electrically connected to the first node, a first electrode of the eleventh transistor is electrically connected to the second level signal terminal, and a second electrode of the eleventh transistor is electrically connected to the output terminal; The second output module comprises: a twelfth transistor, a control electrode of the twelfth transistor is electrically connected to the second node, a first electrode of the twelfth transistor is electrically connected to the first level signal terminal, and a second electrode of the twelfth transistor is electrically connected to the output terminal; The transmitting driving unit also includes: A first capacitor, a first plate of the first capacitor is electrically connected to the first node, and a second plate of the first capacitor is electrically connected to the first clock signal terminal a second capacitor, wherein a first plate of the second capacitor is electrically connected to the third node, and a second plate of the second capacitor is electrically connected to a second electrode of the eighth transistor; A third capacitor, wherein a first plate of the third capacitor is electrically connected to the second level signal end, and a second plate of the third capacitor is electrically connected to the second node.

23. A driving method for a display panel according to any one of claims 1 to 22, characterized in that: The working process of the display panel includes a first stage and a second stage, and the driving method includes: In the first stage, the control transistor is controlled to be turned on, and the signal of the adjustment signal terminal is provided to the first node; In the second stage, the control transistor is controlled to be turned off.

24. The driving method according to claim 23, characterized in that: The regulating signal terminal is used to transmit a pulse signal including a first level, and the first level is used to control the first output module to shut down; The emission driving circuit further includes a start signal line, wherein the start signal line is electrically connected to the input end of the first-stage emission driving unit; The driving method further includes: within the display time of the frame picture with a frequency of F, controlling the signal transmitted by the start signal line to include at least N pulses, N*F≥240.

25. The driving method according to claim 23, characterized in that: The driving method further includes: controlling the effective level duty ratio of the output signal of the transmitting driving unit to be less than or equal to a first preset value.

26. The driving method according to claim 23, characterized in that: The transmitting driving unit further comprises a bootstrap module, one end of the bootstrap module is connected to the first node, and the other end of the bootstrap module is electrically connected to the first clock signal end; The driving method further includes: controlling the duty cycle of the effective level transmitted by the first clock signal terminal to be less than or equal to a second preset value.

27. A display device, characterized in that: A display panel comprising any one of claims 1-22.

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