Memory Fault Repair Method, Device, Computer Equipment and Storage Medium

Abstract

The present application relates to a memory fault repair method, apparatus, computer device, storage medium, and computer program product. The present application relates to artificial intelligence technology. The method includes: obtaining target remapping information corresponding to a current faulty interface in a memory; the target remapping information is obtained by reallocating the mapping relationship between each instruction signal bit corresponding to a memory access instruction and an instruction transmission interface among a normal interface and a redundant interface based on the positional relationship between the current faulty interface and other instruction transmission interfaces, and the instruction transmission interface is used for transmitting signal data corresponding to the corresponding instruction signal bit in the memory access instruction; generating a fault repair instruction carrying the target remapping information, and sending the fault repair instruction to the memory, so that the memory receives the memory access instruction through the normal interface and the redundant interface based on the target remapping information, ensuring that the memory correctly receives the memory access instruction.

Description

Technical Field

[0001] This application relates to the field of computer technologies, and in particular, to a method and apparatus for repairing memory faults, a computer device, a storage medium, and a computer program product. Background Art

[0002] With the development of computer technologies, various memories have emerged. For example, High Bandwidth Memory (HBM) is a new type of high-speed and high-bandwidth memory. A device can send a memory access instruction to the memory, and the memory can receive the memory access instruction through an instruction transmission interface.

[0003] In traditional technologies, if a fault occurs in the instruction transmission interface of a memory, the memory cannot normally receive a memory access instruction. Summary of the Invention

[0004] Based on this, it is necessary to provide a method and apparatus for repairing memory faults, a computer device, a computer-readable storage medium, and a computer program product that can normally receive a memory access instruction when a fault occurs in the instruction transmission interface for the above technical problems.

[0005] This application provides a method for repairing memory faults. The method includes:

[0006] Obtain target remapping information corresponding to a current faulty interface in a memory; the target remapping information is obtained by reallocating the mapping relationship between each instruction signal bit corresponding to a memory access instruction and an instruction transmission interface between a normal interface and a redundant interface based on the positional relationship between the current faulty interface and other instruction transmission interfaces, and the instruction transmission interface is used to transmit signal data corresponding to a corresponding instruction signal bit in the memory access instruction;

[0007] Generate a fault repair instruction carrying the target remapping information, and send the fault repair instruction to the memory, so that the memory receives the memory access instruction through the normal interface and the redundant interface based on the target remapping information.

[0008] This application also provides an apparatus for repairing memory faults. The apparatus includes:

[0009] A remapping information acquisition module, configured to acquire target remapping information corresponding to a current faulty interface in a memory; the target remapping information is obtained by reallocating the mapping relationship between each instruction signal bit corresponding to a memory access instruction and an instruction transmission interface between a normal interface and a redundant interface based on the positional relationship between the current faulty interface and other instruction transmission interfaces, and the instruction transmission interface is used to transmit signal data corresponding to the corresponding instruction signal bit in the memory access instruction.

[0010] A fault repair instruction sending module, configured to generate a fault repair instruction carrying the target remapping information, and send the fault repair instruction to the memory, so that the memory receives a memory access instruction through the normal interface and the redundant interface based on the target remapping information.

[0011] A computer device, including a memory and a processor, where the memory stores a computer program, and the processor implements the steps of the above-mentioned memory fault repair method when executing the computer program.

[0012] A computer-readable storage medium, on which a computer program is stored, and the computer program implements the steps of the above-mentioned memory fault repair method when executed by a processor.

[0013] A computer program product, including a computer program, and the computer program implements the steps of the above-mentioned memory fault repair method when executed by a processor.

[0014] The above-mentioned memory fault repair method, device, computer equipment, storage medium and computer program product obtain target remapping information corresponding to the current fault interface in the memory, generate a fault repair instruction carrying the target remapping information, and send the fault repair instruction to the memory, so that the memory receives memory access instructions through the normal interface and the redundant interface based on the target remapping information. Among them, the target remapping information is obtained by reallocating the mapping relationship between each instruction signal bit corresponding to the memory access instruction and the instruction transmission interface in the normal interface and the redundant interface based on the positional relationship between the current fault interface and other instruction transmission interfaces. The instruction transmission interface is used to transmit the signal data corresponding to the corresponding instruction signal bit in the memory access instruction. In this way, if a fault occurs in the instruction transmission interface in the memory, by reallocating the mapping relationship between each instruction signal bit corresponding to the memory access instruction and the instruction transmission interface in the normal interface and the redundant interface, the memory can skip the current fault interface when receiving the memory access instruction and receive the signal data corresponding to each instruction signal bit in the memory access instruction through the normal interface and the redundant interface, so that the memory correctly receives the memory access instruction. Moreover, when reallocating the mapping relationship, the mapping relationships between the normal interface, the redundant interface and the instruction signal bit are reallocated based on the positional relationship between the current fault interface and other instruction transmission interfaces, which enables the memory to intelligently skip the current fault interface when receiving the memory access instruction and orderly receive the signal data corresponding to each instruction signal bit in the memory access instruction through the normal interface and the redundant interface, so that the memory can quickly and accurately receive the memory access instruction. Sending the fault repair instruction carrying the target remapping information corresponding to the current fault interface, which is determined by reallocating the mapping relationship between the instruction signal bit and the instruction transmission interface, to the memory enables the memory to quickly repair the fault, and thus quickly and accurately receive the memory access instruction.

[0015] This application provides a memory fault repair method. The method includes:

[0016] Obtain a fault repair instruction; the fault repair instruction carries target remapping information corresponding to the current fault interface in the memory, and the target remapping information is obtained by reallocating the mapping relationship between each instruction signal bit corresponding to the memory access instruction and the instruction transmission interface in the normal interface and the redundant interface based on the positional relationship between the current fault interface and other instruction transmission interfaces, and the instruction transmission interface is used to transmit the signal data corresponding to the corresponding instruction signal bit in the memory access instruction;

[0017] Based on the target remapping information, receive a memory access instruction through the normal interface and the redundant interface.

[0018] The present application also provides a memory failure repair device. The device includes:

[0019] A failure repair instruction acquisition module, configured to acquire a failure repair instruction; the failure repair instruction carries target remapping information corresponding to a current failure interface in a memory; the target remapping information is obtained by reallocating a mapping relationship between each instruction signal bit corresponding to a memory access instruction and an instruction transmission interface among a normal interface and a redundant interface based on a positional relationship between the current failure interface and other instruction transmission interfaces, and the instruction transmission interface is used to transmit signal data corresponding to a corresponding instruction signal bit in the memory access instruction;

[0020] A memory access instruction receiving module, configured to receive a memory access instruction through the normal interface and the redundant interface based on the target remapping information.

[0021] A computer device includes a memory and a processor, the memory stores a computer program, and when the processor executes the computer program, the steps of the above-mentioned memory failure repair method are implemented.

[0022] A computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the above-mentioned memory failure repair method are implemented.

[0023] A computer program product includes a computer program, and when the computer program is executed by a processor, the steps of the above-mentioned memory failure repair method are implemented.

[0024] The above-mentioned memory fault repair method, device, computer device, storage medium, and computer program product obtain a fault repair instruction, and based on target remapping information, receive memory access instructions through a normal interface and a redundant interface. Among them, the fault repair instruction carries the target remapping information corresponding to the current fault interface in the memory. The target remapping information is obtained by reallocating the mapping relationship between each instruction signal bit corresponding to the memory access instruction and the instruction transmission interface in the normal interface and the redundant interface based on the positional relationship between the current fault interface and other instruction transmission interfaces. The instruction transmission interface is used to transmit the signal data corresponding to the corresponding instruction signal bit in the memory access instruction. In this way, if a fault occurs in the instruction transmission interface in the memory, by reallocating the mapping relationship between each instruction signal bit corresponding to the memory access instruction and the instruction transmission interface in the normal interface and the redundant interface, the memory can skip the current fault interface when receiving the memory access instruction, and receive the signal data corresponding to each instruction signal bit in the memory access instruction through the normal interface and the redundant interface, so that the memory can correctly receive the memory access instruction. Moreover, when reallocating the mapping relationship, the mapping relationships between the normal interface, the redundant interface, and the instruction signal bits are reallocated based on the positional relationship between the current fault interface and other instruction transmission interfaces, which can enable the memory to intelligently skip the current fault interface when receiving the memory access instruction, and orderly receive the signal data corresponding to each instruction signal bit in the memory access instruction through the normal interface and the redundant interface, so that the memory can quickly and accurately receive the memory access instruction. Send the fault repair instruction carrying the target remapping information corresponding to the current fault interface, which is determined by reallocating the mapping relationship between the instruction signal bit and the instruction transmission interface, to the memory, and the memory can quickly perform fault repair, thereby quickly and accurately receiving the memory access instruction. Description of the Drawings

[0025] Figure 1 It is an application environment diagram of the memory fault repair method in an embodiment;

[0026] Figure 2 It is a schematic flowchart of the memory fault repair method in an embodiment;

[0027] ]> Figure 3 It is a schematic diagram for explaining each row instruction in an embodiment;

[0028] Figure 4 It is a schematic diagram for explaining each column instruction in an embodiment;

[0029] Figure 5A It is a schematic diagram of the activation instruction sending timing in an embodiment;

[0030] Figure 5B It is a schematic diagram of the refresh instruction sending timing in an embodiment;

[0031] Figure 5C Schematic diagram of the read instruction sending timing in an embodiment;

[0032] Figure 6A Schematic diagram of the remapping relationship and remapping encoding corresponding to the row instruction transmission interface in an embodiment;

[0033] Figure 6B Schematic diagram of the remapping relationship and remapping encoding corresponding to the column instruction transmission interface in an embodiment;

[0034] Figure 7 Schematic flow chart of the memory fault repair method in another embodiment;

[0035] Figure 8 Schematic flow chart of the memory fault repair method in another embodiment;

[0036] Figure 9 Schematic diagram of the curve of the influence of voltage change and temperature change on clock delay in an embodiment;

[0037] Figure 10 Schematic flow chart of the memory fault repair method in another embodiment;

[0038] Figure 11 Block diagram of the structure of the memory fault repair device in an embodiment;

[0039] Figure 12 Block diagram of the structure of the memory fault repair device in another embodiment;

[0040] Figure 13 Internal structure diagram of a computer device in an embodiment;

[0041] Figure 14 Internal structure diagram of a computer device in another embodiment. Detailed implementation manners

[0042] In order to make the objectives, technical solutions and advantages of the present application clearer, the present application will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0043] Embodiments of the present invention can be applied to various scenarios, including but not limited to cloud technology, artificial intelligence, intelligent transportation, assisted driving, etc.

[0044] Artificial intelligence technology is an interdisciplinary subject that involves a wide range of fields, including both hardware-level and software-level technologies. The basic technologies of artificial intelligence generally include technologies such as sensors, dedicated artificial intelligence chips, cloud computing, distributed storage, big data processing technology, operation / interaction systems, and mechatronics. The software technologies of artificial intelligence mainly include several major directions such as computer vision technology, speech processing technology, natural language processing technology, and machine learning / deep learning.

[0045] The solution provided by the embodiments of this application involves technologies such as artificial intelligence chips and big data processing in artificial intelligence, and will be specifically described through the following embodiments:

[0046] The memory fault repair method provided by the embodiments of this application can be applied to an application environment as Figure 1 shown. Among them, the terminal 102 communicates with the server 104 through the network. The data storage system can store the data that the server 104 needs to process. The data storage system can be integrated on the server 104, or placed in the cloud or on other servers. The terminal 102 can be, but is not limited to, various desktop computers, laptop computers, smart phones, tablet computers, Internet of Things devices, and portable wearable devices. The Internet of Things devices can be smart speakers, smart TVs, smart air conditioners, smart in-vehicle devices, etc. The portable wearable devices can be smart watches, smart bracelets, head-mounted devices, etc. The server 104 can be implemented by an independent server or a server cluster or cloud server composed of multiple servers.

[0047] The server 104 obtains the target remapping information corresponding to the current faulty interface in the memory; the target remapping information is obtained by reallocating the mapping relationship between each instruction signal bit corresponding to the memory access instruction and the instruction transmission interface among the normal interface and the redundant interface based on the positional relationship between the current faulty interface and other instruction transmission interfaces. The instruction transmission interface is used to transmit the signal data corresponding to the corresponding instruction signal bit in the memory access instruction. The server 104 generates a fault repair instruction carrying the target remapping information, and sends the fault repair instruction to the memory, so that the memory receives the memory access instruction through the normal interface and the redundant interface based on the target remapping information.

[0048] The terminal 102 can obtain the target remapping information corresponding to the current faulty interface in the memory; the target remapping information is obtained by reallocating the mapping relationship between each instruction signal bit corresponding to the memory access instruction and the instruction transmission interface in the normal interface and the redundant interface based on the positional relationship between the current faulty interface and other instruction transmission interfaces, and the instruction transmission interface is used to transmit the signal data corresponding to the corresponding instruction signal bit in the memory access instruction. The terminal 102 generates a fault repair instruction carrying the target remapping information and sends the fault repair instruction to the memory, so that the memory can receive the memory access instruction through the normal interface and the redundant interface based on the target remapping information.

[0049] In one embodiment, as Figure 2 shown, a memory fault repair method is provided. This method can be applied to a computer device, which can be a terminal or a server, and can be executed independently by the terminal or the server itself, or can be implemented through the interaction between the terminal and the server. This embodiment takes the application of this method to a computer device as an example for illustration, and includes the following steps:

[0050] Step S202, obtain the target remapping information corresponding to the current faulty interface in the memory; the target remapping information is obtained by reallocating the mapping relationship between each instruction signal bit corresponding to the memory access instruction and the instruction transmission interface in the normal interface and the redundant interface based on the positional relationship between the current faulty interface and other instruction transmission interfaces, and the instruction transmission interface is used to transmit the signal data corresponding to the corresponding instruction signal bit in the memory access instruction.

[0051] Among them, the instruction transmission interface is an interface provided by the memory for transmitting the signal data corresponding to the corresponding instruction signal bit in the memory access instruction, so that the memory can receive the memory access instruction sent externally. The current faulty interface refers to the instruction transmission interface that currently has a fault and has been assigned an initial instruction signal bit. The normal interface refers to the instruction transmission interface that currently has no fault and has been assigned an initial instruction signal bit. The redundant interface refers to the redundant interface that has not been assigned an initial instruction signal bit.

[0052] The memory access instruction is an instruction used to access the memory to implement corresponding operation control on the memory. That is, by sending the memory access instruction to the memory, corresponding operation control on the memory can be achieved. For example, the memory access instruction can be an activation instruction for activating the memory; the memory access instruction can be a refresh instruction for refreshing the data stored in the memory; and so on. It can be understood that a memory access instruction can include multiple instruction signal bits, and each instruction signal bit is respectively used to store corresponding signal data. For example, the memory access instruction includes six-bit data, and any one bit of data represents a signal data, and any one bit of data corresponds to an instruction signal bit.

[0053] In the memory, except for the redundant interface, each instruction transmission interface has a corresponding initial instruction signal bit. That is, except for the redundant interface, there is an initial mapping relationship between each instruction transmission interface and each instruction signal bit. The initial instruction signal bit refers to the instruction signal bit corresponding to the start of each instruction transmission interface, and the instruction signal bit that each instruction transmission interface defaults to. The initial mapping relationship refers to the mapping relationship between the instruction transmission interface and the corresponding initial instruction signal bit. For example, assume that the memory includes eight instruction transmission interfaces, namely instruction transmission interfaces A - H, where instruction transmission interface H is the redundant interface. The memory access instruction includes seven - bit data, and the memory access instruction corresponds to seven instruction signal bits, namely instruction signal bits a - g. The initial instruction signal bit corresponding to instruction transmission interface A is a, the initial instruction signal bit corresponding to instruction transmission interface B is b, the initial instruction signal bit corresponding to instruction transmission interface C is c, the initial instruction signal bit corresponding to instruction transmission interface D is d, the initial instruction signal bit corresponding to instruction transmission interface E is e, the initial instruction signal bit corresponding to instruction transmission interface F is f, and the initial instruction signal bit corresponding to instruction transmission interface G is g. There is no corresponding initial instruction signal bit for the redundant interface for the time being. If instruction transmission interface A fails, then the current faulty interface is instruction transmission interface A, the normal interfaces are instruction transmission interfaces B - H, and the redundant interface is instruction transmission interface H.

[0054] Each instruction transmission interface has its own corresponding remapping information. The remapping information is used to perform corresponding fault repair on the memory when the corresponding instruction transmission interface fails. The target remapping information refers to the remapping information corresponding to the current faulty interface. The remapping information is obtained by re - distributing the mapping relationship between each instruction signal bit corresponding to the memory access instruction and the instruction transmission interface among the normal interfaces and the redundant interface based on the positional relationship between the faulty interface and other instruction transmission interfaces. The target remapping information is obtained by re - distributing the mapping relationship between each instruction signal bit corresponding to the memory access instruction and the instruction transmission interface among the normal interfaces and the redundant interface based on the positional relationship between the current faulty interface and other instruction transmission interfaces.

[0055] Based on the positional relationship between the current faulty interface and other instruction transmission interfaces, in the normal interface and the redundant interface, re - allocate the mapping relationship between each instruction signal bit corresponding to the memory access instruction and the instruction transmission interface, so that when the memory receives the memory access instruction, based on the re - allocated mapping relationship, it transmits the signal data on the corresponding instruction signal bit in the memory access instruction through the normal interface and the redundant interface. The memory reads the signal data transmitted from the normal interface and the redundant interface in sequence according to the position sorting of the instruction transmission interface, and then the complete memory access instruction can be obtained. When the memory receives the memory access instruction, there is no need to first read the signal data and then arrange the signal data. By reading the signal data transmitted from the normal interface and the redundant interface in sequence according to the position sorting of the instruction transmission interface, the complete memory access instruction can be obtained quickly.

[0056] It can be understood that there can be at least one redundant interface in the memory.

[0057] In one embodiment, send a memory test instruction to the memory; obtain the instruction response signal returned by the memory; the instruction response signal includes a check signal; determine the working state of the memory based on the check signal; when the working state is a faulty state, determine the current faulty interface by detecting the working state corresponding to each instruction transmission interface.

[0058] Specifically, when determining the current faulty interface, the computer device can first determine whether the memory has a fault, and then determine which specific instruction transmission interface has a fault. The computer device can send a memory test instruction to the memory, and the memory can return an instruction response signal to the computer device. The computer device determines the working state of the memory based on the check signal in the instruction response signal returned by the memory. If the check signal is a preset signal, it is determined that the working state of the memory is a normal state, and there is no faulty instruction transmission interface in the memory currently, and the memory can receive the memory access instruction correctly. If the check signal is not a preset signal, it is determined that the working state of the memory is a faulty state, and there is a faulty instruction transmission interface in the memory currently, and the memory can no longer receive the memory access instruction correctly. When the working state of the memory is a faulty state, further determine which instruction transmission interface has a fault. The computer device can determine the current faulty interface by detecting the working state corresponding to each instruction transmission interface. For example, the working state corresponding to each instruction transmission interface can be detected through the EXTEST test mode (which can also be called external test), and the instruction transmission interface with the working state of faulty state is used as the current faulty interface.

[0059] Step S204, generate a fault repair instruction carrying the target remapping information, and send the fault repair instruction to the memory, so that the memory receives the memory access instruction through the normal interface and the redundant interface based on the target remapping information.

[0060] The fault repair instruction is an instruction for instructing the memory to perform fault repair.

[0061] Specifically, the computer device determines the current faulty interface in the memory, obtains the target remapping information corresponding to the current faulty interface in the memory locally or from another device, generates a fault repair instruction carrying the target remapping information, and sends the fault repair instruction to the memory. Based on the target remapping information, the memory can skip the current faulty interface and receive memory access instructions through the normal interface and the redundant interface.

[0062] In one embodiment, a high-bandwidth memory system is deployed in a computer device, and the high-bandwidth memory system includes a host and a memory. The computer device can obtain target remapping information corresponding to a currently faulty interface in the memory through the host, generate a fault repair instruction carrying the target remapping information through the host, and send the fault repair instruction to the memory through the host.

[0063] In one embodiment, the memory may be a dynamic random access memory, a random access memory, or other types of memory.

[0064] In one embodiment, the memory access instruction includes a row instruction and a column instruction. Accordingly, the memory includes a row instruction transmission interface for transmitting signal data corresponding to the row instruction signal bit corresponding to the row instruction, and a column instruction transmission interface for transmitting signal data corresponding to the column instruction signal bit corresponding to the column instruction. If the current fault interface is a row instruction fault interface, the target remapping information is obtained by reallocating the mapping relationship between each row instruction signal bit corresponding to the memory access instruction and the row instruction transmission interface in the normal row instruction interface and the redundant row instruction interface based on the positional relationship between the row instruction fault interface and the other row instruction transmission interfaces. If the current fault interface is a column instruction fault interface, the target remapping information is obtained by reallocating the mapping relationship between each column instruction signal bit corresponding to the memory access instruction and the column instruction transmission interface in the normal column instruction interface and the redundant column instruction interface based on the positional relationship between the column instruction fault interface and the other column instruction transmission interfaces.

[0065] In one embodiment, Figure 3As shown, the row instructions may specifically include a Row NoOperation instruction, an Activate instruction, a Precharge instruction, a Precharge All instruction, a Single Bank Refresh instruction, a Refresh instruction, a Power-Down Entry instruction, a SelfRefresh Entry instruction, and a Power-Down / Self Refresh Exit instruction. The row instructions correspond to seven row instruction signal bits from R0 to R6, that is, the row instructions include seven fields. Among them, the H field represents 1, the L field represents 0, the V field may represent 1 or 0, the PAR (Parity) field represents the instruction check field, the BA (BankAddress) field represents the Bank address, the RA (Row Address) field represents the row address, and the SID (Stack ID) represents the identification number of the stack.

[0066] In one embodiment, as Figure 4 shown, the column instructions may specifically include a Column NoOperation instruction, a Read instruction, a Read w / AP (Read with AutoPrecharge) instruction, a Write instruction, a Write w / AP (Write withAuto Precharge) instruction, and a Mode Register Set instruction. The column instructions correspond to nine column instruction signal bits from C0 to C8, that is, the column instructions include nine fields. Among them, the H field represents 1, the L field represents 0, the V field may represent 1 or 0, the PAR field represents the instruction check field, the BA field represents the Bank address, the CA (Column Address) field represents the column address, the SID represents the identification number of the stack, and the OP field represents the operation code.

[0067] It can be understood that for the number of row instruction signal bits and column instruction signal bits, the embodiments of the present application are only for illustration and do not specifically limit the number of row instruction signal bits and column instruction signal bits.

[0068] The computer device needs to send corresponding signal data according to the timing that each instruction follows. For example, as Figure 5A shown, with reference to Figure 3According to the details of the activation instruction (i.e., the Activate instruction) in [reference], each field in the activation instruction (corresponding to R0 to R6) needs to be sent at the corresponding timing. The activation instruction is a two-cycle instruction and occupies two clock cycles. As Figure 5B shown, after referring to Figure 3 the details of the refresh instruction (i.e., the Refresh instruction) in [reference], each field in the refresh instruction (corresponding to R0 to R6) needs to be sent at the corresponding timing. The refresh instruction is a single-cycle instruction and occupies one clock cycle. As Figure 5C shown, after referring to Figure 4 the details of the read instruction (i.e., the Read instruction) in [reference], each field in the read instruction (corresponding to C0 to C8) needs to be sent at the corresponding timing. Among them, Clock 1 and Clock 2 are two differential clocks. EN AP (Enable Auto Precharge) means to start auto precharge. DIS AP (Disable Auto Precharge) means to disable auto precharge.

[0069] The transmission of memory access instructions is vulnerable to environmental changes in PVT (Precess Valid Temperature, process voltage temperature) and crosstalk between signals, which may cause faults or damages in the instruction transmission interface during the operation of the memory. Through the memory fault repair method of the present application, when some instruction transmission channels of the memory have operating faults, by reallocating the mapping relationship between each instruction signal bit corresponding to the memory access instruction and the instruction transmission interface between the normal interface and the redundant interface, the repair process can be quickly carried out to ensure that the memory correctly receives the memory access instruction.

[0070] In the above memory fault repair method, by obtaining the target remapping information corresponding to the current fault interface in the memory, generating a fault repair instruction carrying the target remapping information, and sending the fault repair instruction to the memory, so that the memory, based on the target remapping information, receives memory access instructions through the normal interface and the redundant interface. Among them, the target remapping information is obtained by reallocating the mapping relationship between each instruction signal bit corresponding to the memory access instruction and the instruction transmission interface in the normal interface and the redundant interface based on the positional relationship between the current fault interface and other instruction transmission interfaces. The instruction transmission interface is used to transmit the signal data corresponding to the corresponding instruction signal bit in the memory access instruction. In this way, if a fault occurs in the instruction transmission interface in the memory, by reallocating the mapping relationship between each instruction signal bit corresponding to the memory access instruction and the instruction transmission interface in the normal interface and the redundant interface, the memory can skip the current fault interface when receiving the memory access instruction, and receive the signal data corresponding to each instruction signal bit in the memory access instruction through the normal interface and the redundant interface, so that the memory correctly receives the memory access instruction. Moreover, when reallocating the mapping relationship, the mapping relationships between the normal interface, the redundant interface and the instruction signal bit are reallocated based on the positional relationship between the current fault interface and other instruction transmission interfaces, which can enable the memory to intelligently skip the current fault interface when receiving the memory access instruction, and orderly receive the signal data corresponding to each instruction signal bit in the memory access instruction through the normal interface and the redundant interface, so that the memory can receive the memory access instruction quickly and accurately. Sending the fault repair instruction carrying the target remapping information corresponding to the current fault interface, which is determined by reallocating the mapping relationship between the instruction signal bit and the instruction transmission interface, to the memory, the memory can quickly perform fault repair, and thus quickly and accurately receive the memory access instruction.

[0071] In one embodiment, the memory fault repair method further includes:

[0072] Obtaining interface position sorting information; determining a candidate fault interface from each instruction transmission interface; generating remapping information corresponding to the candidate fault interface based on the interface position sorting information and the interface position corresponding to the candidate fault interface; the remapping information is used to indicate that the initial mapping relationship between the forward interface of the candidate fault interface and the initial instruction signal bit remains unchanged, and establishing a mapping relationship between the candidate fault interface and the initial instruction signal bits corresponding to the backward interface of the candidate fault interface and their respective adjacent backward fault-free interfaces; taking the next instruction transmission interface as the candidate fault interface, and returning to execute the step of generating the remapping information corresponding to the candidate fault interface based on the interface position sorting information and the interface position corresponding to the candidate fault interface until the remapping information corresponding to each instruction transmission interface is obtained.

[0073] Among them, the interface position sorting information is used to represent the sorting of the interface positions of each instruction transmission interface. The candidate faulty interface refers to the instruction transmission interface assumed to have a fault. The forward interface refers to the instruction transmission interface arranged before the candidate faulty interface. The backward interface refers to the instruction transmission interface arranged after the candidate faulty interface. The initial mapping relationship refers to the mapping relationship between the instruction transmission interface and the corresponding initial instruction signal bit. The initial instruction signal bit refers to the instruction signal bit corresponding to the start of each instruction transmission interface, and the instruction signal bit that each instruction transmission interface defaults to correspond to. The adjacent backward fault-free interface refers to the interface that is adjacent to an instruction transmission interface, arranged after the instruction transmission interface, and has no fault.

[0074] Specifically, the computer device can obtain the interface position sorting information and generate remapping information corresponding to each instruction transmission interface based on the interface position sorting information. The computer device can randomly select an instruction transmission interface from each instruction transmission interface as the candidate faulty interface, and generate the remapping information corresponding to the candidate faulty interface based on the interface position sorting information and the interface position corresponding to the candidate faulty interface. The remapping information is used to indicate that the initial mapping relationship between the forward interface of the candidate faulty interface and the instruction signal bit remains unchanged, and a new mapping relationship is established between the initial instruction signal bits corresponding to the candidate faulty interface and the backward interface of the candidate faulty interface and their respective adjacent backward fault-free interfaces.

[0075] For example, assume that the memory includes eight instruction transmission interfaces, namely instruction transmission interfaces A - E, where instruction transmission interface E is a redundant interface, and the interface sorting information is A - B - C - D - E. The memory access instruction corresponds to four instruction signal bits, namely instruction signal bits a - d. The initial instruction signal bit corresponding to instruction transmission interface A is a, the initial instruction signal bit corresponding to instruction transmission interface B is b, the initial instruction signal bit corresponding to instruction transmission interface C is c, the initial instruction signal bit corresponding to instruction transmission interface D is d, and there is no corresponding initial instruction signal bit for the redundant interface for the time being. If instruction transmission interface B has a fault, then among the normal interfaces and the redundant interface, the mapping relationship between instruction transmission interface A and instruction signal bit a remains unchanged, a new mapping relationship is established between instruction transmission interface C and instruction signal bit b, a new mapping relationship is established between instruction transmission interface D and instruction signal bit c, and a new mapping relationship is established between instruction transmission interface E and instruction signal bit d. The remapping information corresponding to instruction transmission interface B is used to indicate that the memory transmits the signal data corresponding to instruction signal bits a - c in sequence through instruction transmission interfaces A, C, D, and E.

[0076] The generation method of the remapping information corresponding to each instruction transmission interface is similar. The computer device can use the next instruction transmission interface as a new candidate faulty interface, and generate the remapping information corresponding to the candidate faulty interface based on the interface position sorting information and the interface position corresponding to the candidate faulty interface. Finally, the computer device can obtain the remapping information corresponding to each instruction transmission interface respectively.

[0077] In one embodiment, the interface position sorting information can be sorted in ascending order or in descending order, and can be specifically determined according to the factory interface configuration of the memory or according to actual needs.

[0078] In one embodiment, the instruction transmission interface includes a row instruction transmission interface and a column instruction transmission interface. The row instruction transmission interface and the column instruction transmission interface independently generate the remapping information corresponding to each of them.

[0079] In the above embodiment, based on the interface position sorting information and the interface position corresponding to the candidate faulty interface, the remapping information corresponding to the candidate faulty interface is generated; the remapping information is used to indicate that the initial mapping relationship between the forward interface of the candidate faulty interface and the initial instruction signal bit remains unchanged, and the initial instruction signal bits corresponding to the candidate faulty interface and the backward interface of the candidate faulty interface are mapped to the adjacent backward fault-free interfaces corresponding to them. In this way, there is no need to modify the mapping relationship for all normal interfaces and redundant interfaces, and only the mapping relationship for the candidate faulty interface and the backward interface of the candidate faulty interface needs to be modified, which can ensure the modification efficiency. Further, the memory sequentially reads the signal data transmitted from the normal interface and the redundant interface according to the interface position sorting information, and can quickly obtain the complete memory access instruction, which helps to improve the reading efficiency of the memory access instruction.

[0080] In one embodiment, generating the remapping information corresponding to the candidate faulty interface based on the interface position sorting information and the interface position corresponding to the candidate faulty interface includes:

[0081] Based on the interface position sorting information and the interface position corresponding to the candidate faulty interface, determine the remapping relationship corresponding to the candidate faulty interface; the remapping relationship includes the re-determined mapping relationship between other instruction transmission interfaces and instruction signal bits in the case of the candidate faulty interface failing; generate the remapping code corresponding to the remapping relationship, and obtain the remapping information corresponding to the candidate faulty interface based on the remapping code.

[0082] Among them, the remapping code is an abbreviated representation of the remapping relationship, and can effectively reduce the amount of data transmitted between the computer device and the memory by using simple encoded data to represent complex remapping relationships.

[0083] Specifically, to reduce the amount of data sent, the computer device and the memory can pre - agree on the remapping relationship between other instruction transfer interfaces and instruction signal bits when any instruction transfer interface fails. Specifically, the remapping relationship can be represented by a remapping code. The computer device does not need to send the complex remapping relationship to the memory each time, but only needs to send the remapping code to the memory. The memory can quickly perform fault repair based on the remapping relationship corresponding to the remapping code and correctly receive the memory access instruction through the normal interface and the redundant interface.

[0084] When generating remapping information, the computer device can determine the remapping relationship corresponding to the candidate fault interface based on the interface position sorting information and the interface position corresponding to the candidate fault interface. The remapping relationship includes the mapping relationship re - determined between other instruction transfer interfaces and instruction signal bits in the case of the candidate fault interface failing. Furthermore, the computer device can generate a remapping code corresponding to the remapping relationship, and obtain the remapping information corresponding to the candidate fault interface based on the remapping code. The remapping information includes the remapping code. The computer device sends the fault repair instruction carrying the remapping code to the memory. The memory can quickly determine the remapping relationship corresponding to the remapping code based on the remapping code, transmit the signal data on the corresponding instruction signal bits indicated by the remapping relationship through the normal interface and the redundant interface, and sequentially read the signal data transmitted by the normal interface and the redundant interface to obtain the complete memory access instruction.

[0085] In one embodiment, the remapping code includes the interface identifier corresponding to the candidate fault interface. After receiving the fault repair instruction, the memory can quickly determine the instruction transfer interface that has failed currently based on the fault interface identifier carried in the fault repair instruction, determine its corresponding remapping relationship, and correctly receive the memory access instruction through the normal interface and the redundant interface.

[0086] In the above - mentioned embodiment, based on the interface position sorting information and the interface position corresponding to the candidate fault interface, the remapping relationship corresponding to the candidate fault interface is determined, the remapping code corresponding to the remapping relationship is generated, and the remapping information corresponding to the candidate fault interface is obtained based on the remapping code. In this way, when an instruction transfer interface of the memory fails subsequently, the fault can be quickly repaired by sending the remapping code to the memory, effectively improving the repair efficiency.

[0087] In one embodiment, the remapping code is encoded data with a preset code length, and different instruction transfer interfaces correspond to different remapping codes; among all the candidate encoded data corresponding to the preset code length, except for the remapping codes corresponding to each instruction transfer interface, other encoded data is used to represent that the initial mapping relationship between the instruction transfer interface and the instruction signal bit remains unchanged.

[0088] Specifically, an agreement can be made between the computer device and the memory to use encoded data with a preset encoding length as the remapping encoding. To distinguish different instruction transmission interfaces, different instruction transmission interfaces correspond to different remapping encodings. To avoid the memory from being unable to recognize or misrecognize, among the candidate encoded data corresponding to the preset encoding length, except for the remapping encodings corresponding to each instruction transmission interface, the remaining encoded data is used to represent that the initial mapping relationship between the instruction transmission interface and the initial instruction signal bit remains unchanged.

[0089] In one embodiment, the instruction transmission interface includes a row instruction transmission interface. Refer to Figure 6A , Rx0 to RRx represent the row instruction transmission interface, and RRx represents the redundant interface in the row instruction transmission interface. The x in Rx0 to RRx represents the xth instruction channel. It can be understood that the memory may include at least one instruction channel. Figure 6A The XX in [[ ]] indicates that the corresponding row instruction transmission interface has a fault. If Rx0 has a fault, the corresponding remapping encoding is 0000; if Rx1 has a fault, the corresponding remapping encoding is 0001; if Rx2 has a fault, the corresponding remapping encoding is 0010; if Rx3 has a fault, the corresponding remapping encoding is 0011; if Rx4 has a fault, the corresponding remapping encoding is 0100; if Rx5 has a fault, the corresponding remapping encoding is 0101; if Rx6 has a fault, the corresponding remapping encoding is 0110.

[0090] Taking Rx0 as an example, if Rx0 has a fault, the corresponding remapping relationship is used to represent that the signal data on the initial instruction signal bit corresponding to Rx6 is still transmitted through Rx6, the signal data on the initial instruction signal bit corresponding to Rx0 is transmitted through Rx1, the signal data on the initial instruction signal bit corresponding to Rx1 is transmitted through Rx2, the signal data on the initial instruction signal bit corresponding to Rx2 is transmitted through Rx3, the signal data on the initial instruction signal bit corresponding to Rx3 is transmitted through Rx4, the signal data on the initial instruction signal bit corresponding to Rx4 is transmitted through Rx5, and the signal data on the initial instruction signal bit corresponding to Rx5 is transmitted through RRx.

[0091] If the row instruction transmission interface has no fault, the corresponding encoded data is 1111, and the corresponding mapping relationship is used to represent that the initial mapping relationship remains unchanged. If the row instruction transmission interface has no fault, the redundant interface RRx is idle. Limited by the number of row instruction transmission interfaces, the remaining encoded data from 0111 to 1110 is temporarily reserved. To avoid the memory from being unable to recognize or misrecognize, the encoded data from 0111 to 1110 can also have corresponding remapping relationships, and the remapping relationships corresponding to the encoded data from 0111 to 1110 are used to represent that the initial mapping relationship remains unchanged. In this way, even if the memory receives any data from 0111 to 1110, the memory will not fail to recognize or misrecognize it as other remapping relationships.

[0092] In one embodiment, the instruction transmission interface includes a column instruction transmission interface. Refer to Figure 6B , Cx0 to RCx represent column instruction transmission interfaces, and RCx represents the redundant interface in the column instruction transmission interfaces. The x in Cx0 to RCx represents the xth instruction channel. Figure 6B The XX in

[0093] means that the corresponding row instruction transmission interface has a fault. If Cx0 fails, the corresponding remapped code is 0000; if Cx1 fails, the corresponding remapped code is 0001; if Cx2 fails, the corresponding remapped code is 0010; if Cx3 fails, the corresponding remapped code is 0011; if Cx4 fails, the corresponding remapped code is 0100; if Cx5 fails, the corresponding remapped code is 0101; if Cx6 fails, the corresponding remapped code is 0110; if Cx7 fails, the corresponding remapped code is 0111; if Cx8 fails, the corresponding remapped code is 1000.

[0093] It can be understood that as the number of instruction transmission interfaces increases, the remaining encoded data can also be used as remapped codes. As the number of instruction transmission interfaces increases, the encoding length of the encoded data can also increase. Figure 6A and Figure 6B are only for illustrative purposes and do not constitute specific limitations on the values of the remapped codes corresponding to each instruction transmission interface. For example, the remapped code corresponding to Rx0 can be set to 1110.

[0094] In the above embodiments, the remapped code is encoded data of a preset encoding length, and different instruction transmission interfaces correspond to different remapped codes. Through the remapped codes, the faulty instruction transmission interfaces can be effectively distinguished. Further, among the candidate encoded data corresponding to the preset encoding length, except for the remapped codes corresponding to each instruction transmission interface, other encoded data is used to represent that the initial mapping relationship between the instruction transmission interface and the instruction signal bit remains unchanged, and other encoded data can avoid the memory from being unable to recognize or misrecognize, and avoid the memory from being misrepaired.

[0095] In one embodiment, the memory failure repair method further includes: sending the remapping relationships and remapping encodings respectively corresponding to each instruction transmission interface to the memory, so that the memory stores the remapping relationships and remapping encodings.

[0096] Generating a failure repair instruction carrying target remapping information and sending the failure repair instruction to the memory includes: generating a failure repair instruction carrying a target remapping encoding corresponding to the current failed interface, and sending the failure repair instruction to the memory, so that the memory obtains the target remapping relationship corresponding to the target remapping encoding, and based on the target remapping relationship, receives memory access instructions through normal interfaces and redundant interfaces.

[0097] Specifically, after determining the remapping relationships and remapping encodings respectively corresponding to each instruction transmission interface, the computer device can send the remapping relationships and remapping encodings respectively corresponding to each instruction transmission interface to the memory, and the memory stores the remapping relationships and remapping encodings respectively corresponding to each instruction transmission interface. Thus, when the memory subsequently receives a failure repair instruction carrying a target remapping encoding corresponding to the current failed interface, it can quickly obtain the target remapping relationship corresponding to the target remapping encoding, and quickly receive memory access instructions through normal interfaces and redundant interfaces based on the target remapping relationship.

[0098] In the above embodiment, sending the remapping relationships and remapping encodings respectively corresponding to each instruction transmission interface to the memory, so that the memory stores the remapping relationships and remapping encodings, can enable the memory to quickly perform failure repair based on the remapping relationship when receiving the remapping encoding corresponding to the failed interface subsequently, so as to correctly receive the failure repair instruction.

[0099] In one embodiment, as Figure 7 shown, generating a failure repair instruction carrying target remapping information and sending the failure repair instruction to the memory includes:

[0100] Step S702, generating update configuration information corresponding to a target register in the memory based on the target remapping information; the target register is used to indicate the receiving manner of the memory for receiving memory access instructions.

[0101] Step S704, generating a failure repair instruction carrying the update configuration information and sending the failure repair instruction to the memory, so that the memory updates the current configuration information corresponding to the target register based on the update configuration information.

[0102] Wherein, the memory may include a target register, and the target register is used to indicate the receiving manner of the memory for receiving memory access instructions, that is, the target register is used to indicate the transmission manner and transmission mode of the memory for currently transmitting signal data through the instruction transmission interface.

[0103] The current configuration information refers to the current configuration information of the target register, and the updated configuration information refers to the new configuration information of the target register, which is used to update the current configuration information.

[0104] Specifically, a target register for determining the receiving mode of the received memory access instruction is provided in the memory. The memory can determine the receiving mode of the received memory access instruction based on the configuration information of the target register. Correspondingly, the target remapping information can be used to modify the configuration information of the target memory to achieve the purpose of adjusting the receiving mode of the received memory access instruction. After the computer device obtains the target remapping information corresponding to the current faulty interface, it can generate the updated configuration information corresponding to the target register based on the target remapping information. Furthermore, the computer device generates a fault repair instruction carrying the updated configuration information and sends the fault repair instruction to the memory. After receiving the fault repair instruction, the memory can update the current configuration information corresponding to the target register based on the updated configuration information. Thus, when the memory subsequently receives a memory access instruction, it can, based on the latest configuration information of the target register, know to transmit the signal data on the corresponding instruction signal bits through the currently known normal interface and redundant interface, so as to correctly receive the memory access instruction.

[0105] In the above embodiment, the updated configuration information corresponding to the target register in the memory is generated based on the target remapping information, a fault repair instruction carrying the updated configuration information is generated, and the fault repair instruction is sent to the memory, so that the memory updates the current configuration information corresponding to the target register based on the updated configuration information. In this way, once the current faulty interface is determined, the configuration information of the target register in the memory is modified, so that the memory can determine how to correctly receive the memory access instruction based on the configuration information of the target register, and finally, when receiving the memory access instruction, it can successfully skip the current faulty interface and correctly receive the memory access instruction. Setting up a dedicated target register to indicate the receiving mode of the memory for receiving memory access instructions can ensure that the memory can correctly receive memory access instructions at any time.

[0106] In one embodiment, the memory includes a row instruction transmission interface for transmitting the signal data corresponding to the row instruction signal bits and a column instruction transmission interface for transmitting the signal data corresponding to the column instruction signal bits. The updated configuration information includes the target remapping information and the interface type information corresponding to the current faulty interface; the interface type information is used to indicate that the memory modifies the field information in the current configuration information that matches the interface type corresponding to the current faulty interface based on the target remapping information; the configuration information of the target register includes a first field for determining the mapping relationship corresponding to the row instruction transmission interface and a second field for determining the mapping relationship corresponding to the column instruction transmission interface.

[0107] Specifically, the memory includes a row instruction transmission interface for transmitting signal data corresponding to row instruction signal bits and a column instruction transmission interface for transmitting signal data corresponding to column instruction signal bits. To effectively distinguish whether the current faulty interface is a row instruction transmission interface or a column instruction transmission interface and to ensure that the memory correctly repairs the faulty instruction transmission interface, the updated configuration information may include, in addition to the target remapping information, interface type information corresponding to the current faulty interface. The interface type information can identify the interface type corresponding to the current faulty interface.

[0108] Furthermore, to effectively distinguish whether the current faulty interface is a row instruction transmission interface or a column instruction transmission interface and to ensure that the memory correctly repairs the faulty instruction transmission interface, the configuration information of the target memory includes a first field for determining the mapping relationship corresponding to the row instruction transmission interface and a second field for determining the mapping relationship corresponding to the column instruction transmission interface. The interface type information in the updated configuration information is used to instruct the memory to modify the field information in the current configuration information that matches the interface type corresponding to the current faulty interface based on the target remapping information. If the current faulty interface is a row instruction transmission interface, the target remapping information in the updated configuration information is used to update the field information of the first field. If the current faulty interface is a column instruction transmission interface, the target remapping information in the updated configuration information is used to update the field information of the second field.

[0109] For example, the configuration information of the target register is shown in Table 1. Bits 36 - 39 in the configuration information are the first field for remapping the row instruction transmission interface. Bits 32 - 35 in the configuration information are the second field for remapping the column instruction transmission interface.

[0110] If the field information of the first field is h0, the current faulty interface is the row instruction interface ROW0; if the field information of the first field is h1, the current faulty interface is the row instruction interface ROW1; if the field information of the first field is h2, the current faulty interface is the row instruction interface ROW2; if the field information of the first field is h3, the current faulty interface is the row instruction interface ROW3; if the field information of the first field is h4, the current faulty interface is the row instruction interface ROW4; if the field information of the first field is h5, the current faulty interface is the row instruction interface ROW5; if the field information of the first field is h6, the current faulty interface is the row instruction interface ROW6; if the field information of the first field is hF, there is no current faulty interface. h7 to hE have no specific function for the time being. If the number of row instruction interfaces increases, h7 to hE can be utilized.

[0111] Correspondingly, if the field information of the second field is h0 to h8, the current faulty interface is the column instruction interface COL0 to COL8; if the field information of the second field is hF, there is no current faulty interface. h9 to hE have no specific function temporarily. If the number of column instruction interfaces increases, h7 to hE can be utilized. Here, h represents hexadecimal.

[0112] Table 1

[0113]

[0114]

[0115] For example, if Rx2 (i.e., ROW2) is damaged, the configuration table corresponding to the updated configuration information is shown in Table 2.

[0116] Table 2

[0117] Bit domain describe 71:40 Reserved 32'hFFFFFFFF 39:36 AWORD_ROW[3:0] 4’h2 35:32 AWORD_COL[3:0] 4'hF 31:0 Reserved 32'hFFFFFFFF

[0118] If Cx8 (i.e., COL8) is damaged, the configuration table corresponding to the updated configuration information is shown in Table 3.

[0119] Table 3

[0120] Bit domain describe 71:40 Reserved 32'hFFFFFFFF 39:36 AWORD_ROW[3:0] 4'hF 35：32 AWORD_COL[3:0] 4’h8 31:0 Reserved 32'hFFFFFFFF

[0121] It can be understood that the updated configuration information may include all the data in bits 0 - 71. Then the memory only needs to replace the current configuration information as a whole based on the updated configuration information. The updated configuration information may also only include the data in bits 32 - 35 or 36 - 39. Then the memory only needs to replace the field information of the second field or the first field in the current configuration information based on the updated configuration information.

[0122] In the above embodiments, the configuration information of the target register includes a first field for determining the mapping relationship corresponding to the row instruction transmission interface and a second field for determining the mapping relationship corresponding to the column instruction transmission interface. The updated configuration information includes the target remapping information and the interface type information corresponding to the current faulty interface. The interface type information is used to instruct the memory to modify the field information in the current configuration information that matches the interface type corresponding to the current faulty interface based on the target remapping information. In this way, the memory can quickly determine which instruction transmission interface has a fault based on the first field and the second field in the updated configuration information of the target register, and quickly perform targeted fault repair, so as to correctly receive the memory access instruction.

[0123] In one embodiment, a fault repair instruction carrying updated configuration information is generated and sent to the memory, so that the memory updates the current configuration information corresponding to the target register based on the updated configuration information, including:

[0124] Obtain the channel identifier corresponding to the instruction channel to which the current fault interface belongs in the memory; generate a fault repair instruction carrying the channel identifier and the updated configuration information, and send the fault repair instruction to the memory, so that the memory determines the target register that matches the instruction channel corresponding to the channel identifier, and updates the current configuration information corresponding to the target register based on the updated configuration information.

[0125] Among them, the memory may include at least one instruction channel, and different instruction channels are used to transmit memory access instructions for accessing different storage areas in the memory. The channel identifier is an identifier used to uniquely identify the instruction channel, and may specifically include a string of at least one character among letters, numbers, or symbols. Each instruction channel includes its own instruction transmission interface, and each instruction channel has its own corresponding register.

[0126] Specifically, since there are at least one instruction channel in the memory, and each instruction channel includes an instruction transmission interface, in order to ensure that the memory correctly repairs the faulty instruction transmission interface, after determining the current fault interface, it is necessary to further determine the instruction channel to which the current fault interface belongs. The computer device can obtain the channel identifier corresponding to the instruction channel to which the current fault interface belongs in the memory, generate a fault repair instruction carrying the channel identifier and the updated configuration information, and send the fault repair instruction to the memory. Each instruction channel in the memory has its own corresponding register, and each register is used to indicate the receiving method of the memory access instruction corresponding to the corresponding instruction channel by the memory. After receiving the fault repair instruction, the memory uses the register that matches the instruction channel corresponding to the channel identifier carried in the fault repair instruction as the target register from the registers corresponding to each instruction channel, and updates the current configuration information corresponding to the target register based on the updated configuration information, so that when the memory subsequently receives the memory access instruction corresponding to the channel identifier, it can know, based on the latest configuration information of the target register, to transmit the signal data on the corresponding instruction signal bit through the known normal interface and redundant interface in the corresponding instruction channel, so as to correctly receive the memory access instruction corresponding to the channel identifier.

[0127] In the above embodiments, the channel identifier corresponding to the instruction channel to which the current faulty interface belongs in the memory is obtained; a fault repair instruction carrying the channel identifier and the update configuration information is generated, and the fault repair instruction is sent to the memory, so that the memory determines the target register matching the instruction channel corresponding to the channel identifier, and updates the current configuration information corresponding to the target register based on the update configuration information. In this way, based on the channel identifier and the update configuration information, the memory can correctly repair the faulty instruction transmission interface in the faulty instruction channel, so that it can correctly receive the memory access instruction subsequently.

[0128] In one embodiment, generating a fault repair instruction carrying the channel identifier and the update configuration information and sending the fault repair instruction to the memory includes:

[0129] Generating target configuration information corresponding to the shared register in the memory based on the channel identifier, and generating a channel repair instruction carrying the target configuration information; the target configuration information is used to update the current configuration information corresponding to the shared register, and the configuration information of the shared register is used to instruct the memory to perform fault repair on the faulty instruction channel; generating an interface repair instruction carrying the update configuration information; obtaining the fault repair instruction based on the channel repair instruction and the interface repair instruction; and sending the fault repair instruction to the memory through the test interface provided by the memory.

[0130] Among them, the shared register refers to the register shared among each instruction channel. In the memory, various registers have their respective uses. The shared register is used to instruct the memory to perform fault repair on the faulty instruction channel, and the register exclusive to the instruction channel is used to instruct the memory to perform fault repair on the faulty instruction transmission interface in the instruction channel, and specific fault repair is performed based on the remapping relationship corresponding to the faulty instruction transmission interface.

[0131] The test interface is an interface provided by the memory, which is used to complete the test, boundary scan and repair of the memory.

[0132] Specifically, to ensure that the memory correctly repairs a faulty instruction transmission interface, after determining the current faulty interface and the instruction channel to which the current faulty interface belongs, the computer device can generate target configuration information corresponding to the shared register in the memory based on the channel identifier corresponding to the instruction channel to which the current faulty interface belongs, and generate a channel repair instruction carrying the target configuration information. The channel repair instruction is used to update the current configuration information of the shared register based on the target configuration information, so as to indicate that the memory currently needs to perform a fault repair on the instruction channel corresponding to the channel identifier. The computer device can generate an interface repair instruction carrying updated configuration information. The interface repair instruction is used to update the current configuration information of the target register corresponding to the instruction channel to which the current faulty interface belongs based on the updated configuration information, so as to indicate to the memory how to perform a fault repair on the currently faulty instruction transmission interface in the instruction channel. The computer device can obtain a fault repair instruction based on the channel repair instruction and the interface repair instruction, form the fault repair instruction by combining the channel repair instruction and the interface repair instruction, and finally send the fault repair instruction to the memory through the test interface provided by the memory. After receiving the fault repair instruction, the memory can update the current configuration information of the shared register based on the target configuration information to determine the instruction channel that currently needs to be fault-repaired, initiate the fault repair of the instruction channel, and update the current configuration information of the target register corresponding to the instruction channel to which the current faulty interface belongs based on the updated configuration information to determine the instruction transmission interface that currently needs to be fault-repaired, and initiate the fault repair of the instruction transmission interface.

[0133] In one embodiment, the test interface provided by the memory is an IEEE 1500 interface based on the IEEE 1500 (which can also be referred to as IEEE Std1500) test standard. The shared register is a test shell instruction register (WIR, Wrapper instructions Register) based on the IEEE 1500 test standard, and the register exclusive to the instruction channel is a test shell data register (WDR, Wrapper instructions Register) based on the IEEE Std 1500 test standard. The channel repair instruction can be referred to as a WIR instruction and is used to modify the configuration information of the WIR register. Some configuration contents of the WIR instruction are shown in Table 4. WIR[11:8] represents bits 8 to 11 in the instruction, and the data on bits 8 to 11 is used to represent the channel identifier. WIR[7:0] represents bits 0 to 7 in the instruction, and the data on bits 0 to 7 is used to represent the function of the WIR instruction. When WIR[7:0] is 12h, it indicates that the WIR instruction is used for soft repair. Soft repair is a software repair method.

[0134] The interface repair instruction can be called the WDR instruction, which is used to modify the configuration information of the WDR register. The configuration content of the WDR instruction is shown in Table 1.

[0135] Table 4

[0136]

[0137] In the above embodiments, the fault repair instruction includes a channel repair instruction carrying the target configuration information corresponding to the shared register and an interface repair instruction carrying the updated configuration information corresponding to the target register. Based on the channel repair instruction, the memory can modify the configuration information of the shared register to initiate the fault repair of the corresponding instruction channel, determine the target register that needs to modify the configuration based on the updated configuration information, and based on the interface repair instruction, the memory can modify the configuration information of the corresponding target register to initiate the fault repair of the corresponding instruction transmission interface. Through the test interface provided by the memory, the fault repair instruction can be quickly sent to the memory to quickly initiate the fault repair.

[0138] In one embodiment, the target remapping information is automatically cleared after the memory is powered off. The memory fault repair method further includes:

[0139] After the memory is restarted, re-determine the current faulty interface in the memory, and enter the step of obtaining the target remapping information corresponding to the current faulty interface in the memory for execution.

[0140] Specifically, the transmission of the memory access instruction is easily affected by the environmental changes of PVT (Precess Valid Temperature, process voltage temperature) and the crosstalk between signals, resulting in faults or damages in the instruction transmission interface during the operation of the memory. The faults in the instruction transmission interface are usually soft faults. If the memory is powered off and restarted, the environment that causes the faults in the instruction transmission interface has obviously changed. For example, after the memory is restarted, the temperature has changed, so the instruction transmission interface may not have faults anymore. Therefore, the target remapping information can be automatically cleared after the memory is powered off. After the memory is restarted, the faulty instruction transmission interface may not exist or has changed. To ensure the accuracy of the fault repair, the computer device needs to execute the memory fault repair method again. After the memory is restarted, the computer device needs to re-determine the current faulty interface in the memory, and then obtain the target remapping information corresponding to the current faulty interface in the memory, generate a fault repair instruction carrying the target remapping information, and send the fault repair instruction to the memory, so that the memory can receive the memory access instruction based on the target remapping information through the current normal interface and redundant interface.

[0141] In the above embodiments, the target remapping information is lost after the memory is powered off. After the memory is restarted, the current faulty interface in the memory is re-determined for fault repair to ensure the accuracy of fault repair.

[0142] In one embodiment, the memory fault repair method further includes:

[0143] Obtain the number of redundant interfaces in the memory and the number of faulty interfaces of the current faulty interface; when the number of faulty interfaces is less than or equal to the number of redundant interfaces, proceed to execute the step of obtaining the target remapping information corresponding to the current faulty interface in the memory; when the number of faulty interfaces is greater than the number of redundant interfaces, generate a fault prompt message.

[0144] Specifically, in order to maintain the manufacturing cost of the memory and ensure the utilization rate of the instruction transmission interface, the number of redundant interfaces in the memory can be limited. Therefore, when the number of redundant interfaces in the memory is greater than or equal to the number of faulty interfaces of the current faulty interface, the computer device can obtain the target remapping information corresponding to each current faulty interface in the memory, generate a fault repair instruction carrying each target remapping information, and send the fault repair instruction to the memory to quickly repair the fault. When the number of redundant interfaces in the memory is less than the number of faulty interfaces of the current faulty interface, the computer device can generate a fault prompt message to prompt that a relatively serious fault has occurred in the memory and take other methods for fault repair. The computer device can display the fault prompt message locally or send the fault prompt message to a preset terminal, for example, the terminal held by an operation and maintenance personnel, to quickly notify relevant personnel.

[0145] In the above embodiments, if the number of faulty interfaces is less than or equal to the number of redundant interfaces, automatic fault repair is performed based on the target remapping information corresponding to the current faulty interface to achieve quick repair. If the number of faulty interfaces is greater than the number of redundant interfaces, a fault prompt message is generated to prompt to take other methods for fault repair to achieve correct repair.

[0146] In one embodiment, as Figure 8 shown, a memory fault repair method is provided. This method can be described by taking the memory as an example and includes the following steps:

[0147] Step S802, obtain a fault repair instruction; the fault repair instruction carries the target remapping information corresponding to the current faulty interface in the memory. The target remapping information is obtained by reallocating the mapping relationship between each instruction signal bit corresponding to the memory access instruction and the instruction transmission interface among the normal interfaces and the redundant interfaces based on the positional relationship between the current faulty interface and other instruction transmission interfaces. The instruction transmission interface is used to transmit the signal data corresponding to the corresponding instruction signal bit in the memory access instruction.

[0148] Step S804: Receive memory access instructions through a normal interface and a redundant interface based on the target remapping information.

[0149] Specifically, the memory can receive a fault repair instruction sent from the outside, perform fault repair based on the target remapping information in the fault repair instruction, skip the current faulty interface, and correctly receive the memory access instructions through the normal interface and the redundant interface.

[0150] It can be understood that the specific processes such as the generation of the target remapping information and the generation of the fault repair instruction can refer to the content of the foregoing embodiments and will not be elaborated here.

[0151] In the above memory fault repair method, if a fault occurs in the instruction transmission interface in the memory, by reallocating the mapping relationship between each instruction signal bit corresponding to the memory access instruction and the instruction transmission interface in the normal interface and the redundant interface, the memory can skip the current faulty interface when receiving the memory access instruction, receive the signal data corresponding to each instruction signal bit in the memory access instruction through the normal interface and the redundant interface, and enable the memory to correctly receive the memory access instruction. Moreover, when reallocating the mapping relationship, the mapping relationships between the normal interface, the redundant interface, and the instruction signal bits are reallocated based on the positional relationship between the current faulty interface and other instruction transmission interfaces, which can enable the memory to intelligently skip the current faulty interface when receiving the memory access instruction, orderly receive the signal data corresponding to each instruction signal bit in the memory access instruction through the normal interface and the redundant interface, and enable the memory to quickly and accurately receive the memory access instruction. Sending the fault repair instruction carrying the target remapping information determined by reallocating the mapping relationship between the instruction signal bit and the instruction transmission interface corresponding to the current faulty interface to the memory, the memory can quickly perform fault repair, thereby quickly and accurately receiving the memory access instruction.

[0152] In a specific embodiment, the memory fault repair method of the present application can be applied to fault repair of the transmission channel of the AWORD (ADDRESS WORD) of the HBM (High Bandwidth Memory) DRAM.

[0153] In a chip using HBM, metal interconnects are usually used to connect individual modules. With the development of modern processes, the line width between interconnect wires is getting narrower and narrower, and the coupling effect and interference noise between wires are increasing continuously. At the same time, since HBM supports high-bandwidth data reading, writing, and storage, the heat dissipation problem of HBM chips poses a high challenge. Since the AWORD of HBM can operate at a clock frequency of up to 1.8 GHz, the transmission of AWORD is susceptible to environmental changes in PVT and crosstalk between signals, resulting in faults or damage in the transmission channel of AWORD during the operation of HBM. For example, referring to Figure 9 , when the temperature of the HBM chip drifts, the delay inside the HBM PHY (High Bandwidth Memory Physical) will change simultaneously, and this change will change the value of the delay, thus affecting the original alignment relationship between the clock and data. When a fault occurs in the AWORD channel during operation, if it is not repaired, it may cause errors in the operation of the Host to the HBM DRAM, and in severe cases, it may lead to the loss of data stored in the HBM DRAM. The memory fault repair method of the present application can perform a soft repair on the AWORD channel to ensure that when a running fault occurs in some channels of HBM AWORD, it can be quickly repaired to ensure the correctness of the HBM instruction word transmission.

[0154] HBM AWORD is responsible for completing the function of sending instructions to the HBM DRAM. Only the accurate transmission of HBM AWORD can ensure the correctness of each operation of HBM. The instructions of HBM AWORD are divided into two categories: row instructions and column instructions. The column instruction supported by the HBM2 protocol is 8 bits, i.e., C[7:0], and the row instruction is 6 bits, i.e., R[5:0]. The column instruction supported by the HBM2E protocol is 9 bits, i.e., C[8:0], and the row instruction is 7 bits, i.e., R[6:0]. The memory fault repair method of the present application supports the compatible versions of the HBM2 and HBM2E protocols, that is, it supports both the HBM2 protocol and the HBM2E protocol.

[0155] The inside of HBM contains a total of 8 groups of channels. The HBM DRAM provides a redundant interface for remapping AWORD. As shown in Table 5, it is the AWORD and its redundant interface of the single-channel HBM DRAM.

[0156] Table 5

[0157]

[0158] As can be seen from Table 5, in the AWORD word of HBM, the row instruction word (i.e., the row instruction signal bit) and the column instruction word (i.e., the column instruction signal bit) can be remapped independently. The row instruction word can be mapped to the RR pin, and the column instruction word can be mapped to the RC pin.

[0159] As Figure 10 shown, Figure 10 Figure 1 shows a schematic flow chart for soft repair of the AWORD channel of HBM DRAM. First, the computer device determines the current faulty interface, reads the current configuration information of the WDR register corresponding to the current faulty interface in the HBM DRAM through the host, and records the current configuration information of the WDR register. Then, the computer device configures the updated configuration information of the WDR register through the host. When configuring the updated configuration information, specifically, it configures the register code corresponding to the current faulty interface (i.e., the remapping code). For example, the register code corresponding to the current faulty interface can be queried from the tables shown in Figure 6A and Figure 6B The computer device generates a soft repair remapping table for the WDR register through the host according to the updated configuration information. The information of the soft repair remapping table can refer to Table 1. The computer device sends an IEEE1500 instruction to the HBM DRAM through the host, and sends the soft repair remapping table to the HBM DRAM through the IEEE1500 instruction to update the configuration information of the WDR register corresponding to the current faulty interface. The computer device determines whether the IEEE\alpha instruction has been sent. If the sending is completed, the soft repair for the current faulty interface is completed.

[0160] The host and HBM have pre-agreed on the remapping relationship corresponding to each register code. When the HBM DRAM receives a memory access instruction, it determines the corresponding remapping relationship based on the latest configuration information of the WDR register, skips the current faulty interface based on the remapping relationship, and transmits the signal data on the corresponding instruction signal bit in the memory access instruction through the normal interface and the redundant interface. By sequentially reading the signal data transmitted from the normal interface and the redundant interface, the complete memory access instruction can be obtained. Among them, the remapping relationship is obtained by reallocating the mapping relationship between each instruction signal bit corresponding to the memory access instruction and the instruction transmission interface in the normal interface and the redundant interface based on the positional relationship between the current faulty interface and other instruction transmission interfaces. For example, referring to Figure 6A , if the fault exists on the Rx0 interface and the RRx redundant interface is used for repair, after repair, the Rx6, Rx1, Rx2, Rx3, Rx4, Rx5, and RRx interfaces will respectively transmit the data on the R6, R0, R1, R2, R3, R4, and R5 bits in the storage access instruction sent to the x instruction channel.

[0161] It should be understood that although the steps in the flowcharts involved in the above-described embodiments are sequentially shown according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless there is a clear indication in this article, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. Moreover, at least a part of the steps in the flowcharts involved in the above-described embodiments may include multiple steps or multiple stages. These steps or stages are not necessarily executed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be executed alternately or in turn with at least a part of other steps or steps or stages in other steps.

[0162] Based on the same inventive concept, an embodiment of the present application further provides a memory failure repair device for implementing the memory failure repair method described above. The solution provided by this device to solve the problem is similar to the solution described in the above method. Therefore, the specific limitations in one or more embodiments of the memory failure repair device provided below can refer to the limitations on the memory failure repair method in the above text, and will not be repeated here.

[0163] In one embodiment, as Figure 11 shown, a memory failure repair device 1100 is provided, including: a remapping information acquisition module 1102 and a failure repair instruction sending module 1104, where:

[0164] The remapping information acquisition module 1102 is configured to acquire target remapping information corresponding to the current failed interface in the memory; the target remapping information is obtained by reassigning the mapping relationship between each instruction signal bit corresponding to the memory access instruction and the instruction transmission interface between the normal interface and the redundant interface based on the positional relationship between the current failed interface and other instruction transmission interfaces, and the instruction transmission interface is used to transmit the signal data corresponding to the corresponding instruction signal bit in the memory access instruction.

[0165] The failure repair instruction sending module 1104 is configured to generate a failure repair instruction carrying the target remapping information, and send the failure repair instruction to the memory, so that the memory receives the memory access instruction through the normal interface and the redundant interface based on the target remapping information.

[0166] For the above memory fault repair device, if a fault occurs in the instruction transmission interface in the memory, by reallocating the mapping relationship between each instruction signal bit corresponding to the memory access instruction and the instruction transmission interface between the normal interface and the redundant interface, the memory can skip the current faulty interface when receiving the memory access instruction, and receive the signal data corresponding to each instruction signal bit in the memory access instruction through the normal interface and the redundant interface, so that the memory can correctly receive the memory access instruction. Moreover, when reallocating the mapping relationship, the mapping relationships between the normal interface, the redundant interface and the instruction signal bits are reallocated based on the positional relationship between the current faulty interface and other instruction transmission interfaces, so that the memory can intelligently skip the current faulty interface when receiving the memory access instruction, and orderly receive the signal data corresponding to each instruction signal bit in the memory access instruction through the normal interface and the redundant interface, enabling the memory to receive the memory access instruction quickly and accurately. Send a fault repair instruction carrying the target remapping information corresponding to the current faulty interface, which is determined by reallocating the mapping relationship between the instruction signal bit and the instruction transmission interface, to the memory, and the memory can quickly perform fault repair, thereby quickly and accurately receiving the memory access instruction.

[0167] In one embodiment, the memory fault repair device further includes:

[0168] A remapping information generation module, configured to obtain interface position sorting information; determine a candidate faulty interface from each instruction transmission interface; generate remapping information corresponding to the candidate faulty interface based on the interface position sorting information and the interface position corresponding to the candidate faulty interface; the remapping information is used to indicate that the initial mapping relationship between the forward interface of the candidate faulty interface and the initial instruction signal bit remains unchanged, and map the initial instruction signal bits corresponding to the candidate faulty interface and the backward interface of the candidate faulty interface to their respective adjacent backward fault-free interfaces; use the next instruction transmission interface as the candidate faulty interface, and return to execute the step of generating remapping information corresponding to the candidate faulty interface based on the interface position sorting information and the interface position corresponding to the candidate faulty interface until the remapping information corresponding to each instruction transmission interface is obtained.

[0169] In one embodiment, the remapping information generation module is further configured to determine the remapping relationship corresponding to the candidate faulty interface based on the interface position sorting information and the interface position corresponding to the candidate faulty interface; the remapping relationship includes the re-determined mapping relationship between other instruction transmission interfaces and instruction signal bits in the case of a fault in the candidate faulty interface; generate a remapping code corresponding to the remapping relationship, and obtain the remapping information corresponding to the candidate faulty interface based on the remapping code.

[0170] In one embodiment, the encoded data encoded to a preset encoding length is remapped, and different instruction transmission interfaces correspond to different remapping encodings; among the respective candidate encoded data corresponding to the preset encoding length, except for the remapping encodings corresponding to the respective instruction transmission interfaces, other encoded data is used to represent that the initial mapping relationship between the instruction transmission interface and the initial instruction signal bit remains unchanged.

[0171] In one embodiment, the remapping information generation module is further configured to send the remapping relationships and remapping encodings respectively corresponding to the respective instruction transmission interfaces to the memory, so that the memory stores the remapping relationships and remapping encodings. The fault repair instruction sending module is further configured to generate a fault repair instruction carrying the target remapping encoding corresponding to the current fault interface, and send the fault repair instruction to the memory, so that the memory obtains the target remapping relationship corresponding to the target remapping encoding, and based on the target remapping relationship, receives the memory access instruction through the normal interface and the redundant interface.

[0172] In one embodiment, the fault repair instruction sending module is further configured to generate update configuration information corresponding to the target register in the memory based on the target remapping information; the target register is used to indicate the receiving manner of the memory for receiving the memory access instruction; generate a fault repair instruction carrying the update configuration information, and send the fault repair instruction to the memory, so that the memory updates the current configuration information corresponding to the target register based on the update configuration information.

[0173] In one embodiment, the memory includes a row instruction transmission interface for transmitting signal data corresponding to the row instruction signal bit and a column instruction transmission interface for transmitting signal data corresponding to the column instruction signal bit. The update configuration information includes the target remapping information and interface type information corresponding to the current fault interface; the interface type information is used to indicate that the memory modifies the field information in the current configuration information that matches the interface type corresponding to the current fault interface based on the target remapping information; the configuration information of the target register includes a first field for determining the mapping relationship corresponding to the row instruction transmission interface and a second field for determining the mapping relationship corresponding to the column instruction transmission interface.

[0174] In one embodiment, the fault repair instruction sending module is further configured to obtain the channel identifier corresponding to the instruction channel to which the current fault interface belongs in the memory; generate a fault repair instruction carrying the channel identifier and the update configuration information, and send the fault repair instruction to the memory, so that the memory determines the target register that matches the instruction channel corresponding to the channel identifier, and updates the current configuration information corresponding to the target register based on the update configuration information.

[0175] In one embodiment, the fault repair instruction sending module is further configured to generate target configuration information corresponding to the shared register in the memory based on the channel identifier, and generate a channel repair instruction carrying the target configuration information; the target configuration information is used to update the current configuration information corresponding to the shared register, and the configuration information of the shared register is used to instruct the memory to perform fault repair on the faulty instruction channel; generate an interface repair instruction carrying the updated configuration information; obtain a fault repair instruction based on the channel repair instruction and the interface repair instruction; and send the fault repair instruction to the memory through the test interface provided by the memory.

[0176] In one embodiment, the target remapping information is automatically cleared after the memory is powered off. The memory fault repair device is further configured to:

[0177] After the memory is restarted, re-determine the current faulty interface in the memory, and enter the step of obtaining the target remapping information corresponding to the current faulty interface in the memory for execution.

[0178] In one embodiment, as Figure 12 shown, a memory fault repair device is provided, including: a fault repair instruction obtaining module 1202 and a memory access instruction receiving module 1204, where:

[0179] The fault repair instruction obtaining module 1202 is configured to obtain a fault repair instruction; the fault repair instruction carries target remapping information corresponding to the current faulty interface in the memory; the target remapping information is obtained by reallocating the mapping relationship between each instruction signal bit corresponding to the memory access instruction and the instruction transmission interface among the normal interface and the redundant interface based on the positional relationship between the current faulty interface and other instruction transmission interfaces, and the instruction transmission interface is used to transmit the signal data corresponding to the corresponding instruction signal bit in the memory access instruction.

[0180] The memory access instruction receiving module 1204 is configured to receive a memory access instruction through the normal interface and the redundant interface based on the target remapping information.

[0181] For the above memory failure repair device, if a failure occurs in the instruction transmission interface in the memory, by reallocating the mapping relationship between each instruction signal bit corresponding to the memory access instruction and the instruction transmission interface between the normal interface and the redundant interface, the memory can skip the current faulty interface when receiving the memory access instruction, and receive the signal data corresponding to each instruction signal bit in the memory access instruction through the normal interface and the redundant interface, so that the memory can correctly receive the memory access instruction. Moreover, when reallocating the mapping relationship, the mapping relationships between the normal interface, the redundant interface and the instruction signal bits are reallocated based on the positional relationship between the current faulty interface and other instruction transmission interfaces, which can enable the memory to intelligently skip the current faulty interface when receiving the memory access instruction, and orderly receive the signal data corresponding to each instruction signal bit in the memory access instruction through the normal interface and the redundant interface, so that the memory can quickly and accurately receive the memory access instruction. Sending a failure repair instruction carrying the target remapping information determined by reallocating the mapping relationship between the instruction signal bit and the instruction transmission interface corresponding to the current faulty interface to the memory, the memory can quickly perform failure repair, so as to quickly and accurately receive the memory access instruction.

[0182] Each module in the above memory failure repair device can be implemented in whole or in part by software, hardware and their combination. Each of the above modules can be embedded in or independent of the processor in the computer device in the form of hardware, or stored in the memory in the computer device in the form of software, so as to facilitate the processor to call and execute the operations corresponding to each of the above modules.

[0183] In one embodiment, a computer device is provided. The computer device can be a server, and its internal structure diagram can be as Figure 13 shown. The computer device includes a processor, a memory, an input / output interface (Input / Output, abbreviated as I / O), and a communication interface. Among them, the processor, the memory, and the input / output interface are connected through a system bus, and the communication interface is connected to the system bus through the input / output interface. Among them, the processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program, and a database. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The database of the computer device is used to store data such as remapping information and remapping codes. The input / output interface of the computer device is used for exchanging information between the processor and external devices. The communication interface of the computer device is used for communicating with an external terminal through a network connection. When the computer program is executed by the processor, it implements a memory failure repair method.

[0184] In one embodiment, a computer device is provided. The computer device may be a terminal, and its internal structural diagram may be as shown in Figure 14 . The computer device includes a processor, a memory, an input / output interface, a communication interface, a display unit, and an input device. Among them, the processor, the memory, and the input / output interface are connected through a system bus, and the communication interface, the display unit, and the input device are connected to the system bus through the input / output interface. Among them, the processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The input / output interface of the computer device is used to exchange information between the processor and external devices. The communication interface of the computer device is used to communicate with external terminals in a wired or wireless manner. The wireless manner can be achieved through WIFI, a mobile cellular network, NFC (Near Field Communication), or other technologies. When the computer program is executed by the processor, it implements a method for repairing memory faults. The display unit of the computer device is used to form a visually visible picture, which can be a display screen, a projection device, or a virtual reality imaging device. The display screen can be a liquid crystal display screen or an electronic ink display screen. The input device of the computer device can be a touch layer covering the display screen, or a button, a trackball, or a touchpad provided on the housing of the computer device, or an external keyboard, touchpad, or mouse, etc.

[0185] Those skilled in the art can understand that Figure 13 , 14 the structure shown in is only a block diagram of some structures related to the solution of this application, and does not constitute a limitation on the computer device to which the solution of this application is applied. The specific computer device may include more or fewer components than those shown in the figure, or combine some components, or have different component arrangements.

[0186] In one embodiment, a computer device is further provided, including a memory and a processor. A computer program is stored in the memory, and when the processor executes the computer program, it implements the steps in the above-mentioned method embodiments.

[0187] In one embodiment, a computer-readable storage medium is provided, storing a computer program, and when the computer program is executed by the processor, it implements the steps in the above-mentioned method embodiments.

[0188] In one embodiment, a computer program product or a computer program is provided. The computer program product or the computer program includes computer instructions that are stored in a computer-readable storage medium. A processor of a computer device reads the computer instructions from the computer-readable storage medium, and the processor executes the computer instructions, so that the computer device performs the steps in the foregoing method embodiments.

[0189] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data for analysis, stored data, displayed data, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use, and processing of relevant data need to comply with the relevant laws, regulations, and standards of relevant countries and regions.

[0190] Those of ordinary skill in the art can understand that all or part of the processes in the methods of the above embodiments can be completed by instructing relevant hardware through a computer program. The computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above methods. Among them, any reference to a memory, database, or other medium used in the embodiments provided in the present application can include at least one of non-volatile and volatile memories. Non-volatile memories can include read-only memory (ROM), magnetic tapes, floppy disks, flash memories, optical memories, high-density embedded non-volatile memories, resistive random access memories (ReRAM), magnetoresistive random access memories (MRAM), ferroelectric random access memories (FRAM), phase change memories (PCM), graphene memories, etc. Volatile memories can include random access memory (RAM) or external cache memories, etc. By way of illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM), etc. The databases involved in the embodiments provided in the present application can include at least one of relational databases and non-relational databases. Non-relational databases can include distributed databases based on blockchain, etc., without limitation. The processors involved in the embodiments provided in the present application can be general-purpose processors, central processors, graphics processors, digital signal processors, programmable logics, data processing logics based on quantum computing, etc., without limitation.

[0191] The technical features of the above embodiments can be combined arbitrarily. For the sake of concise description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope described in this specification.

[0192] The above-described embodiments only represent several implementation manners of the present application. The description is relatively specific and detailed, but it should not be construed as a limitation on the patent scope of the present application. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present application, several modifications and improvements can still be made, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the appended claims.

Claims

1. A method for repairing memory faults, characterized in that, The method includes: Obtaining target remapping information corresponding to a current faulty interface in a memory; the target remapping information is obtained by reassigning the mapping relationship between each instruction signal bit corresponding to a memory access instruction and an instruction transmission interface among a normal interface and a redundant interface based on the positional relationship between the current faulty interface and other instruction transmission interfaces, and the instruction transmission interface is used to transmit signal data corresponding to the corresponding instruction signal bit in the memory access instruction; Generating a fault repair instruction carrying the target remapping information, and sending the fault repair instruction to the memory, so that the memory receives the memory access instruction through the normal interface and the redundant interface based on the target remapping information; Generating updated configuration information corresponding to a target register in the memory based on the target remapping information, where the target register is used to indicate the receiving manner of the memory for receiving the memory access instruction, generating a fault repair instruction carrying the updated configuration information, and sending the fault repair instruction to the memory, so that the memory updates the current configuration information corresponding to the target register based on the updated configuration information.

2. The method according to claim 1, characterized in that The method further includes: Obtaining interface position sorting information; Determining a candidate faulty interface from each instruction transmission interface; Generating remapping information corresponding to the candidate faulty interface based on the interface position sorting information and the interface position corresponding to the candidate faulty interface; the remapping information is used to indicate that the initial mapping relationship between the forward interface of the candidate faulty interface and the initial instruction signal bit remains unchanged, and the initial instruction signal bits corresponding to the candidate faulty interface and the backward interface of the candidate faulty interface are mapped to the respective adjacent backward fault-free interfaces; Taking the next instruction transmission interface as the candidate faulty interface, and returning to execute the step of generating remapping information corresponding to the candidate faulty interface based on the interface position sorting information and the interface position corresponding to the candidate faulty interface until the remapping information corresponding to each instruction transmission interface is obtained.

3. The method according to claim 2, wherein The generating remapping information corresponding to the candidate faulty interface based on the interface position sorting information and the interface position corresponding to the candidate faulty interface includes: Determining a remapping relationship corresponding to the candidate faulty interface based on the interface position sorting information and the interface position corresponding to the candidate faulty interface; the remapping relationship includes a re-determined mapping relationship between other instruction transmission interfaces and instruction signal bits in the case where the candidate faulty interface fails; Generating a remapping code corresponding to the remapping relationship, and obtaining the remapping information corresponding to the candidate faulty interface based on the remapping code.

4. The method according to claim 3, characterized in that, The remapping code is encoded data with a preset code length, and different instruction transmission interfaces correspond to different remapping codes; among the respective candidate encoded data corresponding to the preset code length, except for the remapping codes corresponding to each instruction transmission interface, other encoded data are used to represent that the initial mapping relationship between the instruction transmission interface and the initial instruction signal bit remains unchanged.

5. The method according to claim 3, characterized in that, The method further includes: Transmit the remapping relationships and remapping encodings respectively corresponding to the respective instruction transmission interfaces to the memory, so that the memory stores the remapping relationships and remapping encodings; Generating a fault repair instruction carrying the target remapping information and sending the fault repair instruction to the memory includes: Generating a fault repair instruction carrying the target remapping encoding corresponding to the current fault interface, and sending the fault repair instruction to the memory, so that the memory obtains the target remapping relationship corresponding to the target remapping encoding, and based on the target remapping relationship, receives a memory access instruction through the normal interface and the redundant interface.

6. The method according to claim 1, characterized in that, The memory access instruction includes a row instruction and a column instruction; When the current fault interface is a row instruction fault interface, the target remapping information is obtained by reallocating the mapping relationship between the respective row instruction signal bits and the row instruction transmission interfaces corresponding to the memory access instruction in the normal row instruction interface and the redundant row instruction interface based on the positional relationship between the row instruction fault interface and other row instruction transmission interfaces; When the current fault interface is a column instruction fault interface, the target remapping information is obtained by reallocating the mapping relationship between the respective column instruction signal bits and the column instruction transmission interfaces corresponding to the memory access instruction in the normal column instruction interface and the redundant column instruction interface based on the positional relationship between the column instruction fault interface and other column instruction transmission interfaces.

7. The method according to claim 1, characterized in that The memory includes a row instruction transmission interface for transmitting signal data corresponding to row instruction signal bits and a column instruction transmission interface for transmitting signal data corresponding to column instruction signal bits; The updated configuration information includes the target remapping information and the interface type information corresponding to the current fault interface; the interface type information is used to instruct the memory to modify the field information in the current configuration information that matches the interface type corresponding to the current fault interface based on the target remapping information; The configuration information of the target register includes a first field for determining the mapping relationship corresponding to the row instruction transmission interface and a second field for determining the mapping relationship corresponding to the column instruction transmission interface.

8. The method according to claim 1, wherein Generating a fault repair instruction carrying the updated configuration information and sending the fault repair instruction to the memory, so that the memory updates the current configuration information corresponding to the target register based on the updated configuration information, includes: Obtain the channel identifier corresponding to the instruction channel to which the current fault interface belongs in the memory; Generate a fault repair instruction carrying the channel identifier and the updated configuration information, and send the fault repair instruction to the memory, so that the memory determines the target register that matches the instruction channel corresponding to the channel identifier, and updates the current configuration information corresponding to the target register based on the updated configuration information.

9. The method according to claim 8, wherein Generating a fault repair instruction carrying the channel identifier and the updated configuration information and sending the fault repair instruction to the memory includes: Generate target configuration information corresponding to the shared register in the memory based on the channel identifier, and generate a channel repair instruction carrying the target configuration information; the target configuration information is used to update the current configuration information corresponding to the shared register, and the configuration information of the shared register is used to instruct the memory to perform fault repair on the faulty instruction channel; Generate an interface repair instruction carrying the updated configuration information; Obtain the fault repair instruction based on the channel repair instruction and the interface repair instruction; Send the fault repair instruction to the memory through the test interface provided by the memory.

10. The method according to claim 1, characterized in that, The target remapping information is automatically cleared after the memory is powered off, and the method further includes: After the memory is restarted, re-determine the current faulty interface in the memory, and enter the step of obtaining the target remapping information corresponding to the current faulty interface in the memory for execution.

11. A method for repairing memory faults, characterized in that, The method includes: Obtain a fault repair instruction; the fault repair instruction carries target remapping information corresponding to the current faulty interface in the memory, and the target remapping information is obtained by reallocating the mapping relationship between each instruction signal bit corresponding to the memory access instruction and the instruction transmission interface in the normal interface and the redundant interface based on the positional relationship between the current faulty interface and other instruction transmission interfaces, and the instruction transmission interface is used to transmit the signal data corresponding to the corresponding instruction signal bit in the memory access instruction; Receive the memory access instruction through the normal interface and the redundant interface based on the target remapping information; When the fault repair instruction carries the updated configuration information corresponding to the target register in the memory, update the current configuration information corresponding to the target register based on the updated configuration information; the target register is used to indicate the receiving mode of the memory for receiving the memory access instruction, and the updated configuration information is generated based on the target remapping information.

12. A memory failure repair device, characterized in that, The device includes: A remapping information acquisition module, configured to acquire target remapping information corresponding to the current faulty interface in the memory; the target remapping information is obtained by reallocating the mapping relationship between each instruction signal bit corresponding to the memory access instruction and the instruction transmission interface in the normal interface and the redundant interface based on the positional relationship between the current faulty interface and other instruction transmission interfaces, and the instruction transmission interface is used to transmit the signal data corresponding to the corresponding instruction signal bit in the memory access instruction; A fault repair instruction sending module, configured to generate a fault repair instruction carrying the target remapping information, and send the fault repair instruction to the memory, so that the memory receives the memory access instruction through the normal interface and the redundant interface based on the target remapping information; The fault repair instruction sending module is further configured to generate update configuration information corresponding to a target register in the memory based on the target remapping information, where the target register is used to indicate the receiving manner of the memory for receiving a memory access instruction, generate a fault repair instruction carrying the update configuration information, and send the fault repair instruction to the memory, so that the memory updates the current configuration information corresponding to the target register based on the update configuration information.

13. A memory failure repair device, characterized in that, The device includes: A fault repair instruction obtaining module, configured to obtain a fault repair instruction; the fault repair instruction carries target remapping information corresponding to a current fault interface in a memory; the target remapping information is obtained by reassigning the mapping relationship between each instruction signal bit corresponding to the memory access instruction and an instruction transmission interface between a normal interface and a redundant interface based on the positional relationship between the current fault interface and other instruction transmission interfaces, and the instruction transmission interface is used to transmit signal data corresponding to the corresponding instruction signal bit in the memory access instruction; A memory access instruction receiving module, configured to receive a memory access instruction through the normal interface and the redundant interface based on the target remapping information; The memory access instruction receiving module is further configured to, when the fault repair instruction carries update configuration information corresponding to a target register in the memory, update the current configuration information corresponding to the target register based on the update configuration information; the target register is used to indicate the receiving manner of the memory for receiving a memory access instruction, and the update configuration information is generated based on the target remapping information.

14. A computer device, comprising a memory and a processor, the memory storing a computer program, characterized in that, When the processor executes the computer program, the steps of the method according to any one of claims 1 to 11 are implemented.

15. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 11 are implemented.

16. A computer program product comprising a computer program, characterized in that, When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 11 are implemented.

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