Etching method of vanadium oxide film and film coating method of semiconductor device

Abstract

Provided are an etching method of a vanadium oxide film and a film plating method of a semiconductor device. The etching method of the vanadium oxide film comprises: providing a base module comprising a substrate and silicon nitride, the silicon nitride being arranged on the substrate; arranging a mask; patterning photoresist; etching the exposed mask by using inductively coupled plasma etching with C / F-based gas and Ar gas to form a shallow groove, the bottom surface of the shallow groove being the top surface of the vanadium oxide film, and the side surface of the shallow groove being an inclined surface; removing the exposed vanadium oxide film by using inductively coupled plasma etching with Cl-based gas and Ar gas to make the side surface of the shallow groove more obliquely inclined until the etching enters the silicon nitride, to form an etching groove, the bottom wall of the etching groove being composed of the silicon nitride, the side wall of the etching groove being composed of the vanadium oxide and the silicon nitride, the side wall of the etching groove being continuous and coplanar with the re-etched side surface, and the included angle between the bottom wall and the side wall being less than or equal to 65°; and removing the photoresist to form a device module. The film plating method of the semiconductor device comprises plating a film along the etching groove of the device module.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the field of semiconductor, and more particularly to an etching method of vanadium oxide film and a coating method of semiconductor device. BACKGROUND

[0002] Figure 1 is a schematic diagram of a device module 100'. The device module 100' comprises a base module 1'. The base module 1' comprises, from bottom to top, a substrate 11', a silicon dioxide layer 14', a silicon nitride layer 12' and a vanadium oxide film 13'. The top of the device module 100' is formed with an etching groove 5' by etching. The bottom wall 51 of the etching groove 5' is composed of the silicon nitride layer 12', the side wall 52' of the etching groove 5' is composed of the vanadium oxide, and the included angle Θ' between the bottom wall 51' and the side wall 52' of the etching groove 5' is about 90°.

[0003] Based on the later use of such a device module 100', it is necessary to set various suitable materials in the etching groove 5'. For the case that the included angle Θ' between the bottom wall 51' and the side wall 52' is about 90°, the setting of the required materials in the etching groove 5' adopts Figure 2 The filling mode shown is advantageous, but the effect of the coating mode (i.e. the deposition coating mode) is poor.

[0004] When the coating mode is adopted, the coating will be along the bottom wall 51' and the side wall 52'. For the case that the etching groove 5' is relatively shallow, such as Figure 3 As shown, the uniformity of the coated film 200' on the bottom wall 51' is much worse than that on the side wall 52', and the coated film 200' on the bottom wall 51' can not even completely cover the bottom wall 51', and the coated film 200' can also appear bulges at the corner between the top surface of the vanadium oxide film 13' and the side wall 52'. For the case that the etching groove 5' is relatively deep, such as Figure 4 As shown, similarly, the coated film 200' can appear bulges at the corner between the top surface of the vanadium oxide film 13' and the side wall 52', and differently, the uniformity of the coated film 200' becomes worse on both the bottom wall 51' and the side wall 52', the possibility of the coated film 200' not completely covering the bottom wall 51' on the bottom wall 51' is intensified, and the coated film 200' can appear voids (i.e. discontinuity of the uncoated film 200', and the corner is not filled) at the corner between the bottom wall 51' and the side wall 52'. The device module 100' with the coated film shown in Figure 3 and Figure 4 will seriously affect the yield, performance and life of the semiconductor device to which it is applied. SUMMARY

[0005] In view of the problems in the background art, the purpose of the present disclosure is to provide an etching method of a vanadium oxide film and a film plating method of a semiconductor device, which can improve the uniformity of a film plated when etching grooves formed by etching the vanadium oxide film.

[0006] Thus, in some embodiments, an etching method of a vanadium oxide film includes: step one, providing a substrate module, the substrate module including a substrate and silicon nitride, the silicon nitride being disposed on the substrate, the vanadium oxide film directly and entirely covering the silicon nitride; step two, disposing a mask of non-metallic nitride so that the mask covers the entire vanadium oxide film; step three, patterning photoresist so that the photoresist exposes part of the mask; step four, first etching, using inductively coupled plasma etching to etch the exposed mask of the patterned photoresist using C / F-based gas and Ar gas to form a shallow groove, the top of the shallow groove being open, the bottom surface of the shallow groove being the top surface of the vanadium oxide film, and the side surface of the shallow groove being an inclined surface; step five, second etching, using inductively coupled plasma etching to remove the vanadium oxide film exposed in the shallow groove using Cl-based gas and Ar gas, while the second etching makes the side surface of the shallow groove more steeply inclined until the etching depth reaches below the surface of the silicon nitride adjacent to the vanadium oxide film to form an etching groove, the bottom wall of the etching groove being composed of silicon nitride, the side wall of the etching groove being composed of vanadium oxide and silicon nitride below the vanadium oxide, the side wall of the etching groove being continuous and coplanar with the side surface of the shallow groove after the second etching, and the included angle between the bottom wall of the etching groove and the side wall of the etching groove being 65° or less; and step six, removing the photoresist to form a device module.

[0007] In some embodiments, in step one, the substrate module further includes a silicon dioxide layer, the silicon dioxide layer being directly between the substrate and the silicon nitride in the stacking direction of the substrate module.

[0008] In some embodiments, in step one, the thickness of the vanadium oxide film is In step two, the thickness of the mask is The non-metallic nitride is silicon nitride.

[0009] In some embodiments, in step four, the inductively coupled plasma etching uses a radio frequency source; the power of the upper electrode of the radio frequency source is 800-1200W, and the power of the lower electrode of the radio frequency source is 120-200W; the C / F-based gas is CF4 and CHF3; the flow rate of CF4 is 50-90sccm, the flow rate of CHF3 is 40-60sccm, and the flow rate of Ar gas is 40-80sccm; the pressure formed by CF4, CHF3, and Ar in the first etching is 8-12mT; and the process time of the first etching is 10-20s.

[0010] In some embodiments, the included angle between the side surface that is an inclined surface and the top surface of the vanadium oxide film is 75° or less.

[0011] In some embodiments, in step four and step five, the angle between the bottom wall of the etching groove and the side wall of the etching groove is 20-60°, preferably 25-45°, more preferably 30°.

[0012] In some embodiments, in step five, the etching depth goes into the surface of the silicon nitride adjacent to the vanadium oxide film

[0013] In some embodiments, in step five, the inductively coupled plasma etching adopts a radio frequency source;

[0014] The power of the upper electrode of the radio frequency source is 100-400W, and the power of the lower electrode of the radio frequency source is 50-200W; the Cl-based gas is chlorine, the flow rate of the chlorine is 20-200sccm, and the flow rate of the Ar gas is 20-80sccm; the pressure formed by the chlorine and Ar in the etching is 8-14mT.

[0015] In some embodiments, in step five, the process time adopted by the first etching is automatically grabbed by a spectrometer; the process time adopts a main etching time and an over-etching time, the main etching time is defined as the time when the depth of the etching groove formed in the etching process reaches the surface of the silicon nitride, and the over-etching time is defined as the time from when the etching starts to go into the surface of the silicon nitride adjacent to the vanadium oxide film to when the etching stops; the main etching time is 20-30s; the over-etching time is 20%-40% of the main etching time.

[0016] In some embodiments, a film plating method of a semiconductor device comprises the step of plating a film on the bottom wall of the etching groove, the side wall of the etching groove, the side surface of the shallow groove, and the surface of the mask of a device module prepared by the aforementioned etching method of a vanadium oxide film.

[0017] The beneficial effects of the present disclosure are as follows: the inclined surface of the shallow groove formed in step four will serve as the initial guide for the inclined side wall formed in step five, and the Cl-based gas in step five is suitable for fast etching of the vanadium oxide film but slow etching of the silicon nitride below the vanadium oxide film, because the charged ions CL -The reaction speed with the metal vanadium oxide is faster than the non-metal silicon nitride, and the over-etching amount of the silicon nitride can be well controlled at a slow speed. This is also applicable to the case of using a non-metal nitride as a mask. During the second etching process in step five, the etching along the slope of the side surface 41 will be performed outwardly, but the surface area of the mask corresponding to the side surface is smaller than the surface area of the vanadium oxide under the bottom surface of the shallow trench. Thus, the matching of the etching amount and the etching speed is provided, and the side surface of the shallow trench can be further etched to be more inversely inclined during the second etching, and the more inversely inclined side surface is coplanar or substantially coplanar with the slope (i.e., the inclined side wall) formed by the etching of the vanadium oxide film. The coplanarity is beneficial to the uniformity of the subsequent film plating. BRIEF DESCRIPTION OF DRAWINGS

[0018] Figure 1 is a schematic diagram of a device module prepared by a known etching method of a vanadium oxide film.

[0019] Figure 2 is a schematic diagram of the filling of an etching groove of a device module prepared by a known etching method of a vanadium oxide film, in which the filled material is shown in gray.

[0020] Figure 3 is a schematic diagram of the film plating of an etching groove of a device module prepared by a known etching method of a vanadium oxide film.

[0021] Figure 4 is another schematic diagram of the film plating of an etching groove of a device module prepared by a known etching method of a vanadium oxide film.

[0022] Figure 5 is a schematic diagram of the structure when step three of the etching method of a vanadium oxide film according to the present disclosure is completed.

[0023] Figure 6 is a schematic diagram of the structure when step four of the etching method of a vanadium oxide film according to the present disclosure is completed.

[0024] Figure 7 is a schematic diagram of the structure when step five of the etching method of a vanadium oxide film according to the present disclosure is completed.

[0025] Figure 8 is a schematic diagram of the structure when step six of the etching method of a vanadium oxide film according to the present disclosure is completed.

[0026] Figure 9 is Figure 8 is a schematic diagram of the device module after film plating.

[0027] Figure 10 is a schematic diagram of the process time of etching in the etching method of a vanadium oxide film according to the present disclosure.

[0028] Figure 11 are three actual photos of a device module prepared according to the etching method of a vanadium oxide film of the present disclosure, in which the three photos are cross sections taken at upper, middle and lower positions of the substrate using a scanning electron microscope.

[0029] Figure 12 is an actual photo of a device module after film plating according to the etching method of a vanadium oxide film of the present disclosure. Figure 11

[0030] Figure 13 is another actual photo of a device module after film plating prepared according to the etching method of a vanadium oxide film of the present disclosure.

[0031] In the drawings:

[0032] 100' device module 11 substrate

[0033] 1' base module 12 silicon nitride

[0034] 11' substrate 13 vanadium oxide film

[0035] 12' silicon nitride 14 silicon dioxide layer

[0036] 13' vanadium oxide film 2 mask

[0037] 14' silicon dioxide layer 3 photoresist

[0038] 5' etching groove 4 shallow groove

[0039] 51' bottom wall 41 side surface

[0040] 52' side wall 5 etching groove

[0041] 200' film 51 bottom wall

[0042] θ' included angle 52 side wall

[0043] 100 device module θ included angle

[0044] 1 base module 200 film DETAILED DESCRIPTION

[0045] The accompanying drawings illustrate embodiments of the present disclosure and it is understood that the disclosed embodiments are merely examples of the present disclosure, the present disclosure can be implemented in various forms, therefore, the specific details disclosed herein should not be interpreted as limiting, but merely as a basis for the claims and as an illustrative basis for teaching those of ordinary skill in the art to implement the present disclosure in various ways.

[0046] [Etching method of vanadium oxide film]

[0047] Referring to Figures 5 to 8 ​The etching method of the vanadium oxide film according to the present disclosure comprises: step one, providing a base module 1, the base module 1 comprising a substrate 11 and a silicon nitride 12, the silicon nitride 12 being arranged on the substrate 11, and a vanadium oxide film 13 directly and entirely covering the silicon nitride 12; step two, arranging a mask 2 of non-metallic nitride to cover the entire vanadium oxide film 13; step three, arranging a photoresist 3 in a pattern to expose part of the mask 2; step four, first etching, using inductively coupled plasma (ICP) etching to etch the mask 2 exposed by the patterned photoresist 3 using C / F-based gas and Ar gas to form a shallow groove 4, the top of the shallow groove 4 being open, the bottom surface of the shallow groove 4 being the top surface of the vanadium oxide film 13, and the side surface 41 of the shallow groove 4 being an inclined surface; step five, second etching, using inductively coupled plasma etching to remove the vanadium oxide film 13 exposed in the shallow groove 4 using Cl-based gas and Ar gas, while the second etching makes the side surface 41 of the shallow groove 4 more inclined, until the etching depth reaches below the surface of the silicon nitride 12 adjacent to the vanadium oxide film 13 (i.e. over-etching), to form an etching groove 5, the bottom wall 51 of the etching groove 5 being composed of the silicon nitride 12, the side wall 52 of the etching groove 5 being composed of the vanadium oxide and the silicon nitride 12 below the vanadium oxide, the side wall 52 of the etching groove 5 being continuous and coplanar with the side surface 41 of the shallow groove 4 after the second etching, and the included angle θ between the bottom wall 51 of the etching groove 5 and the side wall 52 of the etching groove 5 being less than or equal to 65°; and step six, removing the photoresist 3 to form a device module 100.

[0048] In step one, in an example, the material of the substrate 11 can be silicon or silicon carbide, etc.

[0049] In step one, in an example, the base module 1 further comprises a silicon dioxide layer 14, the silicon dioxide layer 14 being directly located between the substrate 11 and the silicon nitride 12 along the stacking direction of the base module 1.

[0050] In step one, in an example, the base module 1 can be directly provided by using an existing prepared base module, or can be prepared together with the etching method of the vanadium oxide film according to the present disclosure. For example, the silicon nitride 12 is grown on the substrate 11 by CVD; the silicon dioxide layer 14 is grown on the silicon nitride 12 by PVD; and the vanadium oxide film 13 is grown on the silicon dioxide layer 14 by PVD.

[0051] In step one, in an example, the thickness of the vanadium oxide film 13 is 10-100 nm.

[0052] In step two, the mask 2 of non-metallic nitride plays at least two roles. On the one hand, the slope of the side surface 41 of the shallow trench 4 formed in step four will serve as the initial guide for the sloping side wall 52 formed in step five. If the side surface 41 formed in step four is vertical, it will be very difficult to form the required sloping side wall 52 in step five, because the vertical guide of the side surface 41 formed in step four will make the second etching proceed downward vertically, and it will be difficult to form an angle of 65° or less. On the other hand, if the mask 2 is not provided, the wet etching will corrode the surface of the top of the vanadium oxide film 13, affecting the quality of the device module 100 and the subsequent plating effect. The provision of the mask 2 can avoid such corrosion effect.

[0053] In step two, in an example, the non-metallic nitride is silicon nitride. In step two, in an example, the thickness of the mask 2 is 0.5-2 μm.

[0054] In step two, in an example, the mask 2 is grown on the vanadium oxide film 13 by CVD.

[0055] In step three, in an example, the photoresist (PR) is patterned by coating, exposing and developing. In an example, the photoresist 3 is 0.5-2 μm.

[0056] In step four, the C / F-based gas causes a chemical reaction to play a role in etching and forming a polymer, and the Ar gas plays a role in physical bombardment. The C / F-based gas of step four is suitable for fast etching of the mask 2 but slow etching of the vanadium oxide film 13. In addition, because the C / F-based gas is a polymer gas, the gas will also cover the surface of the top of the vanadium oxide film 13, thereby hindering the etching of the vanadium oxide film 13, so that the first etching can effectively and accurately control the position of the surface of the vanadium oxide film 13 exposed to form the shallow trench 4. In addition, the inventors of the present application found in the development process that the C / F-based gas directly etching the vanadium oxide film 13 will also have a side etching phenomenon. Note that, as shown in the figure, the photoresist 3 will also be thinned and shortened by being removed in part during the first etching process. Figure 6

[0057] ​In step four, in an example, the inductively coupled plasma etching employs a radio frequency source; the power of the upper electrode of the radio frequency source is 800-1200 W, and the power of the lower electrode of the radio frequency source is 120-200 W; the C / F-based gas is CF4 and CHF3; the flow rate of CF4 is 50-90 sccm, the flow rate of CHF3 is 40-60 sccm, and the flow rate of Ar gas is 40-80 sccm; the pressure formed by CF4, CHF3 and Ar in the first etching is 8-12 mT; and the process time of the first etching is 10-20 s. The flow rates of CF4 and CHF3 are coordinated to adjust the C / F ratio and then adjust the selectivity ratio of the lateral and longitudinal etching, so as to realize that the side surface 41 of the shallow groove 4 in step four is a bevel. Similarly, the coordination of the powers of the upper electrode and the lower electrode can also help to adjust the selectivity ratio of the lateral and longitudinal etching. In other words, the powers of the upper electrode and the lower electrode, the flow rates of CF4, CHF3 and Ar are coordinated to adjust the selectivity ratio of the lateral and longitudinal etching, so as to realize that the side surface 41 of the shallow groove 4 in step four is a bevel. In an example, the included angle between the beveled side surface 41 and the top surface of the vanadium oxide film 13 is 75° or less.

[0058] In steps four and five, in an example, the included angle θ between the bottom wall 51 of the etching groove 5 and the side wall 52 of the etching groove 5 is 20-60°, preferably 25-45°, and more preferably 30°.

[0059] In step one, in an example, the thickness of the silicon nitride 12 is 100-200 nm, preferably 120-180 nm, and more preferably 150 nm. In step five, the etching depth enters the surface of the silicon nitride 12 adjacent to the vanadium oxide film 13 (i.e. over-etching)

[0060] In step five, the Cl-based gas has a physical and chemical effect, i.e. a chemical reaction caused by the active group of Cl and ion bombardment, and the Ar gas has a physical bombardment effect. The Cl-based gas in step five is suitable for fast etching of the vanadium oxide film 13 but slow etching of the silicon nitride 12 below the vanadium oxide film 13, because the charged ion CL of the Cl-based gas -The reaction speed with the metal vanadium oxide is faster than the non-metal silicon nitride, so not only can the vanadium oxide at the exposed position of the shallow trench 4 be etched completely (i.e. no footing) without remaining on the surface of the silicon nitride 12, but also the amount of over-etching of the silicon nitride 12 can be controlled slowly and well. This is also applicable to the case where the mask 2 uses a non-metal nitride. During the second etching process in step five, the etching of the mask 2 along the slope of the side surface 41 will be outward, but the surface area of the mask 2 corresponding to the side surface 41 is smaller than the surface area of the vanadium oxide under the bottom surface of the shallow trench 4, so that the matching of the etching amount and the etching speed is provided, and the side surface 41 of the shallow trench 4 can be further etched to be more inclined during the second etching, while the more inclined side surface 41 is coplanar or substantially coplanar with the slope (i.e. the inclined side wall 52) formed by etching the vanadium oxide film 13. This coplanarity is conducive to the uniformity of the subsequent plating film. In addition, since the etching of the silicon nitride 12 can be controlled slowly and well, the roughness of the bottom wall 51 of the etching trench 5 can be controlled to be small (i.e. relatively smooth), which is also conducive to the uniformity of the subsequent plating film. It should be noted that, as shown in Figure 7 the first etching process, the photoresist 3 will also be partially removed and thinned and shortened during the second etching process.

[0061] In step five, in an example, inductively coupled plasma etching uses a radio frequency source; the power of the upper electrode of the radio frequency source is 100-400 W, and the power of the lower electrode of the radio frequency source is 50-200 W; the Cl-based gas is chlorine gas, the flow rate of the chlorine gas is 20-200 sccm, and the flow rate of the Ar gas is 20-80 sccm; the pressure formed by the chlorine gas and Ar in the etching is 8-14 mT. Further, in step five, in an example, the flow rate of the chlorine gas is 20-160 sccm. Similarly, the matching of the powers of the upper electrode and the lower electrode can also help to adjust the selection ratio of the lateral and longitudinal etching. Similarly, the matching of the powers of the upper and lower electrodes, the flow rates of the chlorine gas and Ar realizes the selection ratio of the lateral and longitudinal etching, so as to realize the more inclined side wall 52 of the etching trench 5 in step five.

[0062] In step five, in an example, the process time of the second etching is automatically captured by a spectrometer (see Figure 10) ; the process time is the main etching time and the over-etching time. The main etching time is defined as the time for the etching groove 5 to reach the surface of the silicon nitride 12. The over-etching time is defined as the time for the etching to start to enter the surface of the silicon nitride 12 adjacent to the vanadium oxide film 13 until the etching is terminated. In an example, the main etching time is 20-30s; the over-etching time is 20%-40% of the main etching time. By setting the main etching time and the over-etching time, it is ensured that the vanadium oxide near the bottom of the etching groove 5 is etched clean, and there is no residual vanadium oxide at the bottom wall 51 of the etching groove. It is noted that, similarly, the process time for the first etching can also be automatically captured by the spectrometer.

[0063] In step six, in an example, dry stripping and wet stripping are used to remove the photoresist 3.

[0064] [Plating method for semiconductor device]

[0065] The plating method for semiconductor device according to the present disclosure comprises the step of plating a film 200 on the bottom wall 51 of the etching groove 5, the sidewall 52 of the etching groove 5, the side surface 41 of the shallow groove 4, and the surface of the mask 2 of the device module 100 prepared by the etching method for vanadium oxide film.

[0066] The material of the plated film 200 can be any desired material, such as a metal film or a dielectric film, such as silicon nitride or silicon oxide, determined according to the actual use requirements of the semiconductor device. The plating can use a PVD method.

[0067] [Testing]

[0068] Example 1

[0069] Etching process of vanadium oxide film:

[0070] Step one, growing a silicon nitride 12 on a substrate 11 with silicon material by CVD; growing a silicon dioxide layer 14 on the silicon nitride 12 by PVD; growing a vanadium oxide film 13 on the silicon dioxide layer 14 by PVD, the thickness of the vanadium oxide film 13 is 100-200nm.

[0071] Step two, growing a mask 2 on the vanadium oxide film 13 by CVD, the material of the mask 2 is silicon nitride, and the thickness of the mask 2 is 100-200nm.

[0072] Step three, applying photoresist, exposing, and developing to pattern the photoresist 3, so that the exposed part of the mask 2 is exposed, and the thickness of the photoresist 3 is 1μm.

[0073] Step four, first etching, the exposed mask 2 of the patterned photoresist 3 is etched by inductively coupled plasma (ICP) etching using C / F-based gas and Ar gas to form a shallow trench 4, the top of the shallow trench 4 is open, the bottom of the shallow trench 4 is the top of the vanadium oxide film 13, the side 41 of the shallow trench 4 is a slope, wherein the inductively coupled plasma etching uses a radio frequency source; the power of the upper electrode of the radio frequency source is 800 W, the power of the lower electrode of the radio frequency source is 120 W; the C / F-based gas is CF4 and CHF3; the flow rate of CF4 is 70 sccm, the flow rate of CHF3 is 50 sccm, the flow rate of Ar gas is 50 sccm, the pressure formed by CF4, CHF3 and Ar is 10 mT, the process time of the first etching is 15 s, the process time of the first etching is automatically captured by a spectrometer; the angle between the side 41 which becomes a slope and the top of the vanadium oxide film 13 is 75°.

[0074] Step five, second etching, the vanadium oxide film 13 exposed in the shallow trench 4 is removed by inductively coupled plasma etching using Cl-based gas and Ar gas, at the same time, the second etching makes the side 41 of the shallow trench 4 be etched to be more inclined, until and makes the etching depth enter below the surface of the silicon nitride 12 adjacent to the vanadium oxide film 13 (i.e. over-etching), to form an etching trench 5, the bottom wall 51 of the etching trench 5 is composed of the silicon nitride 12, the side wall 52 of the etching trench 5 is composed of the vanadium oxide and the silicon nitride 12 below the vanadium oxide, wherein the inductively coupled plasma etching uses a radio frequency source, the power of the upper electrode of the radio frequency source is 300 W, the power of the lower electrode of the radio frequency source is 150 W, the Cl-based gas is chlorine, the flow rate of the chlorine is 80 sccm, the flow rate of the Ar gas is 40 sccm, the pressure formed by the chlorine and Ar in the etching is 12 mT; the main etching time is 20 s, the over-etching time is 30% of the main etching time, the process time of the second etching is automatically captured by a spectrometer; and

[0075] Step six, the photoresist 3 is removed by dry stripping and wet stripping to form a device module 100.

[0076] The film plating process of the semiconductor device:

[0077] The bottom wall 51 of the etching trench 5, the side wall 52 of the etching trench 5, the side 41 of the shallow trench 4 and the surface of the mask 2 of the device module 100 prepared in the foregoing etching process of the vanadium oxide film are plated, the film plating uses a PVD method, and the material of the film plating is silicon nitride.

[0078] The etching process of the vanadium oxide film is carried out on the same substrate 11, a scanning electron microscope is used to cut the whole substrate 11 into slices, and different etching trenches are observed on the upper, middle and lower three slices of the substrate 11, as shown in Figure 11 The amount of over-etched silicon carbide 12 of the three measurement points is about , as shown inFigure 11 As shown in the photo, the angle between the sidewall and the bottom wall of the etched groove is about 62.4°, and the overall flatness of the sidewall is good. Figure 12 As shown in the photos, the coating has good uniformity and density.

[0079] Example 2

[0080] Etching process of vanadium oxide film:

[0081] Step 1: grow silicon nitride 12 on a silicon substrate 11 by CVD; grow a silicon dioxide layer 14 on the silicon nitride 12 by PVD; grow a vanadium oxide film 13 on the silicon dioxide layer 14 by PVD, and the thickness of the vanadium oxide film 13 is

[0082] Step 2: Use CVD to grow a mask 2 on the vanadium oxide film 13. The material of the mask 2 is silicon nitride and the thickness of the mask 2 is

[0083] Step 3: Apply photoresist, expose, and develop to pattern the photoresist 3 so that the photoresist 3 partially exposes the mask 2. The thickness of the photoresist 3 is 0.9 μm.

[0084] Step 4, the first etching, using inductively coupled plasma (ICP) etching to etch the mask 2 exposed by the patterned photoresist 3 using C / F-based gas and Ar gas to form a shallow groove 4, the top of the shallow groove 4 is open, the bottom of the shallow groove 4 is the top surface of the vanadium oxide film 13, and the side 41 of the shallow groove 4 is a bevel, wherein the inductively coupled plasma etching uses a radio frequency source; the power of the upper electrode of the radio frequency source is 1000W, and the power of the lower electrode of the radio frequency source is 180W; the C / F-based gases are CF4 and CHF3; the flow rate of CF4 is 80sccm, the flow rate of CHF3 is 60sccm, and the flow rate of Ar gas is 40sccm. The pressure formed by CF4, CHF3, and Ar is 8mT. The process time of the first etching is 12s, and the process time of the first etching is automatically captured by a spectrometer; the angle between the side 41 that becomes the bevel and the top surface of the vanadium oxide film 13 is 50°.

[0085] Step five, second etching, the exposed vanadium oxide film 13 in the shallow groove 4 is removed by inductively coupled plasma etching using Cl-based gas and Ar gas, at the same time, the second etching makes the side surface 41 of the shallow groove 4 be etched more steeply, until and makes the etching depth enter the surface of the silicon nitride 12 adjacent to the vanadium oxide film 13 (i.e. over-etching), to form an etching groove 5, the bottom wall 51 of the etching groove 5 is composed of the silicon nitride 12, the side wall 52 of the etching groove 5 is composed of the vanadium oxide and the silicon nitride 12 under the vanadium oxide, wherein the inductively coupled plasma etching uses a radio frequency source, the power of the upper electrode of the radio frequency source is 350 W, the power of the lower electrode of the radio frequency source is 180 W, the Cl-based gas is chlorine, the flow rate of the chlorine is 120 sccm, the flow rate of the Ar gas is 40 sccm, the chlorine and the Ar form a pressure of 10 mT in the etching, the main etching time is 10 s, the over-etching time is 30% of the main etching time, the process time of the second etching is automatically grabbed by the optical spectrometer; and

[0086] Step six, the photoresist 3 is removed by dry stripping and wet stripping, to form the device module 100.

[0087] Plating process of the semiconductor device:

[0088] The bottom wall 51 of the etching groove 5, the side wall 52 of the etching groove 5, the side surface 41 of the shallow groove 4 and the surface of the mask 2 of the device module 100 prepared in the foregoing etching process of the vanadium oxide film are plated, the plating uses the PDV method, and the material of the plating is silicon nitride.

[0089] As shown in the photo of Figure 13 , the included angle of the side wall and the bottom wall of the formed etching groove is about 28.7°, and the planarity of the whole side wall is good. The uniformity and the compactness of the plating are good.

[0090] The foregoing detailed description describes multiple exemplary embodiments, but this document is not intended to be limited to the explicitly disclosed combinations. Therefore, unless otherwise stated, various features disclosed herein can be combined together to form multiple additional combinations that are not shown for the purpose of simplicity.

Claims

1. An etching method of a vanadium oxide thin film, characterized by, It comprises: Step one, providing a base module (1), the base module (1) comprises a substrate (11) and silicon nitride (12), the silicon nitride (12) is arranged on the substrate (11), and a vanadium oxide film (13) is directly and entirely covered on the silicon nitride (12); Step two, arranging a mask (2) of non-metallic nitride to cover the entire vanadium oxide film (13); Step three, arranging a photoresist (3) in a pattern to expose part of the mask (2); Step four, first etching, using inductively coupled plasma (ICP) etching to etch the mask (2) exposed by the patterned photoresist (3) by using C / F-based gas and Ar gas to form a shallow groove (4), the top of the shallow groove (4) is open, the bottom surface of the shallow groove (4) is the top surface of the vanadium oxide film (13), and the side surface (41) of the shallow groove (4) is an inclined surface; Step five, second etching, using inductively coupled plasma etching to remove the vanadium oxide film (13) exposed in the shallow groove (4) by using Cl-based gas and Ar gas, and at the same time, the second etching makes the side surface (41) of the shallow groove (4) be etched to be more inclined, until the etching depth enters below the surface of the silicon nitride (12) adjacent to the vanadium oxide film (13), to form an etching groove (5), the bottom wall (51) of the etching groove (5) is composed of the silicon nitride (12), the side wall (52) of the etching groove (5) is composed of the vanadium oxide and the silicon nitride (12) below the vanadium oxide, the side wall (52) of the etching groove (5) is continuous and coplanar with the side surface (41) of the shallow groove (4) after the second etching, and the included angle (θ) between the bottom wall (51) of the etching groove (5) and the side wall (52) of the etching groove (5) is less than or equal to 65°; Step six, removing the photoresist (3) to form a device module (100); In step four, the inductively coupled plasma etching uses a radio frequency source, the power of the upper electrode of the radio frequency source is 800-1200 W, the power of the lower electrode of the radio frequency source is 120-200 W, the C / F-based gas is CF4 and CHF3, the flow rate of CF4 is 50-90 sccm, the flow rate of CHF3 is 40-60 sccm, and the flow rate of Ar gas is 40-80 sccm; the pressure formed by CF4, CHF3 and Ar in the first etching is 8-12 mT; the process time of the first etching is 10-20 s; and the included angle between the side surface (41) which becomes an inclined surface and the top surface of the vanadium oxide film (13) is less than or equal to 75°; In step five, the inductively coupled plasma etching uses a radio frequency source, the power of the upper electrode of the radio frequency source is 100-400 W, the power of the lower electrode of the radio frequency source is 50-200 W, the Cl-based gas is chlorine, the flow rate of the chlorine is 20-200 sccm, and the flow rate of Ar gas is 20-80 sccm; the pressure formed by the chlorine and Ar in the etching is 8-14 mT.

2. The etching method of the vanadium oxide film according to claim 1, characterized in that ​ In step one, the base module (1) further comprises a silicon dioxide layer (14) which is directly located between the substrate (11) and the silicon nitride (12) along the stacking direction of the base module (1).

3. The method according to claim 1, wherein the etching solution is a mixture of phosphoric acid and nitric acid. In step one, the thickness of the vanadium oxide film (13) is In step two, the thickness of the mask (2) is The non-metallic nitride is silicon nitride.

4. The method according to claim 1, wherein the etching solution is a mixture of phosphoric acid and nitric acid. In step four and step five, the angle (θ) between the bottom wall (51) of the etching groove (5) and the side wall (52) of the etching groove (5) is 20-60°.

5. The method according to claim 4, wherein the etching solution is a mixture of phosphoric acid and nitric acid. In step four and step five, the angle (θ) between the bottom wall (51) of the etching groove (5) and the side wall (52) of the etching groove (5) is 25-45°.

6. The method according to claim 5, wherein the etching solution is a mixture of phosphoric acid and nitric acid. In step four and step five, the angle (θ) between the bottom wall (51) of the etching groove (5) and the side wall (52) of the etching groove (5) is preferably 30°.

7. The method according to claim 1, wherein the etching solution is a mixture of phosphoric acid and nitric acid. In step five, the etch depth is into the surface of the silicon nitride (12) adjacent to the vanadium oxide film (13) 8. The method according to claim 1, wherein the etching solution is a mixture of phosphoric acid and nitric acid. In step five, the process time for the first etching is automatically grabbed by a spectrometer; The process time comprises a main etching time and an over-etching time, The main etching time is defined as the time when the depth of the etching groove (5) formed during the etching process reaches the surface of the silicon nitride (12); The over-etching time is defined as the time when the etching starts to enter the surface below the silicon nitride (12) adjacent to the vanadium oxide film (13) until the etching is terminated; The main etching time is 20-30s; The over-etching time is 20%-40% of the main etching time.

9. A plating method of a semiconductor device, characterized by, The method further comprises the following steps: Plating a film on the bottom wall (51) of the etching groove (5), the side wall (52) of the etching groove (5), the side surface (41) of the shallow groove (4) and the surface of the mask (2) of the device module (100) prepared by the etching method of the vanadium oxide film according to any one of claims 1-8.

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