SiC VDMOS device structure resistant to single particle radiation

Abstract

The application discloses an anti-single-particle radiation SiC VDMOS device structure and belongs to the field of semiconductor devices.The device structure comprises an N-drift region, a P-base region, a P+ high-concentration region, a P+ low-concentration region, an N+ source region, a metal source electrode, a metal drain electrode, a gate oxide layer and a gate polysilicon layer.The N-drift region is located on the top surface of the metal drain electrode; the P-base region is in an L shape and is located on the top of the N-drift region; the P+ high-concentration region is located on the top of the N-drift region and the lower plane of the L-shaped P-base region; the P+ low-concentration region and the N+ source region are both located on the P+ high-concentration region; the metal source electrode is located on the P+ low-concentration region and the N+ source region; the gate oxide layer is located at the middle position of the top of the N-drift region and is in contact with the P-base region and the N+ source region; and the gate polysilicon layer is located above the gate oxide layer.After particle incidence, the P-base region and the P+ high-concentration region expand the electric field range, thereby inhibiting the conduction of a parasitic NPN transistor and effectively improving the anti-single-particle burnout capability of the SiC VDMOS device.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor devices, in particular to a SiC VDMOS device structure resistant to single particle radiation. BACKGROUND

[0002] Compared with silicon (Si), silicon carbide (SiC) material has a series of advantages such as wide band gap, high breakdown field and high thermal conductivity, which can greatly reduce the number and volume of power devices and heat sinks in the equipment; at the same time, the SiC device manufacturing process matches the Si device process technology, which can reduce production cost, so the power MOSFET device prepared by SiC material has important application and broad prospect in the fields of communication, power supply and power transmission.

[0003] However, when the SiC VDMOS device works in a space environment or a nuclear environment, due to the ionization effect caused by particle collision, a large number of electron-hole pairs will be generated inside the device by the incident high-energy particles, and with the drift and diffusion of the carriers, the parasitic transistor will be turned on, and then the single event burnout (SEB) effect will occur, therefore, how to improve the single particle radiation resistance of SiC VDMOS device has been a hot and difficult point of research. SUMMARY

[0004] The purpose of the present application is to provide a SiC VDMOS device structure resistant to single particle radiation, so as to solve the problem of single event burnout effect caused by excessive local temperature of SiC power device under the influence of heavy ions.

[0005] To solve the above technical problems, the present application provides a SiC VDMOS device structure resistant to single particle radiation, which comprises an N-drift region, a P-base region, a P+ high concentration region, a P+ low concentration region, an N+ source region, a metal source electrode, a metal drain electrode, a gate oxide layer and a gate polysilicon layer.

[0006] The N-drift region is located on the top surface of the metal drain electrode.

[0007] The P-base region is in the shape of "L" and is located on the top of the N-drift region.

[0008] The P+ high concentration region is located on the top of the N-drift region and the lower plane of the "L"-shaped P-base region.

[0009] The P+ low concentration region and the N+ source region are both located on the P+ high concentration region.

[0010] The metal source electrode is located on the P+ low concentration region and the N+ source region.

[0011] The gate end oxide layer is located in the middle of the top of the N-drift region and contacts the P-base region and the N+ source region; the gate end polysilicon layer is located above the gate end oxide layer.

[0012] In an embodiment, the P+ high concentration region is located in the surrounding area of the P+ low concentration region, the N+ source region, the P-base region and the N-drift region.

[0013] In an embodiment, the metal source end electrode covers the junction of the P+ low concentration region and the N+ source region.

[0014] In an embodiment, the depth of the P-base region is greater than or equal to the sum of the depths of the N+ source region and the P+ high concentration region.

[0015] In an embodiment, the depth of the P+ low concentration region is greater than the depth of the N+ source region.

[0016] In an embodiment, the width of the P+ high concentration region is the sum of the widths of the P+ low concentration region and the N+ source region.

[0017] In an embodiment, the doping concentration of the P+ high concentration region is higher than the doping concentration of the P+ low concentration region.

[0018] In an embodiment, the doping concentration of the P+ high concentration region is 1E20 cm -3 ~ 1E21 cm -3 .

[0019] In an embodiment, the doping concentration of the P+ low concentration region is 1E19 cm -3 ~ 1E20 cm -3 .

[0020] In the SiC VDMOS device structure provided by the present application, which is resistant to single-particle radiation, there are an N-drift region, a P-base region, a P+ high concentration region, a P+ low concentration region, an N+ source region, a metal source end electrode, a metal drain end electrode, a gate end oxide layer and a gate end polysilicon layer; after particle incidence, the P-base region and the P+ high concentration region expand the electric field range, thereby inhibiting the conduction of the parasitic NPN transistor, effectively improving the ability of the SiC VDMOS device to resist single-particle burnout. BRIEF DESCRIPTION OF DRAWINGS

[0021] Figure 1 is a schematic diagram of a SiC VDMOS device structure provided by the present application, which is resistant to single-particle radiation;

[0022] Figure 2(a) is a schematic diagram of a conventional planar SiC VDMOS device structure;

[0023] Figure 2(b) is a schematic diagram of the total current density of a conventional planar SiC VDMOS device after irradiation;

[0024] Figure 3(a) is a schematic diagram of the SiC VDMOS device structure of the present invention;

[0025] Figure 3(b) is a schematic diagram of the total current density of the SiC VDMOS device after irradiation according to the present invention;

[0026] Figure 4 This is a schematic diagram of the drain current of the present invention and a conventional planar SiC VDMOS device after 10 ns of particle incidence;

[0027] Figure 5 This is a schematic diagram of the device temperature of the present invention and the conventional planar SiC VDMOS device after 10 ns of particle incident. Detailed Implementation

[0028] The following detailed description, in conjunction with the accompanying drawings and specific embodiments, provides a further detailed explanation of the single-event radiation resistant SiC VDMOS device structure proposed in this invention. The advantages and features of this invention will become clearer from the following description and claims. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of this invention.

[0029] This invention provides a SiC VDMOS device structure resistant to single-event radiation, as follows: Figure 1 As shown, it includes an N-drift region 1, a P-base region 2, a P+ high-concentration region 3, a P+ low-concentration region 4, an N+ source region 5, a metal source electrode 6, a metal drain electrode 7, a gate oxide layer 8, and a gate polysilicon layer 9. The N-drift region 1 is located on the top surface of the metal drain electrode 7; the P-base region 2 is L-shaped and located on top of the N-drift region 1, and the lower plane of the L-shaped P-base region 2 may be horizontal with the plane of the N-drift region 1 or may not be horizontal; the P+ high concentration region 3 is located on both the top of the N-drift region 1 and the lower plane of the L-shaped P-base region 2; the P+ low concentration region 4 and the N+ source region 5 are both located on the P+ high concentration region 3; the metal source electrode 6 is located on the P+ low concentration region 4 and the N+ source region 5; the gate oxide layer 8 is located at the top center of the N-drift region 1 and is in contact with the P-base region 2 and the N+ source region 5; the gate polysilicon layer 9 is located above the gate oxide layer 8.

[0030] As shown in Fig. 2(a) and Fig. 3(a), the conventional planar SiC VDMOS device and the device of the present application are modeled by using DevEdit device editor of Technology Computer Aided Design (TCAD) software of Silvaco Company. In Fig. 2(a) and Fig. 3(a), the same reference numerals refer to the same. Figure 1

[0031] Referring to Fig. 2(a), the concentrations of the regions of the conventional planar SiC VDMOS device are as follows: the concentration of N-drift region 1 is 5E15 cm -3 , the concentration of P-base region 2 is 1E18 cm -3 , the concentration of P+ low concentration region 4 is 4.5E19 cm -3 , and the concentration of N+ source region 5 is 4.5E19 cm -3 . The height of P+ low concentration region 4 and N+ source region 5 is substantially the same. The width of P-base region 2 is the sum of the channel length, the width of N+ source region 5 and the width of P+ low concentration region 4.

[0032] Referring to Fig. 3(a), the dimensions and concentrations of the regions of the device of the present application are as follows: the concentration of N-drift region 1 is 5E15 cm -3 , the concentration of P-base region 2 is 1E18 cm -3 , the concentration of P+ high concentration region 3 is 5E20 cm -3 , the concentration of P+ low concentration region 4 is 4.5E19 cm -3 , and the concentration of N+ source region 5 is 4.5E19 cm -3 . The height of P-base region 2 is the sum of the height of P+ high concentration region 3, the height of P+ low concentration region 4 and the height of the portion of P-base region 2 under P+ high concentration region 3. The width of P-base region 2 is the sum of the channel length and the width of the portion of P-base region 2 under P+ high concentration region 3. The height of P+ low concentration region 4 and the height of N+ source region 5 are substantially the same. The width of P+ high concentration region 3 is the sum of the width of P+ low concentration region 4 and the width of N+ source region 5.

[0033] ​As shown in Fig. 2(b) and Fig. 3(b), the single particle effect simulation is carried out by using the Atlas simulation module, the selected models include the carrier generation and recombination (Shockly-Read-Hall, SRH) model, the recombination model and Auger recombination model, the parallel electric field dependence (FLDMOB) model, the concentration temperature dependence (Analytic) model, the impact ionization (Impact Selb) model and the incomplete ionization (Imcomplete) model, the particles are vertically injected and ejected from the gate end of the SiC VDMOS device, the selected particle LET = 10 MeV·cm2 / mg, the current density on the path through which the particles pass after being injected will be significantly increased.

[0034] As shown in Fig. 2(b) and Fig. 3(b), the single particle effect simulation is carried out by using the Atlas simulation module, the selected models include the carrier generation and recombination (Shockly-Read-Hall, SRH) model, the recombination model and Auger recombination model, the parallel electric field dependence (FLDMOB) model, the concentration temperature dependence (Analytic) model, the impact ionization (Impact Selb) model and the incomplete ionization (Imcomplete) model, the particles are vertically injected and ejected from the gate end of the SiC VDMOS device, the selected particle LET = 10 MeV·cm2 / mg, the current density on the path through which the particles pass after being injected will be significantly increased. Figure 4 As shown in Fig. 2(b) and Fig. 3(b), the single particle effect simulation is carried out by using the Atlas simulation module, the selected models include the carrier generation and recombination (Shockly-Read-Hall, SRH) model, the recombination model and Auger recombination model, the parallel electric field dependence (FLDMOB) model, the concentration temperature dependence (Analytic) model, the impact ionization (Impact Selb) model and the incomplete ionization (Imcomplete) model, the particles are vertically injected and ejected from the gate end of the SiC VDMOS device, the selected particle LET = 10 MeV·cm2 / mg, the current density on the path through which the particles pass after being injected will be significantly increased. Figure 5 As shown in Fig. 2(b) and Fig. 3(b), the single particle effect simulation is carried out by using the Atlas simulation module, the selected models include the carrier generation and recombination (Shockly-Read-Hall, SRH) model, the recombination model and Auger recombination model, the parallel electric field dependence (FLDMOB) model, the concentration temperature dependence (Analytic) model, the impact ionization (Impact Selb) model and the incomplete ionization (Imcomplete) model, the particles are vertically injected and ejected from the gate end of the SiC VDMOS device, the selected particle LET = 10 MeV·cm2 / mg, the current density on the path through which the particles pass after being injected will be significantly increased.

[0035] The above description is only a description of the preferred embodiments of the present application, and does not limit the scope of the present application in any way, any modification or modification made by a person skilled in the art according to the above disclosure is within the protection scope of the claims.

Claims

1. A SiC VDMOS device structure resistant to single particle radiation, characterized in that, The N-drift region (1), the P-base region (2), the P+ high concentration region (3), the P+ low concentration region (4), the N+ source region (5), the metal source electrode (6), the metal drain electrode (7), the gate oxide layer (8) and the gate polysilicon layer (9); The N-drift region (1) is located on the top surface of the metal drain electrode (7); The P-base region (2) is in the shape of "L" and is located on the top of the N-drift region (1); The P+ high concentration region (3) is located on the top of the N-drift region (1) and the lower plane of the "L"-shaped P-base region (2); The P+ low concentration region (4) and the N+ source region (5) are both located on the P+ high concentration region (3); The metal source electrode (6) is located on the P+ low concentration region (4) and the N+ source region (5); The gate oxide layer (8) is located on the top of the N-drift region (1) and contacts the P-base region (2) and the N+ source region (5); and the gate polysilicon layer (9) is located above the gate oxide layer (8).

2. The SiC VDMOS device structure resistant to single-particle radiation according to claim 1, wherein, The P+ high concentration region (3) is located in the surrounding area of the P+ low concentration region (4), the N+ source region (5), the P-base region (2) and the N-drift region (1).

3. The SiC VDMOS device structure resistant to single particle radiation as claimed in claim 1, wherein, The metal source electrode (6) covers the junction of the P+ low concentration region (4) and the N+ source region (5).

4. The single event radiation resistant SiC VDMOS device structure of claim 1, wherein, The depth of the P-base region (2) is greater than or equal to the sum of the depths of the N+ source region (5) and the P+ high concentration region (3).

5. The SiC VDMOS device structure resistant to single particle radiation of claim 1, wherein, The depth of the P+ low concentration region (4) is greater than the depth of the N+ source region (5).

6. The SiC VDMOS device structure resistant to single-particle radiation of claim 1, wherein, The width of the P+ high concentration region (3) is the sum of the widths of the P+ low concentration region (4) and the N+ source region (5).

7. The SiC VDMOS device structure resistant to single particle radiation of claim 1, wherein, The doping concentration of the P+ high concentration region (3) is higher than that of the P+ low concentration region (4).

8. The single event radiation resistant SiC VDMOS device structure of claim 7, wherein, The P+ high concentration region (3) has a doping concentration of 1E20 cm -3 ~1E21 cm -3 .

9. The SiC VDMOS device structure resistant to single particle radiation as claimed in claim 7, wherein, The P+ low concentration region (4) has a doping concentration of 1E19 cm -3 ~1E20 cm -3 .

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