Wafer level packaged device and method of manufacturing the same

Abstract

This invention provides a wafer-level packaged device and its fabrication method. The wafer-level packaged device includes at least a molding layer and a 3D IPD structure fabricated within the molding layer. By fabricating an integrated 3D IPD structure within the molding layer, this invention enables the fabrication of higher-performance system-level package structures. Furthermore, the wafer-level packaged device of this invention can simultaneously integrate various electronic chips and components such as millimeter-wave antennas, capacitors, inductors, transistors, GPUs, PMUs, DDR, flash memory, and filters, offering greater flexibility and broader compatibility, thereby reducing package size and lowering packaging costs.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor packaging technology, and in particular relates to a wafer-level packaging device and its fabrication method. Background Technology

[0002] As electronic products, such as computers, tablets, mobile phones, automobiles, home appliances, and IoT devices, develop towards smaller, faster, more energy-efficient, and higher-performance devices, the demand for miniaturization and integration of chips is gradually increasing. Packaging more functional modules into a single chip will inevitably become one of the important trends in the future of semiconductor packaging.

[0003] Typically, to achieve product integration, active devices such as switches, low-noise amplifiers, power amplifiers, baseband, and application processors need to be integrated on a single wafer. In addition, increasingly, wafer-level packaging requires the integration of RF IPDs (Integrated Passive Devices), such as filters, to effectively reduce the size of RF modules.

[0004] Most existing technologies use planar IPDs. Since these IPDs are fabricated on a 2D plane parallel to the silicon substrate, they cannot meet the integration requirements of RF packaging structures, nor can they meet the packaging performance requirements, especially under high-frequency conditions.

[0005] In existing technologies, independent IPDs can also be fixed to the substrate structure using flip chip bonding (FC) or wire bonding (WB). IPDs introduced using this method require additional package space, and a potential problem is that the performance of the packaged IPD may deteriorate due to the introduction of solder balls or wire bonding.

[0006] Therefore, how to integrate 3D IPD into wafer-level packaged devices is a problem that needs to be solved by those skilled in the art. Summary of the Invention

[0007] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a wafer-level packaged device and its fabrication method, which solves the problems of insufficient integration and high cost of the existing IPD in the packaged device.

[0008] To achieve the above and other related objectives, the present invention provides a wafer-level packaging device, the wafer-level packaging device comprising at least a molding layer and a 3D IPD structure fabricated in the molding layer.

[0009] Preferably, the 3D IPD structure includes one or more of the following: a 3D inductor IPD structure, a 3D capacitor IPD structure, and a 3D resistor IPD structure.

[0010] Preferably, the molding layer includes a first surface and a second surface opposite to the first surface, and the 3D inductor IPD structure includes:

[0011] Multiple first metal bonding pads are formed in the first surface of the molding layer;

[0012] Metal pillars are formed in the molding layer and located at both ends of the first metal pad layer;

[0013] A second metal pad layer is formed on the second surface of the molding layer, and the second metal pad layer sequentially connects the metal pillars at both ends of each of the first metal pad layers to form a 3D inductor IPD structure.

[0014] Preferably, the 3D capacitor IPD structure includes at least one set of oppositely disposed metal layers formed in the molding layer, wherein the plane of each set of metal layers is perpendicular to the molding layer.

[0015] Preferably, the wafer-level packaged device further includes a first redistribution layer formed on a first surface of the molding layer and a second redistribution layer formed on a second surface of the molding layer, wherein the first redistribution layer includes a first dielectric layer and a first wiring metal layer formed in the first dielectric layer and connected to the 3D IPD structure, and the second redistribution layer includes a second dielectric layer and a second wiring metal layer formed in the second dielectric layer and connected to the 3D IPD structure.

[0016] Preferably, the wafer-level packaging device is a fan-out wafer-level packaging device, and further includes:

[0017] A metal connecting post is formed in the molding layer and connected to the first wiring metal layer and the second wiring metal layer;

[0018] Multiple chips are soldered to the surface of the second redistribution layer and connected to the second redistribution metal layer;

[0019] Solder balls are formed on the surface of the first redistribution layer and are connected to the first wiring metal layer.

[0020] Preferably, the wafer-level packaging device is an RF ASIC wafer-level packaging device, and further includes:

[0021] An RF ASIC chip is formed on the surface of the second redistribution layer and connected to the second wiring metal layer;

[0022] Solder balls are formed on the surface of the first redistribution layer and are connected to the first wiring metal layer.

[0023] The present invention also provides a method for fabricating a wafer-level packaged device, the method comprising at least:

[0024] Preparation of molding layer;

[0025] A 3D IPD structure is formed in the molding layer.

[0026] Preferably, the 3D IPD structure includes one or more of the following: an inductor IPD structure, a capacitor IPD structure, and a resistor IPD structure.

[0027] Preferably, the method for fabricating the inductor IPD structure in the molding layer includes:

[0028] A substrate having a release layer is provided, and a plurality of first metal pad layers are formed on the surface of the release layer;

[0029] Metal pillars are formed on both ends of the first metal pad layer;

[0030] A molding layer is formed on the surface of the release layer, covering the metal pillar and the first metal pad layer, and the molding layer and the metal pillar are thinned.

[0031] A second metal bonding pad layer is formed on the surface of the molding layer, and the second metal bonding pad layer sequentially connects the metal pillars at both ends of each of the first metal bonding pad layers;

[0032] The substrate is removed through the release layer, thereby forming a 3D inductor IPD structure.

[0033] Preferably, the method for fabricating the 3D capacitor IPD structure in the molding layer includes:

[0034] A substrate having a release layer is provided, and a molding layer is formed with the surface of the release layer;

[0035] The molding layer is etched to form at least one set of oppositely disposed openings that expose the release layer;

[0036] The opening is filled with a metal layer material to form at least one set of oppositely arranged metal layers, and the plane of each set of metal layers is perpendicular to the molding layer.

[0037] The substrate is removed through the release layer, thereby forming a 3D capacitor IPD structure.

[0038] Preferably, the method for fabricating the wafer-level packaged device further includes:

[0039] A first redistribution layer is formed on a first surface of the molding layer, and a second redistribution layer is formed on a second surface of the molding layer. The first redistribution layer includes a first dielectric layer and a first wiring metal layer formed in the first dielectric layer and connected to the 3D IPD structure. The second redistribution layer includes a second dielectric layer and a second wiring metal layer formed in the second dielectric layer and connected to the 3D IPD structure.

[0040] Preferably, the method for fabricating the wafer-level packaged device further includes:

[0041] Metal connecting pillars are formed in the molding layer, and the metal connecting pillars are connected to the first wiring metal layer and the second wiring metal layer;

[0042] Multiple chips are soldered onto the surface of the second redistribution layer, and the chips are connected to the second redistribution metal layer;

[0043] Solder balls are formed on the surface of the first redistribution layer and connected to the first redistribution metal layer to form a fan-out wafer-level package device.

[0044] Preferably, the method for fabricating the wafer-level packaged device further includes:

[0045] An RF ASIC chip is soldered onto the surface of the second redistribution layer, and the RF ASIC chip is connected to the second redistribution metal layer;

[0046] Solder balls are formed on the surface of the first redistribution layer and connected to the first redistribution metal layer to form an RF ASIC wafer-level packaged device.

[0047] As described above, this invention provides a wafer-level packaged device and its fabrication method. The wafer-level packaged device includes at least a molding layer and a 3D IPD structure fabricated within the molding layer. By fabricating an integrated 3D IPD structure within the molding layer, this invention enables the fabrication of higher-performance system-level package structures. Furthermore, the wafer-level packaged device of this invention can simultaneously integrate various electronic chips and components such as millimeter-wave antennas, capacitors, inductors, transistors, GPUs, PMUs, DDR, flash memory, and filters, exhibiting greater flexibility and broader compatibility, thereby reducing package size and lowering packaging costs. Attached Figure Description

[0048] Figures 1 to 7 This is a schematic diagram showing the various steps of the fabrication method of the 3D IPD structure in the wafer-level packaged device of the present invention.

[0049] Figure 8 and Figure 9 These are three-dimensional schematic diagrams of two types of 3D IPD structures.

[0050] Figure 10 and Figure 12 These are schematic diagrams of the first and second redistribution layers in the wafer-level packaging device of the present invention.

[0051] Figure 11 This is a schematic diagram of the structure of the RF ASIC wafer-level packaged device integrating 3D IPD according to the present invention.

[0052] Figure 13 This is a schematic diagram of the structure of the fan-out wafer-level packaged device integrating 3D IPD of the present invention.

[0053] Component designation explanation

[0054] 1 Molding layer

[0055] 2 3D IPD Structure

[0056] 21 3D Inductor IPD Structure

[0057] 211 First metal bonding pad

[0058] 212 Metal Column

[0059] 213 Second metal bonding pad

[0060] 22 3D Capacitor IPD Structure

[0061] 221 Metal Layer

[0062] 3 First Rerouting Layer

[0063] 31 First dielectric layer

[0064] 32 First wiring metal layer

[0065] 4 Second Rerouting Layer

[0066] 41 Second dielectric layer

[0067] 42 Second wiring metal layer

[0068] 5 Metal connecting columns

[0069] 6 chips

[0070] 7, 8 solder balls

[0071] 9 RF ASIC chips

[0072] 10 Substrates

[0073] 11 Release Layer Detailed Implementation

[0074] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0075] Please refer to the accompanying drawings. It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0076] This embodiment provides a wafer-level packaged device, such as Figure 7 , Figure 8 and Figure 9 As shown, the wafer-level packaged device includes at least a molding layer 1 and a 3D IPD structure fabricated in the molding layer 1.

[0077] As an example, the molding layer 1 comprises an epoxy resin, a liquid thermosetting epoxy resin, or a plastic molding compound, and the method for forming the molding layer 1 includes one of compression molding, transfer molding, liquid encapsulation molding, vacuum lamination, and spin coating. The thickness of the molding layer 1 ranges from 10 μm to 200 μm, for example, it can be 30 μm, 50 μm, 80 μm, 100 μm, 150 μm, 180 μm, etc.

[0078] As an example, the 3D IPD structure includes one or more combinations of 3D inductor IPD structure 21, 3D capacitor IPD structure 22, and 3D resistor IPD structure. Of course, depending on the specific package type, the 3D IPD structure can also be designed as other passive devices, and there are no restrictions here.

[0079] In one embodiment, such as Figure 7 and Figure 8As shown, the molding layer 1 includes a first surface and a second surface opposite to the first surface. The 3D inductor IPD structure 21 includes multiple first metal pad layers 211, metal pillars 212, and second metal pad layers 213. The multiple first metal pad layers 211 are formed in the first surface of the molding layer 1; the metal pillars 212 are formed in the molding layer 1 and located at both ends of the first metal pad layers 211; the second metal pad layers 213 are formed in the second surface of the molding layer 1, and the second metal pad layers 213 sequentially connect the metal pillars 212 at both ends of each first metal pad layer 211 to form the 3D inductor IPD structure 21. Figure 7 This is a cross-sectional schematic diagram. Figure 8 This is a three-dimensional schematic diagram.

[0080] As an example, the material of the first metal pad layer 211 includes, but is not limited to, copper. The methods for forming the first metal pad layer 211 include, but are not limited to, PVD, CVD, sputtering, electroplating, and electroless plating. The first metal pad layers 211 are arranged in parallel.

[0081] As an example, the metal pillar 212 includes, but is not limited to, a copper pillar or a titanium pillar, and the method for forming the metal pillar 212 includes, but is not limited to, PVD, CVD, sputtering, electroplating and electroless plating.

[0082] As an example, the material of the second metal pad layer 213 includes, but is not limited to, copper. Methods for forming the second metal pad layer 213 include, but are not limited to, PVD, CVD, sputtering, electroplating, and electroless plating. The second metal pad layers 213 are arranged in parallel.

[0083] In another embodiment, such as Figure 9 As shown, the 3D capacitor IPD structure 22 includes at least one set of metal layers 221 formed in the molding layer 1 and disposed opposite to each other, wherein the plane of each set of metal layers 221 is perpendicular to the molding layer 1.

[0084] It should be noted that the above only provides 3D inductor IPD structure 21 and 3D capacitor IPD structure 22 respectively. In other embodiments, there may be other 3D IPD structures, which will not be listed here.

[0085] As an example, such as Figure 10 and Figure 12As shown, the wafer-level packaged device further includes a first redistribution layer 3 formed on a first surface of the molding layer 1 and a second redistribution layer 4 formed on a second surface of the molding layer 1. The first redistribution layer 3 includes a first dielectric layer 31 and a first wiring metal layer 32 formed in the first dielectric layer 31 and connected to the 3D IPD structure 2. The second redistribution layer 4 includes a second dielectric layer 41 and a second wiring metal layer 42 formed in the second dielectric layer 41 and connected to the 3D IPD structure 2.

[0086] Figure 10 The first wiring metal layer 32 and the second wiring metal layer 42 are not shown.

[0087] As an example, the materials of the first dielectric layer 31 and the second dielectric layer 41 include one of epoxy resin, silicone, PI, PBO, BCB, silicon oxide, phosphosilicate glass and fluorinated glass.

[0088] As an example, the material of the first wiring metal layer 32 and the second wiring metal layer 42 includes one of copper, aluminum and titanium metals, and the method of forming the first wiring metal layer 32 and the second wiring metal layer 42 includes one of PVD, CVD, sputtering, electroplating and chemical plating. The first wiring metal layer 32 and the second wiring metal layer 42 include a single layer or a multilayer structure.

[0089] The wafer-level packaging device may also include other structural layers to form different types of wafer-level packaging devices.

[0090] In one embodiment, such as Figure 11 As shown, the wafer-level packaging device is an RF ASIC wafer-level packaging device, which further includes an RF ASIC chip 9 and solder balls 8. The RF ASIC chip 9 is formed on the surface of the second redistribution layer 4 and connected to the second wiring metal layer (not shown); the solder balls 8 are formed on the surface of the first redistribution layer 3 and connected to the first wiring metal layer (not shown).

[0091] In another embodiment, such as Figure 13 As shown, the wafer-level packaging device is a fan-out wafer-level packaging device, which further includes metal connection pillars 5, multiple chips 6, and solder balls 7. The metal connection pillars 5 are formed in the molding layer 1 and connected to the first wiring metal layer 32 and the second wiring metal layer 42; the chips 6 are soldered to the surface of the second redistribution layer 4 and connected to the second wiring metal layer 42; the solder balls 7 are formed on the surface of the first redistribution layer 3 and connected to the first wiring metal layer 32.

[0092] The solder balls 7 and 8 may be made of materials including, but not limited to, copper or nickel. The surface of the first wiring metal layer 32 may only have solder balls 7 and 8 formed, or metal pillars (not shown) may be formed first, and then solder balls 7 and 8 may be formed; there is no limitation on this.

[0093] It should be noted that the wafer-level packaging device of the present invention can be an RF ASIC wafer-level packaging device and a fan-out wafer-level packaging device, or any other device that needs to integrate a 3D IPD structure, which is not limited here.

[0094] This embodiment also provides a method for fabricating a wafer-level packaged device. The wafer-level packaged device can be obtained by using this method. The fabrication method includes at least: firstly, fabricating a molding layer 1; and then forming a 3D IPD structure 2 in the molding layer.

[0095] As an example, the 3D IPD structure 2 includes one or more of the following: a 3D inductor IPD structure 21, a 3D capacitor IPD structure 22, and a 3D resistor IPD structure. Of course, depending on the specific package type, the 3D IPD structure 2 can also be designed as other passive devices, and this is not a limitation.

[0096] In one embodiment, the 3D IPD structure 2 is a 3D inductor IPD structure 21, and the method for fabricating the 3D inductor IPD structure 21 in the molding layer 1 may include the following steps:

[0097] First, such as Figure 1 As shown, a substrate 10 with a release layer 11 is provided, and so on... Figure 2 As shown, multiple first metal pad layers 211 are formed on the surface of the release layer 11.

[0098] As an example, the substrate 10 includes one of a glass substrate, a metal substrate, a semiconductor substrate, a polymer substrate, and a ceramic substrate. In this embodiment, the substrate 10 is selected as a semiconductor substrate, such as a silicon wafer. The shape of the substrate 10 can be circular, square, or any other desired shape. In this embodiment, the substrate 10 is used to prevent problems such as cracking, warping, and breakage of the device structure layer during subsequent fabrication.

[0099] The release layer 11 is used for subsequent separation of the substrate 10, the molding layer 1, and the first metal pad layer 211. The release layer 11 includes either an adhesive tape layer or a polymer layer. The release layer 11 is coated onto the surface of the substrate 10 by a spin coating process, and then cured and shaped by a laser curing, ultraviolet curing, or thermal curing process.

[0100] As an example, the material of the first metal pad layer 211 includes, but is not limited to, copper. The methods for forming the first metal pad layer 211 include, but are not limited to, PVD, CVD, sputtering, electroplating, and electroless plating. The first metal pad layers 211 are arranged in parallel.

[0101] Then, as Figure 3 As shown, metal pillars 212 are formed on both ends of the first metal pad layer 211.

[0102] As an example, the metal pillar 212 includes, but is not limited to, a copper pillar or a titanium pillar, and the method for forming the metal pillar 212 includes, but is not limited to, PVD, CVD, sputtering, electroplating and electroless plating.

[0103] Next, as Figure 4 As shown, a molding layer 1 is formed on the surface of the release layer 11, covering the metal pillar 212 and the first metal pad layer 211, as follows: Figure 5 As shown, the molding layer 1 and the metal pillar 212 are thinned.

[0104] As an example, the molding layer 1 includes an epoxy resin, a liquid thermosetting epoxy resin, and a plastic molding compound. The method for forming the molding layer 1 includes one of compression molding, transfer molding, liquid encapsulation molding, vacuum lamination, and spin coating. The formed molding layer 1 is as follows... Figure 4 As shown, the metal pillar 212 is then thinned and planarized using methods including but not limited to grinding to expose its surface, resulting in the following: Figure 5 The structure shown.

[0105] Next, as Figure 6 As shown, a second metal solder pad layer 213 is formed on the surface of the molding layer 1, and the second metal solder pad layer 213 sequentially connects the metal pillars 212 at both ends of each of the first metal solder pad layers 211.

[0106] As an example, the material of the second metal pad layer 213 includes, but is not limited to, copper. Methods for forming the second metal pad layer 213 include, but are not limited to, PVD, CVD, sputtering, electroplating, and electroless plating. The second metal pad layers 213 are arranged in parallel.

[0107] Finally, as Figure 7 As shown, the substrate 10 is removed through the release layer 11, thereby forming a 3D inductor IPD structure 21.

[0108] Please refer to the attached document. Figure 8 , Figure 8 for Figure 7The three-dimensional structural diagram shows more clearly the 3D inductor IPD structure 21 prepared in the molding layer 1.

[0109] In another embodiment, the 3D IPD structure 2 is a 3D capacitor IPD structure 22, and the method for fabricating the 3D capacitor IPD structure 22 in the molding layer 1 may include the following steps:

[0110] First, the method for fabricating the 3D capacitor IPD structure in the molding layer includes:

[0111] Then, a substrate having a release layer is provided, and a molding layer is formed with the surface of the release layer;

[0112] Next, the molding layer is etched to form at least one set of oppositely disposed openings that expose the release layer;

[0113] Then, the opening is filled with metal layer material to form at least one set of oppositely arranged metal layers 221, and the plane of each set of metal layers 221 is perpendicular to the molding layer 1;

[0114] Finally, the substrate is removed through the release layer, thereby forming a 3D capacitor IPD structure 22, as shown. Figure 9 The image shown is a 3D view of the IPD structure of a 3D capacitor.

[0115] It should be noted that the above only provides one method for preparing the 3D inductor IPD structure 21 and the 3D capacitor IPD structure 22. In other embodiments, other suitable methods can be used to prepare the corresponding 3D IPD structures, which will not be listed here.

[0116] As an example, such as Figure 10 and Figure 12 As shown, the method for fabricating the wafer-level packaged device may further include the following steps: forming a first redistribution layer 3 on a first surface of the molding layer 1, and forming a second redistribution layer 4 on a second surface of the molding layer 1, wherein the first redistribution layer 3 includes a first dielectric layer 31 and a first wiring metal layer 32 formed in the first dielectric layer 31 and connected to the 3D IPD structure 2, and the second redistribution layer 4 includes a second dielectric layer 41 and a second wiring metal layer 42 formed in the second dielectric layer 41 and connected to the 3D IPD structure 2.

[0117] Figure 10 The first wiring metal layer 32 and the second wiring metal layer 42 are not shown.

[0118] As an example, the materials of the first dielectric layer 31 and the second dielectric layer 41 include one of epoxy resin, silicone, PI, PBO, BCB, silicon oxide, phosphosilicate glass and fluorinated glass.

[0119] As an example, the material of the first wiring metal layer 32 and the second wiring metal layer 42 includes one of copper, aluminum and titanium metals, and the method of forming the first wiring metal layer 32 and the second wiring metal layer 42 includes one of PVD, CVD, sputtering, electroplating and chemical plating. The first wiring metal layer 32 and the second wiring metal layer 42 include a single layer or a multilayer structure.

[0120] Subsequently, the method for fabricating the wafer-level packaged device may also include other steps to form different types of wafer-level packaged devices.

[0121] In one embodiment, it is necessary to form an RF ASIC wafer-level packaged device. The method for fabricating the wafer-level packaged device may further include the following steps, please refer to the appendix. Figure 11 .

[0122] An RF ASIC chip 9 is soldered onto the surface of the second redistribution layer 4, and the RF ASIC chip 9 is connected to the second redistribution metal layer (not shown).

[0123] Solder balls 8 are formed on the surface of the first redistribution layer 3, and the solder balls 8 are connected to the first redistribution metal layer (not shown), thereby forming a... Figure 11 The RF ASIC wafer-level packaged device shown.

[0124] In another embodiment, a fan-out wafer-level packaged device needs to be formed. The method for fabricating the wafer-level packaged device further includes the following steps, please refer to the appendix. Figure 13 .

[0125] First, metal connecting pillars 5 are formed in the molding layer 1, and the metal connecting pillars 5 are connected to the first wiring metal layer 32 and the second wiring metal layer 42. It should be noted that in this step, the fabrication of the metal connecting pillars 5 can be carried out simultaneously with the fabrication of the 3D IPD structure 2, that is, while fabricating the 3D IPD structure 2 in the molding layer 1, the molding layer 1 is etched and metal material is deposited to form the metal connecting pillars 5.

[0126] Then, a plurality of chips 6 are soldered onto the surface of the second redistribution layer 42, and the chips 6 are connected to the second redistribution metal layer 42. Cu-Cu bonding can be used to solder the chips 6, and there is no limitation on this.

[0127] Finally, solder balls 7 are formed on the surface of the first redistribution layer 3, and the solder balls are connected to the first redistribution metal layer 32, thereby forming a... Figure 13 The fan-out wafer-level packaged device shown.

[0128] The solder balls 7 and 8 may be made of materials including, but not limited to, copper or nickel. The surface of the first wiring metal layer 32 may only have solder balls 7 and 8 formed, or metal pillars (not shown) may be formed first, and then solder balls 7 and 8 may be formed; there is no limitation on this.

[0129] It should be noted that the preparation method of the present invention can be used not only to prepare the RF ASIC wafer-level packaged devices and fan-out wafer-level packaged devices listed above, but also any other devices that need to integrate 3D IPD structure 2, which is not limited here.

[0130] The wafer-level packaged device fabrication method of the present invention can achieve the fabrication of a higher performance system-level package structure by fabricating an integrated 3D IPD structure in the molding layer. In addition, the wafer-level packaged device of the present invention can simultaneously integrate various electronic chips and components such as millimeter-wave antennas, capacitors, inductors, transistors, GPUs, PMUs, DDR, flash memory, and filters, which has higher flexibility and wider compatibility, thereby reducing package size and packaging cost.

[0131] Therefore, this invention effectively overcomes the various shortcomings of the prior art and has high industrial application value.

[0132] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for fabricating a wafer-level packaged device, characterized in that, The preparation method includes at least: Preparation of molding layer; A 3D IPD structure is formed in the molding layer; the 3D IPD structure includes one or a combination of 3D inductor IPD structure, 3D capacitor IPD structure and 3D resistor IPD structure. The method for fabricating the 3D inductor IPD structure in the molding layer includes: A substrate having a release layer is provided, and a plurality of first metal pad layers are formed on the surface of the release layer; Metal pillars are formed on both ends of the first metal pad layer; A molding layer is formed on the surface of the release layer, covering the metal pillar and the first metal pad layer, and the molding layer and the metal pillar are thinned. A second metal bonding pad layer is formed on the surface of the molding layer, and the second metal bonding pad layer sequentially connects the metal pillars at both ends of each of the first metal bonding pad layers; The substrate is removed through the release layer, thereby forming a 3D inductor IPD structure.

2. The method for fabricating a wafer-level packaged device according to claim 1, characterized in that: The method for fabricating the 3D capacitor IPD structure in the molding layer includes: A substrate having a release layer is provided, and a molding layer is formed with the surface of the release layer; The molding layer is etched to form at least one set of oppositely disposed openings that expose the release layer; The opening is filled with a metal layer material to form at least one set of oppositely arranged metal layers, and the plane of each set of metal layers is perpendicular to the molding layer. The substrate is removed through the release layer, thereby forming a 3D capacitor IPD structure.

3. The method for fabricating a wafer-level packaged device according to claim 1, characterized in that: The method for fabricating the wafer-level packaged device further includes: A first redistribution layer is formed on a first surface of the molding layer, and a second redistribution layer is formed on a second surface of the molding layer. The first redistribution layer includes a first dielectric layer and a first wiring metal layer formed in the first dielectric layer and connected to the 3D IPD structure. The second redistribution layer includes a second dielectric layer and a second wiring metal layer formed in the second dielectric layer and connected to the 3D IPD structure.

4. The method for fabricating a wafer-level packaged device according to claim 3, characterized in that: The method for fabricating the wafer-level packaged device further includes: Metal connecting pillars are formed in the molding layer, and the metal connecting pillars are connected to the first wiring metal layer and the second wiring metal layer; Multiple chips are soldered onto the surface of the second redistribution layer, and the chips are connected to the second redistribution metal layer; Solder balls are formed on the surface of the first redistribution layer and connected to the first redistribution metal layer to form a fan-out wafer-level package device.

5. The method for fabricating a wafer-level packaged device according to claim 3, characterized in that: The method for fabricating the wafer-level packaged device further includes: An RF ASIC chip is soldered onto the surface of the second redistribution layer, and the RF ASIC chip is connected to the second redistribution metal layer; Solder balls are formed on the surface of the first redistribution layer and connected to the first redistribution metal layer to form an RF ASIC wafer-level packaged device.

6. A wafer-level packaged device prepared by the method for preparing a wafer-level packaged device according to any one of claims 1 to 5, characterized in that, The wafer-level packaged device includes at least a molding layer and a 3D IPD structure fabricated in the molding layer, wherein the 3D IPD structure includes one or more of the following: a 3D inductor IPD structure, a 3D capacitor IPD structure, and a 3D resistor IPD structure. The molding layer includes a first surface and a second surface opposite to the first surface, and the 3D inductor IPD structure includes: Multiple first metal bonding pads are formed in the first surface of the molding layer; Metal pillars are formed in the molding layer and located at both ends of the first metal pad layer; A second metal pad layer is formed on the second surface of the molding layer, and the second metal pad layer sequentially connects the metal pillars at both ends of each of the first metal pad layers to form a 3D inductor IPD structure.

7. The wafer-level packaged device according to claim 6, characterized in that: The 3D capacitor IPD structure includes at least one set of oppositely arranged metal layers formed in the molding layer, wherein the plane of each set of metal layers is perpendicular to the molding layer.

8. The wafer-level packaged device according to claim 6, characterized in that: The wafer-level packaged device further includes a first redistribution layer formed on a first surface of the molding layer and a second redistribution layer formed on a second surface of the molding layer, wherein the first redistribution layer includes a first dielectric layer and a first wiring metal layer formed in the first dielectric layer and connected to the 3D IPD structure, and the second redistribution layer includes a second dielectric layer and a second wiring metal layer formed in the second dielectric layer and connected to the 3D IPD structure.

9. The wafer-level packaged device according to claim 8, characterized in that: The wafer-level packaging device is a fan-out wafer-level packaging device, and further includes: A metal connecting post is formed in the molding layer and connected to the first wiring metal layer and the second wiring metal layer; Multiple chips are soldered to the surface of the second redistribution layer and connected to the second redistribution metal layer; Solder balls are formed on the surface of the first redistribution layer and are connected to the first wiring metal layer.

10. The wafer-level packaged device according to claim 8, characterized in that: The wafer-level packaging device is an RFASIC wafer-level packaging device, and also includes: An RF ASIC chip is formed on the surface of the second redistribution layer and connected to the second wiring metal layer; Solder balls are formed on the surface of the first redistribution layer and are connected to the first wiring metal layer.

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