Semiconductor memory

Abstract

A semiconductor memory includes a plurality of contact pads disposed in an array region of a substrate, and a capacitor array structure disposed on the array region. The capacitor array structure includes a plurality of capacitors each disposed on one of the contact pads, and an intermediate support layer horizontally extending between waists of the plurality of capacitors to divide each of the capacitors into an upper half and a lower half. The lower half of the capacitors adjacent to an edge of the array region is tilted such that the upper half includes a misalignment with the contact pad. This design can adjust stress between adjacent capacitor array structures to achieve a stress buffer effect.

Description

TECHNICAL FIELD

[0001] The present invention relates to a semiconductor memory, in particular, a semiconductor memory including stacked capacitors. BACKGROUND

[0002] Dynamic random access memory (DRAM) is a volatile memory including an array area composed of a plurality of memory cells and a peripheral area composed of a control circuit. Each memory cell is composed of a transistor and a capacitor electrically connected to the transistor, and the storage or release of electric charges in the capacitor is controlled by the transistor to achieve the purpose of storing data. The control circuit can address each memory cell to control the access of data in each memory cell through word lines (WL) and bit lines (BL) that cross the array area and are electrically connected to each memory cell.

[0003] Generally, capacitors are divided into two types, stacked capacitors and trench capacitors. Stacked capacitors are usually disposed on top of transistors, while trench capacitors are usually buried in device substrates. In recent years, in line with the trend of miniaturization of various electronic products, the design of dynamic random access memory devices has also developed towards high integration and high density. Since the memory cells of high-density dynamic random access memory devices are arranged very close to each other, there is almost no way to increase the area of the capacitor in the lateral direction, and it is necessary to increase the height of the stacked capacitor in the vertical direction to increase the area and the value of the capacitor, so the stacked capacitor has become the mainstream structure. However, the overall stacked capacitor is more susceptible to stress and prone to structural defects, causing reliability abnormalities. SUMMARY

[0004] The present invention aims to provide a semiconductor memory including stacked capacitors, wherein the stacked capacitors of the capacitor array structure on the outer side are manufactured to have at least partially inclined axes, with an optimized overall structural stress configuration, to buffer or reduce the stress on the capacitor array structure and improve the reliability of the semiconductor memory.

[0005] One embodiment of the present application provides a semiconductor memory including a substrate including at least an array region and a peripheral region adjacent to an edge of the array region. A plurality of contact pads are disposed in the array region. A capacitor array structure is disposed on the array region. The capacitor array structure includes a plurality of capacitors each disposed on one of the contact pads, and an intermediate support layer horizontally extending between waists of the plurality of capacitors to divide each of the capacitors into an upper half and a lower half, wherein the lower half of the capacitors adjacent to the edge of the array region is tilted to include a misalignment between the upper half and the contact pad.

[0006] Another embodiment of the present application provides a semiconductor memory including a substrate including at least an array region and a peripheral region adjacent to an edge of the array region. A plurality of contact pads are disposed in the array region. A capacitor array structure is disposed on the array region. The capacitor array structure includes a plurality of capacitors each disposed on one of the contact pads, and an intermediate support layer horizontally extending between waists of the plurality of capacitors to divide each of the capacitors into an upper half and a lower half, wherein the upper half of the capacitors adjacent to the edge of the array region is tilted to include a misalignment between the upper half and the contact pad. BRIEF DESCRIPTION OF DRAWINGS

[0007] The accompanying drawings are included to provide a further understanding of the present application and are incorporated in and constitute a part of this specification. The drawings illustrate the principles of the application and, although not necessarily to scale, serve to illustrate various embodiments of the present application. In the drawings, like reference numerals refer to like parts throughout the several views. The drawings are as follows:

[0008] Figure 1 A plan view of a block of a semiconductor memory according to one embodiment of the present application.

[0009] Figure 2 A partial cross-sectional view of the semiconductor memory of Figure 1

[0010] Figure 3 A cross-sectional view of a semiconductor memory according to one embodiment of the present application.

[0011] Figure 4 Another cross-sectional view of the semiconductor memory shown in Figure 3

[0012] A cross-sectional view of a semiconductor memory according to one embodiment of the present application. Figure 5

[0013] Another cross-sectional view of the semiconductor memory shown in Figure 6 Figure 5 Another cross-sectional view of the semiconductor memory shown in​​

[0014] Figure 7 A cross-sectional view of a semiconductor memory according to an embodiment of the present application.

[0015] Figure 8 A cross-sectional view of a semiconductor memory according to an embodiment of the present application. Figure 7 Another cross-sectional view of the semiconductor memory shown.

[0016] Figure 9 A cross-sectional view of a semiconductor memory according to an embodiment of the present application.

[0017] Figure 10 A cross-sectional view of a semiconductor memory according to an embodiment of the present application. Figure 9 Another cross-sectional view of the semiconductor memory shown.

[0018] In the drawings:

[0019] 10 semiconductor memory

[0020] 100 substrate

[0021] 100a edge

[0022] 102 interlayer dielectric layer

[0023] 104 contact pad

[0024] 106 etch stop layer

[0025] 120 capacitor array structure

[0026] 122 capacitor

[0027] 124 intermediate support layer

[0028] 126 top support layer

[0029] 130 insulating cap layer

[0030] 140 planarization layer

[0031] 122a upper half

[0032] 122b lower half

[0033] AX axis

[0034] AX1 upper axis

[0035] AX1-1 extension line

[0036] AX2 lower axis

[0037] BE bottom electrode

[0038] D1 distance

[0039] D2 distance

[0040] D3 distance

[0041] DL dielectric layer

[0042] M1 misalignment

[0043] M2 misalignment

[0044] M3 misalignment

[0045] R1 array region

[0046] R1-1 active array region

[0047] R1-2 dummy array region

[0048] R2 peripheral region

[0049] S1 spacing

[0050] TE top electrode DETAILED DESCRIPTION

[0051] In order to enable one skilled in the art to better understand the present application, several preferred embodiments of the present application are listed below, and the effects and configurations of the present application are described in detail with reference to the accompanying drawings. Those skilled in the art can replace, reorganize, mix the features in several different embodiments to complete other embodiments without departing from the spirit of the present application.

[0052] Referring to Figure 1 is a plan view of a bank of a semiconductor memory 10 according to an embodiment of the present application. The semiconductor memory 10 includes a substrate 100, and a plurality of array regions R1 and a peripheral region R2 defined on the substrate 100. Each array region R1 is a memory array tile (MAT) region, which can be further divided into an active array region R1-1 provided with active memory cells and a dummy array region R1-2 provided with dummy memory cells, wherein the dummy array region R1-2 is interposed between the active array region R1-1 and the peripheral region R2, and surrounds the active cell array region R1-1. The peripheral region R2 is adjacent to the edge of the array region R1, and is internally provided with a local row decoder and a local sense amplifier for controlling the read and write operations of the active memory cells of the array region R1.

[0053] Referring to Figure 2 is Figure 1Fig. 1 is a schematic diagram of a partial cross-sectional view of a semiconductor memory 10. The semiconductor memory 10 of the present application is a stacked capacitor dynamic random access memory (DRAM), which mainly comprises a substrate 100, a capacitor array structure 120 disposed on an array region Rl of the substrate 100, and an insulating cap layer 130 and a planarization layer 140 covering the capacitor array structure 120. The substrate 100 is, for example, a silicon (Si) substrate, an epi-Si substrate, a SiGe substrate, a SiC substrate, or a silicon-on-insulator (SOI) substrate, but is not limited thereto. The substrate 100 has a plurality of transistors (not shown), such as N-type metal-oxide-semiconductor (MOS) transistors, and a plurality of word lines (not shown) and bit lines (not shown) for controlling the switching of the transistors and the read / write operations of memory cells.

[0054] The substrate 100 and the capacitor array structure 120 are separated by an interlayer dielectric layer 102 having a plurality of contact pads 104 for electrically connecting the transistors in the substrate 100 and corresponding capacitors 122 in the capacitor array structure 120. The interlayer dielectric layer 102 is composed of a dielectric material, which can include silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonitride (SiCN), a high-k dielectric material, or a combination thereof, but is not limited thereto. According to an embodiment of the present application, the interlayer dielectric layer 102 mainly comprises silicon nitride (SiN). The contact pads 104 comprise a conductive material, which can include a metal, such as tungsten (W), copper (Cu), aluminum (Al), titanium (Ti), tantalum (Ta), or a compound, an alloy, and / or a composite layer of the aforementioned metal materials, but is not limited thereto. According to an embodiment of the present application, the contact pads 104 mainly comprise tungsten (W). According to some embodiments of the present application, the contact pads 104 are arranged at equal intervals in the interlayer dielectric layer 102, and are separated from each other by a distance S1.

[0055] The capacitor array structure 120 includes a plurality of bottom electrodes BE standing on the contact pads 104 and separated from each other, a capacitor dielectric layer DL covering along the sidewalls of the bottom electrodes BE, and a top electrode TE covering on the capacitor dielectric layer DL and filling the gaps between the bottom electrodes BE. In some embodiments, an etch stop layer 106 is included between the interlayer dielectric layer 102 and the capacitor array structure 120, and the bottom electrodes BE of the respective capacitors 122 each directly contact the contact pads 104 through the etch stop layer 106, and are electrically connected to a corresponding transistor (not shown) in the substrate 100 through the contact pads 104 as a storage node of a storage cell. The etch stop layer 106 includes a dielectric material, such as silicon nitride (SiN), silicon carbide (SiC), silicon carbon nitride (SiCN), nitride doped silicon carbide (NDC), but not limited thereto. The bottom electrodes BE and the top electrode TE each include a conductive material, and the applicable conductive material can include a metal, such as tungsten (W), copper (Cu), aluminum (Al), titanium (Ti), tantalum (Ta), or a compound, alloy, and / or composite layer of the foregoing metal materials, but not limited thereto. In some embodiments, the top electrode TE can include a semiconductor material. The material of the capacitor dielectric layer DL can include silicon oxide (SiO2), silicon nitride (SiN), or a high-k dielectric, but not limited thereto. The bottom electrode BE of the present embodiment can be a hollow cylindrical shape with a closed bottom end, so that the capacitor dielectric layer DL and the top electrode TE also cover along the inner side surface of the bottom electrode BE, increasing the capacitive coupling area between the bottom electrode BE and the top electrode TE, thereby increasing the capacitance. In other embodiments, the bottom electrode BE can be a hollow cylindrical shape or a solid cylindrical shape with an open bottom end, but not limited thereto.

[0056] The capacitor array structure 120 further includes an intermediate support layer 124 connected between the waists of the bottom electrodes BE to provide structural support during the manufacturing process of the capacitor array structure 120, avoiding the collapse of the bottom electrodes BE. Thus, each capacitor 122 can be divided into an upper half 122a above the intermediate support layer 124, and a lower half 122b below the intermediate support layer 124. In some embodiments, the capacitor array structure 120 can further include a top support layer 126 connected between the tops of the bottom electrodes BE to further ensure sufficient structural support of the capacitors 122. The intermediate support layer 124 and the top support layer 126 can include the same or different dielectric materials, such as silicon nitride (SiN), silicon carbide (SiC), silicon carbon nitride (SiCN), nitride doped silicon carbide (NDC), respectively, but not limited thereto.

[0057] AsFigure 2 As shown, each capacitor 122 can include an axis AX extending through the entire height of the capacitor 122 along the center of the capacitor 122. In some embodiments, the axis AX is substantially a straight line without bending when the bottom electrode BE extends straight up without tilting. In more detail, the axis AX can be divided into an upper axis AX1 through the upper half 122a of the capacitor 122 and a lower axis AX2 through the lower half 122b of the capacitor 122, where the lower axis AX2 is preferably substantially vertically aligned with the center of the contact pad 104, so that a larger contact area between the bottom electrode BE and the contact pad 104 can be achieved, thereby reducing the contact resistance.

[0058] The insulating cap layer 130 is conformally deposited on the top and sidewalls of the capacitor array structure 120 (refer to Figure 4 ). The material includes a dielectric material such as silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), but is not limited thereto. The insulating cap layer 130 is used to protect or isolate the capacitor array structure 120. In some embodiments, the insulating cap layer 130 can serve as the etch stop layer 106 when fabricating the top electrode contact plug. The planarization layer 140 is deposited on the substrate 100 and the capacitor array structure 120 and fills the gaps between the capacitor array structure 120 (refer to Figure 4 ) to planarize the significant step difference between the array region R1 and the peripheral region R2 due to the capacitor array structure 120. The planarization layer 140 includes a dielectric material such as silicon oxide (SiO2), undoped silicon glass (USG), boron-doped silicon glass (BSG), boron-phosphorus-doped silicon glass (BPSG), fluorine-doped silicon glass (FSG), silicon oxycarbide (SiOC), or an organic dielectric layer (ODL), but is not limited thereto.

[0059] According to an embodiment of the present application, the method of fabricating the capacitor array structure 120 can include the following steps. First, a stack structure including, from bottom to top, the etch stop layer 106, a sacrificial layer (not shown), the middle support layer 124, another sacrificial layer (not shown), and the top support layer 126 is formed on the substrate 100, and then an etching process is performed to form an array of bottom electrode openings extending through the stack structure and exposing the contact pads 104, respectively. Next, a deposition process is performed to form a conductive layer along the sidewalls and bottom surface of the bottom electrode openings, resulting in hollow cylindrical bottom electrodes BE. Next, the top support layer 126 and the middle support layer 124 are patterned to form openings exposing the sacrificial layers, and then an etching process is performed to hollow out the sacrificial layers, thereby removing the stack structure except in the array region Rl and forming cavities between the top support layer 126, the middle support layer 124, and the substrate 100, exposing the outer lateral surface of the bottom electrodes BE. Next, a deposition process is performed to form a capacitor dielectric layer DL along the inner and outer lateral surfaces of the bottom electrodes BE, and then a conductive material of the top electrodes TE is formed on the capacitor dielectric layer DL and fills the cavities between the top support layer 126, the middle support layer 124, and the substrate 100 and the bottom electrode openings. Subsequently, a reflow process can be optionally performed on the capacitor array structure 120 to reduce the resistance of the conductive material of the top electrodes TE.

[0060] In some embodiments, the planarization layer 140, particularly the portion of the planarization layer 140 filling between adjacent capacitor array structures 120, can serve as a stress adjustment and buffer for the substrate 100 and the capacitor array structures 120. In some embodiments, the capacitor array structures 120 can be tilted to adjust the sidewall profile of the capacitor array structures 120, thereby changing the cross-sectional shape of the planarization layer 140 between adjacent capacitor array structures 120, further improving the overall stress configuration of the semiconductor memory 10, buffering or reducing the stress on the capacitor array structures 120, and improving the reliability of the semiconductor memory 10. Some specific embodiments are provided below to help those skilled in the art understand the technical content of the present application. It should be particularly noted that, for the convenience of illustration and simplification of the drawings, the following embodiments will use the axis AX to represent the position and upright shape of the capacitors 122 on the substrate 100. The detailed structure of the capacitor array structure 120, such as the bottom electrode BE, the top electrode TE, and the capacitor dielectric layer DL, can be referred to the drawings shown. Figure 2

[0061] Please refer to Figure 3 ​Fig. 1 is a schematic cross-sectional view of a semiconductor memory 10 according to an embodiment of the present application. The semiconductor memory 10 includes a substrate 100 having an array region Rl and a peripheral region R2 adjacent to the array region Rl. An interlayer dielectric layer 102 is disposed on the substrate 100 and includes a plurality of contact pads 104 arranged equidistantly in the interlayer dielectric layer 102 with a spacing S1 therebetween. A capacitor array structure 120 is disposed on the interlayer dielectric layer 102 in the array region Rl such that each capacitor 122 corresponds to one of the contact pads 104. It is noted that the intermediate support layer 124 and the top support layer 126 can be made of the same material so that both have the same degree of tensile stress in the horizontal direction from the interior of the array region Rl toward the peripheral region R2. As a result, as shown in Fig. 1, the lower half 122b of the capacitor 122 in the dummy array region Rl-2, especially near the peripheral region R2, is tilted toward the peripheral region R2 with a curved lower half axis AX2, while the upper half 122a substantially maintains perpendicular to the surface of the substrate 100 with a straight upper half axis AXl without bending. The extension line AXl-1 of the upper half axis AXl includes a misalignment with the corresponding contact pad 104. According to an embodiment of the present application, the stress increases as approaching the edge 100a of the array region Rl, so that the misalignment between the extension line AXl-1 of the capacitor 122 and the contact pad 104 increases as the distance between the contact pad 104 and the edge 100a becomes closer. For example, the distances between the outermost three contact pads 104 and the edge 100a are Dl, D2 and D3 in sequence, and the misalignments between the extension line AXl-1 of the capacitor 122 connected to the three contact pads 104 and the contact pads 104 are Ml, M2 and M3 in sequence, where Ml is greater than M2, and M2 is greater than M3. According to an embodiment of the present application, the misalignment Ml is less than the spacing S1 between the contact pads 104. Figure 3 Fig. 2 is another schematic cross-sectional view of the semiconductor memory 10 according to an embodiment of the present application. The semiconductor memory 10 includes a substrate 100 having two array regions Rl separated by a peripheral region R2. Two capacitor array structures 120 are disposed in the array regions Rl, respectively. An insulating cap layer 130 is conformally coated on the top and sidewalls of the capacitor array structures 120 and extends to cover part of the substrate 100. A planarization layer 140 covers the substrate 100 and the capacitor array structures 120 entirely and fills the space between the capacitor array structures 120. The capacitor array structures 120 have an inscribed sidewall profile due to the tilting of the capacitors 122 (as shown in Fig. 1) so that the part of the planarization layer 140 filled between the capacitor array structures 120 has a trapezoidal cross-sectional shape. Figure 3

[0062] Fig. 3 is a schematic cross-sectional view of the semiconductor memory 10 according to another embodiment of the present application. The semiconductor memory 10 includes a substrate 100 having an array region Rl and a peripheral region R2 adjacent to the array region Rl. An interlayer dielectric layer 102 is disposed on the substrate 100 and includes a plurality of contact pads 104 arranged equidistantly in the interlayer dielectric layer 102 with a spacing S1 therebetween. A capacitor array structure 120 is disposed on the interlayer dielectric layer 102 in the array region Rl such that each capacitor 122 corresponds to one of the contact pads 104. It is noted that the intermediate support layer 124 and the top support layer 126 can be made of the same material so that both have the same degree of tensile stress in the horizontal direction from the interior of the array region Rl toward the peripheral region R2. As a result, as shown in Fig. 3, the lower half 122b of the capacitor 122 in the dummy array region Rl-2, especially near the peripheral region R2, is tilted toward the peripheral region R2 with a curved lower half axis AX2, while the upper half 122a substantially maintains perpendicular to the surface of the substrate 100 with a straight upper half axis AXl without bending. The extension line AXl-1 of the upper half axis AXl includes a misalignment with the corresponding contact pad 104. According to an embodiment of the present application, the stress increases as approaching the edge 100a of the array region Rl, so that the misalignment between the extension line AXl-1 of the capacitor 122 and the contact pad 104 increases as the distance between the contact pad 104 and the edge 100a becomes closer. For example, the distances between the outermost three contact pads 104 and the edge 100a are Dl, D2 and D3 in sequence, and the misalignments between the extension line AXl-1 of the capacitor 122 connected to the three contact pads 104 and the contact pads 104 are Ml, M2 and M3 in sequence, where Ml is greater than M2, and M2 is greater than M3. According to an embodiment of the present application, the misalignment Ml is less than the spacing S1 between the contact pads 104. Figure 4 Figure 3 Fig. 4 is another schematic cross-sectional view of the semiconductor memory 10 according to another embodiment of the present application. The semiconductor memory 10 includes a substrate 100 having two array regions Rl separated by a peripheral region R2. Two capacitor array structures 120 are disposed in the array regions Rl, respectively. An insulating cap layer 130 is conformally coated on the top and sidewalls of the capacitor array structures 120 and extends to cover part of the substrate 100. A planarization layer 140 covers the substrate 100 and the capacitor array structures 120 entirely and fills the space between the capacitor array structures 120. The capacitor array structures 120 have an inscribed sidewall profile due to the tilting of the capacitors 122 (as shown in Fig. 1) so that the part of the planarization layer 140 filled between the capacitor array structures 120 has a trapezoidal cross-sectional shape. Figure 3

[0063] Fig. 5 is a schematic cross-sectional view of the semiconductor memory 10 according to another embodiment of the present application. The semiconductor memory 10 includes a substrate 100 having an array region Rl and a peripheral region R2 adjacent to the array region Rl. An interlayer dielectric layer 102 is disposed on the substrate 100 and includes a plurality of contact pads 104 arranged equidistantly in the interlayer dielectric layer 102 with a spacing S1 therebetween. A capacitor array structure 120 is disposed on the interlayer dielectric layer 102 in the array region Rl such that each capacitor 122 corresponds to one of the contact pads 104. It is noted that the intermediate support layer 124 and the top support layer 126 can be made of the same material so that both have the same degree of tensile stress in the horizontal direction from the interior of the array region Rl toward the peripheral region R2. As a result, as shown in Fig. 5, the lower half 122b of the capacitor 122 in the dummy array region Rl-2, especially near the peripheral region R2, is tilted toward the peripheral region R2 with a curved lower half axis AX2, while the upper half 122a substantially maintains perpendicular to the surface of the substrate 100 with a straight upper half axis AXl without bending. The extension line AXl-1 of the upper half axis AXl includes a misalignment with the corresponding contact pad 104. According to an embodiment of the present application, the stress increases as approaching the edge 100a of the array region Rl, so that the misalignment between the extension line AXl-1 of the capacitor 122 and the contact pad 104 increases as the distance between the contact pad 104 and the edge 100a becomes closer. For example, the distances between the outermost three contact pads 104 and the edge 100a are Dl, D2 and D3 in sequence, and the misalignments between the extension line AXl-1 of the capacitor 122 connected to the three contact pads 104 and the contact pads 104 are Ml, M2 and M3 in sequence, where Ml is greater than M2, and M2 is greater than M3. According to an embodiment of the present application, the misalignment Ml is less than the spacing S1 between the contact pads 104. Figure 5 Figure 6 Figure 5 ​​​​​This is a cross-sectional schematic diagram of a semiconductor memory 10 according to an embodiment of the present invention. Figure 6 for Figure 3 Another cross-sectional view of the semiconductor memory 10 shown. This embodiment is similar to... Figure 3 and Figure 4 The main difference in the embodiments is that the intermediate support layer 124 and the top support layer 126 may comprise the same material and have the same degree of compressive stress in the horizontal direction from the interior of the array region R1 to the peripheral region R2, so that the lower half 122b of the capacitor 122 near the peripheral region R2 tilts towards the interior of the array region R1, while the upper half 122a remains substantially perpendicular to the surface of the substrate 100. Figure 5 As shown, the lower axis AX2 of capacitor 122 is a curve, while the upper axis AX1 is a straight line without bends. The extension line AX1-1 of the upper axis AX1 includes a misalignment with the corresponding contact pad 104. According to one embodiment of the invention, the stress gradually increases as it approaches the edge 100a of the array region R1. Therefore, the misalignment between the extension line AX1-1 of capacitor 122 and the contact pad 104 gradually increases as the distance between the contact pad 104 and the edge 100a increases. For example, Figure 5 The distances between the three outermost contact pads 104 and the edge 100a are D1, D2, and D3, respectively. The misalignment between the extension line AX1-1 of the capacitor 122 connected to the three contact pads 104 and the contact pads 104 is M1, M2, and M3, respectively, where M1 is greater than M2, and M2 is greater than M3. According to an embodiment of the present invention, the misalignment M1 is less than the spacing S1 between the contact pads 104. Thus, as... Figure 6 As shown, the capacitor array structure 120 may have an outwardly sloping sidewall profile, so that the portion of the planarization layer 140 filled between the capacitor array structures 120 has an inverted trapezoidal cross-sectional shape.

[0064] Please refer to Figure 7 and Figure 8 . Figure 7 This is a cross-sectional schematic diagram of a semiconductor memory 10 according to an embodiment of the present invention. Figure 8 for Figure 7 Another cross-sectional view of the semiconductor memory 10 shown. This embodiment is similar to... Figure 3 and Figure 4 The main difference in the embodiments is that the intermediate support layer 124 and the top support layer 126 may be made of different materials, such that the intermediate support layer 124 has a stress substantially consistent with the substrate 100, while the top support layer 126 has a stress different from that of the intermediate support layer 124, for example, a tensile stress in the horizontal direction from the interior of the array region R1 towards the peripheral region R2. In this way, the upper half 122a of the capacitor 122 near the peripheral region R2 will tilt towards the peripheral region R2, while the lower half 122b will remain substantially perpendicular to the surface of the substrate 100.Figure 7 As shown, the upper axis AX1 of the capacitor 122 is a curved line, and the lower axis AX2 is a straight line without bending. The misalignment between the extension line AX1-1 (the extension line passing through the portion of the top support layer 126) of the upper axis AX1 and the corresponding contact pad 104 gradually increases as the distance between the contact pad 104 and the edge 100a is closer. For example, the three outermost contact pads 104 in the array have distances D1, D2 and D3 to the edge 100a, respectively, and the misalignment between the extension line AX1-1 of the capacitor 122 connected to the three contact pads 104 and the contact pad 104 is M1, M2 and M3, respectively, where M1 is greater than M2, and M2 is greater than M3. According to an embodiment of the present application, the misalignment M1 is less than the spacing S1 between the contact pads 104. In this way, as shown in FIG. 1C, the upper half 122a of the capacitor 122 near the edge 100a is tilted toward the array region R1, and the lower half 122b is substantially perpendicular to the surface of the substrate 100. Figure 7 As shown, the upper axis AX1 of the capacitor 122 is a curved line, and the lower axis AX2 is a straight line without bending. The misalignment between the extension line AX1-1 (the extension line passing through the portion of the top support layer 126) of the upper axis AX1 and the corresponding contact pad 104 gradually increases as the distance between the contact pad 104 and the edge 100a is closer. For example, the three outermost contact pads 104 in the array have distances D1, D2 and D3 to the edge 100a, respectively, and the misalignment between the extension line AX1-1 of the capacitor 122 connected to the three contact pads 104 and the contact pad 104 is M1, M2 and M3, respectively, where M1 is greater than M2, and M2 is greater than M3. According to an embodiment of the present application, the misalignment M1 is less than the spacing S1 between the contact pads 104. In this way, as shown in FIG. 1C, the upper half 122a of the capacitor 122 near the edge 100a is tilted toward the array region R1, and the lower half 122b is substantially perpendicular to the surface of the substrate 100. Figure 8 As shown, the capacitor array structure 120 can have an inscribed sidewall profile, so that the portion of the planarization layer 140 filled between the capacitor array structures 120 has a trapezoidal cross-sectional shape.

[0065] Please refer to Figure 9 and Figure 10 . Figure 9 is a cross-sectional schematic view of a semiconductor memory 10 according to an embodiment of the present application. Figure 10 is Figure 9 another cross-sectional schematic view of the semiconductor memory 10. The main difference between this embodiment and the embodiment of Figure 3 and Figure 4 is that the intermediate support layer 124 and the top support layer 126 can be selected to include different materials, so that the intermediate support layer 124 has a stress substantially consistent with the substrate 100, and the top support layer 126 has a stress different from that of the intermediate support layer 124, such as a compressive stress in the horizontal direction from inside the array region R1 to the peripheral region R2. In this way, the upper half 122a of the capacitor 122 near the peripheral region R2 is tilted toward the inside of the array region R1, and the lower half 122b is substantially perpendicular to the surface of the substrate 100. As shown in FIG. 2C, the misalignment between the extension line AX1-1 of the upper axis AX1 of the capacitor 122 and the corresponding contact pad 104 gradually increases as the distance between the contact pad 104 and the edge 100a is closer. Figure 9 As shown, the upper axis AX1 of the capacitor 122 is a curved line, and the lower axis AX2 is a straight line without bending. The misalignment between the extension line AX1-1 (the extension line passing through the portion of the top support layer 126) of the upper axis AX1 and the corresponding contact pad 104 gradually increases as the distance between the contact pad 104 and the edge 100a is closer. For example, the three outermost contact pads 104 in the array have distances D1, D2 and D3 to the edge 100a, respectively, and the misalignment between the extension line AX1-1 of the capacitor 122 connected to the three contact pads 104 and the contact pad 104 is M1, M2 and M3, respectively, where M1 is greater than M2, and M2 is greater than M3. According to an embodiment of the present application, the misalignment M1 is less than the spacing S1 between the contact pads 104. In this way, as shown in FIG. 1C, the upper half 122a of the capacitor 122 near the edge 100a is tilted toward the array region R1, and the lower half 122b is substantially perpendicular to the surface of the substrate 100. Figure 9 As shown, the upper axis AX1 of the capacitor 122 is a curved line, and the lower axis AX2 is a straight line without bending. The misalignment between the extension line AX1-1 (the extension line passing through the portion of the top support layer 126) of the upper axis AX1 and the corresponding contact pad 104 gradually increases as the distance between the contact pad 104 and the edge 100a is closer. For example, the three outermost contact pads 104 in the array have distances D1, D2 and D3 to the edge 100a, respectively, and the misalignment between the extension line AX1-1 of the capacitor 122 connected to the three contact pads 104 and the contact pad 104 is M1, M2 and M3, respectively, where M1 is greater than M2, and M2 is greater than M3. According to an embodiment of the present application, the misalignment M1 is less than the spacing S1 between the contact pads 104. In this way, as shown in FIG. 1C, the upper half 122a of the capacitor 122 near the edge 100a is tilted toward the array region R1, and the lower half 122b is substantially perpendicular to the surface of the substrate 100. Figure 10As shown, the capacitor array structure 120 can have an outer slanted sidewall profile, such that the portions of the planarization layer 140 filled between the capacitor array structures 120 have an inverted trapezoidal cross-sectional shape.

[0066] In summary, the present application provides a semiconductor memory 10 including stacked capacitors, wherein the capacitor array structure 120 has an inner tangent or outer slanted sidewall profile, such that the portions of the planarization layer 140 filled between the capacitor array structures 120 have a trapezoidal or inverted trapezoidal cross-sectional shape, thereby improving the overall stress configuration of the semiconductor structure, buffering or reducing the stress experienced by the capacitor array structure 120, and improving the reliability of the semiconductor memory 10. It is to be noted that the above method of tilting the capacitors 122 near the peripheral region R2 by selecting the material of the support layer to generate a desired stress is by way of example, and the present application is not limited thereto. Any method that can tilt the capacitors 122 on the outer side of the capacitor array structure 120 in a desired direction, such as controlling the etching process for making the bottom electrode openings through the support layer and the sacrificial layer to tilt the electrode openings of the outer side capacitors, or controlling the support layer opening pattern design for etching the sacrificial layer to adjust the local support force and stress, or controlling the top electrode deposition process parameters in combination with the support layer opening pattern design to adjust the deposition rate in different regions, or controlling the temperature profile of the annealing process after deposition, can be applied in the present application.

[0067] The preferred embodiments of the present application have been described above with the aid of drawing figures, and are not limited to those embodiments; instead, they will include any changes that do not depart from the spirit and scope of the present application, including equivalents thereof.

Claims

1. A semiconductor memory, characterized by comprising: Comprising: a substrate comprising at least an array region; a peripheral region adjoining an edge of the array region; a plurality of contact pads disposed in the array region; and a capacitor array structure disposed on the array region and comprising: a plurality of capacitors respectively disposed on a contact pad; and an intermediate support layer horizontally extending between waists of the plurality of capacitors and dividing each of the capacitors into an upper half and a lower half, wherein the upper half of the capacitors adjacent to the edge of the array region is tilted to include a misalignment between the upper half and the contact pad, and the lower half of the capacitors adjacent to the edge of the array region is straightened by a lower axis of the lower half of the capacitors; an interlayer dielectric layer disposed between the substrate and the capacitor array structure. The misalignment is less than or equal to a pitch between the contact pads.

2. The semiconductor memory as claimed in claim 1, wherein The misalignment gradually increases as a distance of the capacitors to the edge of the array region decreases.

3. The semiconductor memory as claimed in claim 1, wherein The upper axis of the upper half of the capacitors is perpendicular to a surface of the substrate.

4. The semiconductor memory as claimed in claim 1, wherein The lower axis of the lower half of the capacitors is curved.

5. The semiconductor memory as claimed in claim 1, wherein Further comprising a top support layer horizontally extending between tops of the plurality of capacitors.

6. The semiconductor memory as claimed in claim 1, wherein The intermediate support layer and the top support layer comprise a same material and a same stress.

7. The semiconductor memory as claimed in claim 6, wherein Further comprising:

8. The semiconductor memory as claimed in claim 1, wherein another array region respectively located on two sides of the peripheral region with the array region; another capacitor array structure disposed on the other array region; and a planarization layer covering the substrate and filling a gap between the capacitor array structure and the other capacitor array structure. The planarization layer comprises an inverted trapezoidal cross-sectional shape at a portion between the capacitor array structure. The planarization layer comprises a trapezoidal cross-sectional shape at a portion between the capacitor array structure.

9. The semiconductor memory as claimed in claim 8, wherein, Comprising:

10. The semiconductor memory as claimed in claim 8, wherein, a substrate comprising at least an array region; 11. A semiconductor memory, characterized by comprising: a peripheral region adjoining an edge of the array region; a plurality of contact pads disposed in the array region; and a capacitor array structure disposed on the array region and comprising: a plurality of capacitors respectively disposed on a contact pad; and an intermediate support layer horizontally extending between waists of the plurality of capacitors and dividing each of the capacitors into an upper half and a lower half, wherein the upper half of the capacitors adjacent to the edge of the array region is tilted to include a misalignment between the upper half and the contact pad, and the lower half of the capacitors adjacent to the edge of the array region is straightened by a lower axis of the lower half of the capacitors; an interlayer dielectric layer disposed between the substrate and the capacitor array structure. The misalignment is less than or equal to a pitch between the contact pads. The misalignment gradually increases as a distance of the capacitors to the edge of the array region decreases. The lower axis of the lower half of the capacitors is perpendicular to a surface of the substrate.

12. The semiconductor memory as claimed in claim 11, wherein, The upper axis of the upper half of the capacitors is curved.

13. The semiconductor memory as claimed in claim 11, wherein, Further comprising a top support layer horizontally extending between tops of the plurality of capacitors.

14. The semiconductor memory as claimed in claim 11, wherein, The intermediate support layer and the top support layer comprise a same material and a same stress.

15. The semiconductor memory as claimed in claim 11, wherein, Further comprising:

16. The semiconductor memory as claimed in claim 11, wherein, another array region respectively located on two sides of the peripheral region with the array region; 17. The semiconductor memory as claimed in claim 16, wherein, another capacitor array structure disposed on the other array region; and 18. The semiconductor memory as claimed in claim 11, wherein, a planarization layer covering the substrate and filling a gap between the capacitor array structure and the other capacitor array structure. The planarization layer comprises an inverted trapezoidal cross-sectional shape at a portion between the capacitor array structure. The planarization layer comprises a trapezoidal cross-sectional shape at a portion between the capacitor array structure. ​ ​ 19. The semiconductor memory as claimed in claim 18, wherein, The portion of the planarization layer between the array of capacitors includes an inverted trapezoidal cross-sectional shape.

20. The semiconductor memory as claimed in claim 18, wherein, The portion of the planarization layer between the array of capacitors includes a trapezoidal cross-sectional shape.

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