Semiconductor memory device and method of manufacturing a semiconductor memory device

Abstract

The present disclosure relates to a semiconductor memory device and a method of manufacturing a semiconductor memory device. A semiconductor memory device includes a semiconductor substrate including an upper surface extending in a horizontal direction, a source structure including a trench extending in the horizontal direction, the source structure disposed above the semiconductor substrate, a metal structure in the trench of the source structure and connecting the source structure to the semiconductor substrate, and a memory cell string disposed on both sides of the trench and connected to the source structure.

Description

Technical Field

[0001] This disclosure relates to a semiconductor memory device and a method for manufacturing a semiconductor memory device, and more specifically, to a three-dimensional semiconductor memory device and a method for manufacturing a three-dimensional semiconductor memory device. Background Technology

[0002] To improve the integration of semiconductor memory devices, three-dimensional semiconductor memory devices comprising multiple memory cells arranged in three dimensions have been proposed.

[0003] Three-dimensional semiconductor memory devices can further improve integration by increasing the number of memory cells stacked on a substrate. However, as the number of stacked memory cells increases, the stability of the manufacturing process may decrease. Summary of the Invention

[0004] According to embodiments of the present disclosure, a semiconductor memory device may include: a semiconductor substrate including an upper surface extending in a horizontal direction; a source structure including a trench extending in a horizontal direction, the source structure being disposed above the semiconductor substrate; a metal structure being disposed in the trench of the source structure and connecting the source structure to the semiconductor substrate; and a memory cell string being disposed on both sides of the trench and connected to the source structure.

[0005] According to embodiments of the present disclosure, a semiconductor memory device may include: a semiconductor substrate including a first region, a second region, and a third region, wherein the second region is disposed between the first region and the third region; a gate stack disposed above the first region of the semiconductor substrate; a source structure disposed at a height between the respective gate stacks and the semiconductor substrate to overlap with the first and second regions of the semiconductor substrate; a first source insulating pattern disposed at a height between the respective gate stacks and the semiconductor substrate to overlap with the third region of the semiconductor substrate; a vertical structure disposed between the gate stacks and extending into the source structure; and a metal structure connecting the source structure to the semiconductor substrate.

[0006] According to embodiments of the present disclosure, a method of manufacturing a semiconductor memory device may include the following steps: forming a source stack; forming a first source insulating pattern through the source stack; forming a recess including a first contact hole through the first source insulating pattern and a trench connected to the first contact hole and defined within the source stack; forming a metal structure including a horizontal pattern in the trench and a vertical pattern connected to the horizontal pattern and formed in the first contact hole; forming a preliminary gate stack by alternately stacking a first material layer and a second material layer on the source stack; forming cell plugs through the preliminary gate stack on both sides of the vertical pattern of the metal structure; forming a slit extending through the preliminary gate stack overlapping the horizontal pattern of the metal structure and through the horizontal pattern of the metal structure; and replacing a portion of the source stack with an interlayer semiconductor layer through the slit. Attached Figure Description

[0007] Figure 1 This is a block diagram illustrating a semiconductor memory device according to an embodiment of the present disclosure.

[0008] Figure 2 It is shown Figure 1 The circuit diagram shows an implementation of the memory cell array.

[0009] Figure 3 It is shown schematically. Figure 1 A diagram illustrating an implementation of the arrangement of the memory cell array and peripheral circuitry.

[0010] Figure 4 It is shown Figure 3 A plan view of a portion of the memory cell array shown.

[0011] Figure 5A , Figure 5B and Figure 5C It shows along Figure 4 The cross-sectional views of a semiconductor memory device according to an embodiment of the present disclosure are shown by lines I-I', II-II', and III-III'.

[0012] Figure 6 yes Figure 4 The 3D view of region A shown.

[0013] Figure 7A , Figure 7B and Figure 7C This is a cross-sectional view showing the steps of forming the source stack and etching the source stack.

[0014] Figure 8A , Figure 8B and Figure 8CIt is a cross-sectional view showing the steps of forming the source insulation pattern and the recess.

[0015] Figure 9 , Figure 10A , Figure 10B and Figure 10C This is a diagram illustrating the steps involved in forming the metal structure and the lower contact.

[0016] Figure 11A , Figure 11B and Figure 11C This is a cross-sectional view showing the steps of forming the initial gate stack and the steps of forming the cell plug.

[0017] Figure 12 , Figure 13A , Figure 13B and Figure 13C This is a cross-sectional view showing the steps involved in forming the stepped structure.

[0018] Figure 14A , Figure 14B and Figure 14C This is a cross-sectional view showing the steps of forming the upper insulating layer, the filling insulating layer, and the gate separation structure.

[0019] Figure 15A , Figure 15B , Figure 15C , Figure 16A , Figure 16B , Figure 16C , Figure 17A , Figure 17B and Figure 17C This is a cross-sectional view showing the replacement process and the process of forming the conductive electrode contacts.

[0020] Figure 18 This is a block diagram illustrating the configuration of a memory system according to an embodiment of the present disclosure.

[0021] Figure 19 This is a block diagram illustrating the configuration of a computing system according to an embodiment of the present disclosure. Detailed Implementation

[0022] The specific structural and functional descriptions disclosed herein are merely illustrative in order to describe implementations based on the concepts of this disclosure. Implementations based on the concepts of this disclosure may be carried out in various forms and should not be construed as limited to the specific implementations set forth herein.

[0023] The terms "first" and "second" are used below to distinguish one component from another and are not intended to imply a specific number or order of components. These terms can be used to describe various components, but components are not limited to these terms.

[0024] Some embodiments relate to a semiconductor memory device capable of improving the stability of the manufacturing process and a method of manufacturing the semiconductor memory device.

[0025] Figure 1 This is a block diagram illustrating a semiconductor memory device according to an embodiment of the present disclosure.

[0026] Reference Figure 1 The semiconductor memory device 100 may include a peripheral circuit structure 190 and a memory cell array 110.

[0027] The peripheral circuit structure 190 can be configured to perform programming and verification operations for storing data in the memory cell array 110, read operations for outputting data stored in the memory cell array 110, and erase operations for erasing data stored in the memory cell array 110. The peripheral circuit structure 190 may include input / output circuitry 180, control circuitry 150, voltage generation circuitry 130, row decoder 120, column decoder 170, page buffer 160, and source line driver 140.

[0028] The memory cell array 110 may include a plurality of memory cells for storing data. As an embodiment, the memory cell array 110 may include a three-dimensional memory cell array. The plurality of memory cells may store a single bit of data or two or more bits of data per cell. The plurality of memory cells may be configured into a plurality of memory cell strings. Each memory cell string may include a plurality of memory cells connected in series via a channel layer. The channel layer may be connected to the page buffer 160 via corresponding bit lines BL of a plurality of bit lines BL.

[0029] Input / output circuit 180 can send commands (CMD) and addresses (ADD) received from an external device (e.g., a memory controller) of semiconductor memory device 100 to control circuit 150. Input / output circuit 180 can exchange data (DATA) with external devices and column decoder 170.

[0030] In response to the command CMD and the address ADD, the control circuit 150 can output the operation signal OP_S, the row address RADD, the source line control signal SL_S, the page buffer control signal PB_S, and the column address CADD.

[0031] The voltage generating circuit 130 can generate various operating voltages Vop for programming, verification, reading and erasing operations in response to the operation signal OP_S.

[0032] The row decoder 120 can be connected to the memory cell array 110 via multiple drain select lines DSL, multiple word lines WL, and multiple source select lines SSL. The row decoder 120 can send an operating voltage Vop to the multiple drain select lines DSL, multiple word lines WL, and multiple source select lines SSL in response to the row address RADD.

[0033] In response to the column address CADD, the column decoder 170 can send data DATA input from the input / output circuit 180 to the page buffer 160 or send data DATA stored in the page buffer 160 to the input / output circuit 180. The column decoder 170 can exchange data DATA with the input / output circuit 180 via the column line CLL. The column decoder 170 can exchange data DATA with the page buffer 160 via the data line DTL.

[0034] Page buffer 160 can be connected to memory cell array 110 via bit lines BL. Page buffer 160 can temporarily store data DATA received via multiple bit lines BL in response to page buffer control signal PB_S. Page buffer 160 can sense the voltage or current of multiple bit lines BL during read operations.

[0035] The source line driver 140 can send the source voltage Vsl supplied from the source line driver 140 to the memory cell array 110 in response to the source line control signal SL_S.

[0036] Figure 2 It is shown Figure 1 The circuit diagram shows an implementation of the memory cell array.

[0037] Reference Figure 2 The memory cell array may include multiple memory cell strings CS1 and CS2 connected to multiple bit lines BL. The multiple memory cell strings CS1 and CS2 may be commonly connected to the source line SL. Alternatively, multiple first memory cell strings CS1 and multiple second memory cell strings CS2 may be commonly connected to the source line SL.

[0038] A pair of first memory cell strings CS1 and second memory cell strings CS2 can be connected to each bit line BL.

[0039] Each first memory cell string CS1 and each second memory cell string CS2 may include a source selection transistor SST disposed between the source line SL and the bit line BL, a plurality of memory cells MC, and a drain selection transistor DST.

[0040] A source select transistor (SST) controls the electrical connection between multiple memory cells (MC) and the source line (SL). One SST can be positioned between the source line (SL) and multiple memory cells (MC). Although not shown in the figure, two or more source select transistors can be connected in series between the source line (SL) and multiple memory cells (MC). The gate of the SST can be connected to the source select line (SSL). The operation of the SST can be controlled by a source strobe signal applied to the source select line (SSL).

[0041] Multiple memory cells MC can be positioned between the source select transistor SST and the drain select transistor DST. These multiple memory cells MC can be connected in series between the source select transistor SST and the drain select transistor DST. The gates of the multiple memory cells MC can be connected to multiple word lines WL respectively. The operation of each memory cell MC can be controlled by a cell strobe signal applied to the corresponding word line WL.

[0042] The drain-select transistor (DST) controls the electrical connection between multiple memory cells (MC) and bit lines (BL). The gate of the DST can be connected to either drain select line DSL1 or DSL2. The operation of the DST can be controlled by a drain strobe signal applied to either drain select line DSL1 or DSL2.

[0043] Multiple first memory cell strings CS1 can be connected to a first drain select line DSL1. Multiple second memory cell strings CS2 can be connected to a second drain select line DSL2. Therefore, by selecting one bit line from multiple bit lines BL and one drain select line from the first drain select line DSL1 and the second drain select line DSL2, one of the multiple first memory cell strings CS1 and the multiple second memory cell strings CS2 can be selected.

[0044] Multiple first memory cell strings CS1 and multiple second memory cell strings CS2 can be connected together to each word line WL.

[0045] Multiple first memory cell strings CS1 and multiple second memory cell strings CS2 can be connected together to the source select line SSL. Embodiments of this disclosure are not limited thereto. Although not shown in the figures, as an embodiment, the memory cell array may include first and second source select lines that are separate from each other. The first source select line may be connected to multiple first memory cell strings, and the second source select line may be connected to multiple second memory cell strings.

[0046] Figure 3 It is shown schematically. Figure 1 A diagram illustrating an implementation of the arrangement of the memory cell array and peripheral circuitry.

[0047] Reference Figure 3 The peripheral circuit structure 190 may be disposed below the memory cell array 110. The peripheral circuit structure 190 may include a first region AR1, a second region AR2, and a third region AR3. The second region AR2 may be defined between the first region AR1 and the third region AR3. The first region AR1, the second region AR2, and the third region AR3 may extend parallel to each other. As an embodiment, each of the first region AR1, the second region AR2, and the third region AR3 may extend in the Y-axis direction of the XYZ coordinate system.

[0048] The memory cell array 110 may include a source structure 260, multiple gate stacks (GSTs) and multiple bit lines (BLs).

[0049] The source structure 260 may extend in the XY plane of the XYZ coordinate system. The source structure 260 may overlap with the first region AR1 and the second region AR2 of the peripheral circuit structure 190. The source structure 260 may include an edge EG defined along the boundary between the second region AR2 and the third region AR3 of the peripheral circuit structure 190. The third region AR3 of the peripheral circuit structure 190 may be opened through the source structure 260.

[0050] Multiple gate stacks (GSTs) can be disposed on the source structure 260. The multiple gate stacks (GSTs) can be spaced apart from each other by a slit 261. The slit 261 can intersect the extension directions of the first region AR1, the second region AR2, and the third region AR3 of the peripheral circuit structure 190. Alternatively, the slit 261 can extend in the X-axis direction.

[0051] Each gate stack (GST) may include connections to Figure 2 The diagram shows multiple conductive patterns in the multiple memory cell strings CS1 and CS2. The multiple conductive patterns of the gate stack GST can be spaced apart from each other in the Z-axis direction and can be used as... Figure 2 The diagram shows the source selection line SSL, multiple word lines WL, the first drain selection line DSL1, and the second drain selection line DSL2. Furthermore, in this embodiment, the source structure 260 can be used as... Figure 1 and Figure 2 The source line SL is shown.

[0052] Multiple bit lines BL can be disposed above multiple gate stacks GST. The multiple bit lines BL can extend parallel to each other. The multiple bit lines BL can extend in a direction intersecting slit 261. Alternatively, the multiple bit lines BL can extend in the Y-axis direction.

[0053] The following is for reference Figure 4 , Figure 5A , Figure 5B and Figure 5C describe Figure 3 The structure of the semiconductor memory device shown is illustrated.

[0054] Figure 4 It is shown Figure 3 A plan view of a portion of the memory cell array shown.

[0055] Reference Figure 4 Each gate stack (GST) may include a cell array region (CAR) and a contact region (CTR). The cell array region (CAR) and contact region (CTR) of the gate stack (GST) may overlap with the first region (AR1) of the peripheral circuit structure 190.

[0056] The gate separation structure 251 can be buried in the gate stack GST. The gate separation structure 251 can be... Figure 2 The first drain select line DSL1 and the second drain select line DSL2 shown are insulators that are separate from each other. The gate separation structure 251 may extend parallel to the slit 261. As an embodiment, the gate separation structure 251 may extend in the X-axis direction.

[0057] Multiple cell plugs (CPLs) may be disposed on both sides of the gate separation structure 251. The multiple cell plugs (CPLs) may extend in the Z-axis direction to pass through the cell array region (CAR) of the gate stack (GST).

[0058] The gate stack (GST) can be passed through by a plurality of dummy plugs (DPLs) arranged in a row along the extension direction of the gate separation structure 251. The gate separation structure 251 can extend into each dummy plug (DPL).

[0059] At least one gate stack GST can be penetrated by the filler insulating layer 255 in the contact region CTR. The filler insulating layer 255 can be penetrated by the upper contact 277.

[0060] A vertical structure 270 may be formed in the slit 261. In one embodiment, the slit 261 may be filled by the vertical structure 270. The vertical structure 270 may extend into the source structure 260. The vertical structure 270 may protrude more than the gate stack GST in the horizontal direction. The horizontal direction may be parallel to the XY plane. In another embodiment, the vertical structure 270 may protrude more than the gate stack GST in the X-axis direction. The vertical structure 270 may include a conductive power electrode contact 273 and a spacer insulating layer 271 surrounding the sidewalls of the conductive power electrode contact 273. The conductive power electrode contact 273 may include at least one of a doped semiconductor layer, a metal silicide layer, a metal barrier layer, and a metal layer. Although not shown in the figures, in another embodiment, the vertical structure 270 may be configured with an insulating material filling the slit 261.

[0061] The source structure 260 may overlap with the first region AR1 of the peripheral circuit structure 190 and may protrude further than the gate stack GST in the horizontal direction. Alternatively, the source structure 260 may protrude further than the gate stack GST in the X-axis direction. The source structure 260 may be used as... Figure 1 and Figure 2 The source line SL is shown.

[0062] The peripheral circuit structure 190 may protrude further than the source structure 260 in the horizontal direction. As an implementation, the third region AR3 of the peripheral circuit structure 190 may extend from the second region AR2 to protrude further than the source structure 260 in the X-axis direction.

[0063] like Figures 5A to 5C The peripheral circuit structure 190 may include a semiconductor substrate 201. In the third region AR3 of the peripheral circuit structure 190, the semiconductor substrate may be connected to the source structure 260 via a metal structure 235.

[0064] Metal structure 235 may include a horizontal pattern 235A and a vertical pattern 235B integrated with each other. The vertical pattern 235B of metal structure 235 may overlap with the third region AR3 of peripheral circuit structure 190. The horizontal pattern 235A of metal structure 235 may extend horizontally from the vertical pattern 235B toward vertical structure 270. Horizontal pattern 235A may include a portion buried in source structure 260. Vertical pattern 235B may be spaced apart from source structure 260, and horizontal pattern 235A may protrude further horizontally toward vertical pattern 235B than source structure 260.

[0065] Figure 5A , Figure 5B and Figure 5C It shows along Figure 4 The cross-sectional views of a semiconductor memory device according to an embodiment of the present disclosure are shown by lines I-I', II-II', and III-III'. Figure 5A The first region AR1 of the peripheral circuit structure 190 and the cell array region CAR that overlaps with the gate stack GST are shown. Figure 5B The first region AR1 of the peripheral circuit structure 190 and the contact region CTR that overlaps with the gate stack GST are shown. Figure 5C The second region AR2 and the third region AR3 of the peripheral circuit structure 190 are shown, as well as the overlapping portion of the metal structure 235.

[0066] Reference Figures 5A to 5C The peripheral circuit structure 190 may include a semiconductor substrate 201 and a plurality of transistors TR formed on the semiconductor substrate 201. The plurality of transistors TR may include... Figure 1At least one of the row decoder 120, column decoder 170, page buffer 160, and source line driver 140 shown. In one embodiment, a plurality of transistors TR may be configured in the page buffer 160. Each transistor TR may include a gate insulating layer 205 on the semiconductor substrate 201, a gate electrode 207 on the gate insulating layer 205, and a junction 201J defined on both sides of the gate electrode 207 in the semiconductor substrate 201. Each junction 201J may be part of a plurality of impurity regions defined in the semiconductor substrate 201.

[0067] Similar to the peripheral circuit structure 190, the semiconductor substrate 201 may include a first region AR1, a second region AR2, and a third region AR3. The semiconductor substrate 201 may have an upper surface 201SU extending in a horizontal direction. For example, the semiconductor substrate 201 may have an upper surface 201SU extending along the XY plane. Multiple impurity regions of the semiconductor substrate 201 may be separated by multiple isolation layers 203. The multiple impurity regions may include a junction 201J of a transistor TR and a discharge region 201DI. The junction 201J may include at least one of n-type and p-type impurities. The discharge region 201DI may include impurities with a conductivity type different from that of the source structure 260. As an embodiment, the source structure 260 may include n-type impurities, and the discharge region 201DI may include p-type impurities.

[0068] The peripheral circuit structure 190 may be covered by a lower insulating structure 211. The lower insulating structure 211 may include two or more insulating layers. Each of the discharge region 201DI and the transistor TR may be connected to an interconnect IC1 or IC2. For example, the discharge region 201DI may be connected to the first interconnect IC1, and the transistor TR may be connected to the second interconnect IC2. Each of the first interconnect IC1 and the second interconnect IC2 may be defined by a connection structure between a plurality of conductive patterns 221A, 221B, 221C, 221D, 221E, and 221F buried in the lower insulating structure 211.

[0069] The source structure 260 may have a trench 315T extending in a horizontal direction. The source structure 260 may be disposed on the lower insulating structure 211 at a height between the gate stack GST and the semiconductor substrate 201. The source structure 260 may include a doped semiconductor layer. In one embodiment, the source structure 260 may include a stacked structure of a first semiconductor layer 231, an interlayer semiconductor layer 263, and a second semiconductor layer 233. Each of the first semiconductor layer 231, the interlayer semiconductor layer 263, and the second semiconductor layer 233 may be a doped semiconductor layer and may include n-type impurities. The first semiconductor layer 231 may overlap with the trench 315T. The second semiconductor layer 233 may be disposed above the first semiconductor layer 231 and may be penetrated by the trench 315T. The interlayer semiconductor layer 263 may be disposed between the first semiconductor layer 231 and the second semiconductor layer 233 and may overlap with the trench 315T.

[0070] The source structure 260 can be penetrated by a first source insulating pattern 230A and a second source insulating pattern 230B. The first source insulating pattern 230A and the second source insulating pattern 230B can be disposed on the lower insulating structure 211 at a height between the gate stack GST and the semiconductor substrate 201. The first source insulating pattern 230A can overlap with the third region AR3 of the semiconductor substrate 201. The second source insulating pattern 230B can overlap with the first region AR1 of the semiconductor substrate 201.

[0071] Reference Figure 5B The second source insulating pattern 230B can be passed through the lower contact 237. The lower contact 237 can be connected to the second interconnect IC2. As an embodiment, the lower contact 237 can be connected to the junction 201J of the transistor TR through the second interconnect IC2.

[0072] Reference Figure 5C The first source insulating pattern 230A can be passed through by the vertical pattern 235B of the metal structure 235. The vertical pattern 235B can be connected to the first interconnect IC1. The first interconnect IC1 can electrically connect the vertical pattern 235B and the discharge region 201DI to each other. The vertical pattern 235B can be spaced apart from the source structure 260 in the horizontal direction. As an embodiment, the vertical pattern 235B can be spaced apart from the source structure 260 in the X-axis direction. The first source insulating pattern 230A may include a portion disposed between the vertical pattern 235B of the metal structure 235 and the source structure 260. Therefore, the vertical pattern 235B of the metal structure 235 can be spaced apart from the source structure 260 by the first source insulating pattern 230A.

[0073] Reference Figures 5A to 5CThe horizontal pattern 235A of the metal structure 235 may extend horizontally from the vertical pattern 253B toward the vertical structure 270. In one embodiment, the horizontal pattern 235A may be formed in the trench 315T of the source structure 260. In another embodiment, the horizontal pattern 235A may fill the trench 315T of the source structure 260. The vertical structure 270 may extend toward the semiconductor substrate 201 into the trench 315T. The horizontal pattern 235A of the metal structure 235 may remain between the portion of the vertical structure 270 extending into the trench 315T and the second semiconductor layer 233.

[0074] The power electrode contact 273 of the vertical structure 270 can contact the interlayer semiconductor layer 263 of the source structure 260. The spacer insulating layer 271 of the vertical structure 270 can be disposed between the gate stack GST and the power electrode contact 273, and can extend between the horizontal pattern 235A of the metal structure 235 and the power electrode contact 273.

[0075] The interlayer semiconductor layer 263 of the source structure 260 may have an upper surface 263SU that contacts the horizontal pattern 235A of the metal structure 235. The first semiconductor layer 231 of the source structure 260 may be disposed at the height between the semiconductor substrate 201 and the horizontal pattern 235A of the metal structure 235. The vertical pattern 235B of the metal structure 235 may extend from the horizontal pattern 235A toward the semiconductor substrate 201 to contact the first interconnect IC1.

[0076] Multiple memory cell strings CS can be defined on both sides of the vertical structure 270 and the trench 315T. Each memory cell string CS can be connected to multiple conductive patterns CP of the source structure 260 and the gate stack GST. The gate stack GST may include multiple interlayer insulating layers (ILDs) and multiple conductive patterns CP. The multiple conductive patterns CP and multiple interlayer insulating layers (ILDs) may be alternately stacked on the source structure 260 in the Z-axis direction. Each conductive pattern CP may be formed of various conductive materials such as doped semiconductor layers, metal layers, and conductive metal nitrides. The conductive pattern CP may be formed of a single conductive material, or may include two or more types of conductive materials. Each interlayer insulating layer (ILD) may include a silicon oxide layer.

[0077] The memory cell string CS may be defined by multiple conductive patterns CP and cell plugs CPL. The cell plugs CPL may include a first memory pattern ML1, a channel layer CH, a core insulating layer CO, and a second memory pattern ML2.

[0078] The channel layer CH can penetrate the gate stack GST. The channel layer CH can extend into the source structure 260 to contact the source structure 260. In one embodiment, the channel layer CH can penetrate the second semiconductor layer 233 of the source structure 260 and can extend into the first semiconductor layer 231. The interlayer semiconductor layer 263 of the source structure 260 can contact and surround the sidewalls of the channel layer CH. The channel layer CH can be used as the channel region of a memory cell string CS. The channel layer CH can be configured by semiconductor layers. The channel layer CH can extend along the sidewalls, bottom surface, and top surface of the core insulating layer CO. Doped regions can be defined at the ends of the channel layer CH formed on the core insulating layer CO. The doped regions of the channel layer CH may include n-type impurities.

[0079] A first memory pattern ML1 may be disposed between the gate stack GST and the channel layer CH. The first memory pattern ML1 may extend between the second semiconductor layer 233 of the source structure 260 and the channel layer CH. A second memory pattern ML2 may be disposed between the first semiconductor layer 231 of the source structure 260 and the channel layer CH. Although not specifically shown in the figures, each of the first memory pattern ML1 and the second memory pattern ML2 may include a first barrier insulating layer extending along the surface of the channel layer CH, a data storage layer between the first barrier layer and the channel layer CH, and a tunnel insulating layer between the data storage layer and the channel layer CH. The tunnel insulating layer may include an insulating material capable of charge tunneling. As an embodiment, the tunnel insulating layer may include a silicon oxide layer. The data storage layer may include an insulating material capable of trapping charge. As an embodiment, the data storage layer may include a nitride layer. The first barrier insulating layer may include a silicon oxide layer. Although not shown in the figures, a second barrier insulating layer may be additionally disposed between the first barrier insulating layer and each conductive pattern CP. The second barrier insulating layer may include an oxide with a dielectric constant higher than that of the first barrier insulating layer. As an embodiment, the second barrier insulating layer may include a metal oxide such as an aluminum oxide layer. The second barrier insulating layer can extend between the conductive patterns CP and the interlayer insulating layer ILD that are adjacent to each other in the Z-axis direction.

[0080] The dummy plug DPL can be formed according to a structure similar to that of the cell plug CPL. As an embodiment, the dummy plug DPL may include a first dummy memory pattern DML1, a dummy channel layer DCH, a dummy core insulating layer DCO, and a second dummy memory pattern DML2.

[0081] The dummy channel layer (DCH) can pass through the gate stack (GST) and extend into the first semiconductor layer (231) of the source structure (260). The dummy channel layer (DCH) can extend along the sidewalls and bottom surface of the dummy core insulating layer (DCO). The dummy channel layer (DCH) and the dummy core insulating layer (DCO) can be overlapped by the gate separation structure (251).

[0082] The first dummy memory pattern DML1 may be disposed between the dummy channel layer DCH and the gate stack GST. The first dummy memory pattern DML1 may be retained on the sidewall of the gate separation structure 251, but embodiments of this disclosure are not limited thereto. The second dummy memory pattern DML2 may be disposed between the dummy channel layer DCH and the first semiconductor layer 231 of the source structure 260. The first dummy memory pattern DML1 and the second dummy memory pattern DML2 may be separated from each other through the interlayer semiconductor layer 263 of the source structure 260.

[0083] Multiple conductive patterns CP can be used as Figure 2 The diagram shows a first drain select line DSL1, a second drain select line DSL2, multiple word lines WL, and a source select line SSL. As an implementation, among the multiple conductive patterns CP, at least one layer adjacent to the source structure 260 can be used as... Figure 2 The source selection line SSL is shown. Among the multiple conductive patterns CP, the conductive patterns separated from each other in the horizontal direction by the gate separation structure 251 can be used as... Figure 2 The first drain select line DSL1 and the second drain select line DSL2 are shown. Among the multiple conductive patterns CP, the conductive pattern disposed between each of the first drain select line DSL1 and the second drain select line DSL2 and the source select line SSL can be used as a word line WL.

[0084] Based on the above structure, Figure 2 The memory cell MC shown can be defined at the intersection of the channel layer CH and the conductive pattern CP used as a word line. Additionally, Figure 2 The drain-select transistor (DST) shown can be defined at the intersection of the channel layer CH and the conductive pattern CP used as a first drain-select line or a second drain-select line. Additionally, Figure 2 The source select transistor SST shown can be defined at the intersection of the channel layer CH and the conductive pattern CP used as the source select line. The source select transistor SST, the memory cell MC, and the drain select transistor DST can be connected in series through the channel layer CH, and the memory cell string CS can be configured.

[0085] like Figure 6 As shown, the interlayer insulating layer (ILD) and multiple conductive patterns (CP) of the gate stack (GST) can form a stepped structure. The stepped structure of the gate stack (GST) can be formed in... Figure 4 The contact region CTR is shown. The stepped structure of the gate stack GST can be covered by the upper insulating layer 253.

[0086] The upper insulating layer 253 can be penetrated by the slit 261 and the vertical structure 270. The upper insulating layer 253 can extend to overlap with the third region AR3 of the semiconductor substrate 201.

[0087] The upper insulating layer 253 and the gate stack GST can be penetrated by the fill insulating layer 255. The fill insulating layer 255 can overlap with the second source insulating pattern 230B. The fill insulating layer 255 can be penetrated by the upper contact 277. The upper contact 277 can contact the lower contact 237 and can be connected to the second interconnect IC2 through the lower contact 237. The vertical structure 270 may have a sidewall facing the upper insulating layer 253.

[0088] The lower contact 237 can be formed using the same process as forming the metal structure 235, and may include the same conductive material as the metal structure 235. The metal structure 235 may include a metal with a work function greater than that of the source structure 260. As an embodiment, the metal structure 235 may include tungsten. Charges generated during the manufacture of the semiconductor memory device can be discharged to the discharge region 201DI of the semiconductor substrate 201 through the metal structure 235, which has a work function greater than that of the first semiconductor layer 231 and the second semiconductor layer 233 of the source structure 260.

[0089] Figure 6 yes Figure 4 The diagram shows a 3D representation of region A. Specifically, Figure 6 It is a three-dimensional view of the gate stack GST, source structure 260, metal structure 235 and slit 261.

[0090] Reference Figure 6 The horizontal pattern 235A of the source structure 260 and the metal structure 235 can be more prominent in the horizontal direction than the gate stack GST that forms a stepped structure.

[0091] The horizontal pattern 235A of the metal structure 235 can be formed to have a width wider than that of the slit 261. The horizontal pattern 235A can protrude further than the source structure 260 in the longitudinal direction toward the vertical pattern 235B. As an embodiment, the width direction of the horizontal pattern 235A can be the Y-axis direction, and the length direction of the horizontal pattern 235A can be the X-axis direction.

[0092] The portion of the horizontal pattern 235A retained on both sides of the slit 261 can be inserted between the gate stack GST and the interlayer semiconductor layer 263 of the source structure 260.

[0093] The vertical pattern 235B of the metal structure 235 can be spaced apart from each of the first semiconductor layer 231, the interlayer semiconductor layer 263, and the second semiconductor layer 233 of the source structure 260. Therefore, the phenomenon of damage to the vertical pattern 235B during the process of forming the interlayer semiconductor layer 263 can be improved.

[0094] The following is for reference Figures 7A to 7C , Figures 8A to 8C , Figure 9 , Figures 10A to 10C , Figures 11A to 11C , Figure 12 , Figures 13A to 13C , Figures 14A to 14C , Figures 15A to 15C , Figures 16A to 16C and Figures 17A to 17C A method for manufacturing a semiconductor memory device according to embodiments of the present disclosure is described. Hereinafter, details related to... Figure 3 , Figure 4 and Figures 5A to 5C The same configuration is described repeatedly.

[0095] Figure 7A , Figure 7B and Figure 7C This is a cross-sectional view showing the steps of forming the source stack and etching the source stack.

[0096] Reference Figures 7A to 7C A source stack 300 can be formed on the lower structure 200. The lower structure 200 may include a peripheral circuit structure 190, a lower insulating structure 211 covering the peripheral circuit structure 190, and a first interconnect IC1 and a second interconnect IC2 buried in the lower insulating structure 211.

[0097] The peripheral circuit structure 190 may include a plurality of transistors TR and a discharge region 201DI formed in a semiconductor substrate 201 including a first region AR1, a second region AR2 and a third region AR3. A plurality of isolation layers 203 formed in the semiconductor substrate 201 may insulate the junctions 201J of adjacent transistors TR, or may insulate at least one junction 201J and the discharge region 201DI adjacent to the at least one junction 201J from each other.

[0098] Junction 201J can be formed in the first region AR1 and the second region AR2 of the semiconductor substrate 201. Discharge region 201DI can be formed in the third region AR3 of the semiconductor substrate 201.

[0099] The lower insulating structure 211 may be formed to cover the semiconductor substrate 201 and a plurality of transistors TR. A plurality of conductive patterns 221A, 221B, 221C, 221D, 221E, and 221F that configure each of the first interconnect IC1 and the second interconnect IC2 may be buried in the lower insulating structure 211. The plurality of conductive patterns 221A, 221B, 221C, 221D, 221E, and 221F that are connected to the discharge region 201DI and configure the first interconnect IC1 may be insulated from the plurality of conductive patterns 221A, 221B, 221C, 221D, 221E, and 221F that are connected to the junction 201J and configure the second interconnect IC2 through the lower insulating structure 211.

[0100] The source stack 300 may include a first semiconductor layer 231, a first protective layer 301, a sacrificial layer 303, a second protective layer 305, and a second semiconductor layer 233 sequentially stacked on the lower structure 200. The sacrificial layer 303 may include silicon. For example, the sacrificial layer 303 may include undoped silicon. The first semiconductor layer 231 and the second semiconductor layer 233 may include impurities with a conductivity type different from that of the discharge region 201DI. The first protective layer 301 and the second protective layer 305 may include a material with etch selectivity relative to the sacrificial layer 303. As an embodiment, the first protective layer 301 and the second protective layer 305 may include oxide layers.

[0101] Subsequently, the source stack 300 can be etched to form a first opening 311A ​​and a second opening 311B. The first opening 311A ​​may overlap with a first interconnect IC1 in a third region AR3 of the semiconductor substrate 201. The second opening 311B may overlap with a second interconnect IC2 in a first region AR1 of the semiconductor substrate 201. The first opening 311A ​​may be defined as a line, and the second opening 311B may be defined as a via. Each of the first opening 311A ​​and the second opening 311B may pass through the source stack 300 and expose the underlying insulating structure 211.

[0102] Figure 8A , Figure 8B and Figure 8C It is a cross-sectional view showing the steps of forming the source insulation pattern and the recess.

[0103] Reference Figures 8A to 8C It can be filled by using insulating materials Figure 7C The first opening 311A ​​shown and Figure 7B The second opening 311B shown is used to form source insulation patterns 230A and 230B. Source insulation patterns 230A and 230B may include filler. Figure 7C The first source insulating pattern 230A and the filling shown in the first opening 311A Figure 7B The second source insulating pattern 230B of the second opening 311B is shown. The first source insulating pattern 230A can pass through the source stack 300 in the third region AR3 of the semiconductor substrate 201 and overlap with the first interconnect IC1. The second source insulating pattern 230B can pass through the source stack 300 in the first region AR1 of the semiconductor substrate 201 and overlap with the second interconnect IC2.

[0104] Subsequently, the same masking process can be used to form a first contact hole 315A through the first source insulation pattern 230A and a second contact hole 315B through the second source insulation pattern 230B. The first contact hole 315A may overlap with the first interconnect IC1 and may extend into the lower insulation structure 211 to expose the first interconnect IC1. The second contact hole 315B may overlap with the second interconnect IC2 and may extend into the lower insulation structure 211 to expose the second interconnect IC2.

[0105] Subsequently, a trench 315T can be formed to connect to the first contact hole 315A and extend into the source stack 300. The trench 315T can be defined by etching a portion of the second semiconductor layer 233 and a portion of the first source insulating pattern 230A of the source stack 300. Figure 9 The horizontal pattern 235A of the metal structure 235 shown provides grooves 315T.

[0106] The recess R and the second contact hole 315B defined by the connection structure of the first contact hole 315A and the groove 315T can be formed by the above process.

[0107] Figure 9 , Figure 10A , Figure 10B and Figure 10C This is a diagram illustrating the steps involved in forming the metal structure and the lower contact. Figure 9 This is a plan view of metal structure 235. Figures 10A to 10C This shows the sections taken along lines I-I', II-II', and III-III'. Figure 9 The diagram shows a cross-sectional view of the intermediate process results.

[0108] Reference Figure 9 , Figure 10A , Figure 10B and Figure 10C A horizontal pattern 235A of the metal structure 235 can be formed in the trench 315T. In the embodiment, refer to... Figure 9 , Figure 10A , Figure 10B and Figure 10C The horizontal pattern 235A of the metal structure 235 can fill the trench 315T. The horizontal pattern 235A can pass through the second semiconductor layer 233 that overlaps with the first region AR1 and the second region AR2 of the semiconductor substrate 201. The horizontal pattern 235A can protrude further in the horizontal direction than the source stack 300 to overlap with the third region AR3 of the semiconductor substrate 201.

[0109] A vertical pattern 235B of the metal structure 235 can be formed in the first contact hole 315A. In one embodiment, the vertical pattern 235B of the metal structure 235 can fill the first contact hole 315A. The vertical pattern 235B can be connected to the horizontal pattern 235A and can contact the first interconnect IC1. The vertical pattern 235B can be connected to the discharge region 201DI through the first interconnect IC1.

[0110] The lower contact 237 can be formed in the second contact hole 315B using the process described above for forming the metal structure 235. The lower contact 237 can contact the second interconnect IC2. The lower contact 237 can be connected to the transistor TR through the second interconnect IC2. In this embodiment, the lower contact 237 filling the second contact hole 315B can be formed using the process described above for forming the metal structure 235.

[0111] A metal with a work function greater than that of the second semiconductor layer 233 can be formed in the trench 315T, the first contact hole 315A, and the second contact hole 315B. Therefore, a metal structure 235 and a lower contact 237 can be formed in the trench 315T, the first contact hole 315A, and the second contact hole 315B. As an embodiment, the metal used for the metal structure 235 and the lower contact 237 can be tungsten. Before forming the tungsten for the metal structure 235 and the lower contact 237, a metal barrier layer such as a titanium nitride layer can be further formed. In an embodiment, the metal structure 235 and the lower contact 237 can be formed by filling the trench 315T, the first contact hole 315A, and the second contact hole 315B with metal. In an embodiment, the work function of the metal can be greater than that of the second semiconductor layer 233. As an embodiment, the metal structure 235 and the lower contact 237 can be formed by filling the trench 315T, the first contact hole 315A, and the second contact hole 315B with tungsten.

[0112] Figure 11A , Figure 11B and Figure 11C This is a cross-sectional view showing the steps of forming the initial gate stack and the steps of forming the cell plug.

[0113] Reference Figures 11A to 11C A preliminary gate stack PST can be formed by alternately stacking a plurality of first material layers 321 and a plurality of second material layers 323 on the source stack 300. The plurality of first material layers 321 and the plurality of second material layers 323 can extend to overlap with the metal structure 235, the lower contact 237, the first source insulating pattern 230A and the second source insulating pattern 230B.

[0114] Each first material layer 321 can be provided as Figure 5A and Figure 5BThe interlayer insulating layer (ILD) is shown. Each of the second material layers 323 may include a material having etch selectivity relative to the first material layer 321. As an embodiment, the first material layer 321 may include an oxide such as a silicon oxide layer, and the second material layer 323 may include a nitride layer such as a silicon nitride layer. The etch selectivity of the metal structure 235 relative to each of the first material layer 321 and the second material layer 323 of the initial gate stack PST may be higher than the etch selectivity of the source stack 300 relative to each of the first material layer 321 and the second material layer 323 of the initial gate stack PST.

[0115] Multiple cell plugs CPLs can be formed on both sides of the horizontal pattern 235A of the metal structure 235. Forming the multiple cell plugs CPLs may include: forming a channel hole H through a preliminary gate stack PST passing through a first material layer 321 and a second material layer 323; forming a memory layer ML along the surface of the channel hole H; forming a semiconductor layer along the surface of the memory layer ML; and filling the central region of the channel hole H open through the semiconductor layer using a core insulating layer CO and a doped semiconductor layer. The semiconductor layer and the doped semiconductor layer inside the channel hole H can be configured as a channel layer CH. (Refer to reference...) Figure 5A The first memory pattern ML1 and the second memory pattern ML2 are similar in description, and the memory layer ML may include a barrier insulating layer, a data storage layer and a tunnel insulating layer.

[0116] The dummy plug DPL can be formed using the same process as forming a cell plug CPL. As an embodiment, a dummy via DH can be formed when forming a channel via H. When forming a memory layer ML, a dummy memory layer DML with the same configuration as the memory layer ML can be formed along the surface of the dummy via DH. When forming a semiconductor layer inside the channel via H, a semiconductor layer can be formed inside the dummy via DH. When forming a core insulating layer CO, a dummy core insulating layer DCO with the same configuration as the core insulating layer CO can be formed inside the dummy via DH. When forming a doped semiconductor layer in the channel via H, a doped semiconductor layer can be formed in the dummy via DH. The semiconductor layer and the doped semiconductor layer inside the dummy via DH can be configured with a dummy channel layer DCH.

[0117] The aforementioned channel via H and dummy via DH can extend into the first semiconductor layer 231 of the source stack 300. The channel layer CH and memory layer ML of the cell plug CPL can extend into the first semiconductor layer 231 along the channel via H. The dummy channel layer DCH and dummy memory layer DML of the dummy plug DPL can extend into the first semiconductor layer 231 along the surface of the dummy via DH.

[0118] To improve the integration density of semiconductor memory devices, the number of layers of the first material layer 321 and the second material layer 323 of the preliminary gate stack PST can be increased. As the number of layers of the first material layer 321 and the second material layer 323 increases, high power can be applied to the semiconductor manufacturing equipment during the etching process for forming the channel vias H and dummy vias DH. Due to the high power applied to the semiconductor manufacturing equipment, charge may accumulate in the source stack 300. During the etching of the first material layer 321 and the second material layer 323, a ground voltage can be applied from the support (not shown) of the semiconductor manufacturing equipment to the discharge region 201DI of the semiconductor substrate 201. Therefore, the charge accumulated in the source stack 300 can be discharged through the discharge region 201DI via a metal structure 235 with a work function higher than that of the source stack 300. Therefore, this disclosure reduces arcing.

[0119] Figure 12 , Figure 13A , Figure 13B and Figure 13C This is a cross-sectional view showing the steps involved in forming the stepped structure. Figure 12 This is a plan view showing the stepped structure. Figures 13A to 13C This shows the sections taken along lines I-I', II-II', and III-III'. Figure 12 The image shows a cross-sectional view of the intermediate process results.

[0120] Reference Figure 12 and Figures 13A to 13C The preliminary gate stack PST can be etched to define a stepped structure on a first region AR1 of the semiconductor substrate 201. Therefore, a contact region CTR and a cell array region CAR of the preliminary gate stack PST can be defined. The contact region CTR of the preliminary gate stack PST can be defined as a region having a stepped structure. The cell array region CAR of the preliminary gate stack PST can be defined as a region extending from the contact region CTR to surround the cell plug CPL and the dummy plug DPL.

[0121] When forming the stepped structure, the portion of the metal structure 235 that overlaps with the second region AR2 and the third region AR3 of the semiconductor substrate 201 can be opened.

[0122] Figure 14A , Figure 14B and Figure 14C This is a cross-sectional view showing the steps of forming the upper insulating layer, the filling insulating layer, and the gate separation structure.

[0123] Reference Figures 14A to 14CAn upper insulating layer 253 may be formed to cover the initial gate stack PST and the metal structure 235. Subsequently, a fill insulating layer 255 may be formed to penetrate the portion of the initial gate stack PST that overlaps with the second source insulating pattern 230B and to penetrate a portion of the upper insulating layer 253. The fill insulating layer 255 may overlap with the lower contact 237.

[0124] Subsequently, a gate separation structure 251 can be formed by etching at least one pair of first material layers 321 and second material layers 323 disposed on the uppermost layer of the preliminary gate stack PST. The gate separation structure 251 may extend inside the upper end of the dummy plug DPL.

[0125] Figure 15A , Figure 15B , Figure 15C , Figure 16A , Figure 16B , Figure 16C , Figure 17A , Figure 17B and Figure 17C This is a cross-sectional view showing the replacement process and the process of forming the conductive electrode contacts.

[0126] Reference Figures 15A to 15C This can form a preliminary slit 261A to pass through. Figure 14A and Figure 14B The preliminary gate stack PST is shown. The preliminary slit 261A may overlap with the horizontal pattern 235A of the metal structure 235. Since the etch selectivity of the metal structure 235 relative to the preliminary gate stack PST is higher than that of the source stack 300, the horizontal pattern 235A can be used as an etch stop layer. Therefore, the phenomenon of excessive depth of the preliminary slit 261A can be reduced. The preliminary slit 261A may extend to overlap with the second region AR2 of the semiconductor substrate 201.

[0127] Subsequently, selective removal can be achieved through the initial slit 261A. Figure 14A and Figure 14B The preliminary gate stack PST shown has multiple second material layers 323. Therefore, multiple gate regions 331 can be opened between adjacent first material layers 321 in the Z-axis direction.

[0128] Reference Figures 16A to 16C , can Figure 15A and Figure 15B Multiple conductive patterns CP are formed in the multiple gate regions 331 shown. In the embodiment, refer to... Figures 16A to 16C Multiple conductive patterns (CP) can be used for filling. Figure 15A and Figure 15B Multiple gate regions 331 are shown. Multiple remaining first material layers may be defined as multiple interlayer insulating layers (ILDs). (Refer to the above...) Figures 15A to 15C as well as Figures 16A to 16CAs described, the gate stack GST can be defined by replacing multiple second material layers 232 with multiple conductive patterns CP via a preliminary slit 261A.

[0129] After forming the gate stack (GST), it can be... Figures 15A to 15C The preliminary slit 261A shown removes a portion of the horizontal pattern 235A of the metal structure 235. Therefore, a slit 261 can be defined passing through the horizontal pattern 235A.

[0130] Subsequently, a spacer insulating layer 271 can be formed on the sidewall 261SW of the slit 261. Then, an etching process, such as a back-etching process, can be performed to expose the spacer. Figures 15A to 15C The sacrificial layer 303 is shown. Subsequently, selective removal can be performed. Figures 15A to 15C The etching process of the sacrificial layer 303 is shown. As the sacrificial layer 303 is removed... Figures 15A to 15C The memory layer ML, the virtual memory layer DML, the first protection layer 301, and the second protection layer 305 shown can be exposed.

[0131] Subsequently, the portion of each of the memory layer ML and the dummy memory layer DML exposed between the first semiconductor layer 231 and the second semiconductor layer 233 can be removed. When said portion of each of the memory layer ML and the dummy memory layer DML is removed, Figures 15A to 15C The first protective layer 301 and the second protective layer 305 shown can be removed.

[0132] Through the above process, a horizontal space 341 can be defined between the first semiconductor layer 231 and the second semiconductor layer 233, and the channel layer CH and the dummy channel layer DCH can be exposed through the horizontal space 341. Furthermore, Figure 15A The memory layer ML shown can be divided into a first memory pattern ML1 and a second memory pattern ML2 by a horizontal space 341, and Figure 15A The virtual memory layer ML shown can be divided into a first virtual memory pattern DML1 and a second virtual memory pattern DML2 by the horizontal space 341.

[0133] Reference Figures 17A to 17C It can be accessed through Figures 16A to 16C The slit 261 shown is filled with an interlayer semiconductor layer 263. Figures 16A to 16C The horizontal space 341 is shown. The interlayer semiconductor layer 263 may include a doped semiconductor layer. The interlayer semiconductor layer 263 may include impurities with a conductivity type different from that of the discharge region 201DI. As an embodiment, the discharge region 201DI may include p-type impurities, and the interlayer semiconductor layer 263 may include n-type impurities.

[0134] For reference Figures 16A to 16C and Figures 17A to 17CAs described, the interlayer semiconductor layer 263 can be replaced via slit 261. Figures 15A to 15C The first protective layer 301, the sacrificial layer 303, and the second protective layer 305 shown can thus define the source structure 260 connected to the channel layer CH.

[0135] Subsequently, a filling can be formed. Figures 16A to 16C The conductive power electrode contact 273 of the slit 261 shown. The conductive power electrode contact 273 may be disposed on the spacer insulating layer 271 and may be insulated from the conductive pattern CP of the gate stack GST through the spacer insulating layer 271.

[0136] After that, actions such as forming can be performed. Figure 5B The subsequent process of the upper contact 277 shown.

[0137] Figure 18 This is a block diagram illustrating the configuration of a memory system according to an embodiment of the present disclosure.

[0138] Reference Figure 18 The memory system 1100 includes a memory device 1120 and a memory controller 1110.

[0139] The memory device 1120 may be a multi-chip package configured with multiple flash memory chips. The memory device 1120 may include a metal structure having a horizontal pattern in a trench of a source structure and a vertical pattern extending from the horizontal pattern toward a semiconductor substrate.

[0140] The storage controller 1110 is configured to control the memory device 1120 and may include a static random access memory (SRAM) 1111, a central processing unit (CPU) 1112, a host interface 1113, an error correction block 1114, and a memory interface 1115. The SRAM 1111 serves as the operating memory for the CPU 1112, which performs overall control operations on data exchange with the storage controller 1110. The host interface 1113 includes a data exchange protocol for a host connected to the memory system 1100. The error correction block 1114 detects and corrects errors included in data read from the memory device 1120. The memory interface 1115 interfaces with the memory device 1120. The storage controller 1110 may also include a read-only memory (ROM) storing code data for interfacing with the host.

[0141] The aforementioned memory system 1100 may be a memory card or solid-state drive (SSD) in which memory device 1120 and storage controller 1110 are combined. For example, when the memory system 1100 is an SSD, the storage controller 1110 may communicate with an external (e.g., a host) via one of various interface protocols such as Universal Serial Bus (USB), Multimedia Card (MMC), High-Speed ​​Peripheral Component Interconnect (PCI-E), Serial Advanced Technology Attachment (SATA), Parallel Advanced Technology Attachment (PATA), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), and Integrated Drive Electronics (IDE).

[0142] Figure 19 This is a block diagram illustrating the configuration of a computing system according to an embodiment of the present disclosure.

[0143] Reference Figure 19 The computing system 1200 may include a CPU 1220, random access memory (RAM) 1230, a user interface 1240, a modem 1250, and a memory system 1210 electrically connected to a system bus 1260. When the computing system 1200 is a mobile device, it may also include a battery for supplying operating voltage to the computing system 1200, and may also include an application chipset, a graphics processor, mobile DRAM, etc.

[0144] The memory system 1210 may include a memory device 1212 and a memory controller 1211.

[0145] The memory device 1212 may include a metal structure having a horizontal pattern in a trench of a source structure and a vertical pattern extending from the horizontal pattern toward a semiconductor substrate.

[0146] Storage controller 1211 may have the same features as referenced above. Figure 18 The storage controller 1110 described has the same configuration.

[0147] According to some embodiments of this disclosure, the metal structure may include a horizontal pattern and a vertical pattern extending from the horizontal pattern. The horizontal pattern of the metal structure can serve as an etch stop layer when forming a slit through the initial gate stack. The vertical pattern of the metal structure can contact the source stack and thus serve as a charge discharge path during the etching process for forming a channel via through the initial gate stack. Therefore, this technology can improve the stability of the manufacturing process of semiconductor memory devices and provide semiconductor memory devices with improved reliability.

[0148] Cross-reference to related applications

[0149] This application claims priority to Korean Patent Application No. 10-2021-0061383, filed with the Korean Intellectual Property Office on May 12, 2021, the full disclosure of which is incorporated herein by reference.

Claims

1. A semiconductor memory device, the semiconductor memory device comprising: A semiconductor substrate, the semiconductor substrate including an upper surface extending in a horizontal direction; A source structure including a trench extending in the horizontal direction, the source structure being disposed above the semiconductor substrate; A metal structure located in the trench of the source structure and connected to the semiconductor substrate; as well as A string of memory cells is disposed on both sides of the trench and connected to the source structure. The metal structure includes: A horizontal pattern, which is in the groove; and A vertical pattern that extends from the horizontal pattern toward the semiconductor substrate.

2. The semiconductor memory device according to claim 1, wherein, The horizontal pattern of the metal structure protrudes further in the horizontal direction than the source structure.

3. The semiconductor memory device of claim 2, wherein, The vertical pattern of the metal structure is spaced apart from the source structure in the horizontal direction.

4. The semiconductor memory device according to claim 1, wherein, The semiconductor substrate includes multiple impurity regions separated by an isolation layer. The plurality of impurity regions include discharge regions and transistor junctions, and The vertical pattern of the metal structure is connected to the discharge region.

5. The semiconductor memory device according to claim 4, wherein, The discharge region includes impurities whose conductivity type differs from that of the source structure.

6. The semiconductor memory device of claim 5, wherein, The source structure includes a doped semiconductor layer containing n-type impurities, and The discharge region includes p-type impurities.

7. The semiconductor memory device of claim 4, wherein, The metal structure comprises a metal whose work function is greater than that of the source structure.

8. The semiconductor memory device according to claim 7, wherein, The metallic structure includes tungsten.

9. The semiconductor memory device of claim 4, further comprising: A lower insulating structure is disposed between the semiconductor substrate and the source structure; as well as An interconnect that electrically connects the discharge region and the vertical pattern of the metal structure and is embedded in the lower insulating structure.

10. The semiconductor memory device of claim 1, wherein, The source structure includes: A first semiconductor layer extends in the horizontal direction and overlaps with the trench; A second semiconductor layer, disposed above the first semiconductor layer and penetrated by the trench; and An interlayer semiconductor layer is disposed between the first semiconductor layer and the second semiconductor layer and overlaps with the trench.

11. The semiconductor memory device of claim 10, wherein, The horizontal pattern of the metal structure is in contact with the upper surface of the interlayer semiconductor layer.

12. The semiconductor memory device of claim 1, further comprising: A lower insulating structure is disposed at a height between the semiconductor substrate and the source structure to cover the semiconductor substrate; as well as A source electrode insulating pattern is disposed on the lower insulating structure and between the vertical patterns of the source electrode structure and the metal structure. The horizontal pattern extends over the source electrode insulation pattern.

13. A semiconductor memory device, the semiconductor memory device comprising: A semiconductor substrate, the semiconductor substrate including a first region, a second region and a third region, wherein the second region is disposed between the first region and the third region; A gate stack disposed above the first region of the semiconductor substrate; A source structure is disposed at a height between each of the gate stacks and the semiconductor substrate to overlap with the first region and the second region of the semiconductor substrate; A first source insulating pattern is disposed at a height between each of the gate stacks and the semiconductor substrate to overlap with the third region of the semiconductor substrate; A vertical structure disposed between the gate stacks and extending into the source structure; as well as A metal structure that connects the source structure to the semiconductor substrate. The metal structure includes: A vertical pattern that overlaps with the third region of the semiconductor substrate and passes through the first source insulating pattern; and A horizontal pattern that extends from the vertical pattern toward the vertical structure in a horizontal direction parallel to the upper surface of the semiconductor substrate.

14. The semiconductor memory device of claim 13, wherein, The vertical pattern of the metal structure is spaced apart from the source structure by the first source insulation pattern.

15. The semiconductor memory device of claim 13, wherein, The source structure includes: A first semiconductor layer is disposed at a height between the semiconductor substrate and the horizontal pattern of the metal structure; A second semiconductor layer, disposed above the first semiconductor layer and traversed by the horizontal pattern of the metal structure; and An interlayer semiconductor layer is disposed between the first semiconductor layer and the second semiconductor layer and includes an upper surface that contacts the horizontal pattern of the metal structure.

16. The semiconductor memory device of claim 15, wherein, The vertical structure extends toward the semiconductor substrate to pass through the second semiconductor layer, and The horizontal pattern of the metal structure extends between the vertical structure and the second semiconductor layer.

17. The semiconductor memory device of claim 16, wherein, The vertical structure includes: A conductive power electrode contact that contacts the interlayer semiconductor layer and extends between the gate layers; and A spacer insulating layer is disposed between each of the gate stacks and the conductive electrode contacts and extends between the horizontal pattern of the metal structure and the conductive electrode contacts.

18. The semiconductor memory device of claim 13, wherein, The semiconductor substrate includes multiple impurity regions separated by an isolation layer. The plurality of impurity regions include discharge regions and transistor junctions, and The vertical pattern of the metal structure is connected to the discharge region.

19. The semiconductor memory device of claim 18, further comprising: A lower insulating structure is disposed between the semiconductor substrate and the source structure; A first interconnection electrically connects the discharge region and the vertical pattern of the metal structure and is embedded in the lower insulating structure; A filling insulating layer is provided, which extends through at least one of the gate stacks; A second source insulation pattern, which overlaps with the filling insulation layer and passes through the source structure; A second interconnect is connected to the junction of the transistor and is buried in the lower insulating structure; The lower contact passes through the second source insulation pattern and is connected to the second interconnect. as well as The upper contact passes through the filling insulation layer and is connected to the lower contact.

20. The semiconductor memory device of claim 13, further comprising: A channel layer that passes through each of the gate stacks and is connected to the source structure; as well as A memory layer is disposed between each of the gate stacks and the channel layer. Each of the gate stacks includes an interlayer insulating layer and a conductive pattern alternately disposed on the source structure.

21. A method for manufacturing a semiconductor memory device, the method comprising the following steps: Formation of source electrode stacks; A first source insulation pattern is formed, which passes through the source stack; A recess is formed, the recess including a first contact hole and a trench, the first contact hole passing through the first source electrode insulating pattern, the trench connecting to the first contact hole and being defined inside the source electrode stack; A metal structure is formed, the metal structure including a horizontal pattern and a vertical pattern, the horizontal pattern being in the trench, and the vertical pattern being connected to the horizontal pattern and formed in the first contact hole; A preliminary gate stack is formed by alternately stacking a first material layer and a second material layer on the source stack; Unit plugs are formed on both sides of the vertical pattern of the metal structure, passing through the initial gate stack; A slit is formed that extends through the initial gate stack that overlaps with the horizontal pattern of the metal structure and through the horizontal pattern of the metal structure; as well as A portion of the source stack is replaced by an interlayer semiconductor layer through the slit.

22. The method according to claim 21, wherein, The source layer stack comprises a first semiconductor layer, a first protective layer, a sacrificial layer, a second protective layer, and a second semiconductor layer stacked sequentially. The first protective layer, the sacrificial layer, and the second protective layer are replaced by the interlayer semiconductor layer.

23. The method of claim 22, wherein, The etch selectivity of the initial gate stack relative to the metal structure is higher than that of the initial gate stack relative to the source stack.

24. The method of claim 23, wherein, The sacrificial layer comprises silicon.

25. The method of claim 22, wherein, The metal structure comprises a metal with a work function greater than that of the second semiconductor layer.

26. The method of claim 25, wherein, The metallic structure includes tungsten.

27. The method of claim 21, wherein, The source electrode stack is formed on the lower structure. The lower structure includes: A semiconductor substrate comprising a discharge region separated from each other by an isolation layer and a transistor junction; A lower insulating structure that covers the semiconductor substrate; A first interconnect, which is embedded in the lower insulating structure and connected to the discharge region; and A second interconnect is embedded in the lower insulation structure and connected to the junction.

28. The method of claim 27, wherein, The interlayer semiconductor layer includes impurities whose conductivity type is different from that of the discharge region.

29. The method of claim 28, wherein, The discharge region includes p-type impurities, and The interlayer semiconductor layer includes n-type impurities.

30. The method of claim 27, wherein, The first interconnect is exposed through the recessed first contact hole, and The vertical pattern of the metal structure is connected to the discharge region of the semiconductor substrate via the first interconnect.

31. The method of claim 27, further comprising the step of: A second source insulation pattern is formed, which passes through the source stack overlapping with the second interconnect; A second contact hole is formed, which passes through the second source insulation pattern and exposes the second interconnect; as well as The lower contact is formed within the second contact hole using the process for forming the metal structure.

32. The method of claim 21, further comprising the step of: The second material layer of the initial gate stack is replaced by a conductive pattern through the slit; An insulating layer of spacers is formed on the sidewall of the slit; as well as Conductive power electrode contacts connected to the interlayer semiconductor layer are formed on the spacer insulating layer.

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