Display substrate and manufacturing method thereof, and display device

Abstract

The embodiments of the present application provide a display substrate, a method for preparing the same, and a display device. The display substrate includes: a substrate; a thin film transistor, which is arranged on one side of the substrate, and the thin film transistor includes a gate; a signal transmission layer, which is located on the side of the gate away from the substrate, the gate is electrically connected to the signal transmission layer, and the signal transmission layer is used to connect to an external circuit; wherein: the gate is a closed structure; or the gate is a non-closed structure, the gate has an opening, and the open end of the gate is connected to the signal transmission layer, so that the gate and the signal transmission layer cooperate to form a closed structure. The embodiments of the present application solve the technical problem in the prior art that the gate is in a floating state, which is prone to accumulate static electricity and cause electrostatic damage.

Description

Technical Field

[0001] The present application relates to the field of display technology. Specifically, the present application relates to a display substrate and a preparation method thereof, and a display device. Background Art

[0002] OLED (Organic Light-Emitting Diode) display technology is gaining popularity due to its advantages such as high contrast, wide color gamut, and light weight. Currently, OLED display technology has also become the mainstream development of medium-sized display products such as NB (Notebook Computer) and car-mounted products.

[0003] In existing mid-size OLED display panel design methods, the gates of the TFTs (Thin Film Transistors) of some OLED products are in a floating state, which can easily accumulate static electricity, causing electrostatic damage and reducing product yield. Summary of the Invention

[0004] In response to the shortcomings of the existing methods, this application proposes a display substrate and its preparation method, and a display device to solve the technical problem in the existing technology that the gate is in a floating state, which easily accumulates static electricity and causes static electricity damage.

[0005] In the first aspect, an embodiment of the present application provides a display substrate, comprising: a substrate; a thin film transistor, arranged on one side of the substrate, the thin film transistor including a gate; a signal transmission layer, located on a side of the gate away from the substrate, the gate being electrically connected to the signal transmission layer, and the signal transmission layer being used to connect to an external circuit; wherein: the gate is a closed structure; or, the gate is a non-closed structure, the gate has an opening, and the open end of the gate is connected to the signal transmission layer, so that the gate and the signal transmission layer cooperate to form a closed structure.

[0006] Optionally, the signal transmission layer includes a first transmission line and at least one second transmission line, the first transmission line is used to connect to an external circuit, and one end of each second transmission line is connected to the first transmission line; the first transmission line is connected to the gate, and the end of the second transmission line away from the first transmission line is connected to the open end of the gate, and the orthographic projection of the connection point between the first transmission line and the gate on the substrate does not overlap with the orthographic projection of the connection point between the second transmission line and the gate on the substrate.

[0007] Optionally, the gate is "L"-shaped, including a first gate segment and a second gate segment connected to each other, the first gate segment and the second gate segment are arranged at an angle, the end of the first gate segment away from the second gate segment is connected to the first transmission line, and the end of the second gate segment away from the first gate segment is connected to the second transmission line; or, the gate is "U"-shaped, including a first gate segment, a second gate segment and a third gate segment, the second gate segment is connected to one end of the first gate segment and is arranged at an angle to the first gate segment, and the third gate segment is connected to the other end of the first gate segment and is arranged at an angle to the first gate segment; the first transmission line is connected to the first gate segment, and the number of second transmission lines is two, one of the second transmission lines is connected to the end of the second gate segment away from the first gate segment, and the other second transmission line is connected to the end of the third gate segment away from the first gate segment.

[0008] Optionally, the gate is "U"-shaped, including a first gate segment, a second gate segment and a third gate segment connected in sequence, the first gate segment and the second gate segment are arranged at an angle, and the third gate segment and the second gate segment are arranged at an angle; the signal transmission layer includes a first transmission line, and the first transmission line is used to connect to an external circuit; the end of the first gate segment away from the second gate segment is connected to the first transmission line, and the end of the third gate segment away from the second gate segment is connected to the first transmission line.

[0009] Optionally, the gate is in a "mouth" shape, the signal transmission layer includes a first transmission line, and the first transmission line is used to connect to an external circuit; both sides of the "mouth" of the gate are connected to the first transmission line.

[0010] Optionally, the display substrate further includes a first insulating layer, which is located between the gate and the signal transmission layer and covers the gate; the signal transmission layer is electrically connected to the gate via at least two first through holes penetrating the first insulating layer.

[0011] In a second aspect, an embodiment of the present application provides a display device, comprising: the above-mentioned display substrate.

[0012] In a third aspect, an embodiment of the present application provides a method for preparing a display substrate, comprising: providing a substrate, and making a gate of a thin film transistor on one side of the substrate; making a signal transmission layer on a side of the gate away from the substrate, the gate being electrically connected to the signal transmission layer, and the signal transmission layer being used to connect to an external circuit; the gate being a closed structure; or, the gate being a non-closed structure, the gate having an opening, and the open end of the gate being connected to the signal transmission layer, so that the gate and the signal transmission layer cooperate to form a closed structure.

[0013] Optionally, a gate of a thin film transistor is formed on one side of a substrate, including: forming a metal film layer on one side of the substrate, and patterning the metal film layer through a composition process to form a gate; and a signal transmission layer is formed on a side of the gate away from the substrate, including: forming an electric transmission film layer on one side of the substrate, and patterning the electric transmission film layer through a composition process to form a signal transmission layer.

[0014] Optionally, before forming the signal transmission layer on the side of the gate away from the substrate, the method for preparing the display substrate also includes: forming a first insulating layer on one side of the substrate through a composition process, the first insulating layer covering the gate, and the first insulating layer is provided with at least two first through holes to expose the gate.

[0015] The beneficial technical effects brought about by the technical solutions provided in the embodiments of the present application include:

[0016] In an embodiment of the present application, the gate is a closed structure. When an operating voltage or an operating current is provided to the gate through the signal transmission layer, the gate itself can form a closed loop; or the gate is a non-closed structure with an opening. By connecting the open end of the gate to the signal transmission layer, the gate and the signal transmission layer cooperate to form a closed structure. When an operating voltage or an operating current is provided to the gate through the signal transmission layer, the gate as a whole can form a closed loop with the signal transmission layer. In an embodiment of the present application, the gate itself can form a closed loop, or the gate as a whole can form a closed loop with the signal transmission layer, thereby avoiding the gate being in a floating state, reducing the accumulation of static charge, preventing other defects caused by electrostatic damage, and improving product yield.

[0017] Additional aspects and advantages of the present application will be given in part in the following description, which will become apparent from the following description, or will be learned through practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the following description of the embodiments in conjunction with the accompanying drawings, in which:

[0019] Figure 1 A top view of a display substrate provided in an embodiment of the present application (showing only the gate electrode, signal transmission layer, and semiconductor layer of the display substrate);

[0020] Figure 2 A stacking diagram of a display substrate provided in an embodiment of the present application;

[0021] Figure 3 A top view of another display substrate provided in an embodiment of the present application (showing only the gate electrode, signal transmission layer, and semiconductor layer of the display substrate);

[0022] Figure 4A top view of another display substrate provided in an embodiment of the present application (showing only the gate electrode, signal transmission layer, and semiconductor layer of the display substrate);

[0023] Figure 5 A top view of another display substrate provided in an embodiment of the present application (showing only the gate electrode, signal transmission layer, and semiconductor layer of the display substrate);

[0024] Figure 6 A top view of another display substrate provided in an embodiment of the present application (showing only the gate electrode, signal transmission layer, and semiconductor layer of the display substrate);

[0025] Figure 7 A flow chart of a method for preparing a display substrate provided in an embodiment of the present application;

[0026] Figures 8 to 11 Schematic diagram of the structure of different processes in a method for preparing a display substrate provided in an embodiment of the present application.

[0027] Reference numerals:

[0028] 100-display substrate; 10-substrate; 20-gate; 21-first gate segment; 22-second gate segment; 23-third gate segment; 30-signal transmission layer; 31-first transmission line; 32-second transmission line; 40-first insulating layer; 41-first through hole; 50-semiconductor layer; 51-source; 52-drain; 53-channel; 60-second insulating layer; 70-planar layer. DETAILED DESCRIPTION

[0029] The following describes the embodiments of the present application in conjunction with the accompanying drawings. It should be understood that the embodiments described below in conjunction with the accompanying drawings are exemplary descriptions for explaining the technical solutions of the embodiments of the present application and do not constitute a limitation on the technical solutions of the embodiments of the present application.

[0030] Those skilled in the art will understand that, unless otherwise stated, the singular forms "a," "an," "said," and "the" used herein may also include the plural forms. It should be further understood that the term "comprising" used in the specification of this application refers to the presence of the described features, integers, steps, operations, elements, and / or components, but does not exclude the implementation of other features, information, data, steps, operations, elements, components, and / or combinations thereof supported by the technical field. It should be understood that when we refer to an element as being "connected" or "coupled" to another element, the element may be directly connected or coupled to the other element, or it may refer to the element and the other element establishing a connection relationship through an intermediate element. In addition, the "connection" or "coupling" used herein may include wireless connection or wireless coupling. The term "and / or" used herein refers to at least one of the items defined by the term, for example, "A and / or B" may be implemented as "A," or as "B," or as "A and B."

[0031] In order to make the objectives, technical solutions and advantages of this application clearer, the implementation methods of this application will be further described in detail below with reference to the accompanying drawings.

[0032] With the continuous development of OLED display technology, medium-sized OLED display devices are also becoming increasingly popular. However, compared with small-sized display products, medium-sized display products have a higher electrostatic damage rate and bright spot incidence rate, and both are strongly correlated with TFT. The high incidence of this defect has caused a loss in product yield.

[0033] In the existing design method of medium-sized OLED display panels, for example, the gate of one / some TFTs in the 7T1C pixel circuit included in the display panel adopts a "U"-shaped structure. The gate of the "U"-shaped structure is electrically connected to the external circuit through a signal transmission layer. Since the gate of the "U"-shaped structure is electrically connected to the signal transmission layer through only one connection point, the entire gate is in a floating state, which easily accumulates static electricity, causing electrostatic damage and reducing product yield.

[0034] At the same time, since the gate of the "U"-shaped structure is electrically connected to the signal transmission layer only through a through-hole, the design of the through-hole makes the gate and the signal transmission layer conductive through surface contact, and the voltage is transmitted from the signal transmission layer to the gate through a through-hole, resulting in a large resistance between the contact surface of the gate and the signal transmission layer, causing gate voltage loss, making the gate voltage low, resulting in serious leakage of T1 TFT, and increasing the risk of leakage-type bright spots in T1 TFT.

[0035] The display substrate, preparation method thereof, and display device provided in this application are intended only to solve the above technical problems of the prior art.

[0036] The following is a detailed description of the technical solution of the present application and how the technical solution of the present application solves the above-mentioned technical problems with specific embodiments. It should be noted that the following embodiments can refer to, draw on, or combine with each other, and the same terms, similar features, and similar implementation steps in different embodiments will not be repeated.

[0037] The embodiment of the present application provides a display substrate. The structural diagram of the display substrate 100 is shown in FIG. Figures 1 to 6 As shown, it includes: a substrate 10, a thin film transistor and a signal transmission layer 30, the thin film transistor is arranged on one side of the substrate 10, and the thin film transistor includes a gate 20; the signal transmission layer 30 is located on the side of the gate 20 away from the substrate 10, the gate 20 is electrically connected to the signal transmission layer 30, and the signal transmission layer 30 is used to connect to an external circuit; wherein: the gate 20 is a closed structure (such as Figure 4 Alternatively, the gate 20 is a non-closed structure (as shown in FIG. Figure 1 、 Figure 3 、 Figure 5 and Figure 6 As shown), the gate 20 has an opening, and the open end of the gate 20 is connected to the signal transmission layer 30, so that the gate 20 and the signal transmission layer 30 cooperate to form a closed structure.

[0038] In the embodiment of the present application, substrate 10 is used to support thin-film transistors and signal transmission layer 30. Gate 20 is connected to an external circuit through signal transmission layer 30. The external circuit can provide an operating voltage or operating current to the thin-film transistor through signal transmission layer 30, enabling the thin-film transistor to operate normally. The thin-film transistor can be used to control the light emission of display substrate 100.

[0039] In the embodiment of the present application, the gate 20 is a closed structure. When an operating voltage or an operating current is supplied to the gate 20 through the signal transmission layer 30, the gate 20 itself can form a closed loop. Alternatively, the gate 20 is a non-closed structure with an opening. By connecting the open end of the gate 20 to the signal transmission layer, the gate 20 and the signal transmission layer 30 cooperate to form a closed structure. When an operating voltage or an operating current is supplied to the gate 20 through the signal transmission layer 30, the gate 20 as a whole can form a closed loop with the signal transmission layer 30. In the embodiment of the present application, the gate 20 itself can form a closed loop, or the gate 20 as a whole can form a closed loop with the signal transmission layer 30, thereby avoiding the gate 20 being in a floating state, reducing the accumulation of static charge, preventing other defects caused by electrostatic damage, and improving product yield.

[0040] Alternatively, as Figure 1 and Figure 2As shown, in the embodiment of the present application, the thin film transistor further includes a semiconductor layer 50 , which is disposed on one side of the substrate 10 and between the gate 20 and the substrate 10 .

[0041] Specifically, if Figure 1 As shown, in an embodiment of the present application, the semiconductor layer 50 includes a source 51, a drain 52 and a channel 53 located between the source 51 and the drain 52, and the channel 53 is used to separate the source 51 and the drain 52 so that the source 51 and the drain 52 are not electrically connected, and the orthographic projection of the gate 20 on the substrate 10 covers the orthographic projection of the channel 53 on the substrate 10.

[0042] like Figure 1 As shown, in the embodiment of the present application, the source electrode 51 is located on the side of the second gate segment 22 away from the third gate segment 23, and the drain electrode 52 is located between the second gate segment 22 and the third gate segment 23. Of course, in an optional embodiment, the drain electrode can also be located on the side of the second gate segment 22 away from the third gate segment 23, and the source electrode 51 is located between the second gate segment 22 and the third gate segment 23, according to actual needs.

[0043] In an optional embodiment, the thin film transistor further includes an active layer and / or a gate insulating layer, and the source electrode 51 and the drain electrode 52 are both electrically connected to the active layer. The specific configuration of the active layer and / or the gate insulating layer is similar to that in the prior art and will not be further described here.

[0044] Alternatively, as Figure 2 As shown, the display substrate 100 of the embodiment of the present application further includes a first insulating layer 40, which is located between the gate 20 and the signal transmission layer 30, and covers the gate 20; the signal transmission layer 30 is electrically connected to the gate 20 through at least two first through holes 41 passing through the first insulating layer 40.

[0045] In the embodiment of the present application, the signal transmission layer 30 is electrically connected to the gate 20 via at least two first through-holes 41, and voltage is transmitted from the signal transmission layer 30 to the gate 20 via the at least two first through-holes 41. Compared to the existing technology of connecting via only one through-hole, the at least two first through-holes 41 are spaced apart in the embodiment of the present application, so that at least two parallel circuits are formed between the signal transmission layer 30 and the gate 20. Therefore, the voltage division of each first through-hole 41 is reduced, effectively reducing the resistance between the gate 20 and the signal transmission layer 30 at the contact surface, reducing the voltage loss of the gate 20, increasing the voltage of the gate 20, and reducing the incidence of leakage-type bright spots.

[0046] Alternatively, as Figure 2As shown, the display substrate 100 of the embodiment of the present application further includes a planar layer 70 , which is located between the first insulating layer 40 and the signal transmission layer 30 , and covers the first insulating layer 40 . The planar layer 70 is used to form a flat plane.

[0047] Alternatively, as Figure 2 As shown, in the embodiment of the present application, the flat layer 70 is provided with at least two second through holes, and the at least two second through holes are arranged in a one-to-one correspondence with the at least two first through holes 41. The signal transmission layer 30 is electrically connected to the gate 20 through the at least two second through holes passing through the flat layer 70 and the at least two first through holes 41 passing through the first insulating layer 40.

[0048] Optionally, the material of the planar layer 70 is resin.

[0049] Alternatively, as Figure 2 As shown, the display substrate 100 of the embodiment of the present application further includes a second insulating layer 60 . The second insulating layer 60 is located between the semiconductor layer 50 and the gate 20 , and the second insulating layer 60 covers the semiconductor layer 50 .

[0050] Specifically, in the embodiment of the present application, the specific configuration of the second insulating layer 60 is similar to that in the prior art and will not be repeated here.

[0051] In a specific embodiment, Figure 1 and Figure 3 As shown, in the embodiment of the present application, the signal transmission layer 30 includes a first transmission line 31 and at least one second transmission line 32, the first transmission line 31 is used to connect to an external circuit, and one end of each second transmission line 32 is connected to the first transmission line 31; the first transmission line 31 is connected to the gate 20, and the end of the second transmission line 32 away from the first transmission line 31 is connected to the open end of the gate 20, and the orthographic projection of the connection point between the first transmission line 31 and the gate 20 on the substrate 10 does not overlap with the orthographic projection of the connection point between the second transmission line 32 and the gate 20 on the substrate 10.

[0052] In the embodiment of the present application, the signal transmission layer 30 includes a first transmission line 31 and a second transmission line 32 connected to the first transmission line 31. The first transmission line 31 is used to connect to an external circuit. The first transmission line 31 is connected to the gate 20. The end of the second transmission line 32 away from the first transmission line 31 is connected to the open end of the gate 20. The gate 20 cooperates with the first transmission line 31 and the second transmission line 32 to form a closed structure. When an operating voltage or an operating current is provided to the gate 20 through the first transmission line 31, the gate 20 as a whole, the first transmission line 31 and the second transmission line 32 can form a closed loop, thereby preventing the gate 20 from being in a floating state, reducing the accumulation of static charge, preventing electrostatic damage, and improving product yield.

[0053] Specifically, in an optional embodiment, as Figure 1 As shown, the gate 20 is U-shaped and includes a first gate segment 21, a second gate segment 22 and a third gate segment 23. The second gate segment 22 is connected to one end of the first gate segment 21 and is arranged at an angle to the first gate segment 21. The third gate segment 23 is connected to the other end of the first gate segment 21 and is arranged at an angle to the first gate segment 21. A first transmission line 31 is connected to the first gate segment 21. There are two second transmission lines 32, one of which is connected to an end of the second gate segment 22 away from the first gate segment 21, and the other is connected to an end of the third gate segment 23 away from the first gate segment 21.

[0054] In the embodiment of the present application, the second gate segment 22, the first gate segment 21, and the third gate segment 23 are connected in sequence, and a first transmission line 31 is connected to the first gate segment 21, one second transmission line 32 is connected to the end of the second gate segment 22 away from the first gate segment 21, and another second transmission line 32 is connected to the end of the third gate segment 23 away from the first gate segment 21. In this way, when an operating voltage or operating current is provided to the gate 20 via the first transmission line 31, the first transmission line 31, the first gate segment 21, the second gate segment 22, and the corresponding second transmission line 32 can form a closed loop. The first transmission line 31, the first gate segment 21, the third gate segment 23, and the corresponding second transmission line 32 can form a closed loop. The first gate segment 21, the second gate segment 22, the two second transmission lines 32, and the third gate segment 23 can form a closed loop. The gate 20 as a whole can form a closed loop with the first transmission line 31 and the second transmission line 32, thereby preventing the gate 20 from being in a floating state, reducing static charge accumulation, preventing electrostatic damage, and improving product yield.

[0055] In addition, in the embodiment of the present application, the first transmission line 31 is connected to the first gate segment 21 through a first through-hole 41, one of the second transmission lines 32 is connected to the second gate segment 22 through a first through-hole 41, and another second transmission line 32 is connected to the third gate segment 23 through a first through-hole 41. The signal transmission layer 30 is electrically connected to the gate 20 through three first through-holes 41. Since the three first through-holes 41 are arranged at intervals, three parallel circuits are formed between the signal transmission layer 30 and the gate 20. Therefore, the voltage division of each first through-hole 41 is reduced, effectively reducing the resistance between the gate 20 and the signal transmission layer 30 at the contact surface, reducing the voltage loss of the gate 20, increasing the voltage of the gate 20, and reducing the incidence of leakage-type bright spots.

[0056] Specifically, if Figure 1As shown, in the embodiment of the present application, the extension direction of the first transmission line 31 is at an angle to the extension direction of the semiconductor layer 50 (optionally, the angle is 90°), and the "U"-shaped opening direction of the gate 20 is parallel to the extension direction of the first transmission line 31, that is, it is at an angle to the extension direction of the semiconductor layer 50 (optionally, the angle is 90°). The connection point between the first transmission line 31 and the first gate segment 21 is located on one side of the semiconductor layer 50, and the connection point between the second transmission line 32 and the second gate segment 22, as well as the connection point between the other second transmission line 32 and the third gate segment 23, are all located on the other side of the semiconductor layer 50. This arrangement can reduce crosstalk, make the potential more stable, obtain a better potential average value, minimize the impact of voltage drop, and make the signal loading of the gate 20 more stable.

[0057] Of course, in an optional embodiment, the extension direction of the first transmission line 31 can be parallel to the extension direction of the semiconductor layer 50 according to actual needs. At this time, the "U"-shaped opening direction of the gate 20 is parallel to the extension direction of the semiconductor layer 50, and there is an angle between the extension direction of the second transmission line 32 and the extension direction of the semiconductor layer 50. The connection point between the second transmission line 32 and the second gate segment 22 is located on one side of the semiconductor layer 50, and the connection point between the other second transmission line 32 and the third gate segment 23 is located on the other side of the semiconductor layer 50.

[0058] The embodiment of the present application improves the structure of the signal transmission layer so that the two ends of the floating of the "U"-shaped gate are respectively connected to the signal transmission layer, thereby avoiding the floating problem of the gate, reducing the accumulation of static charge, preventing electrostatic damage, and improving product yield.

[0059] Specifically, in another optional embodiment, as Figure 3 As shown, the gate 20 is "L"-shaped, including a first gate segment 21 and a second gate segment 22 connected to each other. The first gate segment 21 and the second gate segment 22 are arranged at an angle. The end of the first gate segment 21 away from the second gate segment 22 is connected to the first transmission line 31, and the end of the second gate segment 22 away from the first gate segment 21 is connected to the second transmission line 32.

[0060] In the embodiment of the present application, the first gate segment 21 and the second gate segment 22 are connected, and the end of the first gate segment 21 away from the second gate segment 22 is connected to the first transmission line 31, and the end of the second gate segment 22 away from the first gate segment 21 is connected to the second transmission line 32. In this way, when an operating voltage or operating current is provided to the gate 20 via the first transmission line 31, the first transmission line 31, the first gate segment 21, the second gate segment 22, and the second transmission line 32 can form a closed loop. The gate 20 as a whole can form a closed loop with the first transmission line 31 and the second transmission line 32, thereby preventing the gate 20 from being in a floating state, reducing static charge accumulation, preventing electrostatic damage, and improving product yield.

[0061] In addition, in the embodiment of the present application, the first transmission line 31 is connected to the first gate segment 21 through a first through-hole 41, and the second transmission line 32 is connected to the second gate segment 22 through a first through-hole 41. The signal transmission layer 30 is electrically connected to the gate 20 through the two first through-holes 41. Since the two first through-holes 41 are arranged at intervals, two parallel circuits are formed between the signal transmission layer 30 and the gate 20. Therefore, the voltage division of each first through-hole 41 is reduced, effectively reducing the resistance between the gate 20 and the signal transmission layer 30 at the contact surface, reducing the voltage loss of the gate 20, increasing the voltage of the gate 20, and reducing the incidence of leakage-type bright spots.

[0062] Specifically, if Figure 3 As shown, in the embodiment of the present application, there is an angle between the extension direction of the first transmission line 31 and the extension direction of the semiconductor layer 50 (optionally, the angle is 90°), the connection point between the first gate segment 21 and the first transmission line 31 is located on one side of the semiconductor layer 50, and the connection point between the second gate segment 22 and the second transmission line 32 is located on the other side of the semiconductor layer 50. Through this setting, crosstalk can be reduced, the potential can be made more stable, a better potential average value can be obtained, the voltage drop effect is smaller, and the signal loading of the gate 20 is made more stable.

[0063] Of course, in an optional embodiment, according to actual needs, the extension direction of the first transmission line 31 can be parallel to the extension direction of the semiconductor layer 50, the extension direction of the second transmission line 32 can have an angle with the extension direction of the semiconductor layer 50, and the gate 20 can be located on one side of the semiconductor layer 50.

[0064] In another specific embodiment, Figure 4 As shown, in the embodiment of the present application, the gate 20 is in a "mouth" shape, and the signal transmission layer 30 includes a first transmission line 31, which is used to connect to an external circuit; both sides of the "mouth" of the gate 20 are connected to the first transmission line 31.

[0065] In the embodiment of the present application, the gate 20 is in a "mouth" shape and has a closed structure. When an operating voltage or an operating current is provided to the gate 20 through the first transmission line 31, the gate 20 itself can form a closed loop. At the same time, since the two opposite sides of the gate 20 are connected to the first transmission line 31, the gate 20 and the first transmission line 31 can form a closed loop, thereby preventing the gate 20 from being in a floating state, reducing the accumulation of static charge, preventing electrostatic damage, and improving product yield.

[0066] In addition, in the embodiment of the present application, the two opposite sides of the gate 20 are connected to the first transmission line 31 through a first through hole 41 respectively, that is, the signal transmission layer 30 is electrically connected to the gate 20 through two first through holes 41. Since the two first through holes 41 are arranged at intervals, two parallel circuits are formed between the signal transmission layer 30 and the gate 20. Therefore, the voltage division of each first through hole 41 is reduced, which effectively reduces the resistance between the gate 20 and the signal transmission layer 30 at the contact surface, reduces the voltage loss of the gate 20, increases the voltage of the gate 20, and reduces the incidence of leakage-type bright spots.

[0067] The embodiment of the present application improves the structure of the gate and sets the gate 20 to a "mouth" shape. The gate 20 itself can form a closed loop, avoiding the floating problem of the gate, reducing the accumulation of static charge, preventing electrostatic damage, and improving product yield.

[0068] Specifically, if Figure 4 As shown, in the embodiment of the present application, there is an angle between the extension direction of the first transmission line 31 and the extension direction of the semiconductor layer 50 (optionally, the angle is 90°), and the first transmission line 31 is connected to the two sides of the gate 20 on both sides of the semiconductor layer 50. The two connection points of the first transmission line 31 and the gate 20 are respectively located on both sides of the semiconductor layer 50. Through this setting, crosstalk can be reduced, the potential can be made more stable, a better potential average value can be obtained, the voltage drop effect is smaller, and the signal loading of the gate 20 is made more stable.

[0069] Of course, in an optional embodiment, the extension direction of the first transmission line 31 can be parallel to the extension direction of the semiconductor layer 50 according to actual needs. In this case, the first transmission line 31 is connected to the two sides of the gate 20 that are spaced apart along the extension direction of the semiconductor layer 50; or, the extension direction of the first transmission line 31 and the extension direction of the semiconductor layer 50 have an angle (optionally, the angle is less than 90°), and the first transmission line 31 is connected to the two adjacent sides of the gate 20.

[0070] In another specific embodiment, Figure 5As shown, in the embodiment of the present application, the gate 20 is "U"-shaped, including a first gate segment 21, a second gate segment 22 and a third gate segment 23 connected in sequence, the first gate segment 21 and the second gate segment 22 are arranged at an angle, and the third gate segment 23 and the second gate segment 22 are arranged at an angle; the signal transmission layer 30 includes a first transmission line 31, and the first transmission line 31 is used to connect to an external circuit; the end of the first gate segment 21 away from the second gate segment 22 is connected to the first transmission line 31, and the end of the third gate segment 23 away from the second gate segment 22 is connected to the first transmission line 31.

[0071] In the embodiment of the present application, the first gate segment 21, the second gate segment 22, and the third gate segment 23 are connected in sequence, and the end of the first gate segment 21 away from the second gate segment 22 is connected to the first transmission line 31, and the end of the third gate segment 23 away from the second gate segment 22 is connected to the first transmission line 31. In this way, when an operating voltage or operating current is provided to the gate 20 via the first transmission line 31, the first transmission line 31, the first gate segment 21, the second gate segment 22, and the third gate segment 23 can form a closed loop. The gate 20 as a whole can form a closed loop with the first transmission line 31, thereby preventing the gate 20 from being in a floating state, reducing static charge accumulation, preventing electrostatic damage, and improving product yield.

[0072] In addition, in the embodiment of the present application, the first gate segment 21 is connected to the first transmission line 31 through a first through-hole 41, and the third gate segment 23 is connected to the first transmission line 31 through a first through-hole 41. The signal transmission layer 30 is electrically connected to the gate 20 through the two first through-holes 41. Since the two first through-holes 41 are arranged at intervals, two parallel circuits are formed between the signal transmission layer 30 and the gate 20. Therefore, the voltage division of each first through-hole 41 is reduced, effectively reducing the resistance between the gate 20 and the signal transmission layer 30 at the contact surface, reducing the voltage loss of the gate 20, increasing the voltage of the gate 20, and reducing the incidence of leakage-type bright spots.

[0073] Specifically, if Figure 5 As shown, in the embodiment of the present application, the extension direction of the first transmission line 31 forms an angle with the extension direction of the semiconductor layer 50 (optionally, the angle is 90°), and the "U"-shaped opening direction of the gate 20 is the same as the extension direction of the semiconductor layer 50. The two connection points between the first transmission line 31 and the gate 20 are located on either side of the semiconductor layer 50. This arrangement can reduce crosstalk, make the potential more stable, obtain a better potential average value, minimize the impact of voltage drop, and make the signal loading of the gate 20 more stable.

[0074] Of course, in an optional embodiment, the extension direction of the first transmission line 31 may be parallel to the extension direction of the semiconductor layer 50 according to actual needs (eg Figure 6As shown), at this time, there is an angle between the "U"-shaped opening direction of the gate 20 and the extension direction of the semiconductor layer 50 (optionally, the angle is 90°).

[0075] In an embodiment of the present application, the gate 20 of the display substrate is a closed structure; alternatively, the gate 20 is a non-closed structure, the gate 20 has an opening, and the open end of the gate 20 is connected to the signal transmission layer 30, so that the gate 20 and the signal transmission layer 30 cooperate to form a closed structure, so that the gate 20 itself can form a closed loop, or the gate 20 as a whole can form a closed loop with the signal transmission layer 30, thereby avoiding the gate 20 in a floating state, reducing the accumulation of static charge, preventing other defects caused by electrostatic damage, and improving product yield.

[0076] Moreover, in the embodiment of the present application, the signal transmission layer 30 is electrically connected to the gate 20 through at least two first through holes 41. Since the at least two first through holes 41 are arranged at intervals, at least two parallel circuits are formed between the signal transmission layer 30 and the gate 20, which effectively reduces the resistance of the first through holes 41, makes the voltage division of the first through holes 41 less, reduces the voltage loss of the gate, increases the gate voltage, ensures the high voltage of the gate, and reduces the occurrence rate of leakage-type bright spots.

[0077] The embodiments of the present application, without increasing the number of masks or process complexity, achieve self-closure of the gate 20 or formation of a closed loop between the gate 20 and the signal transmission layer 30 by improving the structure of the gate 20 or the signal transmission layer 30. This prevents the gate 20 from being in a floating state, reduces static charge accumulation, prevents other defects caused by electrostatic damage, and improves product yield. Furthermore, the gate 20 is electrically connected to the signal transmission layer 30 via at least two first through holes 41, effectively reducing gate voltage loss, increasing gate voltage, ensuring a high gate voltage, and reducing the incidence of leakage-type bright spots.

[0078] In the embodiment of the present application, the display substrate can be applied to a medium-sized OLED display device. The structure of the gate 20 and the signal transmission layer 30 can be applied to a 6T1C, 7T1C, or 8T1C pixel circuit on a display panel.

[0079] Based on the same inventive concept, an embodiment of the present application provides a display device, including the above-mentioned display substrate 100. Specifically, the display device can be a display device such as a smart phone, a tablet computer, a PC (Personal Computer), or a smart TV.

[0080] It should be noted that, since the display device of the embodiment of the present application includes the display substrate of the embodiment of the present application, the display device of the embodiment of the present application also has the above-mentioned beneficial effects of the display substrate of the embodiment of the present application, which will not be repeated here.

[0081] Based on the same inventive concept, the present invention provides a method for preparing a display substrate. The flow chart of the method is as follows: Figure 7 As shown, the method includes:

[0082] S101, providing a substrate 10, and forming a gate 20 of a thin film transistor on one side of the substrate 10;

[0083] S102 , forming a signal transmission layer 30 on a side of the gate 20 away from the substrate 10 .

[0084] The gate 20 is electrically connected to the signal transmission layer 30, which is used to connect to an external circuit. The gate 20 can be a closed structure, or it can be an open structure, with an opening connected to the signal transmission layer 30 at the open end, so that the gate 20 and the signal transmission layer 30 cooperate to form a closed structure.

[0085] A display substrate is prepared using the above method. A gate electrode 20 and a signal transmission layer 30 are both located on one side of a substrate 10, which supports the gate electrode 20 and the signal transmission layer 30. The gate electrode 20 is connected to an external circuit via the signal transmission layer 30. The external circuit can provide an operating voltage or current to the gate electrode 20 through the signal transmission layer 30 to control the thin film transistor.

[0086] The gate 20 prepared by the above method is a closed structure. When an operating voltage or an operating current is provided to the gate 20 through the signal transmission layer 30, the gate 20 itself can form a closed loop; or the prepared gate 20 is a non-closed structure with an opening. By connecting the open end of the gate 20 to the signal transmission layer, the gate 20 and the signal transmission layer 30 cooperate to form a closed structure. When an operating voltage or an operating current is provided to the gate 20 through the signal transmission layer 30, the gate 20 as a whole can form a closed loop with the signal transmission layer 30. In the embodiment of the present application, the gate 20 itself can form a closed loop, or the gate 20 as a whole can form a closed loop with the signal transmission layer 30, thereby avoiding the gate 20 being in a floating state, reducing the accumulation of static charge, preventing other defects caused by electrostatic damage, and improving product yield.

[0087] Optionally, the preparation method of the embodiment of the present application further includes: forming a conductive layer on one side of the substrate 10; patterning the conductive layer by a composition process to form a semiconductor layer 50. The semiconductor layer 50 (such as Figure 8 shown).

[0088] Optionally, the preparation method of the embodiment of the present application further includes: forming an insulating film layer on one side of the substrate 10; patterning the insulating film layer by a composition process to form a second insulating layer 60; the second insulating layer 60 is located between the semiconductor layer 50 and the gate 20, and the second insulating layer 60 covers the semiconductor layer 50. The second insulating layer 60 is formed on the side of the semiconductor layer 50 away from the substrate 10 by the above method (such as Figure 8 shown).

[0089] In an optional embodiment, the method for preparing the display substrate further includes fabricating structures such as an active layer and / or a gate insulating layer of a thin film transistor. It should be noted that in the embodiments of the present application, the fabrication methods for fabricating structures such as an active layer and / or a gate insulating layer of a thin film transistor are similar to those in the prior art and will not be further described herein.

[0090] It should be noted that, in the embodiment of the present application, the manufacturing method of the semiconductor layer 50 and the second insulating layer 60 is similar to that in the prior art, and will not be described in detail here.

[0091] Optionally, in the embodiment of the present application, the gate 20 is formed on a side of the second insulating layer 60 away from the substrate 10 .

[0092] Optionally, in the embodiment of the present application, the gate 20 of the thin film transistor is formed on one side of the substrate 10, including: forming a metal film layer on one side of the substrate 10, and patterning the metal film layer through a composition process to form the gate 20. The gate 20 (such as Figure 9 shown).

[0093] Optionally, in an embodiment of the present application, before forming the signal transmission layer 30 on the side of the gate 20 away from the substrate 10, the method for preparing the display substrate also includes: forming a first insulating layer 40 on one side of the substrate 10 through a composition process, the first insulating layer 40 covering the gate 20, and the first insulating layer 40 is provided with at least two first through holes 41 to expose the gate 20.

[0094] Specifically, in an optional embodiment, the manufacturing of the first insulating layer 40 includes: manufacturing an insulating film layer on one side of the substrate 10, and patterning the insulating film layer through a composition process to form the first insulating layer 40 (such as Figure 9 As shown in FIG, a first insulating layer 40 covers the gate 20, and the first insulating layer 40 is provided with at least two first through holes 41 to expose the gate 20. The first insulating layer 40 is formed by the above-mentioned method.

[0095] Optionally, in the embodiment of the present application, before forming the signal transmission layer 30 on the side of the gate 20 away from the substrate 10, the method for preparing the display substrate further includes: forming a flat film layer on one side of the substrate 10; patterning the flat film layer by a composition process to form a flat layer 70; the flat layer 70 is located between the first insulating layer 40 and the signal transmission layer 30, and the flat layer 70 covers the first insulating layer 40, and the flat layer 70 is provided with at least two second through holes, and the at least two second through holes correspond to the at least two first through holes 41 one by one to expose the gate 20. The flat layer 70 (such as Figure 10 shown).

[0096] Optionally, in the embodiment of the present application, the signal transmission layer 30 is formed on the side of the gate 20 away from the substrate 10, including: forming an electric transmission film layer on one side of the substrate 10, and patterning the electric transmission film layer through a composition process to form the signal transmission layer 30. The signal transmission layer 30 (such as Figure 11 During the formation process, the electric transmission film layer is deposited into at least two second through holes and at least two first through holes 41 , thereby achieving the purpose of electrically connecting the signal transmission layer 30 to the gate 20 through the second through holes and the first through holes 41 .

[0097] In the embodiment of the present application, the corresponding gate 20 , first insulating layer 40 , planarization layer 70 and signal transmission layer 30 can be manufactured according to actual needs.

[0098] In a specific embodiment, Figure 1 and Figure 3 As shown, in the embodiment of the present application, the signal transmission layer 30 includes a first transmission line 31 and at least one second transmission line 32, the first transmission line 31 is used to connect to an external circuit, and one end of each second transmission line 32 is connected to the first transmission line 31; the first transmission line 31 is connected to the gate 20, and the end of the second transmission line 32 away from the first transmission line 31 is connected to the open end of the gate 20, and the orthographic projection of the connection point between the first transmission line 31 and the gate 20 on the substrate 10 does not overlap with the orthographic projection of the connection point between the second transmission line 32 and the gate 20 on the substrate 10.

[0099] Specifically, in an optional embodiment, as Figure 1As shown, the gate 20 is U-shaped and includes a first gate segment 21, a second gate segment 22 and a third gate segment 23. The second gate segment 22 is connected to one end of the first gate segment 21 and is arranged at an angle to the first gate segment 21. The third gate segment 23 is connected to the other end of the first gate segment 21 and is arranged at an angle to the first gate segment 21. A first transmission line 31 is connected to the first gate segment 21. There are two second transmission lines 32, one of which is connected to an end of the second gate segment 22 away from the first gate segment 21, and the other is connected to an end of the third gate segment 23 away from the first gate segment 21.

[0100] Specifically, in another optional embodiment, as Figure 3 As shown, the gate 20 is "L"-shaped, including a first gate segment 21 and a second gate segment 22 connected to each other. The first gate segment 21 and the second gate segment 22 are arranged at an angle. The end of the first gate segment 21 away from the second gate segment 22 is connected to the first transmission line 31, and the end of the second gate segment 22 away from the first gate segment 21 is connected to the second transmission line 32.

[0101] In another specific embodiment, Figure 4 As shown, in the embodiment of the present application, the gate 20 is a "mouth"-shaped structure, and the signal transmission layer 30 includes a first transmission line 31, which is used to connect to an external circuit; both sides of the gate 20 are connected to the first transmission line 31.

[0102] In another specific embodiment, Figure 5 and Figure 6 As shown, in the embodiment of the present application, the gate 20 is "U"-shaped, including a first gate segment 21, a second gate segment 22 and a third gate segment 23 connected in sequence, the first gate segment 21 and the second gate segment 22 are arranged at an angle, and the third gate segment 23 and the second gate segment 22 are arranged at an angle; the signal transmission layer 30 includes a first transmission line 31, and the first transmission line 31 is used to connect to an external circuit; the end of the first gate segment 21 away from the second gate segment 22 is connected to the first transmission line 31, and the end of the third gate segment 23 away from the second gate segment 22 is connected to the first transmission line 31.

[0103] It should be noted that the preparation method of the display substrate of the embodiment of the present application can be used to prepare a display substrate (for example, used to prepare the display substrate of the embodiment of the present application), and the prepared display substrate has the above-mentioned beneficial effects of the display substrate of the embodiment of the present application, which will not be repeated here.

[0104] The following describes in detail the method for preparing the display substrate in the embodiment of the present application with reference to a specific embodiment.

[0105] When the embodiment of the present application is implemented, a substrate 10 is first provided, and then a bottom semiconductor layer 50 is formed on the substrate 10 through a patterning process. Figure 8 Then, a second insulating layer 60 is formed on the substrate 10 by a patterning process, and the second insulating layer 60 covers the semiconductor layer 50, as shown. Figure 8 Then, a gate 20 is formed on the substrate 10. The gate 20 is formed on the side of the second insulating layer 60 away from the substrate 10, as shown. Figure 9 Then a first insulating layer 40 is formed on one side of the substrate 10, and the first insulating layer 40 covers the gate 20, as shown Figure 9 As shown; then a flat layer 70 is formed on the substrate 10 by a patterning process, and the flat layer 70 covers the first insulating layer 40. The flat layer 70 is provided with at least two second through holes by the patterning process, and the first insulating layer 40 is provided with at least two first through holes 41. The at least two second through holes correspond to the at least two first through holes 41 one by one to expose the gate 20, as shown Figure 10 Finally, a signal transmission layer 30 is formed by a patterning process, and the signal transmission layer 30 is electrically connected to the gate 20 through the second through hole and the first through hole 41, as shown Figure 11 As shown; the display substrate is finally obtained.

[0106] It should be noted that the above patterning process includes the coating, exposure, development, etching of the photoresist and part or all of the processes of removing the photoresist.

[0107] By applying the embodiments of the present application, at least the following beneficial effects can be achieved:

[0108] In an embodiment of the present application, the gate is a closed structure. When an operating voltage or an operating current is provided to the gate through the signal transmission layer, the gate itself can form a closed loop; or the gate is a non-closed structure with an opening. By connecting the open end of the gate to the signal transmission layer, the gate and the signal transmission layer cooperate to form a closed structure. When an operating voltage or an operating current is provided to the gate through the signal transmission layer, the gate as a whole can form a closed loop with the signal transmission layer. In an embodiment of the present application, the gate itself can form a closed loop, or the gate as a whole can form a closed loop with the signal transmission layer, thereby avoiding the gate being in a floating state, reducing the accumulation of static charge, preventing other defects caused by electrostatic damage, and improving product yield.

[0109] Those skilled in the art will appreciate that the steps, measures, and schemes in the various operations, methods, and processes discussed in this application may be interchanged, modified, combined, or deleted. Furthermore, other steps, measures, and schemes in the various operations, methods, and processes discussed in this application may also be interchanged, modified, rearranged, decomposed, combined, or deleted. Furthermore, steps, measures, and schemes in the prior art that are similar to those disclosed in this application may also be interchanged, modified, rearranged, decomposed, combined, or deleted.

[0110] In the description of this application, the directions or positional relationships indicated by words such as "center", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", and "outside" are exemplary directions or positional relationships based on the accompanying drawings. They are intended to facilitate or simplify the description of the embodiments of this application, and do not indicate or imply that the device or component referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, they should not be understood as limitations on this application.

[0111] The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature specified as "first" or "second" may explicitly or implicitly include one or more of such features. Throughout this application, unless otherwise specified, "plurality" means two or more.

[0112] In the description of this application, it should be noted that, unless otherwise expressly specified or limited, the terms "mounted," "connected," and "connected" should be understood broadly. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to direct connections, indirect connections through an intermediate medium, or internal communication between two components. Those skilled in the art will understand the specific meanings of the above terms in this application based on the specific circumstances.

[0113] In the description of this specification, specific features, structures, materials or characteristics may be combined in an appropriate manner in any one or more embodiments or examples.

[0114] It should be understood that, although the various steps in the flowchart of the accompanying drawings are displayed in sequence as indicated by the arrows, the order of implementation of these steps is not limited to the order indicated by the arrows. Unless otherwise clearly stated herein, in some implementation scenarios of the embodiments of the present application, the steps in each process can be performed in other orders as required. Moreover, some or all of the steps in each flowchart may include multiple sub-steps or multiple stages based on actual implementation scenarios. Some or all of these sub-steps or stages may be executed at the same time, or may be executed at different times in different scenarios at the execution time. The execution order of these sub-steps or stages may be flexibly configured as required, and the embodiments of the present application do not limit this.

[0115] The above is only part of the implementation methods of the present application. It should be pointed out that for ordinary technicians in this technical field, without departing from the technical concept of the solution of the present application, other similar implementation methods based on the technical ideas of the present application also fall within the protection scope of the embodiments of the present application.

Claims

1. A display substrate, characterized in that: include: substrate; a thin film transistor, disposed on one side of the substrate, the thin film transistor including a gate; A signal transmission layer is located on a side of the gate away from the substrate, the gate is electrically connected to the signal transmission layer, and the signal transmission layer is used to connect to an external circuit; wherein: The gate is a closed structure, the gate is in a "mouth" shape, the signal transmission layer includes a first transmission line, the first transmission line is used to connect to an external circuit, and both sides of the "mouth" of the gate are connected to the first transmission line; or, the gate is a non-closed structure, the gate has an opening, and the open end of the gate is connected to the signal transmission layer, so that the gate and the signal transmission layer cooperate to form a closed structure.

2. The display substrate according to claim 1, wherein: The signal transmission layer includes a first transmission line and at least one second transmission line, the first transmission line is used to connect to an external circuit, and one end of each second transmission line is connected to the first transmission line; The first transmission line is connected to the gate, and an end of the second transmission line away from the first transmission line is connected to the open end of the gate, and an orthographic projection of a connection point between the first transmission line and the gate on the substrate does not overlap with an orthographic projection of a connection point between the second transmission line and the gate on the substrate.

3. The display substrate according to claim 2, wherein: The gate is L-shaped and includes a first gate segment and a second gate segment connected to each other, the first gate segment and the second gate segment are arranged at an angle, an end of the first gate segment away from the second gate segment is connected to the first transmission line, and an end of the second gate segment away from the first gate segment is connected to the second transmission line; or The gate is U-shaped and includes a first gate segment, a second gate segment, and a third gate segment. The second gate segment is connected to one end of the first gate segment and is arranged at an angle to the first gate segment. The third gate segment is connected to the other end of the first gate segment and is arranged at an angle to the first gate segment. The first transmission line is connected to the first gate segment. There are two second transmission lines, one of which is connected to an end of the second gate segment away from the first gate segment, and the other is connected to an end of the third gate segment away from the first gate segment.

4. The display substrate according to claim 1, wherein The gate is U-shaped and includes a first gate segment, a second gate segment, and a third gate segment connected in sequence, wherein the first gate segment and the second gate segment are arranged at an angle, and the third gate segment and the second gate segment are arranged at an angle; The signal transmission layer includes a first transmission line, and the first transmission line is used to connect to an external circuit; One end of the first gate segment away from the second gate segment is connected to the first transmission line, and one end of the third gate segment away from the second gate segment is connected to the first transmission line.

5. The display substrate according to any one of claims 1 to 4, characterized in that It also includes a first insulating layer, the first insulating layer is located between the gate and the signal transmission layer, and the first insulating layer covers the gate; The signal transmission layer is electrically connected to the gate through at least two first through holes penetrating the first insulating layer.

6. A display device, characterized in that: A display substrate comprising the display substrate according to any one of claims 1 to 5.

7. A method for preparing a display substrate, characterized in that: include: Providing a substrate, and manufacturing a gate of a thin film transistor on one side of the substrate; A signal transmission layer is formed on a side of the gate away from the substrate, the gate is electrically connected to the signal transmission layer, and the signal transmission layer is used to connect to an external circuit; The gate is a closed structure, the gate is in a "mouth" shape, the signal transmission layer includes a first transmission line, the first transmission line is used to connect to an external circuit, and both sides of the "mouth" of the gate are connected to the first transmission line; or, the gate is a non-closed structure, the gate has an opening, and the open end of the gate is connected to the signal transmission layer, so that the gate and the signal transmission layer cooperate to form a closed structure.

8. The method for preparing a display substrate according to claim 7, wherein: The method of manufacturing a gate of a thin film transistor on one side of the substrate comprises: forming a metal film layer on one side of the substrate, and patterning the metal film layer through a composition process to form the gate; The step of forming a signal transmission layer on a side of the gate away from the substrate comprises: An electric transmission film layer is manufactured on one side of the substrate, and the electric transmission film layer is patterned by a composition process to form the signal transmission layer.

9. The method for preparing a display substrate according to claim 7, wherein: Before forming a signal transmission layer on a side of the gate away from the substrate, the method further comprises: A first insulating layer is formed on one side of the substrate through a patterning process, wherein the first insulating layer covers the gate and is provided with at least two first through holes to expose the gate.

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