A semiconductor structure, a method for manufacturing a semiconductor structure, and a semiconductor device

Abstract

The present invention discloses a semiconductor structure, a method for manufacturing a semiconductor structure, and a semiconductor device. The structure includes a substrate provided with an active region and a shallow trench isolation region, wherein the upper surface of the shallow trench isolation region is lower than the upper surface of the active region; a stacked structure conformally covering the substrate; a first insulating layer covering the stacked structure is further provided on the shallow trench isolation region, a second insulating layer covering the first insulating layer, and a third insulating layer covering the second insulating layer; a first insulating layer covering the stacked structure is provided on the active region, and the upper surface of the first insulating layer and the upper surface of the third insulating layer are in the same plane. This structure can provide a semiconductor structure with a flat upper surface, and avoids the problem in the prior art that the first insulating layer on the active region is polished to be level with the first insulating layer on the shallow trench isolation region, which increases the risk of leakage and reduces the working stability of the semiconductor device.

Description

Technical Field

[0001] This application is a divisional application of the application with the application number CN202110691169.6 and the invention title "A Semiconductor Structure, a Method for Preparing a Semiconductor Structure, and a Semiconductor Device". Background Art

[0002] In the process of preparing an existing semiconductor structure, multiple planarization processes are usually required to provide a flat working surface for subsequent processes. For a substrate including a shallow trench isolation region and an active region, when planarizing the surface of the substrate, due to the different materials of the shallow trench isolation region and the active region, the upper surface of the shallow trench isolation region will be lower than the upper surface of the active region, so that a stacked structure and a masking layer will be conformally formed during subsequent deposition. In order to provide a flat working surface for subsequent processes, it is usually necessary to grind the masking layer located on the active region, so that the masking layer on the active region becomes thinner, greatly increasing the risk of leakage and reducing the working stability of semiconductor devices. Summary of the Invention

[0003] The technical problem to be solved by the present invention is: how to provide a semiconductor structure with a flat upper surface to reduce the risk of leakage and improve the stability of semiconductor devices.

[0004] To solve the above technical problem, the present invention provides a semiconductor structure, a method for preparing a semiconductor structure, and a semiconductor device.

[0005] In a first aspect of the present invention, a semiconductor structure is provided, which includes:

[0006] A substrate, the substrate includes an active region and a shallow trench isolation region, and the upper surface of the shallow trench isolation region is lower than the upper surface of the active region;

[0007] A stacked structure, the stacked structure conformally covers the substrate;

[0008] A first insulating layer, the first insulating layer conformally covers the stacked structure;

[0009] A second insulating layer, the second insulating layer covers the first insulating layer disposed on the shallow trench isolation region;

[0010] A third insulating layer, the third insulating layer is disposed on the second insulating layer, and the upper surface of the third insulating layer is in the same plane as the upper surface of the first insulating layer disposed on the active region.

[0011] In some embodiments, the materials of the first insulating layer, the second insulating layer, and the third insulating layer are different.

[0012] In some embodiments, the etching selectivity of the third insulating layer is greater than that of the first insulating layer and less than that of the second insulating layer.

[0013] In some embodiments, the stacked structure includes:

[0014] a dielectric layer that conformally covers the substrate;

[0015] a conductive layer disposed on the dielectric layer.

[0016] In some embodiments, the semiconductor structure further includes: an insulating spacer layer located on the sidewalls of the stacked structure and the first insulating layer, and the second insulating layer covers the insulating spacer layer.

[0017] A second aspect of the present invention provides a method for manufacturing a semiconductor structure, which includes:

[0018] providing a substrate, the substrate including an active region and a shallow trench isolation region, and the upper surface of the shallow trench isolation region is lower than the upper surface of the active region;

[0019] sequentially depositing a stacked structure, a first insulating layer, a second insulating layer, and a third insulating layer that conformally cover the substrate, and the thickness of the third insulating layer is greater than or equal to the thickness of the second insulating layer and the height difference between the second insulating layer on the active region and the second insulating layer on the shallow trench isolation region;

[0020] grinding the third insulating layer at a first grinding rate until the second insulating layer disposed on the active region is exposed;

[0021] grinding the second insulating layer at a second grinding rate to expose the first insulating layer disposed on the active region, wherein the first grinding rate is different from the second grinding rate;

[0022] continuing to grind the third insulating layer so that the upper surface of the third insulating layer is coplanar with the upper surface of the first insulating layer disposed on the active region.

[0023] In some embodiments, continuing to grind the third insulating layer so that the upper surface of the third insulating layer is coplanar with the upper surface of the first insulating layer disposed on the active region includes:

[0024] grinding the third insulating layer at a third grinding rate so that the upper surface of the third insulating layer is coplanar with the upper surface of the first insulating layer disposed on the active region, wherein the third grinding rate is the same as or different from the first grinding rate, and the third grinding rate is different from the second grinding rate.

[0025] In some embodiments, the third insulating layer is polished at the first polishing rate by using a first polishing liquid; the second insulating layer is polished at the second polishing rate by using a second polishing liquid, and the first polishing liquid is different from the second polishing liquid.

[0026] In some embodiments, after the first insulating layer disposed on the active region is exposed, the first insulating layer, the second insulating layer, and the third insulating layer are continuously polished at a fourth polishing rate until the first insulating layer on the active region meets a preset thickness.

[0027] In some embodiments, the first insulating layer, the second insulating layer, and the third insulating layer are continuously polished at the fourth polishing rate by using a fourth polishing liquid.

[0028] In some embodiments, the materials of the first insulating layer, the second insulating layer, and the third insulating layer are different.

[0029] In some embodiments, the etch selectivity of the third insulating layer is greater than the etch selectivity of the first insulating layer and less than the etch selectivity of the second insulating layer.

[0030] In some embodiments, the stacked structure in which the deposition conformally covers the substrate includes: a dielectric layer and a conductive layer that are sequentially deposited to conformally cover the substrate.

[0031] In a third aspect of the present invention, a semiconductor device is provided, which includes the semiconductor structure described in any one of the above.

[0032] Compared with the prior art, one or more of the above embodiments may have the following advantages or beneficial effects:

[0033] Applying the semiconductor structure provided by the present invention, the structure includes a substrate provided with an active region and a shallow trench isolation region, wherein the upper surface of the shallow trench isolation region is lower than the upper surface of the active region; a stacked structure that conformally covers the substrate; a first insulating layer covering the stacked structure is further provided on the shallow trench isolation region, a second insulating layer covering the first insulating layer, and a third insulating layer covering the second insulating layer; a first insulating layer covering the stacked structure is provided on the active region, and the upper surface of the first insulating layer and the upper surface of the third insulating layer are in the same plane. This structure can provide a semiconductor structure with a flat upper surface, and avoids the problem in the prior art of polishing the first insulating layer on the active region to be level with the first insulating layer on the shallow trench isolation region to achieve planarization, which increases the risk of leakage and reduces the working stability of semiconductor devices. Description of the Drawings

[0034] The scope of the present disclosure can be better understood by reading the following detailed description of exemplary embodiments in conjunction with the accompanying drawings. The accompanying drawings included are:

[0035] Figure 1 A schematic cross-sectional structure diagram of a semiconductor structure provided by an embodiment of the present invention is shown;

[0036] Figure 2 A schematic cross-sectional structure diagram of another semiconductor structure provided by an embodiment of the present invention is shown;

[0037] Figure 3 A schematic flow diagram of a method for fabricating a semiconductor structure provided by an embodiment of the present invention is shown;

[0038] Figure 4 A schematic flow diagram of another method for fabricating a semiconductor structure provided by an embodiment of the present invention is shown;

[0039] Figures 5 to 9 A schematic cross-sectional structure diagram corresponding to each step in the method for fabricating a semiconductor structure provided by an embodiment of the present invention is shown. Detailed Embodiments

[0040] To make the objectives, technical solutions, and advantages of the present invention clearer, the following will describe in detail the implementation methods of the present invention in conjunction with the accompanying drawings and embodiments, so as to fully understand how the present invention applies technical means to solve technical problems and achieve the realization process of technical effects and implement accordingly.

[0041] In the process of fabricating existing semiconductor structures, multiple planarization processes are usually required to provide a flat working surface for subsequent processes. For a substrate including a shallow trench isolation region and an active region, when planarizing the surface of the substrate, due to the different materials of the shallow trench isolation region and the active region, the upper surface of the shallow trench isolation region will be lower than the upper surface of the active region, and thus a stacked structure and a masking layer will be conformally formed during subsequent deposition. In order to provide a flat working surface for subsequent processes, it is usually necessary to grind the masking layer located on the active region, thereby thinning the masking layer on the active region, greatly increasing the risk of leakage current, and reducing the working stability of semiconductor devices.

[0042] In view of this, the present invention provides a semiconductor structure, which includes a substrate provided with an active region and a shallow trench isolation region, wherein the upper surface of the shallow trench isolation region is lower than the upper surface of the active region; a stacked structure conformally covering the substrate; a first insulating layer covering the stacked structure on the shallow trench isolation region, a second insulating layer covering the first insulating layer, and a third insulating layer covering the second insulating layer; a first insulating layer covering the stacked structure on the active region, and the upper surface of the first insulating layer and the upper surface of the third insulating layer are in the same plane. This structure can provide a semiconductor structure with a flat upper surface, and avoids the problem in the prior art that the first insulating layer on the active region is polished to be level with the first insulating layer on the shallow trench isolation region, which increases the risk of leakage and reduces the working stability of semiconductor devices.

[0043] Embodiment 1

[0044] See Figure 1 as shown Figure 1 shows a schematic diagram of a semiconductor structure provided by an embodiment of the present invention, which includes:

[0045] A substrate 10, the substrate 10 includes a shallow trench isolation region 101 and an active region 102, and the upper surface of the shallow trench isolation region 101 is lower than the upper surface of the active region 102;

[0046] A stacked structure 11, the stacked structure 11 conformally covers the substrate 10;

[0047] A first insulating layer 12, the first insulating layer 12 conformally covers the stacked structure 11;

[0048] A second insulating layer 13, the second insulating layer 13 covers the first insulating layer 12 provided on the shallow trench isolation region 101;

[0049] A third insulating layer 14, the third insulating layer 14 is provided on the second insulating layer 13, and the upper surface of the third insulating layer 14 and the upper surface of the first insulating layer 12 provided on the active region 102 are in the same plane.

[0050] In some embodiments, the substrate 10 may include a silicon substrate, a silicon-on-insulator (SOI) substrate, a germanium substrate, a silicon-germanium substrate, etc.

[0051] According to requirements, a stacked structure 11 may also be deposited on the substrate 10. Among them, the stacked structure 11 may include a dielectric layer conformally covering the substrate 10 and a conductive layer provided on the dielectric layer. Both the dielectric layer and the conductive layer are conformal with the substrate 10, that is, the stacked structure 11 conformally covering the substrate 10 also shows that the upper surface of the stacked structure 11 located on the shallow trench isolation region 101 is lower than the upper surface of the stacked structure 11 located on the active region 102.

[0052] In some embodiments, the dielectric layer may include a silicon oxide layer or a silicon nitride layer, and the conductive layer may include a polysilicon layer.

[0053] In some embodiments, the first insulating layer 12 conformally covers the stacked structure 11, and the upper surface of the first insulating layer 12 located on the shallow trench isolation region 101 is lower than the upper surface of the first insulating layer 12 located on the active region 102. As an example, the first insulating layer 12 may include a silicon nitride layer or a silicon oxynitride layer.

[0054] On the shallow trench isolation region 101, a second insulating layer 13 conformal to the first insulating layer 12 and a third insulating layer 14 with a substantially horizontal upper surface are sequentially provided. In some embodiments, the materials of the first insulating layer 12, the second insulating layer 13, and the third insulating layer 14 are different. Under the same grinding conditions, the first insulating layer 12, the second insulating layer 13, and the third insulating layer 14 may have different etching resistances. In some embodiments, the etching selectivity of the third insulating layer 14 may be greater than the etching selectivity of the first insulating layer 12 and less than the etching selectivity of the second insulating layer 13.

[0055] In some embodiments, the thickness of the second insulating layer 13 may be less than the thickness of the third insulating layer 14 and / or the first insulating layer 12. To improve the convenience of subsequent etching, a thin second insulating layer 13 may also be provided, such that the thickness of the second insulating layer 13 is much less than the thickness of the third insulating layer 14 or much less than the height difference between the first insulating layer 12 on the active region 102 and the first insulating layer 12 on the shallow trench isolation region 101.

[0056] In the embodiments of the present invention, the upper surface of the third insulating layer 14 is in the same plane as the upper surface of the first insulating layer 12 provided on the active region 102. On the basis of ensuring that a sufficient thickness of the masking layer is provided for the conductive layer to avoid leakage, a stacked structure formed by the second insulating layer 13 and the third insulating layer 14 is provided on the first insulating layer 12 in the shallow trench isolation region 101, forming a semiconductor structure with a flat upper surface, which is beneficial to facilitating subsequent processes and improving the performance of semiconductor devices.

[0057] In other embodiments, see Figure 2 as shown Figure 2FIG. 0 shows a schematic cross-sectional structure of another semiconductor structure provided by an embodiment of the present invention. The semiconductor structure may further include: an insulating spacer layer 15 located on the sidewalls of the stacked structure 11 and the first insulating layer 12, and a second insulating layer 13 covering the insulating spacer layer 15. That is, in the embodiment of the present invention, a gate structure may also be prepared by providing a stacked structure 11, a first insulating layer 12, and an insulating spacer layer 15, and then a second insulating layer 13 and a third insulating layer 14 covering the gate structure are provided. Among them, the insulating spacer layer 15 may be disposed on the upper surface of the shallow trench isolation region 101, and the insulating spacer layer 15 may be prepared from materials such as silicon nitride.

[0058] The above is a semiconductor structure provided by an embodiment of the present invention. The structure includes a substrate 10 provided with an active region 102 and a shallow trench isolation region 101, wherein the upper surface of the shallow trench isolation region 101 is lower than the upper surface of the active region 102; a stacked structure 11 conformally covering the substrate 10; a first insulating layer 12 covering the stacked structure 11 on the shallow trench isolation region 101, a second insulating layer 13 covering the first insulating layer 12, and a third insulating layer 14 covering the second insulating layer 13; a first insulating layer 12 covering the stacked structure 11 on the active region, and the upper surface of the first insulating layer 12 and the upper surface of the third insulating layer 14 are in the same plane. This structure can provide a semiconductor structure with a flat upper surface, and avoids the problem in the prior art that the first insulating layer 12 on the active region 102 is polished to be horizontal with the first insulating layer 12 on the shallow trench isolation region 101, which increases the risk of leakage and reduces the working stability of the semiconductor device.

[0059] The above is a semiconductor structure provided by an embodiment of the present invention. The present invention also provides a method for manufacturing a semiconductor structure. For details, please refer to the description of Embodiment 2.

[0060] Embodiment 2

[0061] See Figure 3 as shown in Figure 3 FIG. 16 shows a schematic flow chart of a method for manufacturing a semiconductor structure provided by an embodiment of the present invention, which may include:

[0062] Step S101: Provide a substrate including an active region and a shallow trench isolation region, and the upper surface of the shallow trench isolation region is lower than the upper surface of the active region.

[0063] Step S102: Sequentially deposit a stacked structure, a first insulating layer, a second insulating layer, and a third insulating layer conformally covering the substrate. The thickness of the third insulating layer is greater than or equal to the thickness of the second insulating layer and the height difference between the second insulating layer on the active region and the second insulating layer on the shallow trench isolation region.

[0064] Step S103: Grind the third insulating layer at a first grinding rate until the second insulating layer disposed on the active region is exposed.

[0065] Step S104: Grind the second insulating layer at a second grinding rate to expose the first insulating layer disposed on the active region, where the first grinding rate is different from the second grinding rate.

[0066] Step S105: Continue to grind the third insulating layer so that the upper surface of the third insulating layer is in the same plane as the upper surface of the first insulating layer disposed on the active region.

[0067] In the embodiment of the present invention, the grinding rate can be controlled by selecting different materials as the insulating layer and / or selecting different grinding fluids. Finally, based on the regulation of the grinding rate, the height between the upper surface of the semiconductor structure located on the shallow trench isolation region and the upper surface located on the active region is adjusted.

[0068] As an example, when grinding the third insulating layer at a first grinding rate with a first grinding fluid until the second insulating layer is exposed, the upper surface of the currently remaining third insulating layer can be higher than the upper surface of the first insulating layer in the active region and lower than the upper surface of the exposed second insulating layer; further, the second insulating layer can be ground at a second grinding rate with a second grinding fluid, while still grinding the third insulating layer at the first grinding rate, and making the second grinding rate greater than the first grinding rate, until the first insulating layer is exposed and the upper surface of the third insulating layer and the upper surface of the first insulating layer disposed on the active region are in the same plane. In some other embodiments, when the second insulating layer is exposed, the third insulating layer can also be continuously ground at a third grinding rate, and the third grinding rate can be different from the first grinding rate, so that the upper surface of the third insulating layer is in the same plane as the upper surface of the first insulating layer disposed on the active region. Among them, the third grinding rate can be achieved by selecting a suitable third grinding fluid.

[0069] In other embodiments, the grinding rate can also be selected based on the upper surface topography corresponding to when the second insulating layer is exposed to achieve the regulation of the height. For specific details, please refer to the following description.

[0070] See Figure 4 as shown Figure 4 shows a schematic flow chart of a method for manufacturing a semiconductor structure provided by an embodiment of the present invention, which includes:

[0071] Step S201: Provide a substrate 20, where the substrate 20 includes a shallow trench isolation region 201 and an active region 202, and the upper surface of the shallow trench isolation region 201 is lower than the upper surface of the active region 202;

[0072] Step S202: Sequentially deposit a conformal stack structure 21 covering the substrate 20, a first insulating layer 22, a second insulating layer 23, and a third insulating layer 24. The thickness of the third insulating layer 24 is greater than or equal to the thickness of the second insulating layer 23 and the height difference between the second insulating layer 23 on the active region 202 and the second insulating layer 23 on the shallow trench isolation region 201.

[0073] Step S203: Grind the third insulating layer 24 at a first grinding rate to expose the second insulating layer 23 disposed on the active region 202 and make the upper surface of the third insulating layer 24 after etching level with the upper surface of the second insulating layer 23.

[0074] Step S204: Grind the exposed second insulating layer 23 at a second grinding rate to expose the first insulating layer 22 disposed on the active region 202, where the first grinding rate is less than the second grinding rate; and,

[0075] Step S205: Continue to grind the third insulating layer 24 at a third grinding rate so that the upper surface of the third insulating layer 24 is in the same plane as the upper surface of the first insulating layer 22 disposed on the active region 202.

[0076] In an embodiment of the present invention, the substrate 20 may include a silicon substrate, a silicon-on-insulator (SOI) substrate, a germanium substrate, a silicon-germanium substrate, etc. Since the materials of the active region 202 and the shallow trench isolation region 201 in the substrate 20 are different, unevenness will occur on the upper surface of the substrate 20 in the shallow trench isolation region 201 and the active region 202 during the preparation process, and the upper surface of the shallow trench isolation region 201 is lower than the upper surface of the active region 202. For details, please refer to Figure 5 as shown.

[0077] In an embodiment of the present invention, step S202 may specifically be to sequentially deposit a conformal stack structure 21 covering the substrate 20, a first insulating layer 22, a second insulating layer 23, and a third insulating layer 24 by using a chemical vapor deposition process or a physical vapor deposition process.

[0078] Among them, refer to Figure 6As shown, the stacked structure 21, the first insulating layer 22, the second insulating layer 23, and the third insulating layer 24 are conformal to the substrate 20, and the upper surface of the third insulating layer 24 on the shallow trench isolation region 201 is lower than the upper surface of the third insulating layer 24 on the active region 202. In some embodiments, the thickness of the third insulating layer 24 may be set to be greater than or equal to the thickness of the second insulating layer 23 and the height difference between the second insulating layer 23 located on the active region 202 and the second insulating layer 23 located on the shallow trench isolation region 201, so as to ensure that when the height is adjusted by a subsequent grinding process, the upper surface of the third insulating layer 24 on the shallow trench isolation region 201 is higher than the upper surface of the first insulating layer 22 exposed on the active region 202. Among them, the materials of the first insulating layer 22, the second insulating layer 23, and the third insulating layer 24 are different.

[0079] In some embodiments, the stacked structure 21 may include a dielectric layer 211 and a conductive layer 212. The stacked structure 21 deposited conformally covering the substrate 20 may be: by using a physical vapor deposition process or a chemical vapor deposition process, the dielectric layer 211 and the conductive layer 212 are sequentially deposited conformally covering the substrate 20. Among them, the dielectric layer 211 may include a silicon oxide layer or a silicon nitride layer, and the conductive layer 212 may include a polysilicon layer.

[0080] In some embodiments, step S203 may specifically be to use a first abrasive liquid to grind the third insulating layer 24 at a first grinding rate until the upper surface of the second insulating layer 23 on the active region 202 is exposed and the upper surface of the remaining third insulating layer 24 is substantially horizontal, and then the etching stops. The schematic cross-sectional structure diagram after etching is as Figure 7 shown.

[0081] Among them, in step S202, the third insulating layer 24 conformal to the substrate 20 is deposited, showing that the upper surface of the third insulating layer 24 on the shallow trench isolation region 201 is lower than the upper surface of the third insulating layer 24 on the active region 202. When performing step S203, a dry etching process or a wet etching process combined with a grinding process may also be used to remove part of the third insulating layer 24. As an example, part of the third insulating layer 24 may be removed by a dry etching process or a wet etching process first, and then the grinding process is used to form a third insulating layer 24 with a horizontal upper surface and expose the upper surface of the second insulating layer 23 located on the active region 202.

[0082] In some embodiments, the polishing rate of etching can be adjusted by selecting insulating layers with different etching selectivity ratios. When the materials of the first insulating layer 22, the second insulating layer 23, and the third insulating layer 24 are different, the etching selectivity of the third insulating layer 24 can be selected to be less than that of the second insulating layer 23. Step S204 and step S205 can be specifically that, under the same polishing conditions, the third insulating layer 24 is polished at a third polishing rate and at the same time the exposed second insulating layer 23 is polished at a second polishing rate until the first insulating layer 22 disposed on the active region 202 is exposed.

[0083] Due to the different etching selectivity ratios of the third insulating layer 24 and the second insulating layer 23, by polishing under the same polishing conditions, that is, the third polishing rate is less than the second polishing rate. When polishing until the first insulating layer 22 disposed on the active region 202 is exposed, the upper surface of the third insulating layer 24 located on the shallow trench isolation region 201 is higher than the upper surface of the first insulating layer 22. For details, reference can be made to Figure 8 the figure shown. Thus, the control of the polishing rate is achieved based on the difference between the etching selectivity of the third insulating layer 24 and the second insulating layer 23, which is further beneficial to adjusting the height between the third insulating layer 24 and the second insulating layer 23 after polishing.

[0084] In other embodiments, the polishing rate of etching can also be adjusted by selecting different etching conditions. Step S204 can be specifically that different polishing liquids are used to polish the third insulating layer 24 at a third polishing rate and the exposed second insulating layer 23 at a second polishing rate until the first insulating layer 22 disposed on the active region 202 is exposed.

[0085] By using different polishing liquids, the third polishing rate during the polishing of the third insulating layer 24 and the second insulating layer 23 is less than the second polishing rate. When polishing until the first insulating layer 22 disposed on the active region 202 is exposed, the upper surface of the third insulating layer 24 located on the shallow trench isolation region 201 is higher than the upper surface of the first insulating layer 22. Thus, the control of the polishing rate is achieved by using different polishing liquids, which is further beneficial to adjusting the height between the third insulating layer 24 and the second insulating layer 23 after polishing.

[0086] In some embodiments, step S205 can be specifically that, under the same polishing conditions, the third insulating layer 24 is continuously polished at a third polishing rate so that the upper surface of the third insulating layer 24 is in the same plane as the upper surface of the first insulating layer 22 disposed on the active region 202. For details, reference can be made to Figure 9 the figure shown.

[0087] Among them, the etching selectivity of the third insulating layer 24 is greater than that of the first insulating layer 22. By polishing under the same polishing conditions, it is beneficial to provide a semiconductor structure with a flat upper surface without significantly thinning the first insulating layer 22. In addition, by ensuring the layer thickness of the first insulating layer 22, the isolation effect on leakage can be effectively guaranteed, which is beneficial to improving the working stability of semiconductor devices.

[0088] In some other embodiments, step S205 may specifically be to continue polishing the third insulating layer 24 at a third polishing rate by using a third polishing liquid, so that the upper surface of the third insulating layer 24 is in the same plane as the upper surface of the first insulating layer 22 provided on the active region 202.

[0089] By using different polishing liquids, the third polishing rate when polishing the third insulating layer 24 and the first insulating layer 22 is less than the second polishing rate. By extending the polishing time, the height difference between the upper surface of the third insulating layer 24 and the exposed upper surface of the first insulating layer 22 can be eliminated to achieve planarization. Thus, by using different polishing liquids, the control of the polishing rate is realized, which is further beneficial to adjusting the height between the third insulating layer 24 and the first insulating layer 22 after polishing.

[0090] In other embodiments, it is also possible to further polish the first insulating layer 22, the second insulating layer 23, and the third insulating layer 24 at a fourth polishing rate by using a fourth polishing liquid until the first insulating layer 22 located on the active region meets the preset layer thickness.

[0091] It should be noted that the third polishing rate may be equal to the first polishing rate. Among them, the selection of the polishing rate during the polishing process can be adjusted based on polishing requirements such as the height difference of the insulating layer.

[0092] The above is a method for fabricating a semiconductor structure provided by an embodiment of the present invention. By providing a substrate 20 having an active region 202 and a shallow trench isolation region 201, wherein the upper surface of the shallow trench isolation region 201 is lower than the upper surface of the active region 202; sequentially depositing a stacked structure 21, a first insulating layer 22, a second insulating layer 23, and a third insulating layer 24 that conformally cover the substrate 20, the thickness of the third insulating layer 24 is greater than or equal to the thickness of the second insulating layer 23 and the height difference between the second insulating layer 23 located on the active region 202 and the second insulating layer 23 located on the shallow trench isolation region 201; grinding the third insulating layer 24 at a first grinding rate to expose the second insulating layer 23 provided on the active region 202; grinding the exposed second insulating layer 23 at a second grinding rate to expose the first insulating layer 22 provided on the active region 202, wherein the first grinding rate is different from the second grinding rate, and grinding the third insulating layer 24 continuously at a third grinding rate so that the upper surface of the third insulating layer 24 is in the same plane as the upper surface of the first insulating layer 22 provided on the active region 202. This method realizes the adjustment of the height difference of the insulating layers located on the active region 202 and the shallow trench isolation region 201 by providing the second insulating layer 23 and the third insulating layer 24 on the first insulating layer 22 and controlling the grinding rate based on the difference in etching selectivity between different insulating layers or by using different grinding conditions, which is beneficial to providing a semiconductor structure with a flat upper surface without significantly thinning the first insulating layer 22. In addition, by ensuring the layer thickness of the first insulating layer 22, the isolation effect on leakage can be effectively ensured, which is beneficial to improving the working stability of semiconductor devices.

[0093] Another aspect of the present invention also provides a semiconductor device, which may include the semiconductor structure described in the above Embodiment 1.

[0094] Although the disclosed embodiments of the present invention are as above, the above content is only an embodiment for facilitating the understanding of the present invention and is not used to limit the present invention. Any person skilled in the art within the technical field to which the present invention pertains can make any modifications and changes in the form of implementation and details without departing from the spirit and scope disclosed by the present invention. However, the protection scope of the present invention shall still be subject to the scope defined by the appended claims.

Claims

1. A semiconductor structure, characterized in that, Comprising: A substrate, the substrate including an active region and a shallow trench isolation region, and in the shallow trench isolation region, there is an upper surface lower than the upper surface of the active region; A first insulating layer, the first insulating layer covering the active region and the shallow trench isolation region; A second insulating layer, the second insulating layer covering the first insulating layer disposed on the shallow trench isolation region, and the second insulating layer contacting the first insulating layer in the shallow trench isolation region; A third insulating layer, the third insulating layer disposed on the second insulating layer, and the upper surface of the third insulating layer being in the same plane as the upper surface of the first insulating layer disposed on the active region.

2. The semiconductor structure according to claim 1, characterized in that, The upper surface of the third insulating layer is in the same plane as the upper surface of the second insulating layer.

3. The semiconductor structure according to claim 1, characterized in that, The end point of the second insulating layer overlaps with the shallow trench isolation region in the position of the orthographic projection.

4. The semiconductor structure according to claim 1, characterized in that, The materials of the first insulating layer, the second insulating layer, and the third insulating layer are different.

5. The semiconductor structure according to claim 4, characterized in that, The etching selectivity of the third insulating layer is greater than the etching selectivity of the first insulating layer and less than the etching selectivity of the second insulating layer.

6. The semiconductor structure according to claim 1, characterized in that, The semiconductor structure further includes a stacked structure, the stacked structure including: A dielectric layer, the dielectric layer conformally covering the substrate; A conductive layer, the conductive layer disposed on the dielectric layer.

7. The semiconductor structure according to claim 1, characterized in that, The semiconductor structure further includes: an insulating spacer layer, the insulating spacer layer contacting the sidewall of the first insulating layer, and the second insulating layer completely covering the insulating spacer layer.

8. The semiconductor structure according to claim 7, characterized in that, The third insulating layer covers the second insulating layer and the insulating spacer layer.

9. A method for manufacturing a semiconductor structure, characterized in that, Comprising: Providing a substrate, the substrate including an active region and a shallow trench isolation region, and in the shallow trench isolation region, there is an upper surface lower than the upper surface of the active region; Sequentially depositing a first insulating layer, a second insulating layer, and a third insulating layer that conformally cover the substrate, the thickness of the third insulating layer being greater than or equal to the thickness of the second insulating layer and the height difference between the second insulating layer located on the active region and the second insulating layer located on the shallow trench isolation region; Grinding the third insulating layer at a first grinding rate until the second insulating layer disposed on the active region is exposed; Grinding the second insulating layer at a second grinding rate to expose the first insulating layer disposed on the active region, wherein the first grinding rate is different from the second grinding rate; Continuing to grind the third insulating layer to make the upper surface of the third insulating layer be in the same plane as the upper surface of the first insulating layer disposed on the active region.

10. The method according to claim 9, characterized in that, Continuing to grind the third insulating layer to make the upper surface of the third insulating layer be in the same plane as the upper surface of the first insulating layer disposed on the active region, including: Grinding the third insulating layer at a third grinding rate to make the upper surface of the third insulating layer be in the same plane as the upper surface of the first insulating layer disposed on the active region, wherein the third grinding rate is the same as or different from the first grinding rate, and the third grinding rate is different from the second grinding rate.

11. The method according to claim 9, characterized in that, The third insulating layer is polished at the first polishing rate by using a first polishing liquid; the second insulating layer is polished at the second polishing rate by using a second polishing liquid, and the first polishing liquid is different from the second polishing liquid.

12. The method according to claim 11, characterized in that, After the first insulating layer disposed on the active region is exposed, the first insulating layer, the second insulating layer, and the third insulating layer are continuously polished at a fourth polishing rate until the first insulating layer on the active region meets a preset thickness.

13. The method according to claim 12, characterized in that, The first insulating layer, the second insulating layer, and the third insulating layer are continuously polished at the fourth polishing rate by using a fourth polishing liquid.

14. The method according to claim 9, characterized in that, The materials of the first insulating layer, the second insulating layer, and the third insulating layer are different.

15. The method according to claim 14, wherein, The etching selectivity of the third insulating layer is greater than that of the first insulating layer and less than that of the second insulating layer.

16. The method according to claim 9, wherein, Before sequentially depositing the first insulating layer, the second insulating layer, and the third insulating layer conformally covering the substrate, it further includes: Depositing a stacked structure conformally covering the substrate, where the stacked structure includes a dielectric layer and a conductive layer sequentially deposited conformally covering the substrate.

17. A semiconductor device, wherein, A semiconductor structure including any one of the semiconductor structures according to claims 1 to 8 above.

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