Semiconductor epitaxial structure and method of making the same

Abstract

The application discloses a semiconductor epitaxial structure and a preparation method thereof. The semiconductor epitaxial structure comprises a high-quality epitaxial layer arranged on a substrate, which comprises an epitaxial restriction layer and a second epitaxial growth layer arranged thereon, the epitaxial restriction layer comprises an outer restriction unit, inner intermittent units and a first epitaxial growth layer, the outer restriction unit surrounds the inner intermittent units and the first epitaxial growth layer in a closed manner, the inner intermittent units are arranged at intervals, and the first epitaxial growth layer is arranged in the regions between the outer restriction unit and the inner intermittent units and between adjacent inner intermittent units. By arranging discontinuous intermittent intervals in the inner intermittent units, the high dislocation between the substrate and the epitaxial layer in the growth process is turned multiple times at the intermittent interval positions by the epitaxial restriction layer, so that the dislocation is fully turned to achieve self-annihilation of the dislocation, the distribution of the penetrating dislocation is greatly reduced, and the crystal quality of the epitaxial semiconductor epitaxial layer of the hetero-substrate is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to a semiconductor epitaxial structure and a preparation method thereof, and belongs to the technical field of semiconductors. BACKGROUND

[0002] Gallium nitride (GaN) as the third generation of semiconductor materials has high band gap, high critical breakdown field, high carrier saturation migration speed, high thermal conductivity and direct band gap, and has great application prospects in the fields of high-temperature, high-frequency, high-power microelectronic devices and high-performance optoelectronic devices. Since the III-nitride is generally grown on a hetero-substrate such as sapphire or SiC, the lattice constant and thermal mismatch between different materials will generate dislocations or defects, which will extend upwards with the growth of the epitaxial layer. These dislocations will act as non-radiative recombination centers when the device is working, affecting the efficiency of the device, and as a leakage current path, causing the leakage current to increase, which will rapidly age the device and affect the working efficiency and service life of the device, thereby restricting its application in the field of semiconductor electronics. SUMMARY

[0003] The main purpose of the present application is to provide a semiconductor epitaxial structure and a preparation method thereof to overcome the shortcomings of the prior art.

[0004] To achieve the above-mentioned purpose of the application, the technical scheme adopted by the present application comprises:

[0005] The semiconductor epitaxial structure provided by the embodiment of the present application comprises: a high-quality epitaxial layer disposed on a substrate; the high-quality epitaxial layer comprises:

[0006] An epitaxial restriction layer comprising an outer restriction unit, an inner intermittent unit and a first epitaxial growth layer, the outer restriction unit surrounds the inner intermittent unit and the first epitaxial growth layer in a closed manner, wherein the inner intermittent unit is arranged in an interval, and the first epitaxial growth layer is distributed and arranged between the outer restriction unit and the inner intermittent unit, and in the region between adjacent inner intermittent units;

[0007] A second epitaxial growth layer disposed on the epitaxial restriction layer.

[0008] The embodiment of the present application also provides a preparation method of a semiconductor epitaxial structure, which comprises:

[0009] A bottom epitaxial layer is disposed on a substrate; and the bottom epitaxial layer is etched to form an outer restriction unit in a closed manner;

[0010] An intermittent epitaxial layer and an intermittent sacrificial layer are alternately arranged inside the outer restriction unit;

[0011] Part of the intermittent epitaxial layer region and part of the intermittent sacrificial layer region are etched away, and the intermittent sacrificial layer is removed, leaving the intermittent epitaxial layer, to obtain an inner intermittent unit arranged in an interval.

[0012] A first epitaxial growth layer is arranged in the region between the outer limiting unit and the inner intermittent unit, and between adjacent inner intermittent units, to form an epitaxial limiting layer;

[0013] A second epitaxial growth layer is arranged on the epitaxial limiting layer to obtain the semiconductor epitaxial structure.

[0014] Compared with the prior art, the present application has at least the following beneficial effects:

[0015] The semiconductor epitaxial structure provided by the present application can improve the leakage and withstand voltage characteristics of the device, improve the crystal quality of the epitaxial semiconductor layer on the hetero-substrate, and widen the application of the semiconductor epitaxial wafer in the microelectronic field, and can be applied to the epitaxial growth of semiconductor power devices. BRIEF DESCRIPTION OF DRAWINGS

[0016] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or the prior art description. Obviously, the drawings described below are only some embodiments of the present application, and those skilled in the art can obtain other drawings according to these drawings without any creative effort.

[0017] Figure 1 is a process diagram of etching to generate a closed outer limiting unit in a typical embodiment of the present application.

[0018] Figure 2 is a top view of the outer limiting unit in a typical embodiment of the present application.

[0019] Figure 3 is a structure diagram of alternately arranging the intermittent epitaxial layer and the intermittent sacrificial layer inside the outer limiting unit in a typical embodiment of the present application.

[0020] Figure 4 is a structure diagram after etching the intermittent epitaxial layer and the intermittent sacrificial layer in a typical embodiment of the present application.

[0021] Figure 5 is a structure diagram of the inner intermittent unit after removing the region of the intermittent sacrificial layer in a typical embodiment of the present application.

[0022] Figure 6 is a structure diagram of the inner intermittent unit in another typical embodiment of the present application.

[0023] Figure 7 It is a structural schematic diagram of an internal interruption unit in another typical embodiment of the present invention.

[0024] Figure 8 It is a schematic diagram of dislocation rotation when growing an epitaxial confinement layer in a typical embodiment of the present invention.

[0025] Figure 9 It is a schematic diagram of a semiconductor epitaxial structure in a typical embodiment of the present invention.

[0026] Figure 10 The half-maximum width test graph of the (102) plane rocking curve of the semiconductor epitaxial wafers obtained in Examples 1 to 5 of the present invention and Comparative Examples 1 to 5 is performed using XRD.

[0027] Figure 11 and Figure 12 They are optical microscope images of the semiconductor epitaxial wafers obtained in Comparative Examples 4 and 5 of the present invention respectively. DETAILED DESCRIPTION

[0028] In view of the deficiencies in the prior art, the inventors of this case have proposed the technical solution of the present invention after long-term research and practice. The technical solution, its implementation process and principles will be further explained below.

[0029] Some embodiments of the present invention provide a semiconductor epitaxial structure comprising a high-quality epitaxial layer disposed on a substrate, the high-quality epitaxial layer comprising:

[0030] The epitaxial confinement layer comprises an outer confinement unit, an inner discontinuity unit, and a first epitaxial growth layer, wherein the outer confinement unit surrounds the inner discontinuity unit and the first epitaxial growth layer in a closed shape, wherein the inner discontinuity units are arranged at intervals, and the first epitaxial growth layer is distributed between the outer confinement unit and the inner discontinuity unit, and in the region between adjacent inner discontinuity units;

[0031] The second epitaxial growth layer is arranged on the epitaxial confinement layer.

[0032] In some embodiments, the height of the outer confinement unit is 1 to 5 μm.

[0033] In some embodiments, the wall thickness of the closed outer limiting unit is 0.2-5 μm.

[0034] Furthermore, the material of the outer limiting unit may be GaN, but is not limited thereto.

[0035] In some embodiments, the distance between two adjacent inner discontinuity units is 0.5-2 μm.

[0036] Further, the thickness of the inner intermittent unit is 0.5-2.5 μm.

[0037] Further, the sectional area of any two of the inner intermittent units is the same or different, which is not limited.

[0038] Further, the material of the inner intermittent unit includes any one of nitride, oxide, metal, organic matter, etc. For example, it can be preferably any one of GaN, AlN, InGaN, AlGaN, AlInGaN, AlInN, InN, Al2O3, SiO2, Si3N4, Ga2O3, ZnO, Fe, Cu, Ag, etc., but is not limited thereto.

[0039] In some embodiments, the two ends of the inner intermittent unit are connected with the four walls of the outer limiting unit, respectively.

[0040] In some embodiments, the material of the first epitaxial growth layer can be GaN, but is not limited thereto.

[0041] Further, the thickness of the second epitaxial growth layer is 1 nm-20 μm.

[0042] Further, the material of the second epitaxial growth layer can be GaN, but is not limited thereto.

[0043] Further, the substrate can be a sapphire substrate, a silicon substrate, a silicon carbide substrate, etc., but is not limited thereto.

[0044] The mechanism of setting the inner intermittent unit inside the outer limiting unit in the present application is that:

[0045] The present application sets the discontinuous intermittent interval in the inner intermittent unit, and the high dislocation between the substrate and the first epitaxial growth layer in the growth process of the epitaxial limiting layer is turned multiple times at the position of the intermittent interval, so that the dislocation is fully turned to achieve self-annihilation of the dislocation, greatly reduces the extension of the dislocation into the second epitaxial growth layer, reduces the distribution of the threading dislocation, and thus improves the leakage and withstand voltage characteristics of the device, and widens the application of the semiconductor epitaxial wafer in the microelectronic field.

[0046] Some embodiments of the present application also provide a preparation method of a semiconductor epitaxial structure, which includes:

[0047] forming an outer limiting unit in a closed shape around the substrate by etching the bottom epitaxial layer;

[0048] alternately setting intermittent epitaxial layers and intermittent sacrificial layers inside the outer limiting unit;

[0049] etching away part of the discontinuous epitaxial layer region and part of the discontinuous sacrificial layer region, and removing the discontinuous sacrificial layer while keeping the discontinuous epitaxial layer, to obtain the inner discontinuous units arranged in intervals;

[0050] arranging a first epitaxial growth layer in the region between the outer limiting units and the inner discontinuous units, and between adjacent inner discontinuous units, to form an epitaxial limiting layer;

[0051] arranging a second epitaxial growth layer on the epitaxial limiting layer, to obtain the semiconductor epitaxial structure.

[0052] In some embodiments, the thickness of the bottom epitaxial layer is 1-5 μm.

[0053] Further, the material of the bottom epitaxial layer can be GaN, but is not limited thereto.

[0054] Further, the wall thickness of the outer limiting units in the shape of a closed square is 0.2-5 μm.

[0055] In some embodiments, the materials of the discontinuous epitaxial layer and the discontinuous sacrificial layer are different, and are independently selected from any one of nitride, oxide, metal, organic matter, etc. For example, it can be preferred to be any one of GaN, AlN, InGaN, AlGaN, AlInGaN, AlInN, InN, Al2O3, SiO2, Si3N4, Ga2O3, ZnO, Fe, Cu, Ag, etc., but is not limited thereto.

[0056] Further, the thickness of the discontinuous epitaxial layer or the discontinuous sacrificial layer is 0.5-2.5 μm, and the total thickness of the discontinuous epitaxial layer and the discontinuous sacrificial layer does not exceed the height of the outer limiting unit.

[0057] Further, the thickness of any two discontinuous epitaxial layers or discontinuous sacrificial layers is the same or different.

[0058] Further, the preparation method comprises removing the discontinuous sacrificial layer by at least solution wet etching.

[0059] In some embodiments, the preparation method comprises arranging a first epitaxial growth layer in the region between the outer limiting units and the inner discontinuous units, and between adjacent inner discontinuous units, by using MOCVD epitaxial growth technology. Preferably, the present application can further comprise annealing the outer limiting units and the inner discontinuous units on the substrate before the growth of the first epitaxial growth layer, to eliminate the sidewall damage of the outer limiting units and the inner discontinuous units caused by dry etching, so that a complete interface performance can be formed when the first epitaxial growth layer is grown. The temperature of the annealing treatment is 500-700 °C, and the time is 1-15 min.

[0060] In some embodiments, the first epitaxial growth layer has a growth temperature of 1000-1100°C and a growth pressure of 200-400 torr.

[0061] Further, the second epitaxial growth layer has a growth temperature of 1100-1200°C and a growth pressure of 100-300 torr.

[0062] Further, the first epitaxial growth layer, the second epitaxial growth layer, the material and thickness of the substrate, etc. are as described above, and will not be repeated here.

[0063] In some embodiments, the method for preparing the semiconductor epitaxial wafer specifically comprises:

[0064] 1) providing a substrate, and setting a bottom epitaxial layer on the substrate;

[0065] 2) etching the bottom epitaxial layer by etching to form an outer limiting unit in a closed shape;

[0066] 3) alternately setting an intermittent epitaxial layer and an intermittent sacrificial layer inside the outer limiting unit;

[0067] 4) forming the alternating intermittent epitaxial layer region and intermittent sacrificial layer region inside the epitaxial limiting unit by etching process;

[0068] 5) removing the intermittent sacrificial layer region to form an inner intermittent unit inside the outer limiting unit, and the inner intermittent unit has discontinuous intermittent intervals;

[0069] 6) setting a first epitaxial growth layer in the region adjacent to the outer limiting unit and the inner intermittent unit and the intermittent interval, to form an epitaxial limiting layer;

[0070] 7) setting a second epitaxial growth layer on the epitaxial limiting layer to obtain a high-quality epitaxial layer, and the high-quality epitaxial layer and the substrate constitute a semiconductor epitaxial wafer.

[0071] In a more specific embodiment, the present application provides a method for preparing a semiconductor epitaxial wafer, which specifically comprises the following steps:

[0072] 1) providing a sapphire substrate 100, and setting a GaN bottom epitaxial layer 200 with a thickness of 1-5 μm on the substrate, as shown in Figure 1 ;

[0073] 2) as shown in Figure 1 , etching the GaN bottom epitaxial layer 200 by ICP dry etching to form a GaN outer limiting unit 210 with a wall thickness of 1-10 mm, in a closed shape, and its top view is shown in Figure 2 ;

[0074] 3) Al2O3 discontinuous epitaxial layers 300 and SiO2 discontinuous sacrificial layers 400 with a thickness of 0.5 to 2.5 μm are alternately arranged inside the GaN outer confinement unit 210, as shown in FIG. Figure 3 As shown, the total thickness of the Al2O3 discontinuous epitaxial layer 300 and the SiO2 discontinuous sacrificial layer 400 does not exceed the height of the GaN outer confinement unit 210;

[0075] 4) Al2O3 discontinuous epitaxial layer regions 310 and SiO2 discontinuous sacrificial layer regions 410 are formed alternately in the GaN epitaxial confinement unit 210 by etching process, as shown in FIG. Figure 4 As shown;

[0076] 5) A mixed solution of 49% HF aqueous solution and 40% NH4F aqueous solution in a volume ratio of 1:6 is used to wet-etch and remove the SiO2 discontinuous sacrificial layer region 410, forming an Al2O3 inner discontinuous unit 320 inside the GaN outer limiting unit 210, wherein the inner discontinuous interval has a discontinuous interval, such as Figure 5 Specifically, if the GaN outer confinement unit 210 is understood to be arranged vertically on the substrate surface, then the Al2O3 inner discontinuity unit 320 is arranged in a direction parallel to the substrate horizontally;

[0077] Depending on the different growth positions and thicknesses of the Al2O3 discontinuous epitaxial layer and the SiO2 discontinuous sacrificial layer in step 3), the structural distribution of the Al2O3 discontinuous units formed after the SiO2 discontinuous sacrificial layer is finally removed may also be different. For example, see Figure 6 and Figure 7 As shown, they are also within the protection scope of the present invention.

[0078] 6) Using MOCVD epitaxial growth technology, the outer confinement unit and the inner discontinuity unit on the substrate are annealed in an N2 atmosphere, and then a first GaN epitaxial growth layer 500 is formed in the GaN outer confinement unit 210 and the Al2O3 inner discontinuity unit 320 and the adjacent area of ​​the discontinuity interval, as shown in FIG. Figure 8 As shown, a GaN epitaxial confinement layer 600 is formed;

[0079] 7) A second GaN epitaxial growth layer 700 is provided on the GaN epitaxial confinement layer 600 to obtain a high-quality GaN epitaxial layer, such as Figure 9 As shown, high-quality GaN epitaxial layers and sapphire substrates constitute GaN semiconductor epitaxial wafers.

[0080] In summary, the semiconductor epitaxial wafer provided by the present invention sets a discontinuous discontinuous interval in the internal discontinuous unit, and utilizes the high dislocation between the substrate and the epitaxial layer during the growth of the epitaxial confinement layer to turn multiple times at the position of the discontinuous interval (such as Figure 8The dislocation is caused to turn around fully to reach dislocation self-annihilation, greatly reduces the extension of the dislocation into the epitaxial layer, reduces the distribution of the penetrating dislocation, and thus can improve the leakage and withstand voltage characteristics of the device, improve the crystal quality of the hetero-substrate epitaxial semiconductor epitaxial layer, and widen the application of the semiconductor epitaxial wafer in the microelectronic field, and can be suitable for epitaxial growth of semiconductor power devices.

[0081] The technical solutions of the present application will be described in more detail below in combination with the drawings and several embodiments, but it should be understood that the following embodiments are only for explanation and illustration of the technical solutions, but do not limit the scope of the present application. In addition, unless otherwise specified, various raw materials, reaction equipment, detection equipment and methods used in the following embodiments are known in the art.

[0082] Embodiment 1

[0083] This embodiment is illustrated by taking a high-quality GaN epitaxial layer as an example, and the intermittent epitaxial layer uses Al2O3 and the intermittent sacrificial layer uses SiO2. The specific preparation process includes the following steps:

[0084] 1) A sapphire substrate is provided, and a GaN bottom epitaxial layer with a thickness of 3 μm is grown on the substrate, wherein the growth temperature is 1085 ℃, the growth pressure is 150 torr, and the growth atmosphere is H2;

[0085] 2) The GaN bottom epitaxial layer is etched by ICP dry etching to form a GaN outer limiting unit with a wall thickness of 2 μm, which is closed, wherein the ICP power is 950 W, the etching gas is 20% BCl3 and 80% Cl2, and the etching pressure is 10 mtorr;

[0086] 3) The Al2O3 intermittent epitaxial layer with a thickness of 0.5 μm and the SiO2 intermittent sacrificial layer with a thickness of 0.5 μm are alternately arranged inside the GaN outer limiting unit by using the PECVD method, and the total thickness of the Al2O3 intermittent epitaxial layer and the SiO2 intermittent sacrificial layer does not exceed the height of the GaN outer limiting unit, wherein the Al2O3 intermittent epitaxial layer uses trimethylaluminum (TMAl) and oxygen (O2), the growth temperature is 300 ℃, and the growth pressure is 0.2 torr; the SiO2 intermittent sacrificial layer uses silane (SiH4) and nitrogen dioxide (NO2), the growth temperature is 400 ℃, and the growth pressure is 3.5 torr;

[0087] 4) The Al2O3 intermittent epitaxial layer region and the SiO2 intermittent sacrificial layer region are formed inside the GaN epitaxial limiting unit by using the ICP dry etching process, wherein the ICP power is 950 W, the etching gas is 20% BCl3 and 80% Cl2, and the etching pressure is 10 mtorr;

[0088] 5) Wet etching with 49% HF and 40% NH4F in volume ratio of 1:6 to remove the SiO2 sacrificial layer in the discontinuous region, and form the Al2O3 inner discontinuous layer in the inner region of the outer confinement layer.

[0089] 6) Using MOCVD epitaxial growth technology, a first GaN epitaxial growth layer with a thickness of 3 μm is grown in the region adjacent to the outer confinement layer and the inner discontinuous layer, to form a GaN epitaxial confinement layer, wherein the growth temperature is 1005 °C, and the growth pressure is 400 torr.

[0090] 7) A second GaN epitaxial growth layer with a thickness of 5 μm is grown on the GaN epitaxial confinement layer to obtain a high-quality GaN epitaxial layer, wherein the growth temperature is 1125 °C, the growth pressure is 200 torr, and the growth atmosphere is H2.

[0091] Example 2

[0092] The difference between this example and Example 1 is that:

[0093] In step 6), the first GaN epitaxial growth layer has a thickness of 1 μm, and the growth temperature is 1000 °C and the growth pressure is 300 torr.

[0094] In step 7), the second GaN epitaxial growth layer has a thickness of 0.2 μm.

[0095] Example 3

[0096] The difference between this example and Example 1 is that:

[0097] In step 6), the first GaN epitaxial growth layer has a thickness of 5 μm, and the growth temperature is 1100 °C and the growth pressure is 200 torr.

[0098] In step 7), the second GaN epitaxial growth layer has a thickness of 15 μm.

[0099] Example 4

[0100] The difference between this example and Example 1 is that:

[0101] In step 6), the outer confinement layer and the inner discontinuous layer on the substrate are first annealed, and then the first GaN epitaxial growth layer is grown, wherein the annealing temperature is 700 °C and the annealing time is 1 min.

[0102] In step 7), the growth temperature of the second GaN epitaxial growth layer is 1100 °C, the growth pressure is 300 torr, and the thickness of the grown second GaN epitaxial growth layer is 1 nm.

[0103] Example 5

[0104] This example differs from Example 1 in that:

[0105] In step 6), the outer confinement unit and the inner discontinuous unit on the substrate are annealed first, and then the first GaN epitaxial growth layer is grown, the annealing temperature is 500 °C, and the time is 15 min.

[0106] In step 7), the growth temperature of the second GaN epitaxial growth layer is 1200 °C, the growth pressure is 100 torr, and the thickness of the grown second GaN epitaxial growth layer is 20 μm.

[0107] The thickness of the bottom epitaxial layer in the above examples can be any value in the range of 1 to 5 μm, and the wall thickness of the outer confinement unit in the shape of a closed square can be any value in the range of 0.2 to 5 μm. The thickness of the discontinuous epitaxial layer or the discontinuous sacrificial layer can be controlled to be in the range of 0.5 to 2.5 μm.

[0108] Comparative Example 1

[0109] This comparative example differs from Example 1 in that a second GaN epitaxial growth layer having a thickness of 5 μm is continuously grown epitaxially on the GaN bottom epitaxial layer of step 1).

[0110] Comparative Example 2

[0111] This comparative example differs from Example 1 in that a second GaN epitaxial growth layer having a thickness of 0.2 μm is continuously grown epitaxially on the GaN bottom epitaxial layer of step 1).

[0112] Comparative Example 3

[0113] This comparative example differs from Example 1 in that a second GaN epitaxial growth layer having a thickness of 15 μm is continuously grown epitaxially on the GaN bottom epitaxial layer of step 1).

[0114] Comparative Example 4

[0115] This example differs from Example 1 in that a second GaN epitaxial growth layer is continuously grown epitaxially on the GaN bottom epitaxial layer of step 1), and the growth temperature is 1075 °C.

[0116] Comparative Example 5

[0117] This example differs from Example 1 in that a second GaN epitaxial growth layer is continuously grown epitaxially on the GaN bottom epitaxial layer of step 1), and the growth temperature is 1275 °C.

[0118] XRD was used to test the half-peak width of the (102) plane rocking curve of Examples 1 to 5 and Comparative Examples 1 to 5, and the data are as follows: Figure 10 shown.

[0119] from Figure 10 It can be seen that the above embodiments have lower (102) half-widths compared to the comparative examples, because the (102) half-widths directly reflect the distribution of threading dislocations in the epitaxial layer. Low (102) half-widths have low threading dislocations, so the embodiments have lower threading dislocations. In addition, the overall fluctuation of the (102) half-widths of embodiments 1 to 5 is small, while the fluctuation of the (102) half-widths in the comparative examples is large, especially the (102) half-widths in comparative examples 4 and 5 exceed 350 arcsec. Compared with comparative example 1, the (102) half-widths of comparative examples 4 and 5 are more affected by the growth temperature. Through an optical microscope, it was found that comparative example 4 has a large number of black spots (such as Figure 11 As shown), while Comparative Example 5 has a large number of hexagonal defects (as shown Figure 12 Compared with Example 1, the half-peak widths of Examples 4 and 5 are both less than 200 arcsec, and all of the examples have smooth surfaces, indicating that the growth temperature of the embodiments of the present invention has a larger process window, thereby improving the stability of the growth process.

[0120] The above embodiments are merely preferred embodiments for the purpose of fully illustrating the present invention, and the scope of protection of the present invention is not limited thereto. Equivalent substitutions or modifications made by those skilled in the art based on the present invention are all within the scope of protection of the present invention. The scope of protection of the present invention shall be subject to the claims.

Claims

1. A semiconductor epitaxial structure, characterized in that include: A high-quality epitaxial layer is provided on a foreign substrate; the high-quality epitaxial layer comprises: An epitaxial confinement layer comprising an outer confinement unit, an inner discontinuity unit, and a first epitaxial growth layer, wherein the outer confinement unit has a height of 1 to 5 μm and a wall thickness of 0.2 to 5 μm, and the outer confinement unit is closed on all sides and surrounds the inner discontinuity unit and the first epitaxial growth layer; wherein the inner discontinuity units have a thickness of 0.5 to 2.5 μm and are spaced apart in both the vertical and horizontal directions, with a spacing of 0.5 to 2 μm between two adjacent inner discontinuity units, and both ends of the inner discontinuity units are respectively connected to the four walls of the outer confinement unit; and the first epitaxial growth layer is distributed between the outer confinement unit and the inner discontinuity unit, and in the region between adjacent inner discontinuity units; The second epitaxial growth layer is arranged on the epitaxial confinement layer.

2. The semiconductor epitaxial structure according to claim 1, wherein: The material of the outer limiting unit is selected from GaN.

3. The semiconductor epitaxial structure according to claim 1, wherein: The cross-sectional areas of any two of the internal discontinuity units are the same or different.

4. The semiconductor epitaxial structure according to claim 1, wherein: The material of the internal discontinuity unit is selected from any one of GaN, AlN, InGaN, AlGaN, AlInGaN, AlInN, InN, Al2O3, SiO2, Si3N4, Ga2O3, ZnO, Fe, Cu, and Ag.

5. The semiconductor epitaxial structure according to claim 1, wherein: The material of the first epitaxial growth layer is selected from GaN.

6. The semiconductor epitaxial structure according to claim 1, wherein: The thickness of the second epitaxial growth layer is 1 nm to 20 μm.

7. The semiconductor epitaxial structure according to claim 1, wherein: The material of the second epitaxial growth layer is selected from GaN.

8. The semiconductor epitaxial structure according to claim 1, wherein: The heterogeneous substrate is selected from any one of a sapphire substrate, a silicon substrate, and a silicon carbide substrate.

9. A method for preparing a semiconductor epitaxial structure, characterized in that include: A bottom epitaxial layer with a thickness of 1 to 5 μm is provided on a foreign substrate; and etching the bottom epitaxial layer to form an outer confinement unit with a wall thickness of 0.2 to 5 μm and a closed shape on all sides; Alternately arranging discontinuous epitaxial layers and discontinuous sacrificial layers inside the outer restriction unit, wherein the thickness of the discontinuous epitaxial layers or the discontinuous sacrificial layers is 0.5-2.5 μm, and the total thickness of the discontinuous epitaxial layers and the discontinuous sacrificial layers does not exceed the height of the outer restriction unit; Etching away a portion of the discontinuous epitaxial layer region and a portion of the discontinuous sacrificial layer region, and removing the discontinuous sacrificial layer, retaining the discontinuous epitaxial layer, to obtain inner discontinuous units spaced apart in both the horizontal and vertical directions, with both ends of the inner discontinuous units respectively connected to the four walls of the outer confinement unit; Disposing a first epitaxial growth layer between the outer restriction unit and the inner discontinuity unit, and in the region between adjacent inner discontinuity units, to form an epitaxial restriction layer; A second epitaxial growth layer is provided on the epitaxial restriction layer to obtain a semiconductor epitaxial structure.

10. The preparation method according to claim 9, characterized in that: The material of the bottom epitaxial layer is selected from GaN.

11. The preparation method according to claim 9, characterized in that: The thicknesses of any two of the discontinuous epitaxial layers or discontinuous sacrificial layers are the same or different.

12. The preparation method according to claim 9, characterized in that: The material of the discontinuous epitaxial layer or the discontinuous sacrificial layer is selected from any one of GaN, AlN, InGaN, AlGaN, AlInGaN, AlInN, InN, Al2O3, SiO2, Si3N4, Ga2O3, ZnO, Fe, Cu, and Ag.

13. The preparation method according to claim 9, characterized in that The preparation method comprises: removing the discontinuous sacrificial layer by at least wet etching.

14. The preparation method according to claim 9, wherein include: The MOCVD epitaxial growth technology is used to set a first epitaxial growth layer between the outer restriction unit and the inner discontinuity unit and in the area between adjacent inner discontinuity units, with a growth temperature of 1000-1100° C. and a growth pressure of 200-400 torr.

15. The preparation method according to claim 9, characterized in that: The material of the first epitaxial growth layer is selected from GaN.

16. The preparation method according to claim 9, characterized in that The preparation method comprises: before the growth of the first epitaxial growth layer, performing annealing treatment on the outer restriction unit and the inner discontinuity unit, wherein the annealing treatment temperature is 500-700° C. and the time is 1-15 minutes.

17. The preparation method according to claim 9, characterized in that: The growth temperature of the second epitaxial growth layer is 1100-1200° C., and the growth pressure is 100-300 torr.

18. The preparation method according to claim 9, characterized in that: The thickness of the second epitaxial growth layer is 1 nm to 20 μm.

19. The preparation method according to claim 9, characterized in that: The material of the second epitaxial growth layer is selected from GaN.

20. The preparation method according to claim 9, characterized in that: The foreign substrate is selected from a sapphire substrate.

Images