Accumulator hardware implementation method and device supporting continuous writing of accumulation results

Abstract

The application provides an accumulator hardware implementation method and device supporting continuous writing of accumulation results, and belongs to the technical field of high-performance microprocessor design. The method comprises the following steps: S1: determining the starting entry of the current accumulation result writing in the accumulator based on the enable bit corresponding to the current accumulation result; S2: sequentially writing the current accumulation result into the accumulator from the starting entry; S3: obtaining the ending entry of the current accumulation result writing, and obtaining the latching entry of the current accumulation result based on the ending entry; and S4: latching the latching entry of the current accumulation result. In programming, the programmer can realize the continuous writing function of the accumulation result based on the enable bit, so it is not necessary to manually calculate the accumulator buffer address of the current writing, and therefore the programming complexity and the possibility of errors in calculating the address can be reduced, and the programming efficiency is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of high-performance microprocessor design, in particular to an accumulator hardware implementation method and device supporting continuous writing of accumulation results. BACKGROUND

[0002] Artificial intelligence technology has been widely used in image recognition, speech processing and other fields, and plays an increasingly powerful role. It can be predicted that in the near future, artificial intelligence will be applied to more fields, and technology will be more complex. Along with it, the number of layers of neural networks is deeper and the size is larger. The most core operation of artificial intelligence algorithm is convolution and matrix multiplication operation, which has high demand for hardware resources and becomes the part that needs to be optimized in hardware design. The current academic and industrial circles usually use systolic array to accelerate convolution and matrix multiplication operation. Two-dimensional systolic array is the most commonly used systolic array structure. When working, the north end data is transmitted from north to south, and the west end data is transmitted from west to east, to drive the basic units in the systolic array to complete matrix multiplication operation by data flow, and send the intermediate accumulation result to the accumulator buffer on the south side for accumulation and caching. Since the accumulator buffer has multiple entries (such as 64), when writing the accumulation result into the accumulator buffer, the starting entry number and the number of accumulator buffer entries required need to be specified.

[0003] The existing systolic array design needs to specify the starting entry number and the number of entries required when writing the accumulation result into the accumulator buffer each time. This is usually determined by the programmer through calculation, which on the one hand increases the burden of the programmer programming; on the other hand, if the starting entry number and the number of entries are calculated incorrectly, it will cause hardware errors. SUMMARY

[0004] In order to solve the above problems, the present application provides an accumulator hardware implementation method and device supporting continuous writing of accumulation results.

[0005] In a first aspect, the present application provides an accumulator hardware implementation method supporting continuous writing of accumulation results, comprising the following steps:

[0006] S1: determining the starting entry of the current accumulation result writing in the accumulator based on the enable bit corresponding to the current accumulation result;

[0007] S2: sequentially writing the current accumulation result into the accumulator from the starting entry;

[0008] S3: obtaining the ending entry of the current accumulation result writing, and obtaining the latching entry of the current accumulation result based on the ending entry; S4: latching the latching entry of the current accumulation result.

[0009] Preferably, step S3 specifically comprises:

[0010] S31: obtaining the buffer entry number of the current accumulation result;

[0011] S32: calculating the end entry by the buffer entry number and the start entry;

[0012] S33: taking the entry pointed by the end entry plus 1 as the latch entry of the current time.

[0013] Preferably, the step S1 specifically comprises:

[0014] S11: identifying the corresponding enable bit in the current accumulation result, and obtaining the value of the enable bit;

[0015] S12: if the value of the enable bit is 1, taking the previously latched latch entry in the accumulator as the start entry of the current write, and if the value of the enable bit is not 1, taking the target entry in the accumulator as the start entry of the current write.

[0016] Preferably, the step S2 specifically comprises:

[0017] S21: identifying the start position corresponding to the start entry in the accumulator;

[0018] S22: obtaining the write direction of the current accumulation result, and sequentially writing the current accumulation result into the accumulator from the start position based on the write direction.

[0019] In the second aspect, the embodiments of the present application provide an accumulator hardware implementation device supporting continuous write of accumulation result, comprising

[0020] a start entry determination module, configured to determine the start entry of the current write in the accumulator based on the enable bit corresponding to the current accumulation result;

[0021] a write module, configured to sequentially store the current accumulation result in the accumulator from the start entry;

[0022] a latch entry determination module, configured to obtain the end entry of the current accumulation result, and obtain the latch entry of the current time based on the end entry;

[0023] a latch module, configured to latch the latch entry of the current time.

[0024] Preferably, the latch entry determination module comprises:

[0025] a statistical unit, configured to obtain the buffer entry number of the current accumulation result;

[0026] a first calculation unit, configured to calculate the end entry by the buffer entry number and the start entry;

[0027] a second calculation unit, configured to take the entry pointed by the end entry plus 1 as the latch entry of the current time.

[0028] Preferably, the start entry determination module comprises

[0029] an enable bit determination unit configured to identify the corresponding enable bit in the current accumulation result and obtain the value of the enable bit;

[0030] a judgment unit configured to, if the value of the enable bit is 1, take the previously latched latch entry in the accumulator as the start entry for the current write, and if the value of the enable bit is not 1, take the target entry in the accumulator as the start entry for the current write.

[0031] Preferably, the write module comprises

[0032] a start determination unit configured to identify the start position corresponding to the start entry in the accumulator;

[0033] a write determination unit configured to obtain the write direction of the current accumulation result and sequentially write the current accumulation result into the accumulator from the start position based on the write direction.

[0034] In a third aspect, an electronic device is provided, which includes a memory, a processor, and a computer program stored in the memory and capable of running on the processor. The processor implements the steps of the method provided in the first aspect or any possible implementation manner of the first aspect when executing the computer program.

[0035] In a fourth aspect, a computer readable storage medium is provided, which stores a computer program. The computer program is executed by a processor to implement the steps of the method provided in the first aspect or any possible implementation manner of the first aspect.

[0036] The present application has the following beneficial effects. First, the start entry for the current accumulation result is determined in the accumulator according to the enable bit, then the current accumulation result is sequentially written into the accumulator according to the start entry, then the latch entry of the current accumulation result is obtained according to the end entry of the current accumulation result, and finally the latch entry of the current accumulation result is latched, so that the start entry in the accumulator can be quickly determined when the subsequent accumulation result is written, and the user does not need to specify the start entry, the programmer can implement the accumulation result continuous writing function based on the enable bit when programming, and thus it is not necessary to manually calculate the accumulator buffer address for the current write, so that the programming complexity and the possibility of error when calculating the address can be reduced, and the programming efficiency is improved. BRIEF DESCRIPTION OF DRAWINGS

[0037] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings needed in the embodiments. Obviously, the drawings in the following description only constitute some embodiments of the present application, and for those skilled in the art, other drawings can also be obtained from these drawings without creative effort.

[0038] Figure 1 A flowchart of a cumulative result continuous writing supporting accumulator hardware implementation method provided by an embodiment of the present application;

[0039] Figure 2 A structural diagram of a cumulative result continuous writing supporting accumulator hardware implementation device provided by an embodiment of the present application;

[0040] Figure 3 A structural diagram of an electronic device provided by an embodiment of the present application;

[0041] Figure 4 A schematic diagram of a cumulative result continuous writing supporting accumulator hardware implementation method provided by an embodiment of the present application. DETAILED DESCRIPTION

[0042] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application.

[0043] In the following description, the terms "first", "second", etc. are only for the purpose of description and cannot be understood as indicating or implying relative importance. The following description provides a plurality of embodiments of the present application, and different embodiments can be replaced or combined, so the present application can also be considered to include all possible combinations of the same and / or different embodiments described. Thus, if one embodiment includes features A, B, C, and another embodiment includes features B, D, the present application should also be considered to include one or more embodiments of all other possible combinations of A, B, C, and D, even if the embodiment is not explicitly described in the following content.

[0044] The following description provides examples and does not limit the scope, applicability or examples set forth in the claims. Changes can be made to the functions and arrangements of the described elements without departing from the scope of the present application. Various examples can appropriately omit, replace or add various processes or components. For example, the described methods can be executed in different order from the described order, and various steps can be added, omitted or combined. In addition, features described with respect to some examples can be combined into other examples.

[0045] Please refer to Figure 1 . Figure 1is a flowchart of an accumulator hardware implementation method provided by an embodiment of the present application, which supports continuous writing of accumulation results. In the embodiment of the present application, the method comprises the following steps:

[0046] S1: determining a starting entry for writing the current accumulation result in the accumulator based on the enable bit corresponding to the current accumulation result;

[0047] S2: sequentially writing the current accumulation result in the accumulator from the starting entry;

[0048] S3: obtaining an ending entry for writing the current accumulation result, and obtaining a latch entry for the current accumulation result based on the ending entry;

[0049] S4: latching the latch entry for the current accumulation result.

[0050] In the embodiment of the present application, a plurality of entries are provided in the accumulator, each entry has a unique corresponding address, when it is needed to write the current accumulation result in the accumulator, the enable bit of the accumulation result is obtained first, the starting entry is determined based on the enable bit, that is, the address corresponding to the starting entry in the accumulator is determined, the current accumulation result is written from the address, which facilitates fast writing of the accumulation result in the accumulator, after the writing operation is completed, the ending entry of the accumulation result in the accumulator is obtained, that is, the address corresponding to the ending entry is obtained, the latch entry for the current accumulation result is obtained according to the ending entry, that is, the address of the latch entry is determined according to the address of the ending entry, the latch entry is latched, that is, the address corresponding to the latch entry is stored in a latch module, so that the address is retrieved from the latch module when the accumulation result is written next time, so that the latch entry in the accumulator is determined, and the programming complexity is reduced by providing the function of obtaining the writing address of the current accumulation result based on the last writing address of the previous accumulation result, and the possibility of error in calculating the writing address of the accumulator buffer is reduced.

[0051] In an implementation manner, step S3 specifically comprises:

[0052] S31: obtaining the number of buffer entries of the current accumulation result;

[0053] S32: calculating the ending entry by using the number of buffer entries and the starting entry;

[0054] S33: taking the entry pointed to by the ending entry plus 1 as the latch entry for the current accumulation result.

[0055] In the embodiment of the present application, two variables are defined first. initIdx represents the starting entry number of the accumulator buffer, and maxIdx represents the maximum entry number of the accumulator buffer. The calculation method is that the sum of initIdx and the number of buffer entries required to be cached this time, and then plus 1, that is, the next entry of the last written entry this time. initIdx is the starting entry, maxIdx is the ending entry, and the entry pointed to by maxIdx plus 1 is the latch entry.

[0056] In an implementable manner, step S1 specifically includes:

[0057] S11: identifying the corresponding enable bit in the current accumulation result, and obtaining the value of the enable bit;

[0058] S12: if the value of the enable bit is 1, the previously latched latch entry in the accumulator is taken as the starting entry of the current write, and if the value of the enable bit is not 1, the target entry in the accumulator is taken as the starting entry of the current write.

[0059] In the embodiment of the present application, at the end of each accumulation result write, the accumulator buffer control logic controls the latch module to store the value of the latch entry. Before the start of the next round of calculation, the westward data is loaded at the same time, and whether to enable continue (a certain bit of the control signal represents whether to enable) is specified in the accumulator buffer control logic. If the bit is 1 (indicating that continue is enabled), the previously latched latch entry is selected as the starting entry number of the current write at the end of the current calculation; otherwise, the entry specified in the accumulator buffer control logic (that is, initIdx) is selected as the starting entry of the current accumulation result.

[0060] Referring to Figure 4 , Figure 4The schematic diagram in the accumulator hardware implementation method supporting continuous writing of accumulation result provided in the embodiments of the present application. 6 represents the starting entry of the previous writing (i.e. the previous initIdx); 7 represents the last entry written in the previous writing; 8 is the next entry of the last entry written in the previous writing, i.e. the latch entry that needs to be latched; 9 represents the starting entry number specified in the current writing (i.e. the current initIdx). When the previous writing ends, the entry number corresponding to 8 is latched, which can be stored in a latch module. When the enable bit corresponding to the next accumulation result is 1, the entry number stored in the latch module is called, the corresponding latch entry in the accumulator is found according to the entry number, and then the latch entry is taken as the starting entry of the current accumulation result. If the enable continue in the current writing, the current accumulation result is written from 8, otherwise the current accumulation result is written from 9. By providing the function of obtaining the current writing address based on the last writing address in the previous writing, the complexity of programming is reduced, and the possibility of error in calculating the writing accumulator buffer address is also reduced. By enabling the continuous writing function of the accumulation result during programming, it is not necessary to manually calculate the accumulator buffer address for the current writing, so the complexity of programming and the possibility of error in calculating the address can be reduced, and the programming efficiency is improved. The programmer sets the value of the enable bit of each accumulation result during programming. The value of the enable bit of the first accumulation result is not set to 1, so the starting entry corresponding to the first accumulation result in the accumulator is specified by the programmer. The target entry in the accumulator is taken as the starting entry of the first accumulation result, the first accumulation result is written into the accumulator according to the starting entry, the ending entry corresponding to the first accumulation result is obtained, the latch entry corresponding to the first accumulation result is obtained according to the ending entry, and the enable bit of the subsequent accumulation result is set to 1 by the programmer during programming. When the subsequent accumulation result is written, the starting entry is the latch entry corresponding to the previous accumulation result, so that the subsequent accumulation result can be continuously written into the accumulator buffer without separately specifying the writing address.

[0061] In an implementation manner, step S2 specifically includes:

[0062] S21: identifying a starting position corresponding to a starting entry in the accumulator;

[0063] S22: obtaining a writing direction of the current accumulation result, and sequentially writing the current accumulation result into the accumulator based on the writing direction.

[0064] In the embodiments of the present application, after the starting position is identified, the first entry of the current accumulation result is written into the starting position, and the current accumulation result is sequentially written into the accumulator according to the writing direction of the current accumulation result.

[0065] The above description will be further illustrated by the following Figure 2The application provides an accumulator hardware implementation device supporting continuous writing of accumulation results. Figure 2 The accumulator hardware implementation device supporting continuous writing of accumulation results is used for executing the method of the embodiment shown in the figure. Figure 1 The method of the embodiment shown in the figure is only used for describing the part related to the application, and the specific technical details are not disclosed, please refer to the application Figure 1 The embodiment shown in the figure.

[0066] Please refer to Figure 2 , Figure 2 The application provides an accumulator hardware implementation device supporting continuous writing of accumulation results. Figure 2 As shown in the figure, the device comprises

[0067] The start item determination module 201 is used for determining the start item of the current writing in the accumulator based on the enable bit corresponding to the current accumulation result;

[0068] The writing module 202 is used for sequentially storing the current accumulation result in the accumulator from the start item;

[0069] The latch item determination module 203 is used for obtaining the end item of the current accumulation result writing, and obtaining the latch item of the current accumulation result based on the end item;

[0070] The latch module 204 is used for latching the latch item of the current accumulation result.

[0071] In the embodiment of the application, when the current accumulation result needs to be written in the accumulator, the start item determination module 201 obtains the enable bit of the accumulation result, and determines the start item based on the enable bit, so as to facilitate and quickly write the accumulation result in the accumulator. After the writing operation of the writing module 202 is completed, the latch item determination module 203 obtains the end item of the accumulation result in the accumulator, and obtains the latch item of the current accumulation result according to the end item. The latch module 204 latches the latch item, which aims to reduce the complexity of programming by providing the function of obtaining the last writing address before the current writing address, and reduces the possibility of error in calculating the writing accumulator buffer address

[0072] In one implementation manner, the latch item determination module 203 comprises:

[0073] The statistical unit is used for obtaining the buffer item number of the current accumulation result;

[0074] The first calculation unit is used for calculating the end item by using the buffer item number and the start item;

[0075] The second calculation unit is used for taking the item pointed by the end item plus 1 as the latch item of the current accumulation result.

[0076] In an implementation, the start entry determination module 201 comprises

[0077] an enable bit determination unit configured to identify the corresponding enable bit in the current accumulation result, and obtain the value of the enable bit;

[0078] a judgment unit configured to, if the value of the enable bit is 1, take the previously latched entry in the accumulator as the start entry for the current write, and if the value of the enable bit is not 1, take the target entry in the accumulator as the start entry for the current write.

[0079] In an implementation, the write module 202 comprises

[0080] a start determination unit configured to identify the start position corresponding to the start entry in the accumulator;

[0081] a write determination unit configured to obtain the write direction of the current accumulation result, and write the current accumulation result into the accumulator from the start position according to the write direction.

[0082] Those skilled in the art can clearly understand that the technical solutions of the embodiments of the present application can be implemented by means of software and / or hardware. The "unit" and "module" in the specification refer to software and / or hardware that can independently complete or cooperate with other components to complete a specific function, and the hardware can be, for example, a Field-Programmable Gate Array (FPGA), an Integrated Circuit (IC), etc.

[0083] The various processing units and / or modules of the embodiments of the present application can be implemented by means of analog circuits that implement the functions of the embodiments of the present application, or by means of software that implements the functions of the embodiments of the present application.

[0084] Referring to Figure 3 , a structural schematic diagram of an electronic device related to the embodiments of the present application is shown, which can be used to implement the method shown in Figure 1 . As shown in Figure 3 , the electronic device 300 can comprise at least one central processor 301, at least one network interface 304, a user interface 303, a memory 305, and at least one communication bus 302.

[0085] The communication bus 302 is used to realize the connection and communication between the components.

[0086] The user interface 303 can comprise a display screen (Display) and a camera (Camera), and the optional user interface 303 can further comprise a standard wired interface and a wireless interface.

[0087] The network interface 304 can optionally include a standard wired interface, a wireless interface (e.g., a WI-FI interface).

[0088] The central processor 301 can include one or more processing cores. The central processor 301 connects various parts within the electronic device 300 through various interfaces and lines, and performs various functions of the terminal 300 and processes data by running or executing instructions, programs, code sets or instruction sets stored in the memory 305, and calling data stored in the memory 305. The central processor 301 can be implemented in at least one of a hardware form of a digital signal processing (DSP), a field-programmable gate array (FPGA), and a programmable logic array (PLA). The central processor 301 can integrate one or a combination of a central central processor (CPU), a graphics central processor (GPU), and a modem. The CPU mainly processes an operating system, a user interface, and an application program, etc.; the GPU is responsible for rendering and drawing content to be displayed on a display screen; and the modem is used for processing wireless communication. It can be understood that the above-mentioned modem can also not be integrated into the central processor 301, but can be implemented by a separate chip.

[0089] The memory 305 can include a random access memory (RAM) and a read-only memory (ROM). The memory 305 can include a non-transitory computer-readable storage medium. The memory 305 can be used to store instructions, programs, codes, code sets or instruction sets. The memory 305 can include a program storage area and a data storage area. The program storage area can store instructions for implementing an operating system, instructions for at least one function (such as a touch function, a sound playing function, an image playing function, etc.), instructions for implementing the above-mentioned various method embodiments, etc.; the data storage area can store data involved in the above-mentioned various method embodiments, etc. The memory 305 can optionally be at least one storage device located away from the above-mentioned central processor 301. For example, Figure 3As shown, the memory 305 as a computer storage medium can include an operating system, a network communication module, a user interface module, and program instructions.

[0090] In Figure 3 In the electronic device 300 as shown, the user interface 303 is mainly used to provide an interface for user input, and obtain data input by the user; and the central processor 301 can be used to call an accumulator hardware implementation application stored in the memory 305 to support continuous writing of accumulation results, and specifically perform the following operations:

[0091] S1: determining, based on the enable bit corresponding to the current accumulation result in the accumulator, a starting entry for writing the current accumulation result;

[0092] S2: sequentially writing the current accumulation result into the accumulator from the starting entry;

[0093] S3: obtaining an ending entry for writing the current accumulation result, and obtaining a latching entry of the current accumulation result based on the ending entry; and S4: latching the latching entry of the current accumulation result.

[0094] The application also provides a computer readable storage medium having a computer program stored thereon, the program being executed by a processor to implement the steps of the above method. The computer readable storage medium can include, but is not limited to, any type of disk, including a floppy disk, an optical disk, a DVD, a CD-ROM, a micro drive, and a magneto-optical disk, a ROM, a RAM, an EPROM, an EEPROM, a DRAM, a VRAM, a flash memory device, a magnetic card or an optical card, a nanosystem (including a molecular memory IC), or any type of medium or device suitable for storing instructions and / or data.

[0095] It should be noted that, for the foregoing method embodiments, in order to simply describe, they are all described as a series of action combinations, but those skilled in the art should know that the application is not limited to the action sequence described, because according to the application, certain steps can be performed in other sequences or simultaneously. Secondly, those skilled in the art should know that the embodiments described in the specification all belong to preferred embodiments, and the actions and modules involved are not necessarily necessary for the application.

[0096] In the above embodiments, the description of each embodiment has its own focus, and the parts not described in detail in a certain embodiment can be referred to the related description of other embodiments.

[0097] In several embodiments provided in the present application, it should be understood that the disclosed apparatus can be implemented in other manners. For example, the division of the apparatus embodiments described above is merely illustrative, and the division can be other manners in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between the units shown or discussed can be indirect coupling or communication connection through some interfaces, devices or units, and can be electrical, mechanical or other forms.

[0098] The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, i.e., they can be located in one place or distributed on multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the embodiment.

[0099] In addition, the functional units in each embodiment of the present application can be integrated into a processing unit, or each unit can be physically present separately, or two or more units can be integrated into one unit. The integrated unit can be realized in the form of hardware or in the form of a software functional unit.

[0100] If the integrated unit is realized in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer readable memory. Based on this understanding, the technical solutions of the present application essentially or the part of the prior art that contributes to the technical solutions or all or part of the technical solutions can be embodied in the form of a software product, which is stored in a memory and includes a plurality of instructions for causing a computer device (which can be a personal computer, a server or a network device, etc.) to execute all or part of the steps of the embodiments of the present application. The aforementioned memory includes: a U disk, a read-only memory (Read-Only Memory, ROM), a random access memory (Random Access Memory, RAM), a mobile hard disk, a magnetic disk or an optical disk, and various media that can store program codes.

[0101] Those of ordinary skill in the art can understand that all or part of the steps of the various methods in the above embodiments can be completed by a program instructing relevant hardware, and the program can be stored in a computer readable memory, which can include a flash disk, a read-only memory (Read-Only Memory, ROM), a random access memory (Random Access Memory, RAM), a magnetic disk or an optical disk, etc.

[0102] The above merely show example embodiments of the present disclosure, and cannot limit the scope of the present disclosure. That is, equivalent changes and modifications made in accordance with the teachings of the present disclosure are still within the scope of the present disclosure. Those skilled in the art will readily conceive of other implementations of the present disclosure upon considering the specification and practicing the disclosure herein. The present application is intended to cover any variations, uses, or adaptive changes of the present disclosure following the general principles of the present disclosure and including common knowledge or conventional technical means in the art not described in the present disclosure. The specification and examples are merely considered as exemplary, and the scope and spirit of the present disclosure are defined by the claims.

Claims

1. An accumulator hardware implementation method supporting continuous write of accumulation results, characterized in that, The method comprises the following steps: S1: determining a starting entry in the accumulator based on the enable bit corresponding to the current accumulation result to which the current accumulation result is written; S2: sequentially writing the current accumulation result into the accumulator from the starting entry; S3: obtaining an ending entry to which the current accumulation result is written, and obtaining a latching entry of the current accumulation result based on the ending entry; S4: latching the latching entry of the current accumulation result; Step S1 specifically comprises: S11: identifying the enable bit corresponding to the current accumulation result, and obtaining the value of the enable bit; S12: if the value of the enable bit is 1, taking the previously latched latching entry in the accumulator as the starting entry of the current writing, and if the value of the enable bit is not 1, taking the target entry in the accumulator as the starting entry of the current writing.

2. The accumulator hardware implementation method of claim 1, wherein, Step S3 specifically comprises: S31: obtaining the number of buffered entries of the current accumulation result; S32: calculating the ending entry by using the number of buffered entries and the starting entry; S33: taking the entry pointed to by adding 1 to the ending entry as the latching entry of the current accumulation result.

3. The accumulator hardware implementation method of claim 1 or 2, wherein, Step S2 specifically comprises: S21: identifying the starting position corresponding to the starting entry in the accumulator; S22: obtaining the writing direction of the current accumulation result, and sequentially writing the current accumulation result into the accumulator from the starting position based on the writing direction.

4. An accumulator hardware implementation device that supports contiguous write of accumulation results, characterized by: The method comprises the following steps: The starting entry determination module is configured to determine a starting entry in the accumulator based on the enable bit corresponding to the current accumulation result to which the current accumulation result is written; The writing module is configured to sequentially store the current accumulation result in the accumulator from the starting entry; The latching entry determination module is configured to obtain an ending entry to which the current accumulation result is written, and obtain a latching entry of the current accumulation result based on the ending entry; The latching module is configured to latch the latching entry of the current accumulation result. The starting entry determination module comprises The enable bit determination unit is configured to identify the enable bit corresponding to the current accumulation result, and obtain the value of the enable bit; 5. An accumulator hardware implementation device supporting cumulative result continuous write-in as recited in claim 4, characterized by: The judging unit is configured to, if the value of the enable bit is 1, take the previously latched latching entry in the accumulator as the starting entry of the current writing, and if the value of the enable bit is not 1, take the target entry in the accumulator as the starting entry of the current writing. The latching entry determination module comprises: The statistical unit is configured to obtain the number of buffered entries of the current accumulation result; The first calculation unit is configured to calculate the ending entry by using the number of buffered entries and the starting entry; 6. An accumulator hardware implementation device supporting cumulative result continuous write-in as claimed in claim 4 or 5, characterized by, The second calculation unit is configured to take the entry pointed to by adding 1 to the ending entry as the latching entry of the current accumulation result. The writing module comprises The starting determination unit is configured to identify the starting position corresponding to the starting entry in the accumulator; 7. An electronic device comprising a memory, a processor, and a computer program stored on the memory and executable on the processor, characterized in that, The writing determination unit is configured to obtain the writing direction of the current accumulation result, and sequentially write the current accumulation result into the accumulator from the starting position based on the writing direction.

8. A computer-readable storage medium having stored thereon a computer program, characterized in that, The processor executes the computer program to implement the steps of the method according to any one of claims 1-3. The computer program is executed by the processor to implement the steps of the method according to any one of claims 1-3.

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