Compiling method for register overflow, electronic device and medium

Abstract

The application relates to the computer technical field, in particular to a compiling method for register overflow, an electronic device and a medium. The method is applied to the electronic device, and the method comprises the following steps: a compiler acquires a program to be compiled; the compiler compiles the program to be compiled to obtain an execution instruction; wherein the compiling of the program to be compiled by the compiler comprises the following steps: in response to register overflow of a first variable corresponding to a first register included in the program to be compiled, a variable part overflowing from the first register is allocated to a first storage unit corresponding to the first register; in response to register overflow of a second variable corresponding to a second register included in the program to be compiled, a variable part overflowing from the second register is allocated to a second storage unit corresponding to the second register. The method provided in the application can reduce time consumption caused by register overflow and improve program performance.

Description

Technical Field

[0001] This invention relates to the field of computer technology, and more specifically to a compilation method, electronic device, and medium for register overflow. Background Technology

[0002] Registers are storage areas within a processor (such as a central processing unit, CPU) used to store data (including instructions) read from memory and intermediate results of processor operations. Register allocation is a stage in the program compilation process, specifically during the Intermediate Representation (IR) stage, before executable code is output. During this stage, if the data storage demand exceeds the amount of data that a register can store or allocate, a register overflow occurs. Currently, register overflow typically results in the data exceeding the register's storage capacity being allocated to the electronic device's main memory. However, the access speed to main memory is lower than that to registers.

[0003] For example, the registers of an electronic device may include scalar registers and vector registers. When the data storage requirement exceeds the data capacity of the scalar register or vector register, a register overflow occurs. That is, the portion of the data exceeding the capacity of the scalar register or vector register is allocated to the stack of the electronic device's main memory. When the processor executes this portion of data, it needs to read this portion of the data from the main memory.

[0004] As can be seen, the above-mentioned compilation method for register overflow will increase the main memory access time when executing instructions, and since the main memory access speed is low, it will affect program performance. Summary of the Invention

[0005] To address the issue of register overflow affecting program performance, embodiments of this application provide a compilation method, electronic device, and medium for handling register overflow.

[0006] In a first aspect, embodiments of this application provide a compilation method for register overflow, applied to an electronic device, wherein the electronic device is equipped with a compiler, and the electronic device includes a plurality of registers, a first storage unit, and a second storage unit located in a processor; and the method includes:

[0007] The compiler obtains the program to be compiled;

[0008] The compiler compiles the program to be compiled to obtain executable instructions;

[0009] The compilation of the program to be compiled by the compiler includes:

[0010] If the first register corresponding to the first variable included in the program to be compiled overflows, the variable portion overflowing from the first register is allocated to the first storage unit corresponding to the first register.

[0011] If the second register corresponding to the second variable included in the program to be compiled overflows, the overflowed variable portion of the second register is allocated to the second storage unit corresponding to the second register;

[0012] The processor accesses the first storage unit and the second storage unit at different speeds.

[0013] It is understood that in some embodiments, the electronic device may further include a third storage unit, and if a third register corresponding to a third variable included in the program to be compiled overflows, the compiler can allocate the overflowed variable portion of the third register to the third storage unit corresponding to the third register. The processor's access speed to the third storage unit may differ from that to the first and second storage units, or the processor's access speed to the third storage unit may be the same as that to the first or second storage unit. That is, the registers in the embodiments of this application are not limited to the aforementioned first and second registers, and the storage units of the electronic device are not limited to the first and second storage units.

[0014] The compilation method for register overflow provided in this application allocates the variable overflowing from the first register to the first storage unit and the variable overflowing from the second register to the second storage unit. That is, different register overflow variables are allocated to different storage units, instead of uniformly allocating the register overflow variables to the main memory of the electronic device. This can reduce the time spent accessing the first register and the variable overflowing from the second register each time, reduce the time overhead caused by register overflow, and improve program performance.

[0015] In one possible implementation of the first aspect described above, the first register is a vector register and the second register is a scalar register.

[0016] In one possible implementation of the first aspect above, if the first register corresponding to the first variable included in the program to be compiled overflows, the overflowed variable portion of the first register is allocated to the first storage unit corresponding to the first register, including:

[0017] The compiler determines that the first register has overflowed and determines the first register category corresponding to the first register;

[0018] The compiler determines the first memory unit corresponding to the first register class based on the first register class;

[0019] The compiler allocates the variable portion that overflows from the first register to the first storage unit corresponding to the first register class.

[0020] In one possible implementation of the first aspect above, if the second register corresponding to the second variable included in the program to be compiled overflows, the overflowed variable portion of the second register is allocated to the second storage unit corresponding to the second register, including:

[0021] The compiler determines that the second register has overflowed and determines the second register category corresponding to the second register;

[0022] The compiler determines the second memory unit corresponding to the second register class based on the second register class.

[0023] The compiler allocates the variable portion that overflows from the second register to the second storage unit corresponding to the second register class.

[0024] In one possible implementation of the first aspect described above, the first register category and the second register category are determined based on the access frequency of the plurality of registers.

[0025] In one possible implementation of the first aspect described above, the processor accesses the first register of the first register category more frequently than it accesses the second register of the second register category, and the processor accesses the first memory unit at a higher speed than it accesses the second memory unit.

[0026] In one possible implementation of the first aspect described above, the electronic device includes a processor, the first storage unit is a storage unit located within the processor, and the second storage unit is an external storage unit located outside the processor.

[0027] It is understood that, in the embodiments of this application, for registers of a higher usage frequency, the use of processor-dedicated storage units with faster access speeds can reduce the time spent accessing the overflowing data of such registers each time. Furthermore, since these registers are used frequently, meaning most data is stored in these registers, the time overhead caused by register overflows can be reduced, thus improving program performance. For registers of a lower usage frequency, the speed of access to the storage unit has a lower impact on program performance, and the overflowing data can be stored in main memory with slower access speeds.

[0028] In one possible implementation of the first aspect described above, the first storage unit is a static random access memory (SRAM) and the second storage unit is a double-rate synchronous dynamic random access memory (DRAM).

[0029] In one possible implementation of the first aspect described above, the first storage unit includes a first stack storage area;

[0030] The compiler allocates the variable portion overflowing from the first register to the first storage unit corresponding to the first register, including:

[0031] The compiler allocates the variable portion of the first register overflow to the first stack storage area, wherein the variable portion of the first register overflow is stored in the first stack storage area in a stack manner.

[0032] In one possible implementation of the first aspect described above, the second storage unit includes a second stack storage area;

[0033] The compiler allocates the variable portion overflowing from the second register to the second storage unit corresponding to the second register, including:

[0034] The compiler allocates the variable portion of the second register overflow to the second stack storage area, wherein the variable portion of the second register overflow is stored in the second stack storage area in a stack manner.

[0035] It is understandable that different register overflow variables are stored in stack storage areas with different storage units, so that the overflow data of the same type of register is stored in the same storage unit. The length difference between the stored values ​​of the same type of register is small, the bubble is small, and the utilization rate of stack storage area is high.

[0036] In one possible implementation of the first aspect above, the compiler allocates the variable portion of the first register overflow to the first storage unit corresponding to the first register, including:

[0037] The compiler allocates the variable portion that overflowed from the first register to the first storage unit;

[0038] The compiler inserts a register overflow instruction into the variable portion of the first register that overflows;

[0039] The compiler allocates the variable portion overflowing from the second register to the second storage unit corresponding to the second register, including:

[0040] The compiler allocates the overflow portion of the variable from the second register to the second storage unit;

[0041] The compiler inserts a register overflow instruction into the variable portion of the second register that overflows.

[0042] Secondly, embodiments of this application provide a compilation apparatus for register overflow, applied to an electronic device, wherein the electronic device is equipped with a compiler, and the electronic device includes a plurality of registers, a first storage unit, and a second storage unit located in a processor; and the apparatus includes:

[0043] The program acquisition module is used by the compiler to acquire the program to be compiled;

[0044] The program compilation module is used by the compiler to compile the program to be compiled into executable instructions;

[0045] The program compilation module is used by the compiler to compile the program to be compiled, specifically for:

[0046] If the first register corresponding to the first variable included in the program to be compiled overflows, the variable portion overflowing from the first register is allocated to the first storage unit corresponding to the first register.

[0047] If the second register corresponding to the second variable included in the program to be compiled overflows, the overflowed variable portion of the second register is allocated to the second storage unit corresponding to the second register;

[0048] The processor accesses the first storage unit and the second storage unit at different speeds.

[0049] Thirdly, embodiments of this application provide an electronic device, including one or more processors; one or more memories; and one or more memories storing one or more programs, which, when executed by one or more processors, cause the electronic device to execute the above-described compilation method for register overflow.

[0050] Fourthly, embodiments of this application provide a computer-readable storage medium storing instructions that, when executed on a computer, cause the computer to perform the aforementioned compilation method for register overflow.

[0051] Fifthly, embodiments of this application provide a computer program product, which includes instructions that, when executed, cause a computer to perform the above-described compilation method for register overflow. Attached Figure Description

[0052] Figure 1 The diagram shows an application scenario of a compilation method for register overflow.

[0053] Figure 2 The diagram shown is a schematic representation of a stack storage area provided in an embodiment of this application.

[0054] Figure 3a The diagram shown is a schematic representation of a stack space provided in an embodiment of this application.

[0055] Figure 3b The diagram shown is a schematic diagram of another stack space structure provided in an embodiment of this application;

[0056] Figure 4 The diagram shown is a flowchart of a compilation method for register overflow provided in an embodiment of this application;

[0057] Figure 5 The diagram shown is a flowchart of another compilation method for register overflow provided in an embodiment of this application;

[0058] Figure 6 The image shown is a schematic diagram of a compiled program code provided in an embodiment of this application;

[0059] Figure 7 The diagram shown is a schematic representation of an electronic device for a compilation method for register overflow provided in an embodiment of this application.

[0060] Figure 8 The diagram shown is a schematic of a program module of a compiler for register overflow provided in an embodiment of this application. Detailed Implementation

[0061] The illustrative embodiments of this application include, but are not limited to, a compilation method, electronic device, and medium for register overflow. The embodiments of this application will now be described in further detail with reference to the accompanying drawings.

[0062] In the following description, numerous technical details are presented to enable the reader to better understand the present invention. However, those skilled in the art will understand that the technical solutions claimed in the claims of the present invention can be implemented even without these technical details and with various variations and modifications based on the following embodiments.

[0063] To better understand the solutions of the embodiments of this application, the relevant terms and concepts that may be involved in the embodiments of this application will be introduced below.

[0064] Static Random Access Memory (SRAM) uses transistors to store information. Once power is lost, all data is lost; however, as long as power is supplied, the data persists without dynamic refreshing. SRAM offers fast read and write speeds without the need for refreshing, but it is expensive and has a small capacity. It is generally used as the internal RAM (Random Access Memory) of a System-on-Chip (SOC).

[0065] Double Data Rate Synchronous Dynamic Random Access Memory (DDR) is synchronized with the system bus speed, i.e., the system clock. It ensures data integrity through continuous refresh, allowing reading and writing of data at any address, and transmitting data twice per clock cycle. DDR features high integration density, low power consumption, low cost, and is suitable for large-capacity storage. It is typically used as a cache or internal RAM in microcontroller units (MCUs).

[0066] Compilation: Compilation is the process of converting user programs (usually written in a high-level source language, or source files) into intermediate representations (IR), and performing multiple transformations on the IR to finally generate the corresponding target language code (usually assembly code or binary executable code oriented towards the target architecture).

[0067] A compiler is software that translates computer code written in one programming language (source language) into another language (target language). It generally consists of three parts: front-end, middleware, and back-end.

[0068] Scalar register: A register used to perform scalar calculations.

[0069] Vector register: A register used to perform vector calculations. Generally, it is wider than a scalar register; one vector is equivalent to several scalars.

[0070] Physical registers: The actual registers that exist in the target architecture (or target chip), which can include scalar registers and vector registers.

[0071] Intermediate Representation (IR): This refers to the internal representation generated by the compiler after scanning the source program. It represents the semantics and syntactic structure of the source program. Each stage of the compiler analyzes or optimizes the intermediate representation. For example, in a compiler where the front-end input language is OpenCL and the target platform's assembly code is assembly language, the intermediate representation is the process of converting the source code from OpenCL to assembly language, and can be implemented using an intermediate representation. The intermediate representation can be an abstract syntax tree, reverse Polish notation, or 3-address code, etc. IR is divided into multiple levels. Higher-level IR (closer to the source language program) may not have virtual registers, only variables; while lower-level IR (closer to the target machine) may not have variables, only virtual and physical registers.

[0072] Virtual register: A number assigned to an operand in the source file during compilation. During the translation from a higher-level IR to a lower-level IR, the concept of a "variable" is mapped to the concept of a "virtual register." There can be an unlimited number of virtual registers, but they are ultimately mapped to a finite number of physical registers on the target machine.

[0073] Register allocation: The process of mapping virtual registers to physical registers. Register allocation improves program execution speed by allocating as many virtual registers as possible to physical registers, that is, by having as many variables reside in registers as possible.

[0074] Register overflow: When register allocation occurs and the number of physical registers is insufficient, the value currently in the register is moved to the address space of another memory location (usually the stack storage area on main memory), and then retrieved from that address space when needed. Specifically, for any overflowing variable, a (store) instruction is inserted after each definition of the variable, and a (load) instruction is inserted before each use of the variable.

[0075] As mentioned earlier, existing compilation methods for register overflow in the technology increase the main memory access time during instruction execution, and because the main memory access speed is low, it will affect program performance.

[0076] For example, refer to Figure 1 As shown, the electronic device 10 includes a compiler 100, a DDR 200, and a processor 300. The compiler 100 reads the program from the DDR 200 (main memory) and allocates the compiled data to the registers of the processor 300.

[0077] It is understood that processor 300 may include application processor (AP), modem processor, graphics processing unit (GPU), image signal processor (ISP), controller, video codec, digital signal processor (DSP), baseband processor, and / or neural network processing unit (NPU), etc. Processor 300 may also include CPU, GPU, etc.

[0078] Specifically, after reading the program from DDR 200, compiler 100 compiles the program and outputs an assembly file or binary file executable by processor 300. During the program compilation stage, compiler 100 can allocate data to the corresponding registers according to data type. For example, compiler 100 can allocate scalar data to scalar register 301 of processor 300 and vector data to vector register 302 of processor 300.

[0079] Furthermore, the compiler can pre-allocate overflow data for each register. That is, when a register overflows, the overflowed data is stored in the pre-allocated memory. For example, compiler 100 can allocate overflow data from scalar register 301 to DDR 200. Then, when processor 300 executes the compiled program, if scalar register 301 is full and there is still scalar data to be stored in scalar register 301, that portion of scalar data will be stored in DDR 200. Similarly, compiler 100 can allocate overflow data from vector register 302 to DDR 200. Then, when processor 300 executes the compiled program, if vector register 302 is full and there is still vector data to be stored in vector register 302, that portion of vector data will be stored in DDR 200. Furthermore, when the processor 300 executes the compiled program and needs to process the overflowed scalar or vector data, the processor 300 needs to read the overflowed scalar or vector data from the DDR 200.

[0080] As can be seen, current compilation methods for register overflow mainly store the overflow data in the main memory of the electronic device. However, when the processor 300 processes the data stored in the register, it needs to access the main memory by reading data from the DDR 200. Since the access speed of the DDR 200 is low (one access to main memory takes tens to hundreds of cycles), the speed at which the processor 300 executes the program is reduced, thereby increasing the time overhead of the processor 300 in executing the program and affecting program performance.

[0081] Therefore, this application provides a compilation method for register overflow detection, applicable to electronic devices. In the embodiments of this application, considering the different access frequencies of different registers by the processor, and the different access speeds of the processor to different memory locations (e.g., faster access to dedicated memory on the processor and slower access to the main memory of the electronic device), the compiler can classify the registers on the processor based on the access information of each register to determine the categories of multiple registers and the correspondence between each register category and each memory location.

[0082] Thus, during the compilation phase where the compiler allocates registers to the program to be compiled, the target registers corresponding to the data in the program to be compiled are first determined. Then, based on the amount of data in the program to be compiled and the amount of data that the register can store, it is determined whether there is an overflow in the target register. If an overflow occurs, the category of the target register is obtained. Based on the correspondence between the categories of registers and the memory units, the memory units corresponding to the category of the target register are determined. The amount of data in the program to be compiled that corresponds to the amount of data that the target register can store is allocated to the target register. The overflow data (data in the program to be compiled that exceeds the amount of data that the register can store) is allocated to the memory units corresponding to the category of the target register. If it is determined that there is no overflow in the target register, all the data in the program to be compiled is allocated to the target register.

[0083] It's understandable that the method to determine if the target register is overflowing is as follows: if the amount of data in the program to be compiled is less than or equal to the amount of data the register can store, then the target register will not overflow. If the amount of data in the program to be compiled is greater than the amount of data the register can store, then the target register will overflow.

[0084] It is understandable that access information can include the frequency of data access to the register (i.e., the frequency of register usage), and different registers have different usage frequencies.

[0085] In some embodiments, the register categories may include a high-frequency use class and a low-frequency use class.

[0086] The storage units of an electronic device may include: dedicated storage units for processors with faster access speeds (e.g., dedicated SRAM unit 303) and main memory with slower access speeds (e.g., DDR 200).

[0087] In this process, the electronic device categorizes the registers on the processor based on the access information of each register to determine the types of multiple registers, which may include:

[0088] Registers whose usage frequency exceeds a set threshold are classified as high-frequency registers, while those whose usage frequency is less than or equal to the set threshold are classified as low-frequency registers. The set threshold can be set according to the processor model or function of the electronic device and is not limited here. For example, in an Artificial Intelligence (AI) accelerator, which mainly processes image, audio, and video data, the vector registers on the processor in the AI ​​accelerator have a high usage frequency, exceeding the set threshold, so they belong to the high-frequency register category. Scalar registers, on the other hand, have a low usage frequency, less than or equal to the set threshold, so they belong to the low-frequency register category. It is understood that the above-described scalar and vector registers are just one example in the embodiments of this application; the processor of the electronic device may include more or fewer registers than described above, and this application does not impose any limitations on this.

[0089] In other embodiments, the register categories can be divided in other ways, such as dividing the register categories into three types: the most frequently used category, the relatively frequently used category, and the least frequently used category. Then, registers whose usage frequency is greater than a first set threshold are classified as the most frequently used category, registers whose usage frequency is less than the first set threshold but greater than a second set threshold are classified as the relatively frequently used category, and registers whose usage frequency is less than the second set threshold are classified as the least frequently used category, etc.

[0090] Of course, the above-mentioned methods for classifying and determining the types of registers are only some examples of the methods for classifying and determining the types of registers in this application, and not all of them.

[0091] Determining the memory location corresponding to each register data category may include: determining that the memory location corresponding to the register with higher usage frequency is a dedicated memory location of the processor with faster access speed (e.g., dedicated SRAM cell 303), and determining that the memory location corresponding to the register with lower usage frequency is the main memory with slower access speed (e.g., DDR 200).

[0092] In this embodiment, the above method is used to determine the storage unit corresponding to the register category. Therefore, for registers of a higher usage frequency, the use of processor-dedicated storage units with faster access speeds reduces the time spent accessing overflowing data in each instance. Furthermore, since these registers are used frequently, meaning most data is stored in these registers, the time overhead caused by register overflows is reduced, improving program performance. For registers of a lower usage frequency, the speed of access to the storage unit has a lower impact on program performance, and overflowing data can be stored in main memory with slower access speeds.

[0093] In some embodiments, the same register category can correspond to multiple registers, and thus the same storage unit can also store overflow data from multiple registers. For example, the processor's registers include vector registers, tensor registers, and scalar registers. Since tensor registers and vector registers are both high-frequency registers, they can use the same storage unit (e.g., a dedicated storage unit for the processor) to store their overflow data, while scalar registers use other storage units (e.g., main memory) to store their overflow data.

[0094] In some embodiments, stacked storage areas may be provided in each storage unit of the electronic device (e.g., Figure 2 The overflow data of the register can be stored through the stack storage area 201 of the DDR 200 and the stack storage area 202 of the dedicated SRAM unit 303.

[0095] This application embodiment uses register-based access information to store overflow data from different registers in different storage units, which can reduce access to main memory caused by register overflow during program execution, reduce the time overhead caused by register overflow, and thus improve program performance.

[0096] Furthermore, because different registers store values ​​of varying lengths, using the same stack storage area to store register overflow data introduces bubbles into the stack storage area, reducing stack space utilization. For chips requiring memory address alignment, the greater the length difference between the values ​​stored in different types of registers, the larger the bubble and the lower the stack storage area utilization. For example, each value stored in a scalar register requires 32 bits of stack storage, while each value stored in a vector register requires 128 to 512 bits, resulting in a bubble of up to 480 bits. Based on the above solution, the overflow data from registers of the same type is stored in the same memory cell, and the length difference between the values ​​stored in registers of the same type is small, resulting in smaller bubbles and higher stack storage area utilization.

[0097] It is understood that different storage units correspond to different storage components in electronic devices. Taking an electronic device as an AI accelerator as an example, its storage module may include dedicated storage units on the processor (e.g., dedicated SRAM units) and the main memory of the AI ​​accelerator (e.g., DDR). The processor can read programs from the main memory for the AI ​​accelerator's compiler to compile. The compiler then temporarily stores the compiled executable instructions in the processor's dedicated storage units, allowing the processor to execute the corresponding instructions by accessing these dedicated storage units. In some embodiments, the AI ​​accelerator may also include dedicated storage units of the processor and other storage components besides the main memory; this application does not impose any limitations on this.

[0098] In some embodiments, the corresponding register data overflow storage unit is determined based on the register access information, that is, the storage unit corresponding to the overflow data is determined based on the frequency of register usage. For example, for vector registers and scalar registers in an AI accelerator, since vector registers are used more frequently, the overflow data of vector registers is determined to be allocated to a dedicated storage unit of the processor with faster access speed (e.g., a dedicated SRAM unit), while scalar registers are used less frequently, so the overflow data of scalar registers is determined to be allocated to main memory with slower access speed (e.g., DDR).

[0099] It is understood that electronic devices include, but are not limited to, mobile phones, netbooks, tablets, smartwatches, or other desktop devices, laptop devices, handheld devices, wearable devices, smart home devices, and in-vehicle devices, such as Ultra-mobile Personal Computers (UMPCs), smart cameras, netbooks, Personal Digital Assistants (PDAs), Portable Multimedia Players (PMPs), AR (Augmented Reality) / VR (Virtual Reality) devices, aircraft, robots, etc. Electronic devices can also be accelerators within terminal devices (mobile phones, tablets, laptops), such as AI accelerators. This application does not limit the specific type and structure of the electronic devices.

[0100] Continue to refer to Figure 1 The compilation method for register overflow in the embodiments of this application will be further described.

[0101] The compiler 100 reads the program from DDR 200 (main memory) and stores the compiled executable instructions in the registers of the processor 300. Specifically, after reading the program from DDR 200, the compiler 100 compiles the program and allocates the data to different registers on the processor 300 according to the data type.

[0102] In some embodiments, the registers of the processor 300 include a scalar register 301 and a vector register 302. When compiling the main function, the compiler 100 can first determine the allocation of each register, that is, determine that the compiled scalar data is allocated to the scalar register 301 of the processor 300, and the vector data is allocated to the vector register 302 of the processor 300. Simultaneously, the compiler 100 determines the category of each register based on its access information (e.g., usage frequency), and then allocates the storage location for the overflow data of each register according to the register category. Specifically, for vector registers with higher usage frequency, they are determined to be high-frequency registers, and therefore, when a register overflow occurs, the overflow data is allocated to the faster-access dedicated SRAM cell 303. For scalar registers with lower usage frequency, they are determined to be low-frequency registers, and therefore, when a register overflow occurs, the overflow data is allocated to the slower-access DDR 200.

[0103] Furthermore, when the processor 300 executes the compiled executable instructions, if the scalar register 301 becomes full and there is still scalar data that needs to be stored in the scalar register 301, a register overflow will occur, and the overflowed scalar data will be stored in DDR 200. Similarly, if the vector register 302 becomes full and there is still vector data that needs to be stored in the vector register 302, a register overflow will occur, and the overflowed vector data will be stored in the dedicated SRAM unit 303. Further, when the processor 300 executes subsequent instructions, if it encounters overflowed scalar data, it needs to read the overflowed scalar data from DDR 200; if it encounters overflowed vector data, it needs to read the overflowed vector data from the dedicated SRAM unit 303.

[0104] In some embodiments, in order for the compiler 100 to automatically allocate storage space and storage location for register overflow data in a dedicated storage unit (e.g., a dedicated SRAM unit) or a DDR unit, a corresponding stack storage area can be set in the dedicated SRAM unit or DDR unit as the stack space of that storage unit. For example, Figure 2As shown, a DDR stack storage area 201 is set in the storage cell of DDR200, and an SRAM stack storage area 202 is set in the storage cell of dedicated SRAM cell 303. Furthermore, overflow data from scalar register 301 can be stored in the DDR stack storage area 201 of DDR200, and overflow data from vector register 302 can be stored in the SRAM stack storage area 202 of dedicated SRAM cell 303.

[0105] For example, in some embodiments, the data storage structure of the stack storage area can be as follows: Figure 3a As shown, this data storage structure is the stack space of the storage unit. In the stack space, data can only be inserted and deleted at one end of the data structure (i.e., the top of the stack), and data follows the Last-In-First-Out (LIFO) principle. It can be understood that the stack pointer SP points to the top of the stack space.

[0106] When overflow data needs to be stored in the stack storage area, the `pushq` instruction can be used, for example, to store the overflow data in the stack storage area. The compiler will calculate the total stack space required for the overflow data, and the address pointed to by the stack pointer `SP` will be reduced by a corresponding amount based on the calculation result. Then, based on the offset of the overflow data relative to `SP`, the program variables will be pushed onto the stack storage area sequentially. It can be understood that after storing data, the stack space will grow downwards. Each increase in space corresponds to the stack frame of the stored program. For example, if new overflow data needs to be stored after data 5, and the new overflow data includes data 6, the processor will, based on the storage space and location allocated by the compiler for the new overflow data, reduce the stack pointer `SP` by a certain amount and store the data 6 from the new overflow data into the stack storage area, as shown below. Figure 3b As shown. At this point, the stack pointer SP points to the top of the stack space.

[0107] It's understandable that when the processor confirms that the instruction corresponding to data 6 has been executed, it can release the stack space corresponding to that instruction. For example, for an instruction whose input includes data 6, once the instruction has been executed and the processor confirms that the instruction contains data 6, it will release the stack space corresponding to data 6.

[0108] The following is combined with Figure 4 Taking a mobile phone as an example, the compilation method for register overflow in the embodiments of this application will be further described.

[0109] Figure 4 The diagram shown is a flowchart of a compilation method for register overflow provided in an embodiment of this application.

[0110] like Figure 4 As shown, the method includes the following steps:

[0111] 401: Compiler 100 determines the type of each register and the corresponding memory unit based on the access information of each register.

[0112] It can be understood that register access information can include the frequency of data access to the register, i.e., the frequency of register usage. Registers can include scalar registers and vector registers, etc.

[0113] It is understandable that different storage units correspond to different storage components in an electronic device. The storage units of an electronic device may include dedicated storage units for a processor with faster access speeds (e.g., dedicated SRAM unit 303) and main memory with slower access speeds (e.g., DDR 200). It may also include other external memory with even slower access speeds.

[0114] In some embodiments, the compiler 100 determines the category of each register based on its usage frequency, and then allocates the storage unit required to store its overflow data according to the category of each register. For example, for a processor 300 including a vector register 302 and a scalar register 301, the vector register 302 is used frequently, therefore, the vector register 302 is determined to be a high-frequency register, and the storage unit corresponding to the high-frequency register is determined to be a dedicated storage unit of the processor 300 (e.g., a dedicated SRAM unit 303), that is, the overflow data of the vector register 302 is allocated to the dedicated storage unit of the processor 300 (e.g., a dedicated SRAM unit 303); the scalar register 301 is used less frequently, therefore, the scalar register 301 is determined to be a low-frequency register, and the storage unit corresponding to the low-frequency register is determined to be a main memory with slower access speed (e.g., DDR 200), that is, the overflow data of the scalar register 301 is allocated to the main memory with slower access speed (e.g., DDR 200).

[0115] In other embodiments, the register categories can be divided in other ways, such as dividing the register categories into three types: the most frequently used category, the relatively frequently used category, and the least frequently used category. Then, registers whose usage frequency is greater than a first set threshold are classified as the most frequently used category, registers whose usage frequency is less than the first set threshold but greater than a second set threshold are classified as the relatively frequently used category, and registers whose usage frequency is less than the second set threshold are classified as the least frequently used category, etc.

[0116] Of course, the above-mentioned methods for classifying and determining the types of registers are only some examples of the methods for classifying and determining the types of registers in this application, and not all of them.

[0117] In some embodiments, the same register category can correspond to multiple registers, and thus the same storage unit can also store overflow data from multiple registers. For example, the processor's registers include vector registers, tensor registers, and scalar registers. Since tensor registers and vector registers are both high-frequency registers, they can use the same storage unit (e.g., a dedicated storage unit for the processor) to store their overflow data, while scalar registers use other storage units (e.g., main memory) to store their overflow data.

[0118] In some embodiments, the data overflowing from the register can be stored in a stacked manner in the stack storage area of ​​the corresponding memory cell. For example, the data overflowing from the scalar register 301 is stored in the DDR stack storage space 201 of the DDR 200, and the data overflowing from the vector register 302 is stored in the SRAM stack storage space 202 of the dedicated SRAM cell 303.

[0119] In some embodiments, different stack storage regions can be distinguished by different stack IDs. Further, when the processor 200 determines the memory unit corresponding to its overflow data based on the register access information, it can determine the stack ID corresponding to the overflow data of each register. For example, for vector register 302, the stack ID of the SRAM stack storage region in its corresponding dedicated SRAM unit 303 can be determined. Therefore, when the compiler determines that vector register 302 has overflowed, it can allocate the overflowed data of vector register 302 to the SRAM stack storage region of dedicated SRAM unit 303 according to the stack ID corresponding to vector register 302. For scalar register 301, the stack ID of the DDR stack storage region in its corresponding DDR 200 can be determined. Therefore, when the compiler determines that scalar register 301 has overflowed, it can allocate the overflowed data of scalar register 301 to the DDR stack storage region of DDR 200 according to the stack ID corresponding to scalar register 301. For example, the stack ID of the DDR stack storage region is 0, and the stack ID of the SRAM stack storage region is 1. In step 401, it can be determined that the data overflowing from scalar register 301 is stored in the DDR stack storage area with stack ID 0, and the data overflowing from vector register 303 is stored in the SRAM stack storage area with stack ID 1.

[0120] It is understandable that the DDR stack storage area and the SRAM stack storage area are the same in terms of stack frame management, except that the stack ID is different and is used for storing SRAM variables and non-SRAM variables.

[0121] 402: Compiler 100 acquires and compiles the program to be compiled, and while compiling the program to be compiled, compiler 100 determines the target register corresponding to the data to be stored in the program to be compiled.

[0122] It is understandable that the program to be compiled contains instructions written in a high-level language, such as C or C++.

[0123] It is understandable that the data to be stored in the program to be compiled includes variables. The compiler 100 determines the register corresponding to the data to be stored in the program to be compiled by determining the type of the variable to be stored in the program and determining the register corresponding to the variable based on the variable type. For example, for a scalar variable, its corresponding destination register is determined to be a scalar register, and for a vector variable, its corresponding destination register is determined to be a vector register.

[0124] In some embodiments, when compiling a program, the compiler 100 may first convert the program into an intermediate representation, such as an abstract syntax tree, reverse Polish notation, or 3-address code. During this process, the compiler 100 may perform register allocation. Specifically, the compiler 100 may map variables in the program to virtual registers and then determine the corresponding physical register (i.e., the target register).

[0125] 403: Determine if there is an overflow in the target register.

[0126] It is understandable that when storing a variable into the corresponding register, step 403 needs to be executed to determine whether the target register has an overflow condition. If it does, it means that a register overflow will occur when storing the variable into the target register again, and the variable needs to be stored into the memory unit corresponding to the target register, i.e., step 404 needs to be executed. If there is no overflow condition, it means that the target register can still store the variable, and the variable can be directly stored into the target register, i.e., step 405 needs to be executed.

[0127] It's understandable that the method to determine if the target register is overflowing is as follows: if the amount of data in the program to be compiled is less than or equal to the amount of data the register can store (i.e., a preset storage threshold), then the target register will not overflow. If the amount of data in the program to be compiled exceeds the amount of data the register can store, then the target register will overflow.

[0128] In some embodiments, step 403 determines whether the target register has overflowed. Specifically, the compiler 100 determines that the storage space of the physical register corresponding to the virtual register has been fully allocated, marks the virtual register as "overflowing," and determines that the physical register (i.e., the target register) has overflowed. Further, when it is determined that the target register has overflowed, overflow code is inserted after the definition of the corresponding overflowing variable. The overflow code will be described below and will not be elaborated here.

[0129] 404: Compiler 100 determines the target class of the target register and the target storage unit corresponding to the target class, allocates the data corresponding to the data volume that can be stored in the target register to the target register, and allocates the overflow data to the corresponding target storage unit.

[0130] It is understandable that overflow data can refer to the portion of the data to be allocated that exceeds the amount of data that the register can store.

[0131] For example, if a register can store 300 MB of data and the amount of data to be allocated is 350 MB, then 300 MB of the data to be allocated can be allocated to the target register, while the 50 MB of data exceeding the register's storage capacity can be allocated to the target memory unit.

[0132] When the remaining part of the data to be allocated overflows due to insufficient register storage space, the data can be used as the overflowed part of the target register, that is, the data can be allocated to the target storage unit corresponding to the target class of the target register.

[0133] In some embodiments, if the overflowed data of the target register is allocated to the stack storage area of ​​the target storage unit, then in step 404, the target storage unit corresponding to the target category is determined, that is, the stack ID corresponding to the target category is determined, and then the overflowed data of the target register is allocated to the stack storage area corresponding to the stack ID.

[0134] 405: Compiler 100 allocates the data to be allocated to the target register.

[0135] It is understandable that after a compiler completes the compilation of a program, it obtains instructions that an electronic device can execute, such as assembly language instructions.

[0136] This application embodiment uses register-based access information to store overflow data from different registers in different storage units, which can reduce access to main memory caused by register overflow during program execution, reduce the time overhead caused by register overflow, and thus improve program performance.

[0137] Furthermore, since the lengths of values ​​stored in different registers vary, using the same stack storage area to store register overflow data can introduce bubbles into the stack storage area, reducing stack space utilization. In this embodiment, different storage units are used to store overflow data from different registers, and register values ​​of different lengths are stored in different storage units, which can improve the utilization of the stack storage area of ​​each storage unit.

[0138] The following example uses a processor 300 that includes a scalar register 301 and a vector register 302. The register categories include frequently used and infrequently used classes, and overflowing data is stored in the stack storage area of ​​the corresponding memory unit. Figure 5 The present application will further describe a compilation method for register overflow in an embodiment of this application.

[0139] Figure 5 The image shows a compilation method for register overflow provided in an embodiment of this application.

[0140] like Figure 5 As shown, the method includes:

[0141] 501: Compiler 100 determines that scalar register 301 is classified as a low-frequency class and vector register 302 is classified as a high-frequency class based on the frequency of use of scalar register 301 and vector register 302.

[0142] It is understandable that since the processor uses vector register 302 more frequently than scalar register 301, scalar register 301 is classified as a less frequently used class, while vector register 302 is classified as a more frequently used class.

[0143] 502: Compiler 100 determines that the memory unit corresponding to the less frequently used class register is DDR 200, and determines that the memory unit corresponding to the more frequently used class register is dedicated SRAM unit 303.

[0144] It is understandable that the processor accesses less frequently used registers less often, so the variables that overflow from the less frequently used registers can be stored in the main memory (i.e., DDR 200) of the electronic device, which has a slower access speed. The processor accesses more frequently used registers more often, so the variables that overflow from the more frequently used registers can be stored in the processor's dedicated memory unit (i.e., dedicated SRAM unit 303), which has a faster access speed.

[0145] In some embodiments, the main memory of the electronic device can be other types of storage units, and variables that overflow from registers with lower frequency of use can be stored in these storage units instead of DDR 200. In some embodiments, the dedicated storage units of the processor of the electronic device are storage units other than dedicated SRAM units, and variables that overflow from registers with higher frequency of use are stored in the corresponding dedicated storage units instead of dedicated SRAM units. This application does not impose any limitations on this.

[0146] 503: Compiler 100 retrieves and compiles the program to be compiled.

[0147] It can be understood that compiling a program means converting a program from a high-level programming language that is not readable by the computer into machine language that is readable by the computer.

[0148] 504: Compiler 100 completes the initialization of the stack pointer and dual-stack information.

[0149] It is understood that the initialization of the stack pointer includes the initialization of the stack pointer of the SRAM stack storage area 202 of the dedicated SRAM unit 302, and the initialization of the stack pointer of the DDR stack storage area 201 of the DDR 200.

[0150] In some embodiments, the stack pointer is initialized when the compiler 100 begins compiling the main function of the program to be compiled. For example, for a C language program, the stack pointer is initialized when the compiler 100 begins compiling the main function of the program to be compiled.

[0151] In some embodiments, each stack pointer of a stack storage region has its corresponding stack pointer address register, and the highest address of the stack storage region is assigned to the corresponding stack pointer address register. Further, in some embodiments, the initialization of the stack pointer is the initialization of the stack pointer of the SRAM stack storage region of the dedicated SRAM unit. The initialization of the stack pointer of the DDR stack storage region of DDR 200 can be performed by the processor, without the need for compiler 100.

[0152] It is understood that in some embodiments, dual-stack information initialization includes the initialization of stack information in the SRAM stack storage area 202 of the dedicated SRAM unit 302, and the initialization of stack information in the DDR stack storage area 201 of the DDR 200. The stack information includes the stack ID of the stack storage area, the current usage of the stack storage area, a mapping table between the stack storage area and register types, and a linked list of overflow variables for the stack storage area.

[0153] It is understandable that the dual-stack information is generated by compiler 100 when compiling the program to be compiled, and the purpose of generating dual-stack information is for compiler 100 to use. It is stored in the corresponding file of the compiler and is not stored in the same location as the program to be compiled.

[0154] In some embodiments, the initialization of dual-stack information is performed when the compiler 100 starts compiling a function, which can be done when compiling the main function or when compiling a sub-function.

[0155] In some embodiments, before initializing the dual-stack information, corresponding storage space needs to be allocated for it. The current stack storage area usage is initialized to zero. The mapping table between stack storage areas and register types represents the correspondence between stack storage areas and register types, and the overflow variable list of the stack storage area represents the variables that can be stored in the registers. For example, in a function containing scalar variables x and y, the overflow variable list of the DDR stack storage area corresponding to DDR 200 of scalar register 301 includes the overflow scalar variable objects x and y.

[0156] 505: Compiler 100 allocates scalar variables to be stored in the program to scalar register 301 and vector variables to be stored to vector register 302.

[0157] It can be understood that step 504 is the register allocation stage of the compiler's compilation instruction stage, in which registers for storing each variable are allocated.

[0158] In some embodiments, when compiling a program, the compiler 100 may first convert the program into an intermediate representation, such as an abstract syntax tree, reverse Polish notation, or 3-address code. During this process, the compiler 100 may perform register allocation. Specifically, the compiler 100 may map variables in the program to virtual registers and then determine the corresponding physical register (i.e., the target register).

[0159] 506: Compiler 100 determines whether a scalar register and / or vector register has overflowed.

[0160] It is understandable that when compiler 100 overflows during the process of allocating variables to registers, it indicates that the corresponding register has reached its storage limit. The overflowed variable needs to be stored in the stack storage area of ​​the pre-determined storage unit where the register overflows. Therefore, overflow code needs to be inserted into the compiled program and the stack information corresponding to the stack storage area needs to be updated according to the overflow variable, i.e., step 506 is executed.

[0161] In some embodiments, step 403 determines whether the target register has an overflow situation. Specifically, the compiler 100 determines that the storage space of the physical register corresponding to the virtual register has been fully allocated, then marks the virtual register as "overflow" and determines that the physical register (i.e., the target register) has an overflow situation.

[0162] 507: Compiler 100 determines the target class corresponding to the register where the overflow occurred, updates the stack pointer and stack information of the corresponding storage unit according to the target class and the overflowed part of the variables to be stored, and inserts overflow code for the variables to be stored.

[0163] The registers that overflow include scalar register 301 and vector register 302, and the overflowed variables in the variables to be stored include scalar variables and / or vector variables.

[0164] In some embodiments, the inserted overflow code includes overflow start code and overflow end code. Between the overflow start code and overflow end code, it is necessary to insert a store instruction with the stack pointer register as the base address and the stack address offset of the variable as the offset value after the variable definition point, and to insert a load instruction with the stack pointer address register as the base address and the stack address offset of the variable as the offset value before the variable usage point.

[0165] It can be understood that the variable definition point is the location where the variable is defined, and a `store` directive is inserted before each line of code. The variable usage point is the location where a value is assigned to the variable, and a `load` directive is inserted before each line of code. The following will combine... Figure 6 The explanation will be illustrated with code examples, and will not be elaborated upon here.

[0166] In some embodiments, when inserting the overflow start (prologue) code, the stack size (including the space occupied by variables in the overflow variable list in the stack information and the total space occupied by other information on the stack storage area) of each stack storage area is used to insert two stack pointer adjustment instructions in the first basic block (i.e., prologue) of the function (i.e., determine the address corresponding to the current stack pointer based on the stack size of the current stack storage area and the initialized stack pointer). There is one adjustment instruction for each stack pointer.

[0167] In some embodiments, when inserting the overflow termination code, a restore instruction for the stack pointers of the DDR stack storage area and the SRAM stack storage area can be inserted in the final base block of the function. This means readjusting the address corresponding to the stack pointer address register to the highest address of the stack storage area. Each stack storage area's stack pointer has one restore instruction.

[0168] It's understandable that during the overflow start and end code phases of the inserted overflow code, the compiler allocates stack space for overflow variables within the function and releases stack space after the function ends. The following section combines... Figure 6 Further details will not be elaborated here.

[0169] 508: Compiler 100 completes the compilation of the program to be compiled and destroys the dual-stack information.

[0170] It is understandable that after the compiler completes the compilation of the program to be compiled, it can output executable instructions, i.e., binary executable files or assembly files. Furthermore, it is necessary to release the storage space allocated for dual-stack information during the compilation process of the compiler 100. This means that for each stack information, the stack ID of its stack storage area is cleared, the current usage of the stack storage area is cleared (i.e., the usage is restored to zero), the mapping table between the stack storage area and register types is cleared, the overflow variable linked list of the stack storage area is cleared, etc., and then the storage space corresponding to the dual-stack information is reclaimed.

[0171] Figure 6 The image shown is a schematic diagram of a compiled program code provided in an embodiment of this application.

[0172] Figure 6 In this context, the compiled code is an assembly file, and its corresponding user program is as follows:

[0173] Source code:

[0174] main(){

[0175] x = ...;

[0176] va = ...;

[0177] y = ...;

[0178] ...

[0179] … = x;

[0180] … = va;

[0181] … = y;

[0182] ...}

[0183] Assume that in the code above, the scalar variables x and y are both 4 bytes and will overflow, and the vector variable va occupies 32 bytes and will overflow. Here, sp0 represents the stack pointer address register located in the DDR stack storage area of ​​DDR 200, stacksize0 represents the usage of the DDR stack storage area, sp1 represents the stack pointer address register of the SRAM stack storage area of ​​the dedicated SRAM unit 303, stacksize1 represents the usage of the SRAM stack storage area, r0, r1, r2, and r3 are scalar registers storing the values ​​of variables x and y, and t0 and t1 are vector registers storing the value of vector variable va.

[0184] In some embodiments, the dual-stack information generated based on the user code described above is as shown in Table 1 below:

[0185] Table 1

[0186] Stack id=0 Stack id=1 Stack size = 8 Stack size = 32 (Scalar register) (Vector register) Objects->x->y Objects->va

[0187] As shown in Table 1 above, scalar register 301 is a low-frequency register, with a stack ID of 0 for its corresponding DDR stack storage area. Vector register 302 is a high-frequency register, with a stack ID of 1 for its corresponding SRAM stack storage area. The length of scalar variables is 8 bytes, and the length of vector variables is 32 bytes. The linked list of overflow variables in the stack information with stack ID 0 contains variable objects x and y, while the linked list of overflow variables in the stack information with stack ID 1 contains variable object va.

[0188] Continue to refer to Figure 6 In the assembly file, within the prologue of the main function (i.e. Figure 6 The bb0 phase includes the initialization of sp1, the adjustment of sp0, and the adjustment of sp1. After the definition points of overflow variables x and y, and after the definition point of variable va, the values ​​of variables x, y, and va are saved. Specifically, this can be done using an insert store instruction, for example... Figure 6 Instructions such as "str0", "st t0", and "st r1" in bb1 are used to save variable values ​​onto the corresponding stack. Before the overflow points of variables x, y, and va, their values ​​are restored. Specifically, this can be achieved by inserting load instructions, for example... Figure 6 In instructions like "ld r2", "ld t2", and "ld r3" in bb1, the values ​​of variables are retrieved from the corresponding stack storage areas and stored in registers. Within the epilogue of the main function (i.e., Figure 6 (BB2 stage), which includes the recovery of SP0 and SP1.

[0189] It is understandable that since values ​​r0 and t0 are the first variables to overflow from scalar register 301 and vector register 301 respectively, their stack address offsets are both 0. That is, the stack address of value r0 is sp0+0, and the stack address of value t0 is sp1+0. Value r1 is the second variable to overflow from scalar register 301, and since the length of value r0 is 4 bytes, the stack address offset of variable r1 is 4. That is, the stack address of value r1 is sp0+4. The same logic applies to the other values. Figure 6 As shown.

[0190] Figure 7 According to some embodiments of this application, a schematic diagram of the structure of an electronic device 10 adapted to the compilation method for register overflow of this application is shown. Figure 7As shown, the electronic device 10 may include a processor 710, a power module 740, a memory 780, a mobile communication module 730, a wireless communication module 720, a sensor module 790, an audio module 750, a camera 770, an interface module 760, buttons 701, and a display screen 702, etc.

[0191] It is understood that the structures illustrated in the embodiments of the present invention do not constitute a specific limitation on the electronic device 10. In other embodiments of this application, the electronic device 10 may include more or fewer components than illustrated, or combine some components, or split some components, or have different component arrangements. The illustrated components may be implemented in hardware, software, or a combination of software and hardware.

[0192] Processor 710 may include one or more processing units, such as processing modules or circuits of a Central Processing Unit (CPU), Image Signal Processing (ISP), Video Processing Unit (VPU), Graphics Processing Unit (GPU), Digital Signal Processor (DSP), Micro-programmed Control Unit (MCU), Artificial Intelligence (AI) processor, or Field Programmable Gate Array (FPGA). Different processing units may be independent devices or integrated into one or more processors. Processor 710 may include storage units for storing instructions and data. In some embodiments, the storage units in processor 710 are cache memories. The ISP, VPU, and memory 780 may be coupled via a bus to form a system-on-chip (SOC). In other embodiments, the ISP, VPU, and memory 780 may also be independent devices.

[0193] The memory 780 can be used to store data, software programs, and modules. It can be volatile memory, such as random-access memory (RAM) or double data rate synchronous dynamic random access memory (DDRSDRAM).

[0194] The power module 740 may include a power supply, a power management component, etc. The power supply may be a battery. The power management component manages the charging of the power supply and the power supply to other modules. In some embodiments, the power management component includes a charging management module and a power management module. The charging management module receives charging input from a charger; the power management module connects to the power supply and the processor 710. The power management module receives input from the power supply and / or the charging management module to supply power to the processor 710, the display 702, the camera 770, and the wireless communication module 720, etc.

[0195] The mobile communication module 730 may include, but is not limited to, antennas, power amplifiers, filters, and LNAs (Low Noise Amplifiers). The mobile communication module 730 can provide wireless communication solutions, including 2G / 3G / 4G / 5G, for use on the electronic device 10. The mobile communication module 730 can receive electromagnetic waves via the antenna, filter and amplify the received electromagnetic waves, and then transmit them to a modem processor for demodulation. The mobile communication module 730 can also amplify the signal modulated by the modem processor and convert it into electromagnetic waves for radiation via the antenna. In some embodiments, at least some functional modules of the mobile communication module 730 may be housed in the processor 710. In some embodiments, at least some functional modules of the mobile communication module 730 and at least some modules of the processor 710 may be housed in the same device. Wireless communication technologies can include Global System for Mobile Communications (GSM), General Packet Radio Service (GPRS), Code Division Multiple Access (CDMA), Wideband Code Division Multiple Access (WCDMA), Time-Division Code Division Multiple Access (TD-SCDMA), Long Term Evolution (LTE), Bluetooth (BT), Global Navigation Satellite System (GNSS), Wireless Local Area Networks (WLAN), Near Field Communication (NFC), Frequency Modulation (FM), Infrared (IR) technology, etc.The GNSS may include the Global Positioning System (GPS), the Global Navigation Satellite System (GLONASS), the BeiDou Navigation-Satellite System (BDS), the Quasi-Zenith Satellite System (QZSS), and / or satellite-based augmentation systems (SBAS).

[0196] The wireless communication module 720 may include an antenna, which enables the transmission and reception of electromagnetic waves. The wireless communication module 720 can provide solutions for wireless communication applications on the electronic device 10, including wireless local area networks (WLANs) (such as wireless fidelity (Wi-Fi) networks), Bluetooth (BT), global navigation satellite system (GNSS), frequency modulation (FM), near field communication (NFC), and infrared (IR) technologies. The electronic device 10 can communicate with networks and other devices through wireless communication technologies.

[0197] In some embodiments, the mobile communication module 730 and the wireless communication module 720 of the electronic device 10 may also be located in the same module.

[0198] Display screen 702 is used to display human-computer interaction interfaces, images, videos, etc. Display screen 702 includes a display panel. The display panel can be a liquid crystal display (LCD), an organic light-emitting diode (OLED), an active-matrix organic light-emitting diode (AMOLED), a flexible light-emitting diode (FLED), a Mini-LED, a Micro-LED, a quantum dot light-emitting diode (QLED), etc.

[0199] The sensor module 790 may include proximity sensors, pressure sensors, gyroscope sensors, barometric pressure sensors, magnetic sensors, accelerometers, distance sensors, fingerprint sensors, temperature sensors, touch sensors, ambient light sensors, bone conduction sensors, etc.

[0200] The audio module 750 is used to convert digital audio information into analog audio signal output, or to convert analog audio input into digital audio signal. The audio module 750 can also be used for encoding and decoding audio signals. In some embodiments, the audio module 750 may be located in the processor 710, or some functional modules of the audio module 750 may be located in the processor 710. In some embodiments, the audio module 750 may include a speaker, a handset, a microphone, and a headphone jack.

[0201] The camera 770 is used to capture still images or videos. An object is projected onto a photosensitive element by generating an optical image through the lens. The photosensitive element converts the light signal into an electrical signal, which is then passed to the ISP (Image Signal Processing) to be converted into a digital image signal. The electronic device 10 can realize the shooting function through the ISP, camera 770, VPU, GPU (Graphics Processing Unit), display screen 702, and application processor. The camera 770 can be a fixed-focus lens, zoom lens, fisheye lens, panoramic lens, etc.

[0202] The interface module 760 includes an external memory interface, a universal serial bus (USB) interface, and a subscriber identification module (SIM) card interface. The external memory interface can be used to connect an external memory card, such as a Micro SD card, to expand the storage capacity of the electronic device 10. The external memory card communicates with the processor 710 through the external memory interface to perform data storage. The USB interface is used for communication between the electronic device 10 and other electronic devices. The SIM card interface is used to communicate with the SIM card installed in the electronic device 10, for example, to read or write phone numbers stored in the SIM card.

[0203] In some embodiments, the electronic device 10 further includes buttons 701, a motor, and indicators. Buttons 701 may include volume buttons, a power button, etc. The motor is used to generate a vibration effect in the electronic device 10, for example, vibrating when the user's electronic device 10 is called to prompt the user to answer the call. The indicator may include a laser indicator, a radio frequency indicator, an LED indicator, etc.

[0204] Figure 8 The diagram shows a program module schematic of a compiler apparatus 800 for register overflow provided in an embodiment of this application. It can be used to execute the compiler method for register overflow provided in this embodiment, for example, executing steps 401 to 405 as described above. This apparatus is applied to an electronic device, which has a compiler installed on it. The electronic device includes multiple registers located in a processor, a first storage unit, and a second storage unit. The apparatus includes:

[0205] The program acquisition module 801 is used by the compiler to acquire the program to be compiled.

[0206] The program compilation module 802 is used by the compiler to compile the program to be compiled and obtain the instructions to be executed.

[0207] Among them, the program compilation module 801 is used by the compiler to compile the program to be compiled, specifically for:

[0208] If the first register corresponding to the first variable included in the program to be compiled overflows, the variable portion overflowing from the first register will be allocated to the first storage unit corresponding to the first register.

[0209] If the second register corresponding to the second variable included in the program to be compiled overflows, the overflowed variable portion of the second register will be allocated to the second storage unit corresponding to the second register.

[0210] The processor accesses the first and second memory units at different speeds.

[0211] The various embodiments of the mechanisms disclosed in this application can be implemented in hardware, software, firmware, or a combination of these implementation methods. Embodiments of this application can be implemented as computer programs or program code executable on a programmable system, the programmable system including at least one processor, a storage system (including volatile and non-volatile memory and / or storage elements), at least one input device, and at least one output device.

[0212] Program code can be applied to input instructions to execute the functions described in this application and generate output information. The output information can be applied to one or more output devices in a known manner. For the purposes of this application, the processing system includes any system having a processor such as, for example, a digital signal processor (DSP), a microcontroller, an application-specific integrated circuit (ASIC), or a microprocessor.

[0213] The program code can be implemented using a high-level programming language or an object-oriented programming language to communicate with the processing system. This includes, but is not limited to, OpenCL, C, C++, and Java. However, for languages ​​like C++ and Java, due to their memory conversion requirements, the application of the compilation method for register overflow in this application's embodiments may differ somewhat. Those skilled in the art can make modifications based on the specific high-level language, all without departing from the scope of this application's embodiments.

[0214] In some cases, the disclosed embodiments may be implemented in hardware, firmware, software, or any combination thereof. The disclosed embodiments may also be implemented as instructions carried or stored thereon on one or more temporary or non-temporary machine-readable (e.g., computer-readable) storage media, which may be read and executed by one or more processors. For example, the instructions may be distributed via a network or through other computer-readable media. Therefore, machine-readable media may include any mechanism for storing or transmitting information in a machine-readable (e.g., computer-readable) form, including but not limited to floppy disks, optical disks, CD-ROMs, magneto-optical disks, read-only memory (ROM), random access memory (RAM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), magnetic cards or optical cards, flash memory, or tangible machine-readable storage for transmitting information (e.g., carrier waves, infrared signals, digital signals, etc.) using the Internet in the form of electrical, optical, acoustic, or other propagation signals. Therefore, machine-readable media include any type of machine-readable medium suitable for storing or transmitting electronic instructions or information in a machine-readable (e.g., computer-readable) form.

[0215] In the accompanying drawings, some structural or methodological features may be shown in a specific arrangement and / or order. However, it should be understood that such a specific arrangement and / or order may not be necessary. Rather, in some embodiments, these features may be arranged in a manner and / or order different from that shown in the illustrative drawings. Furthermore, the inclusion of structural or methodological features in a particular figure does not imply that such features are required in all embodiments, and in some embodiments, these features may be omitted or may be combined with other features.

[0216] It should be noted that all units / modules mentioned in the device embodiments of this application are logical units / modules. Physically, a logical unit / module can be a physical unit / module, a part of a physical unit / module, or a combination of multiple physical units / modules. The physical implementation of these logical units / modules themselves is not the most important factor; the combination of functions implemented by these logical units / modules is the key to solving the technical problems proposed in this application. Furthermore, to highlight the innovative aspects of this application, the above-described device embodiments of this application have not introduced units / modules that are not closely related to solving the technical problems proposed in this application. This does not mean that the above-described device embodiments do not contain other units / modules.

[0217] It should be noted that in the examples and description of this patent, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one" does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0218] Although this application has been illustrated and described with reference to certain preferred embodiments thereof, those skilled in the art should understand that various changes in form and detail may be made thereto without departing from the spirit and scope of this application.

Claims

1. A compilation method for register overflow, applied to electronic devices, characterized in that, The electronic device is equipped with a compiler, and the electronic device includes multiple registers located in a processor, a first memory unit, and a second memory unit; and the method includes: The compiler obtains the program to be compiled; The compiler compiles the program to be compiled to obtain executable instructions; The compilation of the program to be compiled by the compiler includes: If the first register corresponding to the first variable included in the program to be compiled overflows, the variable portion overflowing from the first register is allocated to the first storage unit corresponding to the first register. The first storage unit is determined based on the first register category of the first register, and the first register category is determined based on the access frequency of the first register. If the second register corresponding to the second variable included in the program to be compiled overflows, the variable portion overflowing from the second register is allocated to the second storage unit corresponding to the second register. The second storage unit is determined based on the second register category of the second register, and the second register category is determined based on the access frequency of the second register. The processor accesses the first storage unit and the second storage unit at different speeds.

2. The compilation method for register overflow according to claim 1, characterized in that, The first register is a vector register, and the second register is a scalar register.

3. The compilation method for register overflow according to claim 1, characterized in that, When the first register corresponding to the first variable included in the program to be compiled overflows, the overflowed variable portion of the first register is allocated to the first storage unit corresponding to the first register, including: The compiler determines that the first register has overflowed and determines the first register category corresponding to the first register; The compiler determines the first memory unit corresponding to the first register class based on the first register class; The compiler allocates the variable portion that overflows from the first register to the first storage unit corresponding to the first register class.

4. The compilation method for register overflow according to claim 3, characterized in that, When the second register corresponding to the second variable included in the program to be compiled overflows, the overflowed variable portion of the second register is allocated to the second storage unit corresponding to the second register, including: The compiler determines that the second register has overflowed and determines the second register category corresponding to the second register; The compiler determines the second memory unit corresponding to the second register class based on the second register class. The compiler allocates the variable portion that overflows from the second register to the second storage unit corresponding to the second register class.

5. The compilation method for register overflow according to claim 4, characterized in that, The first register category and the second register category are determined based on the access frequency of the plurality of registers.

6. The compilation method for register overflow according to claim 4, characterized in that, The processor accesses the first register of the first register category more frequently than it accesses the second register of the second register category, and the processor accesses the first memory unit faster than it accesses the second memory unit.

7. The compilation method for register overflow according to claim 1, characterized in that, The electronic device includes a processor, the first storage unit is a storage unit located in the processor, and the second storage unit is an external storage unit located outside the processor.

8. The compilation method for register overflow according to claim 7, characterized in that, The first storage unit is a static random access memory, and the second storage unit is a double data rate synchronous dynamic random access memory.

9. The compilation method for register overflow according to claim 1, characterized in that, The first storage unit includes a first stack storage area; The compiler allocates the variable portion overflowing from the first register to the first storage unit corresponding to the first register, including: The compiler allocates the variable portion of the first register overflow to the first stack storage area, wherein the variable portion of the first register overflow is stored in the first stack storage area in a stack manner.

10. The compilation method for register overflow according to claim 1, characterized in that, The second storage unit includes a second stack storage area; The compiler allocates the variable portion overflowing from the second register to the second storage unit corresponding to the second register, including: The compiler allocates the variable portion of the second register overflow to the second stack storage area, wherein the variable portion of the second register overflow is stored in the second stack storage area in a stack manner.

11. The compilation method for register overflow according to claim 1, characterized in that, The compiler allocates the variable portion overflowing from the first register to the first storage unit corresponding to the first register, including: The compiler allocates the variable portion that overflowed from the first register to the first storage unit; The compiler inserts a register overflow instruction into the variable portion of the first register that overflows; The compiler allocates the variable portion overflowing from the second register to the second storage unit corresponding to the second register, including: The compiler allocates the overflow portion of the variable from the second register to the second storage unit; The compiler inserts a register overflow instruction into the variable portion of the second register that overflows.

12. An electronic device, characterized in that, include: Memory, used to store instructions executed by one or more processors of an electronic device, and A processor is one of the processors in an electronic device, used to control the execution of the compilation method for register overflow as described in any one of claims 1 to 11.

13. A computer-readable storage medium, characterized in that, The storage medium stores instructions that, when executed on a computer, cause the computer to perform the compilation method for register overflow as described in any one of claims 1 to 11.

14. A computer program product, characterized in that, The computer program product includes instructions that, when executed, cause a computer to perform the compilation method for register overflow as described in any one of claims 1 to 10.

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