Screening circuit and data screening method

Abstract

The application provides a screening circuit and a data screening method, and relates to the technical field of data storage, which comprises a CPU, a screening circuit and a register configured by the CPU; the screening circuit is used for obtaining a preset screening rule, calculating a target physical address according to the screening rule and a preset starting address; the CPU is used for obtaining the target physical address, reading valid data from the target physical address and storing the read valid data into the register. The target physical address is an address screened based on the screening rule, and the address is a required valid address, so that the data stored in the register are all valid data, the situation of "taking and not using" is avoided, and the data transmission time is also reduced due to the fact that invalid data is not stored.

Description

Technical Field

[0001] This invention relates to the field of data filtering technology, and in particular to a filtering circuit and a data filtering method. Background Technology

[0002] For any CPU, reading data from memory is one of the most basic operations. Typically, the CPU will provide a specified address range to read data from memory into registers for processing. However, often the CPU will not use all the data within a consecutive address range, but only a portion of the data within a certain address range. The selection of data within this address range can be determined by a sequence called the "Skip Bit Map".

[0003] Current technology first stores the data corresponding to a certain address range into a register, and then determines whether to discard the data based on the Skip Bit Map, thereby achieving the purpose of data filtering. If the above process is all handled by the CPU, it will increase the CPU's workload and reduce the efficiency of the entire circuit system. Secondly, in the current technology, storing data into the register first and then performing the discarding will result in some data being discarded, leading to a situation where data is "retrieved but not used," causing the register to be stored invalidally, wasting some data transmission time and increasing circuit overhead. Summary of the Invention

[0004] In view of this, the purpose of the present invention is to provide a screening circuit and a data screening method that can directly select valid data and avoid invalid storage.

[0005] In a first aspect, embodiments of the present invention provide a filtering circuit, including a CPU, and a filtering circuit and a register configured in the CPU; the filtering circuit is used to obtain a preset filtering rule, calculate a target physical address according to the filtering rule and a preset starting address; the CPU is used to obtain the target physical address, read valid data from the target physical address, and store the read valid data in a register.

[0006] In conjunction with the first aspect, the present invention provides a first possible implementation of the first aspect, wherein the filtering circuit includes a processing unit and an addition circuit connected to the processing unit; the processing unit is configured to acquire filtering rules and calculate the offset of the target physical address relative to the starting address according to the filtering rules; the addition circuit is configured to calculate the target physical address according to the offset and the starting address.

[0007] In conjunction with the first aspect, this embodiment of the invention provides a second possible implementation of the first aspect, wherein the addition circuit includes a number sequence, a data selector, and a continuous address sequence; the data selector is used to select a sequence value in the number sequence and obtain a sequence value corresponding to the continuous address sequence based on the position of the sequence value in the number sequence; the data selector is also used to calculate the target physical address based on the sequence value of the continuous address sequence and the offset.

[0008] In conjunction with the first aspect, this embodiment of the invention provides a third possible implementation of the first aspect, wherein the numbering sequence includes a plurality of sequence values ​​that increase sequentially from 0, and the continuous address sequence includes relative positions based on a preset starting address; the step of obtaining a sequence value corresponding to the continuous address sequence based on the position of the sequence value in the numbering sequence includes: adding the specific value of the sequence value relative to 0 and the relative position corresponding to the continuous address sequence to obtain the sequence value corresponding to the continuous address sequence.

[0009] In conjunction with the first aspect, this embodiment of the invention provides a fourth possible implementation of the first aspect, wherein the addition circuit includes: a multi-stage adder and a continuous address sequence; the multi-stage adder is used to process the continuous address sequence to obtain a sequence value corresponding to the continuous address sequence.

[0010] In conjunction with the first aspect, the present invention provides a fifth possible implementation of the first aspect, wherein the step of processing the continuous address sequence to obtain a sequence value corresponding to the continuous address sequence includes: a multi-stage adder incrementing each address sequentially by one from the starting address of the continuous address sequence to obtain a sequence value corresponding to the continuous address sequence.

[0011] In conjunction with the first aspect, this embodiment of the invention provides a sixth possible implementation of the first aspect, wherein the above-mentioned addition circuit includes: an adder and a continuous address sequence; the adder is used to add the offset to the continuous address sequence to directly obtain the target physical address.

[0012] In conjunction with the first aspect, this embodiment of the invention provides a seventh possible implementation of the first aspect, wherein the preset starting address corresponds to a continuous address sequence; the step of obtaining the preset filtering rule and calculating the target physical address according to the filtering rule and the preset starting address includes: determining the correspondence between the filtering rule and the continuous address sequence; wherein the correspondence result includes valid parameters and invalid parameters; when the correspondence result indicates a valid parameter, the current address of the continuous address sequence is determined as the target physical address.

[0013] In conjunction with the first aspect, this embodiment of the invention provides an eighth possible implementation of the first aspect, wherein the preset filtering rule is a Skip Bit Map sequence.

[0014] Secondly, embodiments of the present invention also provide a data filtering method, which is applied to the filtering circuit mentioned above. The filtering circuit includes a CPU, and a filtering circuit and register configured on the CPU. The method includes: obtaining a preset filtering rule through the filtering circuit; calculating a target physical address according to the filtering rule and a preset starting address; obtaining the target physical address through the CPU; reading valid data from the target physical address; and storing the read valid data in a register.

[0015] The embodiments of this invention bring the following beneficial effects: This invention provides a filtering circuit and a data filtering method. First, a preset filtering rule is obtained through the filtering circuit. Based on the filtering rule and a preset starting address, the target physical address is calculated. After the target physical address is determined, the CPU obtains the target physical address, reads valid data from the target physical address, and stores the read valid data in a register. The target physical address is the address filtered based on the filtering rule, and this address is the required valid address, ensuring that the data stored in the register is all valid data, avoiding the situation of "taking but not using". At the same time, since invalid data is not stored, data transmission time is also reduced.

[0016] Other features and advantages of the invention will be set forth in the description which follows, and will be apparent in part from the description, or may be learned by practicing the invention. The objects and other advantages of the invention are realized and obtained in accordance with the structures particularly pointed out in the description, claims and drawings.

[0017] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0018] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0019] Figure 1 A schematic diagram of a screening circuit provided in an embodiment of the present invention;

[0020] Figure 2This is a flowchart for calculating the target physical address based on a bitmap sequence, provided in an embodiment of the present invention.

[0021] Figure 3 A schematic diagram of another screening circuit provided in an embodiment of the present invention;

[0022] Figure 4 A flowchart of a data filtering method provided in an embodiment of the present invention;

[0023] Figure 5 This is a schematic diagram of the structure of an electronic device provided in an embodiment of the present invention.

[0024] Icons: 10-Filtering circuit; 11-CPU; 12-Register; 101-Processing unit; 102-Adder circuit. Detailed Implementation

[0025] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0026] For any CPU, reading data from memory is one of the most basic operations. Typically, the CPU will provide a specified address range to read data from memory into registers for processing. However, often the CPU will not use all the data within a consecutive address range, but only a portion of the data within a certain address range. The selection of data within this address range can be determined by a sequence called the "Skip Bit Map".

[0027] Current technology first stores the data corresponding to a certain address range into a register, and then determines whether to discard the data based on the Skip Bit Map, thereby achieving the purpose of data filtering. If the above process is all handled by the CPU, it will increase the CPU's workload and reduce the efficiency of the entire circuit system. Secondly, in the current technology, storing data into the register first and then performing the discarding will result in some data being discarded, leading to a situation where data is "retrieved but not used," causing the register to be stored invalidally, wasting some data transmission time and increasing circuit overhead.

[0028] Based on this, the filtering circuit and data filtering method provided in this embodiment of the invention can directly select valid data and avoid invalid storage in registers.

[0029] To facilitate understanding of this embodiment, a screening circuit disclosed in this embodiment of the invention will first be described in detail.

[0030] In one possible implementation, embodiments of the present invention provide a screening circuit, specifically, as shown in the example below. Figure 1 The schematic diagram of a filtering circuit shown includes a CPU 11, a filtering circuit 10 configured on the CPU 11, and a register 12. The filtering circuit 10 is used to obtain a preset filtering rule, calculate the target physical address according to the filtering rule and the preset starting address. The CPU 11 is used to obtain the target physical address, read valid data from the target physical address, and store the read valid data in the register 12.

[0031] Specifically, the preset filtering rules include valid and invalid parameters, and the aforementioned starting address also corresponds to a continuous address sequence; for ease of understanding, Figure 2 A flowchart illustrating the calculation of a target physical address based on a bitmap sequence is shown, such as... Figure 2 As shown, the steps described above for obtaining preset filtering rules, calculating the target physical address based on the filtering rules and the preset starting address include the following steps:

[0032] Step S1: Determine the correspondence between the filtering rules and the continuous address sequence.

[0033] Step S2: When the corresponding result indicates a valid parameter, the current address of the continuous address sequence is determined as the target physical address.

[0034] Specifically, there are multiple valid parameters and multiple invalid parameters in the above filtering rules, and these multiple valid parameters and multiple invalid parameters are arranged in order.

[0035] In a specific implementation, the above continuous address sequence can be mapped one-to-one with each of the sequentially arranged parameters in the above filtering rules, starting from its starting address. When the current address corresponds to a valid parameter, it indicates that the address is a valid address, and when the current address corresponds to an invalid parameter, it indicates that the address is an invalid address. The register 12 of the present invention only stores address data that is a valid address. Therefore, only the address that indicates a valid parameter can be determined as the target physical address.

[0036] Furthermore, physical addresses identified as target physical addresses are reserved so that CPU 11 can read valid data from them and store the read valid data in register 12. Other addresses not identified as target physical addresses are skipped during the data storage process in register 12.

[0037] This invention provides a filtering circuit that first obtains preset filtering rules through filtering circuit 10, calculates the target physical address based on the filtering rules and a preset starting address, and then obtains the target physical address through CPU 11, reads valid data from the target physical address, and stores the read valid data in register 12. The target physical address is the address filtered based on the filtering rules, and this address is the required valid address. That is, this invention performs address rounding first, so when retrieving data, the data can be directly stored in register 12 based on the filtered address, avoiding unnecessary data transmission and preventing the situation of "retrieval without use". Simultaneously, since the number of filtered addresses is less than the number of unfiltered addresses, less data needs to be transmitted, thus reducing data transmission time. Furthermore, the number of registers 12 used for storing data is also reduced accordingly, further conserving circuit resources.

[0038] For ease of understanding, Figure 1 On this basis, Figure 3 A schematic diagram of another filtering circuit is shown. This filtering circuit includes a processing unit 101 and an adder circuit 102 connected to the processing unit 101. The processing unit 101 is used to acquire filtering rules and calculate the offset of the target physical address relative to the starting address based on the filtering rules. The adder circuit 102 is used to calculate the target physical address based on the offset and the starting address.

[0039] In specific implementation, the valid and invalid parameters corresponding to the above filtering rules can correspond to different values. The processing unit 101 offsets each address of the above continuous address sequence relative to the starting address according to the valid or invalid parameters in the filtering rules, and then, based on the offset result, assigns multiple addresses of the continuous address sequence to valid addresses or invalid addresses respectively.

[0040] Specifically, the above filtering rule can be a Skip Bit Map sequence, in which the bit map sequence contains sequentially arranged "0" or "1", where "1" can correspond to the above valid parameter and "0" can correspond to the above invalid parameter.

[0041] Specifically, the bitmap sequence described above can be 01010011, which is an 8-bit sequence. Furthermore, the length of the bitmap sequence can also be any other bit sequence; the length of the bitmap sequence is not limited here. The left side of the bitmap sequence represents the high-order bits, and the right side represents the low-order bits. Specifically, the low-order bit, i.e., the last "1", corresponds to the offset of the first address in the consecutive address sequence; the second-lowest bit, i.e., the second-to-last "1", corresponds to the offset of the second address in the consecutive address sequence, and so on. The address where the offset corresponds to a value of 1 in the bitmap sequence is the target physical address.

[0042] Furthermore, the above-mentioned adder circuit 102 may include a data selector, and a number sequence and a consecutive address sequence corresponding to the data selector; wherein, the data selector is used to select a sequence value in the number sequence, and obtain a sequence value corresponding to the consecutive address sequence based on the position of the sequence value in the number sequence.

[0043] In practical implementation, a numbering sequence starting from 0 and incrementing sequentially can be added to the circuit. This sequence is added to the obtained consecutive address sequence starting from the starting address, thus obtaining the desired sequence value corresponding to the consecutive address sequence. Specifically, the aforementioned numbering sequence contains multiple sequence values ​​that increment sequentially starting from 0. When the aforementioned numbering sequence contains a sequence value that increments by one starting from 0, the second sequence value in the numbering sequence is 1, and the third sequence value is 2.

[0044] Furthermore, the aforementioned consecutive address sequence also corresponds to a relative position based on a preset starting address, such as the starting address being the first address of the consecutive address sequence. Further, based on the specific value of the sequence value relative to 0 and the relative position of the consecutive address sequence, the specific value of the sequence value can be added to the consecutive address sequence to obtain the sequence value corresponding to the consecutive address sequence. For example, the sequence value of the first address in the consecutive address sequence can be 0, the sequence value of the second address can be 1, and the sequence value of the third address can be 2.

[0045] Furthermore, the aforementioned data selector is also used to calculate the target physical address based on the sequence value of the consecutive address sequence and the offset. In specific implementation, after obtaining the sequence value of the consecutive address sequence based on the number sequence, the above sequence value can be processed with the filtering rules, and the sequence value of the address corresponding to the offset of valid data can be determined as the sequence value of the target physical address, thereby extracting the target physical address.

[0046] The addition circuit 102 in this embodiment of the invention, which includes a data selector, a number sequence, and a continuous address sequence, first obtains the sequence value of the continuous address sequence based on the number sequence, and then determines the target physical address based on the above sequence value and the offset based on the filtering rules. It is clear whether the target physical address obtained by filtering corresponds to the valid parameters in the filtering rules, thereby making the filtering result more accurate.

[0047] Furthermore, the above-mentioned adder circuit 102 can be further simplified, for example, by removing the numbering sequence. In this embodiment, the above-mentioned adder circuit 102 may include a multi-stage adder and a continuous address sequence.

[0048] Specifically, a multi-stage adder can be used to process the continuous address sequence to obtain the corresponding sequence value. For example, the multi-stage adder increments each address sequentially by one, starting from the beginning of the continuous address sequence, to obtain the corresponding sequence value. In a practical implementation, the continuous address sequence is passed sequentially through the multi-stage adder, starting from the beginning. Each adder increments each address sequentially by one. After all addresses have passed through the multi-stage adder, the corresponding sequence value can be obtained.

[0049] Furthermore, the aforementioned adder circuit 102 may also include an adder and a continuous address sequence. The adder can add the offset to the starting address of the continuous address sequence. In this case, each subsequent address in the continuous address sequence corresponds to a specific offset, allowing direct acquisition of the final target physical address. In practical implementation, after adding the current address and the offset, the address to be added directly corresponds to the offset to be added.

[0050] Specifically, when the aforementioned offset corresponds to a valid parameter, the address corresponding to that offset is directly added to determine the target physical address. Compared to the addition circuits 102 in the two embodiments described above, the addition circuit 102 in this embodiment eliminates numerous adders or data selectors.

[0051] Furthermore, based on the above embodiments, this embodiment of the invention also provides a data filtering method applied to the above-mentioned filtering circuit. The filtering circuit includes a CPU, and filtering circuits and registers configured in the CPU, specifically, as follows: Figure 4 The flowchart shown illustrates a data filtering method, which includes:

[0052] Step S402: Obtain the preset filtering rules through the filtering circuit, and calculate the target physical address based on the filtering rules and the preset starting address.

[0053] Step S404: Obtain the target physical address through the CPU, read valid data from the target physical address, and store the read valid data in a register.

[0054] The data filtering method provided in this embodiment of the invention has the same technical features as the filtering circuit provided in the above embodiment, so it can also solve the same technical problems and achieve the same technical effects.

[0055] This invention also provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, it implements the above-described... Figure 4 The steps of the method shown.

[0056] This invention also provides a computer-readable storage medium storing a computer program, which is executed by a processor. Figure 4 The steps of the method shown.

[0057] This invention also provides a schematic diagram of the structure of an electronic device, such as... Figure 5 The diagram shows the structure of the electronic device, which includes a processor 51 and a memory 50. The memory 50 stores computer-executable instructions that can be executed by the processor 51. The processor 51 executes the computer-executable instructions to implement the above-mentioned... Figure 4 The method shown.

[0058] exist Figure 5 In the illustrated embodiment, the electronic device further includes a bus 52 and a communication interface 53, wherein the processor 51, the communication interface 53, and the memory 50 are connected via the bus 52.

[0059] The memory 50 may include high-speed random access memory (RAM) or non-volatile memory, such as at least one disk storage device. Communication between this system network element and at least one other network element is achieved through at least one communication interface 53 (which can be wired or wireless), such as the Internet, wide area network, local area network, metropolitan area network, etc. The bus 52 may be an ISA (Industry Standard Architecture) bus, a PCI (Peripheral Component Interconnect) bus, or an EISA (Extended Industry Standard Architecture) bus, or an AMBA (Advanced Microcontroller Bus Architecture) bus. AMBA defines three types of buses: APB (Advanced Peripheral Bus), AHB (Advanced High-performance Bus), and AXI (Advanced eXtensible Interface). The bus 52 can be divided into address bus, data bus, control bus, etc. For ease of representation, Figure 5 The symbol is represented by a single double-headed arrow, but this does not mean that there is only one bus or one type of bus.

[0060] The processor 51 may be an integrated circuit chip with signal processing capabilities. In implementation, each step of the above method can be completed by the integrated logic circuitry in the hardware of the processor 51 or by instructions in software form. The processor 51 may be a general-purpose processor, including a Central Processing Unit (CPU), a Network Processor (NP), etc.; it may also be a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field-Programmable Gate Array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. The general-purpose processor may be a microprocessor or any conventional processor. The steps of the method disclosed in the embodiments of this application can be directly embodied in the execution of a hardware decoding processor, or executed by a combination of hardware and software modules in the decoding processor. The software modules may reside in random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, registers, or other mature storage media in the art. The storage medium is located in the memory. The processor 51 reads the information in the memory and, in conjunction with its hardware, completes the aforementioned task. Figure 4 The method shown.

[0061] The computer program product of the filtering circuit and data filtering method provided in the embodiments of the present invention includes a computer-readable storage medium storing program code. The instructions included in the program code can be used to execute the methods described in the preceding method embodiments. For specific implementation, please refer to the method embodiments, which will not be repeated here.

[0062] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working process of the system and apparatus described above can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0063] Furthermore, in the description of the embodiments of the present invention, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in the present invention based on the specific circumstances.

[0064] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this invention, essentially, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0065] In the description of this invention, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing the invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0066] Finally, it should be noted that the above embodiments are merely specific implementations of the present invention, used to illustrate the technical solutions of the present invention, and not to limit it. The scope of protection of the present invention is not limited thereto. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that any person skilled in the art can still modify or easily conceive of changes to the technical solutions described in the foregoing embodiments within the technical scope disclosed in the present invention, or make equivalent substitutions for some of the technical features; and these modifications, changes, or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be covered within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A screening circuit, characterized in that, Includes a CPU, as well as filtering circuitry and registers configured in the CPU; The filtering circuit is used to obtain a preset filtering rule, and calculate the target physical address based on the filtering rule and a preset starting address; the preset filtering rule is a Skip Bit Map sequence. The CPU is configured to acquire the target physical address, read valid data from the target physical address, and store the read valid data in the register. The filtering circuit includes a processing unit and an addition circuit connected to the processing unit. The processing unit is used to obtain the filtering rules and calculate the offset of the target physical address relative to the starting address according to the filtering rules. The adder circuit is used to calculate the target physical address based on the offset and the starting address; The preset starting address corresponds to a continuous address sequence; The step of obtaining the preset filtering rules and calculating the target physical address based on the filtering rules and the preset starting address includes: Determine the correspondence between the filtering rules and the consecutive address sequence; wherein the correspondence includes valid parameters and invalid parameters; When the corresponding result indicates a valid parameter, the current address of the continuous address sequence is determined as the target physical address.

2. The screening circuit according to claim 1, characterized in that, The adder circuit includes a number sequence, a data selector, and a consecutive address sequence; The data selector is used to select a sequence value in the numbering sequence and obtain a sequence value corresponding to the consecutive address sequence based on the position of the sequence value in the numbering sequence. The data selector is also used to calculate the target physical address based on the sequence value of the consecutive address sequence and the offset.

3. The screening circuit according to claim 2, characterized in that, The numbering sequence contains multiple sequence values ​​that increase sequentially starting from 0, and the consecutive address sequence includes relative positions based on a preset starting address; The step of obtaining the sequence value corresponding to the consecutive address sequence based on the position of the sequence value in the number sequence includes: Based on the specific value of the sequence value relative to 0 and the relative position of the consecutive address sequence, the specific value of the sequence value is added to the consecutive address sequence to obtain the sequence value corresponding to the consecutive address sequence.

4. The screening circuit according to claim 1, characterized in that, The addition circuit includes: a multi-stage adder and a continuous address sequence; The multi-stage adder is used to process the continuous address sequence to obtain a sequence value corresponding to the continuous address sequence.

5. The screening circuit according to claim 4, characterized in that, The step of processing the continuous address sequence to obtain the sequence value corresponding to the continuous address sequence includes: The multi-stage adder increments each address sequentially by one, starting from the beginning address of the continuous address sequence, to obtain the sequence value corresponding to the continuous address sequence.

6. The screening circuit according to claim 1, characterized in that, The addition circuit includes: an adder and a continuous address sequence; The adder is used to add the offset to the continuous address sequence to directly obtain the target physical address.

7. A data filtering method, characterized in that, The method, applied to the filtering circuit according to any one of claims 1 to 6, wherein the filtering circuit includes a CPU, and a filtering circuit and register configured on the CPU, comprises: The filtering circuit obtains a preset filtering rule, and the target physical address is calculated based on the filtering rule and the preset starting address; the preset filtering rule is a Skip Bit Map sequence. The CPU obtains the target physical address, reads valid data from the target physical address, and stores the read valid data in the register. The filtering circuit includes a processing unit and an addition circuit connected to the processing unit; the processing unit is used to obtain the filtering rules and calculate the offset of the target physical address relative to the starting address according to the filtering rules; the addition circuit is used to calculate the target physical address according to the offset and the starting address. The preset starting address corresponds to a continuous address sequence. The step of obtaining the preset filtering rule and calculating the target physical address based on the filtering rule and the preset starting address includes: determining the correspondence between the filtering rule and the continuous address sequence; wherein the correspondence result includes valid parameters and invalid parameters; when the correspondence result indicates a valid parameter, the current address of the continuous address sequence is determined as the target physical address.

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