A multi-core processor wcet analysis method supporting multi-level consistency protocol

Abstract

The application relates to a multi-core processor WCET analysis method supporting a multi-level consistency protocol and belongs to the technical field of computer application. The method is aimed at a multi-level consistency processor architecture, adopts a hierarchical division idea, divides the multi-level consistency processor into multi-level consistency domains, analyzes data access of the multi-core processor from two levels of domain access and cross-domain access, obtains a state update function of Cache of the multi-level consistency domain, realizes WCET analysis of the multi-core processor with the multi-level consistency protocol, and solves the WCET analysis problem under the nesting condition of the Cache consistency protocol of the multi-core processor.

Description

Technical Field

[0001] This invention relates to the field of computer application technology, and in particular to a method for analyzing the worst-case execution time (WCET) of a multi-core processor that supports a multi-level consistency protocol. Background Technology

[0002] Due to their superior computing performance, multi-core processors are now widely used in embedded real-time systems. Multi-core processors typically employ a Symmetric Multi-Processor (SMP) architecture, achieving communication between cores through reading and writing shared data. However, reading shared data into a private cache can lead to inconsistencies among multiple data copies, resulting in cache consistency issues. Therefore, consistency protocols are needed to maintain data consistency.

[0003] Compared to single-core processors, multi-core processors face challenges such as shared resource contention and inter-core task interference, making task timing predictability more difficult. The use of cache coherence protocols in multi-core processors further complicates WCET prediction. However, WCET is a crucial parameter in embedded real-time systems and a prerequisite for task orchestration and schedulability analysis. The lack of WCET analysis methods for multi-core processors is a key factor limiting their widespread adoption. Summary of the Invention

[0004] Technical problems to be solved

[0005] To address the aforementioned issues, this invention proposes the concept of a multi-level consistency domain to describe the architecture of a multi-level consistency protocol. It divides data access in multi-core processors into two levels: intra-domain access and cross-domain access. Based on the cache read / write policy and the MESI consistency protocol, it derives the cache state update functions within and across consistency domains, thereby enabling WCET analysis in the case of nested multi-level consistency protocols.

[0006] Technical solution

[0007] A WCET analysis method for multi-core processors supporting multi-level consistency protocols, characterized by the following steps:

[0008] Step 1: Establish a multi-core processor cache model:

[0009] CA = (C S C W C C )

[0010] In the formula: C S Representing the structure of the cache, CW This indicates the cache write policy. Within a consistency domain, a write-through and non-write-allocation write policy is used. Between consistency domains, a write-back and write-allocation write policy is used. C Represents the cache coherence protocol, cache structure C S The L1 cache is private, the L2 cache is locally shared, and the L3 cache is globally shared. W Within a consistency domain, a write-through and non-write-assignment write strategy is used; between consistency domains, a write-back and write-assignment write strategy is used. C C This applies only to the MESI consensus protocol, where M represents the Modify state, E represents the Exclusive state, S represents the Shared state, and I represents the Invalid state.

[0011] C S It describes the entire processor's cache hierarchy and the specific configuration of each cache level; the model description of each level in the cache hierarchy is as follows:

[0012] C S =(capacity,block_size,associativity,cores)

[0013] In the formula, capacity represents the cache capacity, block_size represents the block size, associativity represents the associativity, and cores represents the kernels sharing this cache. For L1 cache, which is completely exclusive to the kernel and there is no sharing, the cache can be modeled by instantiating the cache models at each level.

[0014] Step 2: Define and configure the cache's time parameters:

[0015] Ψ R (m,m′) / Ψ W (m,m′): Represents the cache read / write access latency and state transition within the domain, where m represents the accessed data and m′ represents a copy of the accessed data;

[0016] Ψ′ R (m,m′) / Ψ′ W (m,m′): Represents the cross-domain cache read / write access latency and state transition, where m represents the accessed data and m′ represents a copy of the accessed data;

[0017] T: Represents access time delay, and H is defined. p Indicates the private cache access hit time delay, H iThis indicates the cache hit time latency at level i, L. i→j Inv represents the time delay of loading data from level i cache to level j cache, Inv represents the time delay of invalidating other data copies within the domain, and Inv′ represents the time delay of invalidating other data copies across domains.

[0018] m s / m′ s : Indicates the local / remote cache status;

[0019] This indicates that the accessed shared data was replaced out of the cache, resulting in a replacement miss / miss.

[0020] Step 3: Partitioning the Consistency Region

[0021] A set of kernels that use the same consistency protocol to manage data replicas is called a consistency domain. Multi-level consistency domains adopt the idea of ​​hierarchical domain partitioning, where a lower-level consistency domain is a node clump of an upper-level consistency domain.

[0022] Step 4: Intra-domain read access WCET analysis

[0023] When the kernel issues a read request for data m, if m exists in L1 (its state may be E or S) and no replacement miss has occurred, a read hit can be achieved in L1, and the data access latency is H. L1 The state of all cache blocks will not change;

[0024] If data m is within the domain, and its state is E or S, but a replacement occurs and the data is missing, then the data access latency is the time Ψ′ to read data from L2. R Simultaneously, data needs to be loaded from the L2 cache into the local L1 cache. Considering consistency requirements, the data access latency is max(Ψ′). R ,L L2-L1 The cache state remains unchanged.

[0025] If data m is within the domain, m is in state I, and replica m' is in state E or S, then the data access latency is the time Ψ′ to read data from L2. R Simultaneously, data needs to be loaded from the L2 cache into the local L1 cache. Considering consistency requirements, the data access latency is max(Ψ′). R ,L L2-L1 The state of m is changed to S, and the state of the copy m' is changed to S;

[0026] If data m is not in the domain, a miss will occur in the L2 cache. Assume the time to access the L2 cache is Ψ′.R For Ψ′ R We will analyze the value of m at the next level; at this point, the state of m changes from I to E, and the state of L2 Cache needs to be further analyzed according to the L2 consistency protocol.

[0027] We can derive the state update function for read access latency and state transition within the cache domain:

[0028]

[0029] Step 5: Intra-domain write access WCET analysis

[0030] When the kernel issues a write request to m, if m only exists in the local L1 cache and its state is E, a cache write hit will occur. First, the data needs to be written to L1. According to the model in step 1, C... W As can be seen, due to the use of a write-through strategy, data needs to be written to L2 simultaneously, therefore the data access time is H. L1 +Ψ′ W The cache state remains unchanged; if m exists in the L1 cache and its state is S, a cache write hit will occur, and the data access latency will be H. L1 +Ψ′ W The state transitions to E. Due to the use of a write-failure consistency protocol, the replica's state needs to be modified to I. Considering consistency requirements, the final data access latency is max(H). L1 +Ψ′ W ,Inv);

[0031] If data m is located in the local L1 cache, and the state of m is E or S, and a replacement miss occurs, a write miss will occur; if the state of m is E, the data access time is Ψ′. W And the state changes to I; if the state of m is S, after performing an L2 cache write operation, write invalidation needs to be performed on other replicas, so the access time is max(Ψ′). W Inv), the states of both m and its copy m' are converted to I;

[0032] If data m is within the domain, and the state of m is I while the state of replica m' is E or S, a write operation will be performed on L2, invalidating the data in other replicas. Considering data continuity requirements, the data write latency is max(Ψ′). W Since non-write allocation is used, the state of the local L1 cache does not change, while the state of other replicas changes from E / S to I. The state of the L2 cache will be discussed in the next level.

[0033] If the data m is not within the domain, analogous to the read access case, assuming the write L2 cache access time is Ψ′ W For Ψ′ W We will analyze the value of in the next level; since non-write allocation is used in the domain, the state of m does not change at this time;

[0034] Based on the above analysis, the state update function for write access latency and state transition within the cache domain can be derived:

[0035] Step 6: Cross-domain read access WCET analysis

[0036] When the kernel issues a read request for data m, if it needs to access the L2 cache, the shared data will be managed by the upper-level consistency protocol.

[0037] If data m exists within the domain and is located in the local L2 cache, the data access time is H. L2 The state of all caches across domains remains unchanged;

[0038] When the accessed data m exists in the L2 cache and a replacement miss occurs, the data access latency is H. L3 Simultaneously, data needs to be loaded into the L1 cache. Considering the consistency requirements, the data access latency is max(H). L3 ,L L3-L1 If the state of m is M or E, the state will change to E; if the state of m is S, the state will not change, and the state of the copy m' will not change.

[0039] If the accessed data m does not exist in the domain, there are two possibilities: either data m itself is not in the cache, or data m exists in the cache of another domain. If data m is not in the cache, it needs to be read from main memory, and the data access latency is H. m Simultaneously, data needs to be written from main memory back to the L1 cache. Considering consistency requirements, the data access latency is max(H). m ,L m-L1 The state of L2 changes from I to E;

[0040] If the data exists in another domain, i.e., a data copy m' exists, and if its state is M, the data must first be loaded from the L2 cache of the other domain into the local domain's L2 cache, then loaded into L1, and finally read from L1. The access latency is L. L2-L2 +L L2-L1 +HL1 At this time, the state of data m in L2 changes from I to S, and the state of data replica m' in other domains L2 changes from M to S;

[0041] If the state of data replica m' is E or S, the hit data will be read in L3, and the data access latency will be H. L3 Meanwhile, the data will be loaded into L1. Considering the continuity requirement, the data access latency should be max(H). L3 ,L L3-L1 At this point, the state of data m in L2 changes from I to S, and the state of data replica m' in other domains L2 changes to S;

[0042] Based on the above analysis, the state update functions for cache cross-domain read access time and state transition can be derived as follows:

[0043]

[0044] Step 7: Cross-domain write access WCET analysis

[0045] When the kernel issues a write request for data m, if write access to the L2 cache is required, the shared data will be managed by the upper-level consistency protocol.

[0046] If data m is within the domain and resides in the local L2 cache, with a state of S, and data in other replicas needs to be invalidated, considering continuity requirements, the data access time is max(H). L2 When the state of m changes to M, the replica's state changes from S to I; if the state of m is M or E, the data access time is H. L2 The state changes to M, while other cache states remain unchanged at I.

[0047] If the accessed data m does not exist within the domain, there are two possibilities: either data m itself does not exist in the cache, or data m exists in the cache of another domain; if data m does not exist in the cache, according to the model in step 1, C W As can be seen, since inter-domain allocation uses write allocation, data must first be loaded from main memory into the L2 cache, and then the data is modified in the L2 cache. At this time, the data access latency is H. L2 +L m-L2 The L2 cache state changes from I to M;

[0048] If the data exists in another domain, the state of data m is I. If the state of data replica m' is M, the data must first be loaded from the other domain into the local L2 cache. Then, the data in the local L2 cache is modified, and the state changes to M. Additionally, other replicas must be invalidated. Considering consistency requirements, the data access latency is max(H). L2 +L L2-L2 If the state of a replica is E or S, the data needs to be loaded from the L3 cache into the local L2 cache, the state changes to M, and the other replicas need to be invalidated. Considering continuity requirements, the data access latency is max(H). L2 +L L3-L2 The replica's state is changed to I;

[0049] If m is in state M, E, or S and a replacement miss occurs, a cache write miss will happen. First, the data is loaded from the L3 cache into the L2 cache, and then the write operation is performed. For the cases where m is in state M or E, the data access latency is H. L2 +L L3-L2 The state of m transitions to M; if the state of m is S, the data in other replicas needs to be invalidated. Considering continuity requirements, the data access latency is max(H). L2 +L L3-L2 The state of m changes from S to I.

[0050] Based on the above analysis, the state update function for cache cross-domain write access time and state transition can be derived:

[0051] Beneficial effects

[0052] This invention proposes a WCET analysis method for multi-core processors that supports multi-level consistency protocols. It introduces the concept of a multi-level consistency domain for the first time to describe the scope of multi-level consistency protocols on multi-core processors. It adopts the idea of ​​hierarchical domain division to divide data access in multi-core processors into two levels: intra-domain data access and cross-domain data access. It also addresses the WCET analysis problem in the case of nested multi-level consistency protocols, improves the analysis framework for multi-core processor caches, and provides support for WCET analysis of multi-core real-time systems. Attached Figure Description

[0053] The accompanying drawings are for illustrative purposes only and are not intended to limit the invention. Throughout the drawings, the same reference numerals denote the same parts.

[0054] Figure 1WCET analysis framework for multi-core processors based on consensus protocols;

[0055] Figure 2 MESI Consistency Protocol Cache State Diagram;

[0056] Figure 3 A cache analysis method based on abstract interpretation;

[0057] Figure 4 A schematic diagram of the consistency domain. Detailed Implementation

[0058] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention. Furthermore, the technical features involved in the various embodiments of this invention described below can be combined with each other as long as they do not conflict with each other.

[0059] While enabling multi-core processor coherence protocols can maintain the consistency of data copies in private caches, it also further increases the complexity of WCET analysis.

[0060] First, a cache model is established to describe the cache's structure, read / write methods, replacement policies, and consistency protocols. This model is an abstract description of the actual multi-core processor cache. Next, cache timing parameters are defined and configured, including cache memory access time, data loading time, and expiration time. These parameters provide input for WCET analysis. For processor hardware architectures with multi-level consistency protocols, a hierarchical domain approach is adopted, dividing the processor into multiple consistency domains. Intra-domain data access and cross-domain data access are analyzed separately, ultimately leading to an accurate calculation of the WCET for the multi-core processor.

[0061] Reference Figure 1-4 The steps of this invention regarding a WCET analysis method for multi-core processors supporting multi-level consensus protocols are as follows:

[0062] Step 1: Establish a multi-core processor cache model.

[0063] To analyze cache behavior, it is first necessary to establish a model of the cache for a multi-core processor. The cache model includes the cache's structure configuration, write policies, and replacement policies.

[0064] The cache model established accordingly is as follows:

[0065] CA = (C S C W C C)

[0066] In the formula: C S Representing the structure of the cache, C W This indicates the cache write policy. Within a consistency domain, a write-through and non-write-allocation write policy is used. Between consistency domains, a write-back and write-allocation write policy is used. C This method represents the cache coherence protocol, where the cache structure C... S The L1 cache is private, the L2 cache is locally shared, and the L3 cache is globally shared. W Within a consistency domain, a write-through and non-write-assignment write strategy is used; between consistency domains, a write-back and write-assignment write strategy is used. C C This applies only to the MESI consensus protocol, where M represents the Modify state, E represents the Exclusive state, S represents the Shared state, and I represents the Invalid state. For example... Figure 2 As shown.

[0067] Step 2: Define and configure the cache's time parameters.

[0068] Multi-core processors have private cache, shared cache, and main memory. The cache uses write-back and write-allocation strategies. Cache access is divided into read and write, and both read and write can result in access hits or misses. Therefore, we will analyze cache behavior from four aspects. Before we begin the analysis, we define the following symbols:

[0069] Ψ R (m,m′) / Ψ W (m,m′): Represents the cache read / write access latency and state transition within the domain, where m represents the accessed data and m′ represents a copy of the accessed data;

[0070] Ψ′ R (m,m′) / Ψ′ W (m,m′): Represents the cross-domain cache read / write access latency and state transition, where m represents the accessed data and m′ represents a copy of the accessed data;

[0071] T: Represents access time delay, and H is defined. p Indicates the private cache access hit time delay, H i This indicates the cache hit time latency at level i, L. i→j Inv represents the time delay of loading data from level i cache to level j cache, Inv represents the time delay of invalidating other data copies within the domain, and Inv′ represents the time delay of invalidating other data copies across domains.

[0072] m s / m′ s : Indicates the local / remote cache status;

[0073] This indicates that the accessed shared data was replaced out of the cache, resulting in a replacement miss / miss.

[0074] Step 3: Divide the consistency domain.

[0075] A set of kernels that use the same consistency protocol to manage data replicas is called a consistency domain, such as... Figure 4 As shown, multi-level consistency domains adopt the idea of ​​hierarchical domain partitioning, where a lower-level consistency domain is a node (clump) of an upper-level consistency domain.

[0076] Step 4: Intra-domain read access WCET analysis.

[0077] When the kernel issues a read request for data m, if m exists in L1 (its state may be E or S) and no replacement miss has occurred, a read hit can be achieved in L1, and the data access latency is H. L1 The state of all cache blocks will not change.

[0078] If data m is within the domain, and its state is E or S, but a replacement occurs and the data is missing, then the data access latency is the time Ψ′ to read data from L2. R Simultaneously, data needs to be loaded from the L2 cache into the local L1 cache. Considering consistency requirements, the data access latency is max(Ψ′). R ,L L2-L1 The cache state remains unchanged.

[0079] If data m is within the domain, m is in state I, and replica m' is in state E or S, then the data access latency is the time Ψ′ to read data from L2. R Simultaneously, data needs to be loaded from the L2 cache into the local L1 cache. Considering consistency requirements, the data access latency is max(Ψ′). R ,L L2-L1 When m's state is changed to S, the state of the copy m' is changed to S.

[0080] If data m is not in the domain, a miss will occur in the L2 cache. Assume the time to access the L2 cache is Ψ′. R For Ψ′ R We will analyze the value of in the next level. At this point, the state of m changes from I to E, and the state of the L2 Cache needs further analysis based on the L2 consistency protocol.

[0081] We can derive the state update function for read access latency and state transition within the cache domain:

[0082]

[0083] Step 5: Intradomain write access WCET analysis.

[0084] When the kernel issues a write request to m, if m only exists in the local L1 cache and its state is E, a cache write hit will occur. First, the data needs to be written to L1. According to the model in step 1, C... W As can be seen, since a write-through strategy is used within the domain, data needs to be written to L2 simultaneously, therefore the data access time is H. L1 +Ψ′ W The cache state remains unchanged; if m exists in the L1 cache and its state is S, a cache write hit will occur, and the data access latency will be H. L1 +Ψ′ W The state transitions to E. Due to the use of a write-failure consistency protocol, the replica's state needs to be modified to I. Considering consistency requirements, the final data access latency is max(H). L1 +Ψ′ W Inv).

[0085] If data m is located in the local L1 cache, and m is in state E or S, and a replacement miss occurs, a write miss will occur. If m is in state E, the data access time is Ψ′. W And the state changes to I; if the state of m is S, after performing an L2 cache write operation, write invalidation needs to be performed on other replicas, so the access time is max(Ψ′). W The states of m and its copy m' are both converted to I.

[0086] If data m is within the domain, and the state of m is I while the state of replica m' is E or S, a write operation will be performed on L2, invalidating the data in other replicas. Considering data continuity requirements, the data write latency is max(Ψ′). W Since non-write allocation is used, the state of the local L1 cache does not change, while the state of other replicas changes from E / S to I. The state of the L2 cache will be discussed in the next level.

[0087] If the data m is not within the domain, analogous to the read access case, assuming the write L2 cache access time is Ψ′ W For Ψ′ WWe will analyze the value of in the next level. Since non-write allocation is used within the domain, the state of m does not change at this time.

[0088] Based on the above analysis, the state update function for write access latency and state transition within the cache domain can be derived:

[0089] Step 6: Cross-domain read access WCET analysis.

[0090] When the kernel issues a read request for data m, if it needs to access the L2 cache, the shared data will be managed by the upper-level consistency protocol.

[0091] If data m exists within the domain and is located in the local L2 cache, the data access time is H. L2 The state of all caches across domains remains unchanged.

[0092] When the accessed data m exists in the L2 cache and a replacement miss occurs, the data access latency is H. L3 Simultaneously, data needs to be loaded into the L1 cache. Considering the consistency requirements, the data access latency is max(H). L3 ,L L3-L1 If the state of m is M or E, the state will change to E. If the state of m is S, the state will not change, and the state of the copy m' will not change.

[0093] If the accessed data m does not exist in the domain, there are two possibilities: either data m itself is not in the cache, or data m exists in the cache of another domain. If data m is not in the cache, it needs to be read from main memory, and the data access latency is H. m Simultaneously, data needs to be written from main memory back to the L1 cache. Considering consistency requirements, the data access latency is max(H). m ,L m-L1 The state of L2 changes from I to E.

[0094] If the data exists in another domain, i.e., a data copy m' exists, and if its state is M, the data must first be loaded from the L2 cache of the other domain into the local domain's L2 cache, then loaded into L1, and finally read from L1. The access latency is L. L2-L2 +L L2-L1 +H L1 At this point, the state of data m in L2 changes from I to S, and the state of data replica m' in other domains L2 changes from M to S.

[0095] If the state of data replica m' is E or S, the hit data will be read in L3, and the data access latency will be H. L3 Meanwhile, the data will be loaded into L1. Considering the continuity requirement, the data access latency should be max(H). L3 ,L L3-L1 At this point, the state of data m in L2 changes from I to S, and the state of data replica m' in other domains L2 changes to S.

[0096] Based on the above analysis, the state update functions for cache cross-domain read access time and state transition can be derived as follows:

[0097] Step 7: Cross-domain write access WCET analysis.

[0098] When the kernel issues a write request for data m, if write access to the L2 cache is required, the shared data will be managed by the upper-level consistency protocol.

[0099] If data m is within the domain and resides in the local L2 cache, with a state of S, and data in other replicas needs to be invalidated, considering continuity requirements, the data access time is max(H). L2 When the state of m changes to M, the replica's state changes from S to I; if the state of m is M or E, the data access time is H. L2 The state changes to M, while other cache states remain unchanged at I.

[0100] If the accessed data m does not exist within the domain, there are two possibilities: either data m itself is not in the cache, or data m exists in the cache of another domain. If data m is not in the cache, according to the model in step 1, C... W As can be seen, since inter-domain allocation uses write allocation, data must first be loaded from main memory into the L2 cache, and then the data is modified in the L2 cache. At this time, the data access latency is H. L2 +L m-L2 The L2 cache state changes from I to M.

[0101] If the data exists in another domain, the state of data m is I. If the state of data replica m' is M, the data must first be loaded from the other domain into the local L2 cache. Then, the data in the local L2 cache is modified, and the state changes to M. Additionally, other replicas must be invalidated. Considering consistency requirements, the data access latency is max(H). L2 +L L2-L2If the state of a replica is E or S, the data needs to be loaded from the L3 cache into the local L2 cache, the state changes to M, and the other replicas need to be invalidated. Considering continuity requirements, the data access latency is max(H). L2 +L L3-L2 ,Inv′), the replica's state is changed to I.

[0102] If m is in state M, E, or S and a replacement miss occurs, a cache write miss will happen. First, the data is loaded from the L3 cache into the L2 cache, and then the write operation is performed. For the cases where m is in state M or E, the data access latency is H. L2 +L L3-L2 If the state of m changes to M, and the state of m is S, then the data in other replicas needs to be invalidated. Considering continuity requirements, the data access latency is max(H). L2 +L L3-L2 ,Inv′), the state of m changes from S to I.

[0103] Based on the above analysis, the state update function for cache cross-domain write access time and state transition can be derived:

[0104] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the scope of the technology disclosed in the present invention, and such modifications or substitutions should all be covered within the scope of protection of the present invention.

Claims

1. A WCET analysis method for multi-core processors supporting multi-level consensus protocols, characterized in that... The steps are as follows: Step 1: Establish a multi-core processor cache model: CA=(C S ,C W ,C C ) In the formula: C S Representing the structure of the cache, C W This indicates the cache write policy. Within a consistency domain, a write-through and non-write-allocation write policy is used. Between consistency domains, a write-back and write-allocation write policy is used. C Represents the cache coherence protocol, cache structure C S The L1 cache is private, the L2 cache is locally shared, and the L3 cache is globally shared. W Within a consistency domain, a write-through and non-write-assignment write strategy is used; between consistency domains, a write-back and write-assignment write strategy is used. C C This applies only to the MESI consensus protocol, where M represents the Modify state, E represents the Exclusive state, S represents the Shared state, and I represents the Invalid state. C S It describes the entire processor's cache hierarchy and the specific configuration of each cache level; the model description of each level in the cache hierarchy is as follows: C S =(capacity,block_size,associativity,cores) In the formula, capacity represents the cache capacity, block_size represents the block size, associativity represents the associativity, and cores represents the kernels sharing this cache. For L1 cache, which is completely exclusive to the kernel and there is no sharing, the cache can be modeled by instantiating the cache models at each level. Step 2: Define and configure the cache's time parameters: Ψ R (m,m′) / Ψ W (m,m′): Represents the cache read / write access latency and state transition within the domain, where m represents the accessed data and m′ represents a copy of the accessed data; Ψ′ R (m,m′) / Ψ′ W (m,m′): Represents the cross-domain cache read / write access latency and state transition, where m represents the accessed data and m′ represents a copy of the accessed data; T: Represents access time delay, and H is defined. p Indicates the private cache access hit time delay, H i This indicates the cache hit time latency at level i, L. i→j Inv represents the time delay of loading data from level i cache to level j cache, Inv represents the time delay of invalidating other data copies within the domain, and Inv′ represents the time delay of invalidating other data copies across domains. m s / m′ s : Indicates the local / remote cache status; This indicates that the accessed shared data was replaced out of the cache, resulting in a replacement miss / miss. Step 3: Partitioning the Consistency Region A set of kernels that use the same consistency protocol to manage data replicas is called a consistency domain. Multi-level consistency domains adopt the idea of ​​hierarchical domain partitioning, where a lower-level consistency domain is a node clump of an upper-level consistency domain. Step 4: Intra-domain read access WCET analysis When the kernel issues a read request for data m, if m exists in L1 (its state may be E or S) and no replacement miss has occurred, a read hit can be achieved in L1, and the data access latency is H. L1 The state of all cache blocks will not change; If data m is within the domain, and its state is E or S, but a replacement occurs and the data is missing, then the data access latency is the time Ψ′ to read data from L2. R Simultaneously, data needs to be loaded from the L2 cache into the local L1 cache. Considering consistency requirements, the data access latency is max(Ψ′). R ,L L2-L1 The cache state remains unchanged. If data m is within the domain, m is in state I, and replica m' is in state E or S, then the data access latency is the time Ψ′ to read data from L2. R Simultaneously, data needs to be loaded from the L2 cache into the local L1 cache. Considering consistency requirements, the data access latency is max(Ψ′). R ,L L2-L1 The state of m is changed to S, and the state of the copy m' is changed to S; If data m is not in the domain, a miss will occur in the L2 cache. Assume the time to access the L2 cache is Ψ′. R For Ψ′ R We will analyze the value of m at the next level; at this point, the state of m changes from I to E, and the state of L2 Cache needs to be further analyzed according to the L2 consistency protocol. We can derive the state update function for read access latency and state transition within the cache domain: Step 5: Intra-domain write access WCET analysis When the kernel issues a write request to m, if m only exists in the local L1 cache and its state is E, a cache write hit will occur. First, the data needs to be written to L1. According to the model in step 1, C... W As can be seen, due to the use of a write-through strategy, data needs to be written to L2 simultaneously, therefore the data access time is H. L1 +Ψ′ W The cache state remains unchanged; if m exists in the L1 cache and its state is S, a cache write hit will occur, and the data access latency will be H. L1 +Ψ′ W The state transitions to E. Due to the use of a write-failure consistency protocol, the replica's state needs to be modified to I. Considering consistency requirements, the final data access latency is max(H). L1 +Ψ′ W ,Inv); If data m is located in the local L1 cache, and the state of m is E or S, and a replacement miss occurs, a write miss will occur; if the state of m is E, the data access time is Ψ′. W And the state changes to I; if the state of m is S, after performing an L2 cache write operation, write invalidation needs to be performed on other replicas, so the access time is max(Ψ′). W Inv), the states of both m and its copy m' are converted to I; If data m is within the domain, and the state of m is I while the state of replica m' is E or S, a write operation will be performed on L2, invalidating the data in other replicas. Considering data continuity requirements, the data write latency is max(Ψ′). W Since non-write allocation is used, the state of the local L1 cache does not change, while the state of other replicas changes from E / S to I. The state of the L2 cache will be discussed in the next level. If the data m is not within the domain, analogous to the read access case, assuming the write L2 cache access time is Ψ′ W For Ψ′ W We will analyze the value of in the next level; since non-write allocation is used in the domain, the state of m does not change at this time; Based on the above analysis, the state update function for write access latency and state transition within the cache domain can be derived: Step 6: Cross-domain read access WCET analysis When the kernel issues a read request for data m, if it needs to access the L2 cache, the shared data will be managed by the upper-level consistency protocol. If data m exists within the domain and is located in the local L2 cache, the data access time is H. L2 The state of all caches across domains remains unchanged; When the accessed data m exists in the L2 cache and a replacement miss occurs, the data access latency is H. L3 Simultaneously, data needs to be loaded into the L1 cache. Considering the consistency requirements, the data access latency is max(H). L3 ,L L3-L1 If the state of m is M or E, the state will change to E; if the state of m is S, the state will not change, and the state of the copy m' will not change. If the accessed data m does not exist in the domain, there are two possibilities: either data m itself is not in the cache, or data m exists in the cache of another domain. If data m is not in the cache, it needs to be read from main memory, and the data access latency is H. m Simultaneously, data needs to be written from main memory back to the L1 cache. Considering consistency requirements, the data access latency is max(H). m ,L m-L1 The state of L2 changes from I to E; If the data exists in another domain, i.e., a data copy m' exists, and if its state is M, the data must first be loaded from the L2 cache of the other domain into the local domain's L2 cache, then loaded into L1, and finally read from L1. The access latency is L. L2-L2 +L L2-L1 +H L1 At this time, the state of data m in L2 changes from I to S, and the state of data replica m' in other domains L2 changes from M to S; If the state of data replica m' is E or S, the hit data will be read in L3, and the data access latency will be H. L3 Meanwhile, the data will be loaded into L1. Considering the continuity requirement, the data access latency should be max(H). L3 ,L L3-L1 At this point, the state of data m in L2 changes from I to S, and the state of data replica m' in other domains L2 changes to S; Based on the above analysis, the state update functions for cache cross-domain read access time and state transition can be derived as follows: Step 7: Cross-domain write access WCET analysis When the kernel issues a write request for data m, if write access to the L2 cache is required, the shared data will be managed by the upper-level consistency protocol. If data m is within the domain and resides in the local L2 cache, with a state of S, and data in other replicas needs to be invalidated, considering continuity requirements, the data access time is max(H). L2 When the state of m changes to M, the replica's state changes from S to I; if the state of m is M or E, the data access time is H. L2 The state changes to M, while other cache states remain unchanged at I. If the accessed data m does not exist within the domain, there are two possibilities: either data m itself does not exist in the cache, or data m exists in the cache of another domain; if data m does not exist in the cache, according to the model in step 1, C W As can be seen, since inter-domain allocation uses write allocation, data must first be loaded from main memory into the L2 cache, and then the data is modified in the L2 cache. At this time, the data access latency is H. L2 +L m-L2 The L2 cache state changes from I to M; If the data exists in another domain, the state of data m is I. If the state of data replica m' is M, the data must first be loaded from the other domain into the local L2 cache. Then, the data in the local L2 cache is modified, and the state changes to M. Additionally, other replicas must be invalidated. Considering consistency requirements, the data access latency is max(H). L2 +L L2-L2 If the state of a replica is E or S, the data needs to be loaded from the L3 cache into the local L2 cache, the state changes to M, and the other replicas need to be invalidated. Considering continuity requirements, the data access latency is max(H). L2 +L L3-L2 The replica's state is changed to I; If m is in state M, E, or S and a replacement miss occurs, a cache write miss will happen. First, the data is loaded from the L3 cache to the L2 cache, and then the write operation is performed. For the cases where m is in state M or E, the data access latency is H. L2 +L L3-L2 The state of m transitions to M; if the state of m is S, the data in other replicas needs to be invalidated. Considering continuity requirements, the data access latency is max(H). L2 +L L3-L2 The state of m changes from S to I. Based on the above analysis, the state update function for cache cross-domain write access time and state transition can be derived:

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