Contact resistance acquisition method and device, electronic equipment and storage medium
By calculating the contact resistance based on the type and design parameters of the transistor device, the problem of low calculation accuracy in the prior art is solved, and the simulation accuracy and reliability are improved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- CHANGXIN MEMORY TECH INC
- Filing Date
- 2022-08-17
- Publication Date
- 2026-06-12
AI Technical Summary
Existing technologies for calculating the contact resistance of transistor devices in dynamic random access memory (DRAM) employ a single design rule, resulting in low calculation accuracy and impacting simulation precision and reliability.
Based on the type and design parameters of the transistor device, the contact resistance is determined as the equivalent resistance of multiple contact structures. The resistance value of the contact resistance is calculated using a formula, including determining the type, number, length, and standard unit resistance of the transistor device, and using the corresponding design parameters for calculation.
This improved the simulation accuracy and reliability of transistor devices, and yielded more accurate device electrical characteristics and circuit simulation values.
Smart Images
Figure CN115358170B_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of semiconductor technology, and in particular to a method, apparatus, electronic device, and storage medium for obtaining contact resistance. Background Technology
[0002] Dynamic Random Access Memory (DRAM) utilizes a large number of Metal-Oxide-Semiconductor Field-Effect Transistors (MOTEs). As DRAM technology nodes shrink, various design rules have emerged for transistor devices, resulting in diverse layouts of the gate, source, and drain structures. Consequently, the contact resistance of the transistor also varies with these design rules.
[0003] When simulating transistor devices, the calculation of the contact resistance generated at the source or drain will be based on the calculation method or empirical value of the contact resistance determined under the previous single design rule for the transistor's structural layout, and then applied to the structural layout of the transistor under the current multiple derived design rules.
[0004] However, the above method yields low accuracy in calculating contact resistance, which in turn reduces the accuracy and reliability of the simulation. Summary of the Invention
[0005] This disclosure provides a method, apparatus, electronic device, and storage medium for obtaining contact resistance, thereby improving the accuracy of contact resistance calculation and thus enhancing simulation accuracy and reliability.
[0006] According to some embodiments, the first aspect of this disclosure provides a method for obtaining contact resistance, applied to the model simulation of a transistor device, the transistor device including an active region and a gate located on the active region and a plurality of contact structures electrically connected to the source or drain; characterized in that it includes: determining the type of the transistor device; determining the design parameters of the transistor device according to the type of the transistor device; determining the contact resistance of the transistor device according to the design parameters of the transistor device; wherein the contact resistance of the transistor device is the equivalent resistance of the plurality of contact structures.
[0007] In some embodiments, the classification of transistor devices is determined by at least one of the following: channel type, gate thickness, and gate end structure.
[0008] In some embodiments, determining the type of a transistor device includes: obtaining the channel type of the transistor device, and determining, based on the channel type, whether the transistor device is a P-type transistor device or an N-type transistor device; and / or obtaining the gate thickness of the transistor device, and determining, based on the gate thickness, whether the transistor device is a thick-gate transistor device or a thin-gate transistor device; wherein the gate thickness of the thick-gate transistor device satisfies a first preset thickness range; and the thin-gate transistor device satisfies a second preset thickness range; and / or obtaining the gate end structure of the transistor device, and determining, based on the gate end structure, whether the transistor device is a hammered transistor device or a hammerless transistor device.
[0009] In some embodiments, obtaining the gate end structure of a transistor device includes: obtaining the gate length of the transistor device, and determining the gate end structure of the transistor device based on the channel type, gate thickness, and gate length of the transistor device; wherein the gate end structure of the transistor device includes hammer-type and hammerless type.
[0010] In some embodiments, determining the gate end structure of a transistor device based on the channel type, gate thickness, and gate length of the transistor device includes: determining a preset threshold for the gate length of the transistor device based on the channel type and gate thickness of the transistor device; determining whether the gate length of the transistor device is lower than the preset threshold; if so, the gate end structure of the transistor device is hammered; otherwise, the gate end structure of the transistor device is hammerless.
[0011] In some embodiments, the design parameters of the transistor device include: the length of the active region, the spacing between two adjacent contact structures, the maximum length of the contact structure, and the minimum length between the contact structure and the edge of the active region. Determining the contact resistance of the transistor device based on the design parameters includes: determining the number of contact structures based on the design parameters; determining the length of the contact structure based on the design parameters and the number of contact structures; obtaining the standard unit resistance of the contact structure; and determining the contact resistance of the transistor device based on the number of contact structures, the length of the contact structure, and the standard unit resistance of the contact structure.
[0012] In some embodiments, the number of contact structures is determined according to the design parameters of the transistor device, including: determining the number of contact structures based on a first formula according to the design parameters of the transistor device; wherein the first formula includes: N=ceiling[(W-2×S+P) / Lmax]; where N is the number of contact structures, which is a positive integer; ceiling[] is the calculation rule of rounding up; W is the length of the active region; S is the minimum length between the contact structure and the edge of the active region; P is the interval between two adjacent contact structures; and Lmax is the maximum length of the contact structure.
[0013] In some embodiments, the length of the contact structure is determined based on the design parameters of the transistor device and the number of contact structures, including: determining the length of the contact structure based on a second formula according to the design parameters of the transistor device and the number of contact structures; wherein the second formula includes: Lg=(W-2×S+P) / NP; where Lg is the length of the contact structure; N is the number of contact structures, which is a positive integer; W is the length of the active region; S is the minimum length between the edge of the contact structure and the active region; and P is the interval between two adjacent contact structures.
[0014] In some embodiments, the contact resistance of the transistor device is determined based on the number of contact structures, the length of the contact structures, and the standard unit resistance of the contact structures. This includes: determining the contact resistance of the transistor device based on a third formula, using the number of contact structures, the length of the contact structures, and the standard unit resistance of the contact structures. The third formula includes: Rlicon = Rx × Lg / N; where Rlicon is the contact resistance of the transistor device; Rx is the standard unit resistance of the contact structure; Lg is the length of the contact structure; and N is the number of contact structures, which is a positive integer.
[0015] In some embodiments, obtaining the standard unit resistance of the contact structure includes: determining the standard resistance and standard length of the contact structure according to the type of transistor device; and obtaining the standard unit resistance of the contact structure based on the standard resistance and standard length of the contact structure.
[0016] According to some embodiments, a second aspect of this disclosure provides a contact resistance acquisition device applied to the model simulation of a transistor device, the transistor device including an active region and a gate located on the active region and a plurality of contact structures electrically connected to the source or drain; characterized in that it includes: a first determining unit for determining the type of the transistor device and determining the design parameters of the transistor device according to the type of the transistor device; a second determining unit for determining the contact resistance of the transistor device according to the design parameters of the transistor device; wherein the contact resistance of the transistor device is the equivalent resistance of the plurality of contact structures.
[0017] In some embodiments, the classification of transistor devices is determined by at least one of the following: channel type, gate thickness, and gate end structure.
[0018] In some embodiments, the design parameters of the transistor device include: the length of the active region, the spacing between two adjacent contact structures, the maximum length of the contact structure, and the minimum length between the contact structure and the edge of the active region; the second determining unit is specifically used to determine the number of contact structures based on the design parameters of the transistor device; the second determining unit is further used to determine the length of the contact structure based on the design parameters of the transistor device and the number of contact structures; the second determining unit is further used to obtain the standard unit resistance of the contact structure, and determine the contact resistance of the transistor device based on the number of contact structures, the length of the contact structure, and the standard unit resistance of the contact structure.
[0019] According to some embodiments, a third aspect of this disclosure provides an electronic device, including: a processor and a memory communicatively connected to the processor; the memory stores computer-executable instructions; the processor executes the computer-executable instructions stored in the memory to implement the method as described in the first aspect.
[0020] According to some embodiments, a fourth aspect of this disclosure provides a computer-readable storage medium storing computer-executable instructions that, when executed by a processor, are used to implement the method as described in the first aspect.
[0021] The contact resistance acquisition method, apparatus, electronic device, and storage medium provided in this disclosure are applied to the model simulation of transistor devices. The transistor device includes an active region, a gate located on the active region, and multiple contact structures electrically connected to the source or drain. The method includes: determining the type of the transistor device; determining the design parameters of the transistor device based on the type; and determining the contact resistance of the transistor device based on the design parameters, wherein the contact resistance is the equivalent resistance of the multiple contact structures. In this disclosure, corresponding design parameters are used to calculate the contact resistance value according to different types of transistor devices, making the electrical characteristics of the transistor device more accurate and improving the simulation accuracy and reliability of the transistor device. Attached Figure Description
[0022] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure.
[0023] Figure 1 A flowchart of a method for obtaining contact resistance provided in an embodiment of this disclosure;
[0024] Figure 2A schematic diagram of a hammerless transistor device provided in an embodiment of this disclosure;
[0025] Figure 3 A schematic diagram of a transistor device with a hammerhead provided in an embodiment of this disclosure;
[0026] Figure 4 This is a schematic diagram of a contact resistance acquisition device provided in an embodiment of the present disclosure;
[0027] Figure 5 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this disclosure.
[0028] The accompanying drawings have illustrated specific embodiments of this disclosure, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the concept in any way, but rather to illustrate the concepts of this disclosure to those skilled in the art through reference to particular embodiments. Detailed Implementation
[0029] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numerals in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this disclosure. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this disclosure.
[0030] Dynamic Random Access Memory (DRAM) utilizes a large number of Metal-Oxide-Semiconductor Field-Effect Transistors (MOTEs). As DRAM technology nodes shrink, various design rules have emerged for transistor devices, resulting in diverse layouts of the gate, source, drain, and contact structures. Consequently, the contact resistance of the transistor also varies with these design rules.
[0031] In transistor device simulation, the calculation of contact resistance generated by contact structures on the source or drain is often done by applying the calculation method or empirical value of contact resistance determined under a previous single design rule to the current transistor layout under multiple derived design rules. However, the method of calculating contact resistance based on a single design rule is no longer compatible with the existing layout, which can cause significant errors in device and circuit simulation.
[0032] Based on this, the contact resistance acquisition method, apparatus, electronic device, and storage medium provided in this disclosure aim to solve the above-mentioned technical problems of the prior art. The contact resistance value is calculated using corresponding design parameters based on different types of transistor devices to obtain accurate device electrical characteristics and reliable circuit simulation values.
[0033] The technical solutions of this disclosure and how they solve the aforementioned technical problems will be described in detail below with specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments. The embodiments of this disclosure will now be described with reference to the accompanying drawings.
[0034] Figure 1 This is a flowchart illustrating a method for obtaining contact resistance according to an embodiment of the present disclosure. This method is applied to the model simulation of transistor devices.
[0035] The execution subject of this method can be a contact resistance acquisition device or a model simulation device of a transistor device integrating the contact resistance acquisition device. This device can be implemented through a computer program, such as application software; alternatively, it can be implemented as a medium storing the relevant computer program, such as a USB flash drive or cloud storage; or it can be implemented through a physical device integrating or installing the relevant computer program, such as a computer. The following explanation uses a contact resistance acquisition device as the execution subject as an example.
[0036] like Figure 1 As shown, the method may include the following steps:
[0037] S100. Determine the type of transistor device, and based on the type of transistor device, determine the design parameters of the transistor device;
[0038] S200. Determine the contact resistance of the transistor device based on its design parameters; wherein the contact resistance of the transistor device is the equivalent resistance of multiple contact structures.
[0039] A transistor device includes an active region, a gate located on the active region, and multiple contact structures electrically connected to the source or drain. These contact structures, such as wires connecting the source or drain, introduce contact resistance. Contact resistance affects the intrinsic characteristics of the transistor device, and its value influences the simulation results of the transistor device model.
[0040] Different types of transistor devices exhibit variations in the feature dimensions of the gate and contact structures, as well as their distribution in the active region. These differences all affect the calculation of contact resistance. This embodiment employs corresponding design parameters based on the type of transistor device to calculate the contact resistance value, thereby obtaining accurate device electrical characteristics and reliable circuit simulation values.
[0041] Figure 2 This is a schematic diagram of the structure of a hammerless transistor device provided in an embodiment of the present disclosure. Figure 3 This is a schematic diagram of a transistor device with a hammerhead provided in an embodiment of this disclosure. The following is in conjunction with... Figure 2 and Figure 3 The design parameters of transistor devices are explained.
[0042] like Figure 2 and Figure 3 As shown, it includes an active region, a gate located on the active region, and multiple contact structures symmetrically distributed on both sides of the gate. The gate's extension length in the y-direction is greater than the length of the active region in the y-direction. Each contact structure has the same feature size. Figure 2 and Figure 3 Taking four contact structures as an example, two contact structures are symmetrically distributed on both sides of the gate.
[0043] in, Figure 2 and Figure 3 The design parameters of the transistor device shown include: the length L of the gate in the x-direction (hereinafter referred to as the "gate length"); the length W of the active region in the y-direction (hereinafter referred to as the "active region length"); and the length Lg of the contact structure in the y-direction (hereinafter referred to as the "contact structure length"). Specifically, in... Figure 2 The middle is Lg1 or Figure 3 Lg2 is the distance between two adjacent contact structures in the y-direction; P is the minimum length S between the contact structure and the edge of the active region in the y-direction. Figure 2 S1 or Figure 3 S2 is the middle one.
[0044] in addition, Figure 2 and Figure 3 The design parameters for transistor devices not shown include the maximum length Lmax of the contact structure. Lmax represents the upper limit of the contact structure length in the design rules for this type of transistor device. Figure 2 and Figure 3 The design parameters for transistor devices not shown also include: gate thickness. The gate comprises a gate metal layer and a gate dielectric layer, and the gate thickness is the characteristic dimension of the gate dielectric layer in a direction perpendicular to the plane containing the active region.
[0045] The following explains the calculation process for the equivalent resistance of multiple contact structures located on the same side of the gate in a transistor device based on the above design parameters.
[0046] In some embodiments, step S200, determining the contact resistance of the transistor device based on its design parameters, includes:
[0047] S210. Determine the number of contact structures based on the design parameters of the transistor device;
[0048] S220. Determine the length of the contact structure based on the design parameters of the transistor device and the number of contact structures;
[0049] S230. Obtain the standard unit resistance of the contact structure. Based on the number of contact structures, the length of the contact structure, and the standard unit resistance of the contact structure, determine the contact resistance of the transistor device.
[0050] It should be noted that the number of contact structures determined in step S210 refers to the number of contact structures located on the gate side, and the contact resistance of the transistor device determined in step S230 refers to the equivalent resistance of the contact structures located on the gate side. Based on the symmetry characteristic, the equivalent resistance of the contact structures located on the other side of the gate can be obtained.
[0051] In one feasible implementation, step S210 involves determining the number of contact structures based on the design parameters of the transistor device. Specifically, this includes: establishing a table or database in advance to determine the correspondence between the design parameters and the number of contact structures; and determining the number of contact structures by querying an index based on the design parameters of the transistor device.
[0052] In another feasible implementation, step S210, determining the number of contact structures based on the design parameters of the transistor device, includes:
[0053] Based on the design parameters of the transistor device, the number of contact structures is determined according to a first formula; wherein the first formula includes:
[0054] N=ceiling[(W-2×S+P) / Lmax];
[0055] Where N is the number of contact structures, which is a positive integer; ceiling[] is the rounding rule; W is the length of the active region; S is the minimum length between the edge of the contact structure and the active region; P is the interval between two adjacent contact structures; and Lmax is the maximum length of the contact structure.
[0056] Specifically, the length W of the active region minus the minimum length 2S between the two contact structures and the edge of the active region equals the sum of the lengths of the first number (let's say a) of contact structures and the lengths of the intervals P between the first number minus one (i.e., a-1) of adjacent contact structures. (W-2×S+P) is then equal to the sum of the lengths of the first number (i.e., a) of contact structures and the lengths of the intervals P between the first number (i.e., a) of adjacent contact structures. Lmax is the maximum length of the contact structure. Dividing (W-2×S+P) by Lmax and rounding to the nearest integer yields the maximum number of contact structures that can be arranged on the gate side.
[0057] Furthermore, in some embodiments, step S220, determining the length of the contact structure based on the design parameters of the transistor device and the number of contact structures, includes:
[0058] Based on the design parameters of the transistor device and the number of contact structures, the length of the contact structure is determined using the second formula; wherein the second formula includes:
[0059] Lg=(W-2×S+P) / NP;
[0060] Where Lg is the length of the contact structure; N is the number of contact structures, which is a positive integer; W is the length of the active region; S is the minimum length between the edge of the contact structure and the active region; and P is the interval between two adjacent contact structures.
[0061] Specifically, the aforementioned known (W-2×S+P) is equal to the length of the first number (i.e., a) of contact structures and the length of the interval P between the first number (i.e., a) of adjacent contact structures. Since N is the integer result, (W-2×S+P) / N may not be exactly equal to Lmax; therefore, Lg cannot be determined directly by subtracting P from Lmax.
[0062] Furthermore, in some embodiments, step S230, determining the contact resistance of the transistor device based on the number of contact structures, the length of the contact structures, and the standard unit resistance of the contact structures, includes:
[0063] Based on the number of contact structures, the length of the contact structures, and the standard unit resistance of the contact structures, the contact resistance Rlicon of the transistor device is determined using the third formula; wherein the third formula includes:
[0064] Rlicon = Rx × Lg / N;
[0065] Where Rlicon is the contact resistance of the transistor device; Rx is the standard unit resistance of the contact structure; Lg is the length of the contact structure; and N is the number of contact structures, which is a positive integer.
[0066] Specifically, the resistance value of each contact structure is the same. The contact resistance Rlicon is the equivalent resistance value of multiple contact structures arranged in parallel on the same side of the gate. Therefore, it can be understood that (Rx×Lg) is the resistance value of a single contact structure; (Rx×Lg / N) is the equivalent resistance value of N contact structures connected in parallel.
[0067] Furthermore, in some embodiments, step S230, obtaining the standard unit resistance of the contact structure, specifically includes:
[0068] S231. Based on the type of transistor device, determine the standard resistance Rs and standard length Ls of the contact structure of that type of transistor device;
[0069] S232. Based on the standard resistance Rs and standard length Ls of the contact structure, obtain the standard unit resistance Rx of the contact structure.
[0070] In the simulation program implementing the resistance calculation method for the aforementioned contact structure, each design parameter related to the transistor device to be simulated can be directly used as input. One feasible implementation involves the technician inputting the specific values of each design parameter before simulation. Another feasible implementation involves the simulation program obtaining the specific values of each design parameter by reading a first file, where the specific values of each design parameter are directly recorded.
[0071] This embodiment statistically analyzes the design parameters in different design layouts and finds that some design parameters have the same value in multiple design layouts, while some design parameters have different values in each design layout.
[0072] In some embodiments, the spacing P between two adjacent contact structures in various design layouts takes the same value. Optionally, P can be set to a constant value in the simulation program, thereby reducing repetitive input, saving manpower, or reducing the size of the first file.
[0073] This embodiment further statistically analyzes the design parameters in different design layouts and finds a correlation between the values of the design parameters and the type of transistor. Optionally, the classification of transistor device types can be determined by at least one of the following: channel type, gate thickness, and gate end structure. Specifically, based on channel type, transistor devices can be divided into P-type transistor devices (hereinafter referred to as "PMOS") and N-type transistor devices (hereinafter referred to as "NMOS"); based on gate thickness, transistors can be divided into thick-gate transistor devices (thick MOS) and thin-gate transistor devices (thin MOS); based on gate end structure, transistors can be divided into hammerhead transistor devices (with hammerhead) and hammerless transistor devices (without hammerhead).
[0074] Specifically, the same design parameter may have different values in PMOS and NMOS, and / or different values in thick MOS and thin MOS, and / or different values in hammer-type transistor devices and hammerless transistor devices.
[0075] In some embodiments, the values of the design parameters may depend solely on whether the transistor is a hammered or hammerless transistor. For example, regardless of whether it is a thick-gate or thin-gate transistor, or whether it is PMOS or NMOS, for a hammerless transistor, the minimum length S between the contact structure and the edge of the active region is the same, assumed to be m1; for a hammered transistor, the minimum length S between the contact structure and the edge of the active region is the same, assumed to be m2, where m1 is not equal to m2.
[0076] Optionally, before simulation, the type of the transistor device can be manually entered or recorded in the first file as either a hammerless transistor device or a hammered transistor device. Based on the identified type of the transistor device, the corresponding S value is retrieved. If the S value has multiple decimal places, entering the type of the transistor device rather than entering a specific numerical value is more conducive to reducing the input error rate and also helps to quickly identify input errors.
[0077] In some embodiments, the values of the design parameters may depend both on whether the device is a hammered or hammerless transistor, and on whether it is a thick-gate or thin-gate transistor. For example, for a thin-gate transistor, the minimum length S between the contact structure and the edge of the active region is the same, assuming it to be m1, regardless of whether it is a hammered or hammerless transistor, or whether it is a PMOS or NMOS. For a thick-gate transistor, if it is also a hammerless transistor, the minimum length S between the contact structure and the edge of the active region is the same, assuming it to be m2, regardless of whether it is a PMOS or NMOS. For a thick-gate transistor, if it is also a hammered transistor, regardless of whether it is a PMOS or NMOS, the minimum length S between the contact structure and the edge of the active region is the same, assuming it to be m3. Here, m1, m2, and m3 are all unequal.
[0078] Optionally, before simulation, the type of transistor device can be manually entered or recorded in the first file as either a hammerless or hammered transistor device, and whether it is a thick-gate or thin-gate transistor device. Based on the identified type of transistor device, the corresponding S value is retrieved. If the S value has multiple decimal places, entering the type of transistor device is more beneficial in reducing the input error rate and in quickly identifying input errors than entering a specific numerical value.
[0079] In some embodiments, step S100, determining the type of transistor device includes: obtaining the channel type of the transistor device, and determining the type of transistor device, including a P-type transistor device or an N-type transistor device, based on the channel type of the transistor device.
[0080] And / or,
[0081] The gate thickness of the transistor device is obtained, and the type of the transistor device is determined to be a thick-gate transistor device or a thin-gate transistor device based on the gate thickness; wherein, the gate thickness of the thick-gate transistor device meets a first preset thickness range; and the thin-gate transistor device meets a second preset thickness range.
[0082] And / or,
[0083] Obtain the gate end structure of the transistor device, and determine whether the transistor device is a hammer-type transistor device or a hammerless transistor device based on the gate end structure.
[0084] In determining whether a transistor device is a thick-gate transistor or a thin-gate transistor, one feasible implementation is to manually input the type of the transistor device before simulation or to directly record it in the first file.
[0085] Another feasible implementation is to manually input or directly record the gate thickness of the transistor device in the first file before simulation, compare it with the preset thickness range, and then determine whether it is a thick gate transistor device or a thin gate transistor device.
[0086] To determine whether a transistor device is a hammered or non-hammered transistor device, one feasible approach is to manually input or directly record the type of the transistor device in the first file before simulation.
[0087] Another feasible implementation is to obtain the gate length of the transistor device, and determine the gate end structure of the transistor device based on the channel type, gate thickness, and gate length of the transistor device; wherein the gate end structure of the transistor device includes hammer-type and hammerless type.
[0088] Furthermore, in some embodiments, the gate end structure of the transistor device is determined based on the channel type, gate thickness, and gate length of the transistor device. Specifically, this includes: establishing a table or database in advance to determine the correspondence between the channel type, gate thickness, gate length, and gate end structure of the transistor device; and determining the gate end structure by querying the index.
[0089] Furthermore, in some embodiments, the gate end structure of the transistor device is determined based on the channel type, gate thickness, and gate length of the transistor device, specifically including:
[0090] Based on the channel type and gate thickness of the transistor device, a preset threshold for the gate length of the transistor device is determined; it is then determined whether the gate length of the transistor device is lower than the preset threshold; if so, the gate end structure of the transistor device is hammered; otherwise, the gate end structure of the transistor device is hammerless.
[0091] For example, for thin-gate transistor devices, regardless of whether they are PMOS or NMOS, if the gate length L is less than the value a1, the gate end structure of the transistor device is determined to be hammered; otherwise, it is hammerless. For thick-gate transistor devices, if it is an NMOS, if the gate length L is less than the value a2, the gate end structure of the transistor device is determined to be hammered; otherwise, it is hammerless. For thick-gate transistor devices, if it is a PMOS, if the gate length L is less than the value a3, the gate end structure of the transistor device is determined to be hammered; otherwise, it is hammerless. The values a1, a2, and a3 can be the same or different.
[0092] In some embodiments, in the simulation program, parameter type=1 is set to characterize the hammerless type; parameter type=2 is set to characterize the hammered type. Furthermore, other parameters can be set to characterize PMOS and NMOS; other parameters can also be set to characterize thick-gate and thin-gate.
[0093] The specific steps are as follows:
[0094] (1) Receive the simulation file, which contains the type of transistor device and some design parameters. For example, Ntn is used to characterize the thin-gate N-type transistor device, with a gate length L of 0.2 μm and an active region length W of 3.2 μm.
[0095] (2) Determine the gate end structure: type = f1(W, L, device type). Here, f1 is a function extracted from the design rules relating the active region length W, the gate length L, and the transistor device type (device type). This function f1 is not continuous, and type is a specific data point. The value of device type can be set to characterize the transistor device type as PMOS or NMOS, thick gate or thin gate. For example, setting device type = 1 characterizes thin-gate NMOS; setting device type = 2 characterizes thin-gate PMOS; setting device type = 3 characterizes thick-gate NMOS; and setting device type = 4 characterizes thick-gate PMOS.
[0096] (3) Calculate the number of contact structures: N = (W - 2 * S + P1) / Lmax; S = f2(type, S, W, L, devicetype). Where Lmax is a constant value in the design rules. f2 is a function of the gate end structure type, active region length W, gate length L, transistor device type, and the minimum length S between the contact structure and the edge of the active region. This function f2 is not continuous, and S represents a specific data point. N is an integer.
[0097] (4) Calculate the length of the contact structure: Lg=(W-2*S+P1) / N-P1.
[0098] (5) Calculate the equivalent resistance of multiple contact structures: Rlicon = Rs / Ls*Lg / N.
[0099] The contact resistance acquisition method provided in this disclosure is applied to the model simulation of a transistor device. The transistor device includes an active region, a gate located on the active region, and multiple contact structures electrically connected to the source or drain. The method includes: determining the type of the transistor device; determining the design parameters of the transistor device corresponding to that type based on the transistor device type; and determining the contact resistance of the transistor device based on the design parameters, wherein the contact resistance is the equivalent resistance of the multiple contact structures. In this disclosure, corresponding design parameters are used to calculate the contact resistance value according to different transistor device types, making the electrical characteristics of the transistor device more accurate and improving the simulation accuracy and reliability of the transistor device.
[0100] The following describes the apparatus, electronic device, and storage medium corresponding to the contact resistance acquisition method provided in the above embodiments. The content and effects can be found in the method section.
[0101] Figure 4 This is a schematic diagram of a contact resistance acquisition device provided in an embodiment of the present disclosure. The contact resistance acquisition device is used for model simulation of a transistor device, wherein the transistor device includes an active region, a gate located on the active region, and multiple contact structures electrically connected to the source or drain.
[0102] like Figure 4 As shown, the contact resistance measuring device includes:
[0103] The first determining unit 10 is used to determine the type of transistor device and, based on the type of transistor device, to determine the design parameters of the transistor device.
[0104] The second determining unit 20 is used to determine the contact resistance of the transistor device according to the design parameters of the transistor device; wherein the contact resistance of the transistor device is the equivalent resistance of multiple contact structures.
[0105] In some embodiments, the classification of transistor devices is determined by at least one of the following: channel type, gate thickness, and gate end structure.
[0106] In some embodiments, the first determining unit 10 is specifically used to obtain the channel type of the transistor device, and determine the type of the transistor device as either a P-type transistor device or an N-type transistor device based on the channel type; and / or, the first determining unit 10 is specifically used to obtain the gate thickness of the transistor device, and determine the type of the transistor device as either a thick-gate transistor device or a thin-gate transistor device based on the gate thickness; wherein the gate thickness of the thick-gate transistor device satisfies a first preset thickness range; and the thin-gate transistor device satisfies a second preset thickness range; and / or, the first determining unit 10 is specifically used to obtain the gate end structure of the transistor device, and determine the type of the transistor device as either a hammer-type transistor device or a hammerless transistor device based on the gate end structure.
[0107] In some embodiments, the first determining unit 10 is specifically used to obtain the gate length of the transistor device and determine the gate end structure of the transistor device based on the channel type, gate thickness, and gate length of the transistor device; wherein the gate end structure of the transistor device includes hammer-type and hammerless type.
[0108] In some embodiments, the first determining unit 10 is specifically used to determine a preset threshold for the gate length of the transistor device based on the channel type and gate thickness of the transistor device; the first determining unit 10 is also specifically used to determine whether the gate length of the transistor device is lower than the preset threshold; if so, the gate end structure of the transistor device is hammered; otherwise, the gate end structure of the transistor device is hammerless.
[0109] In some embodiments, the design parameters of the transistor device include: the length of the active region, the spacing between two adjacent contact structures, the maximum length of the contact structure, and the minimum length between the contact structure and the edge of the active region; the second determining unit 20 is specifically used to determine the number of contact structures according to the design parameters of the transistor device; the second determining unit 20 is further used to determine the length of the contact structure according to the design parameters of the transistor device and the number of contact structures; the second determining unit 20 is further used to obtain the standard unit resistance of the contact structure, and determine the contact resistance of the transistor device according to the number of contact structures, the length of the contact structure, and the standard unit resistance of the contact structure.
[0110] In some embodiments, the second determining unit 20 is specifically used to determine the number of contact structures based on the design parameters of the transistor device and a first formula; wherein the first formula includes: N = ceiling[(W-2×S+P) / Lmax]; where N is the number of contact structures and is a positive integer; ceiling[] is the calculation rule of rounding up; W is the length of the active region; S is the minimum length between the edge of the contact structure and the active region; P is the interval between two adjacent contact structures; and Lmax is the maximum length of the contact structure.
[0111] In some embodiments, the second determining unit 20 is specifically used to determine the length of the contact structure based on a second formula according to the design parameters of the transistor device and the number of contact structures; wherein the second formula includes: Lg=(W-2×S+P) / NP; where Lg is the length of a single contact structure; N is the number of contact structures, which is a positive integer; W is the length of the active region; S is the minimum length between the edge of the contact structure and the active region; and P is the interval between two adjacent contact structures.
[0112] In some embodiments, the second determining unit 20 is specifically used to determine the contact resistance of the transistor device based on a third formula, according to the number of contact structures, the length of the contact structures, and the standard unit resistance of the contact structures; wherein the third formula includes: R = Rx × Lg / N; where Rx is the standard unit resistance; Lg is the length of the contact structure; and N is the number of contact structures, which is a positive integer.
[0113] In some embodiments, the second determining unit 20 is specifically used to determine the standard resistance and standard length of the contact structure according to the type of transistor device; the second determining unit 20 is also specifically used to obtain the standard unit resistance of the contact structure according to the standard resistance and standard length of the contact structure.
[0114] The contact resistance acquisition device provided in this disclosure is applied to the model simulation of a transistor device. The transistor device includes an active region, a gate located on the active region, and multiple contact structures electrically connected to the source or drain. The contact resistance acquisition device includes: a first determining unit 10, used to determine the type of the transistor device and, based on the type, determine the design parameters of the transistor device; and a second determining unit 20, used to determine the contact resistance of the transistor device based on the design parameters. The contact resistance of the transistor device is the equivalent resistance of the multiple contact structures. In this disclosure, corresponding design parameters are used to calculate the contact resistance value according to different types of transistor devices, making the electrical characteristics of the transistor device more accurate and improving the simulation accuracy and reliability of the transistor device.
[0115] Figure 5 This is a schematic diagram of the structure of an electronic device provided in an embodiment of the present disclosure, such as... Figure 5 As shown, the electronic device includes:
[0116] The electronic device includes a processor 291 and a memory 292; it may also include a communication interface 293 and a bus 294. The processor 291, memory 292, and communication interface 293 can communicate with each other via the bus 294. The communication interface 293 can be used for information transmission. The processor 291 can invoke logical instructions stored in the memory 292 to execute the methods of the aforementioned embodiments.
[0117] Furthermore, the logic instructions in the aforementioned memory 292 can be implemented as software functional units and, when sold or used as independent products, can be stored in a computer-readable storage medium.
[0118] The memory 292, as a computer-readable storage medium, can be used to store software programs and computer-executable programs, such as program instructions / modules corresponding to the methods in the embodiments of this disclosure. The processor 291 executes functional applications and data processing by running the software programs, instructions, and modules stored in the memory 292, thereby implementing the methods in the above-described method embodiments.
[0119] The memory 292 may include a program storage area and a data storage area. The program storage area may store the operating system and application programs required for at least one function; the data storage area may store data created based on the use of the terminal device. Furthermore, the memory 292 may include high-speed random access memory and may also include non-volatile memory.
[0120] This disclosure provides a computer-readable storage medium storing computer-executable instructions, which, when executed by a processor, are used to implement the methods provided in the foregoing embodiments.
[0121] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This disclosure is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the following claims.
[0122] It should be understood that this disclosure is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this disclosure is limited only by the appended claims.
Claims
1. A method for obtaining contact resistance, applied to the model simulation of a transistor device, the transistor device comprising an active region and a gate located on the active region and a plurality of contact structures electrically connected to the source or drain; characterized in that, include: Determine the type of the transistor device, and based on the type of the transistor device, determine the design parameters of the transistor device; Based on the design parameters of the transistor device, the contact resistance of the transistor device is determined; wherein, the contact resistance of the transistor device is the equivalent resistance of the plurality of contact structures; The design parameters of the transistor device include: the length of the active region, the spacing between two adjacent contact structures, the maximum length of the contact structure, and the minimum length between the contact structure and the edge of the active region. Determining the contact resistance of the transistor device based on its design parameters includes: The number of contact structures is determined based on the design parameters of the transistor device; The length of the contact structure is determined based on the design parameters of the transistor device and the number of contact structures. Obtain the standard unit resistance of the contact structure, and determine the contact resistance of the transistor device based on the number of contact structures, the length of the contact structure, and the standard unit resistance of the contact structure.
2. The method according to claim 1, characterized in that, The classification of the transistor device type is determined by at least one of the following: channel type, gate thickness, and gate end structure.
3. The method according to claim 1, characterized in that, Determining the type of the transistor device includes: Obtain the channel type of the transistor device, and determine the type of the transistor device, including a P-type transistor device or an N-type transistor device, based on the channel type of the transistor device. And / or, The gate thickness of the transistor device is obtained, and the type of the transistor device is determined to be a thick-gate transistor device or a thin-gate transistor device based on the gate thickness of the transistor device; wherein, the gate thickness of the thick-gate transistor device meets a first preset thickness range; and the thin-gate transistor device meets a second preset thickness range. And / or, Obtain the gate end structure of the transistor device, and determine the type of the transistor device as a hammer-type transistor device or a hammerless transistor device based on the gate end structure of the transistor device.
4. The method according to claim 3, characterized in that, The process of obtaining the gate end structure of the transistor device includes: The gate length of the transistor device is obtained, and the gate end structure of the transistor device is determined based on the channel type, gate thickness, and gate length of the transistor device; wherein the gate end structure of the transistor device includes hammer-shaped and hammerless types.
5. The method according to claim 4, characterized in that, Determining the gate end structure of the transistor device based on the channel type, gate thickness, and gate length of the transistor device includes: A preset threshold for the gate length of the transistor device is determined based on the channel type and gate thickness of the transistor device. Determine whether the gate length of the transistor device is lower than the preset threshold; if so, the gate end structure of the transistor device is hammer-shaped; otherwise, the gate end structure of the transistor device is hammerless.
6. The method according to claim 1, characterized in that, Determining the number of contact structures based on the design parameters of the transistor device includes: Based on the design parameters of the transistor device, the number of contact structures is determined according to a first formula; wherein the first formula includes: N=ceiling[(W-2×S+P) / Lmax]; Where N is the number of contact structures, which is a positive integer; ceiling[] is the rounding rule; W is the length of the active region; S is the minimum length between the contact structure and the edge of the active region; P is the interval between two adjacent contact structures; and Lmax is the maximum length of the contact structure.
7. The method according to claim 1, characterized in that, Determining the length of the contact structure based on the design parameters of the transistor device and the number of contact structures includes: Based on the design parameters of the transistor device and the number of contact structures, the length of the contact structure is determined using a second formula; wherein the second formula includes: Lg = (W - 2 × S + P) / NP; Wherein, Lg is the length of the contact structure; N is the number of contact structures, which is a positive integer; W is the length of the active region; S is the minimum length between the edge of the contact structure and the active region; and P is the interval between two adjacent contact structures.
8. The method according to claim 1, characterized in that, Determining the contact resistance of the transistor device based on the number of contact structures, the length of the contact structures, and the standard unit resistance of the contact structures includes: Based on the number of contact structures, the length of the contact structures, and the standard unit resistance of the contact structures, the contact resistance of the transistor device is determined using a third formula; wherein the third formula includes: Rlicon = Rx × Lg / N; Wherein, Rlicon is the contact resistance of the transistor device; Rx is the standard unit resistance of the contact structure; Lg is the length of the contact structure; and N is the number of contact structures, which is a positive integer.
9. The method according to claim 1, characterized in that, Obtaining the standard unit resistance of the contact structure includes: The standard resistance and standard length of the contact structure are determined according to the type of the transistor device. The standard unit resistance of the contact structure is obtained based on its standard resistance and standard length.
10. A contact resistance acquisition device, applied to the model simulation of a transistor device, the transistor device comprising an active region and a gate located on the active region and a plurality of contact structures electrically connected to the source or drain; characterized in that, include: The first determining unit is used to determine the type of the transistor device and, based on the type of the transistor device, determine the design parameters of the transistor device. The second determining unit is used to determine the contact resistance of the transistor device based on the design parameters of the transistor device; wherein the contact resistance of the transistor device is the equivalent resistance of the plurality of contact structures; The design parameters of the transistor device include: the length of the active region, the spacing between two adjacent contact structures, the maximum length of the contact structure, and the minimum length between the contact structure and the edge of the active region. The second determining unit is specifically used to determine the number of contact structures based on the design parameters of the transistor device; The second determining unit is further configured to determine the length of the contact structure based on the design parameters of the transistor device and the number of contact structures; The second determining unit is further configured to obtain the standard unit resistance of the contact structure corresponding to the type of the transistor device, and determine the contact resistance of the transistor device based on the number of contact structures, the length of the contact structures and the standard unit resistance of the contact structures.
11. The apparatus according to claim 10, characterized in that, The classification of the transistor device type is determined by at least one of the following: channel type, gate thickness, and gate end structure.
12. An electronic device, characterized in that, include: A processor, and a memory communicatively connected to the processor; The memory stores computer-executed instructions; The processor executes computer execution instructions stored in the memory to implement the method as described in any one of claims 1-9.
13. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer-executable instructions, which, when executed by a processor, are used to implement the method as described in any one of claims 1-9.