Bit line strobe signal driving circuit
By adjusting the output buffer circuit structure of the bit line gating signal drive circuit, feedback is formed in high voltage mode using the strong driving capability of NMOS, which solves the high power consumption problem caused by the simultaneous conduction of PMOS and NMOS, and achieves low power consumption and high performance level switching.
Patent Information
- Application Number
- CN202211032820.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2022-08-26
- Publication Date
- 2026-02-24
- Estimated Expiration
- 2042-08-26
AI Technical Summary
In bit line gating signal drive circuits, in traditional designs, PMOS and NMOS tend to conduct simultaneously when high voltage flips, resulting in large instantaneous series current, increasing system power consumption and reducing performance.
By adjusting the output buffer circuit structure, the driving capability of NMOS is made much greater than that of PMOS. In high-voltage mode, NMOS pulls down the node first to form feedback, shuts off the competing path, and reduces the series current between PMOS and NMOS.
Without reducing the level switching speed, current consumption in high-voltage mode is significantly reduced, improving system performance and reducing power consumption.
Smart Images
Figure CN115359818B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to semiconductor circuit technology, and in particular to a bit line gating signal driving circuit. Background Technology
[0002] In memory design, because the operation of memory cells requires high voltage, level shifters are typically used in the circuit structure implementation. In flash memory design, bit line gating circuits usually use NMOS transistors as bit line gating switches, and the bit lines are selected or turned off by controlling the potential applied to the gate of the NMOS transistor.
[0003] like Figure 1 As shown, a 4-to-1 bit line gating circuit uses NMOS transistors MN0 to MN3 as gating transistors connected to bit lines (BL0 to BL3), and bit line gating signals YS0 to YS3 are connected to the gates of NMOS transistors MN0 to MN3, respectively. The bit line gating signals YS0 to YS3 are generated by a bit line gating decoding circuit. This decoding circuit typically consists of an address decoder and a driver circuit. The address decoder usually includes address input and enable input; the resulting logic signals are then passed through the driver circuit to generate the final bit line gating signals. The driver circuit primarily provides a large driving capability to drive the load of the bit line gating signals and provides a level-flipping function to switch from logic levels to high-voltage potentials.
[0004] The operating modes and operating voltages of the bit line strobe signals are shown in Table 1. In read mode, the high potential of the bit line strobe signal is the operating power supply VCC. The selected bit line strobe signal (one of YS0 to YS3) requires the operating power supply VCC, while the other unselected bit line strobe signals are at a low level (ground). In write mode, the high potential of the bit line strobe signal is a high voltage power supply, up to 10V. In this mode, the selected bit line strobe signal (one of YS0 to YS3) requires a 10V high voltage, while the other unselected bit line strobe signals are at a low level (ground). Typically, in read mode, the setup time of the bit line strobe signal needs to be less than 10 nanoseconds; in write mode, the setup time of the bit line strobe signal needs to be less than 20 nanoseconds.
[0005] Table 1:
[0006] Selected YS Unselected YS Read mode VCC 0 Write mode HV (10V) 0
[0007] Since the bit line strobe signal requires a high voltage in write mode, it needs to be implemented by a level-flipping circuit in the design.
[0008] Figure 2The traditional bit line strobe signal driving circuit is shown, which is composed of a first level shifter and a second output buffer.
[0009] The level shifter comprises a zeroth PMOS transistor MP00, a first PMOS transistor MP01, a second PMOS transistor MP02, a third PMOS transistor MP03, a zeroth NMOS transistor MN00, a first NMOS transistor MN01 and an inverter INV.
[0010] The output buffer comprises a fourth PMOS transistor MP04 and a second NMOS transistor MN02.
[0011] The drain of the zeroth PMOS transistor MP00 is connected to the source of the second PMOS transistor MP02.
[0012] The drain of the second PMOS transistor MP02, the drain of the zeroth NMOS transistor MN00 and the gate of the first PMOS transistor MP01 are connected to a first flip node OUTI.
[0013] The drain of the first PMOS transistor MP01 is connected to the source of the third PMOS transistor MP03.
[0014] The drain of the third PMOS transistor MP03, the drain of the first NMOS transistor MN01 and the gate of the zeroth PMOS transistor MP00 are connected to a second flip node OUTB.
[0015] The gate of the third PMOS transistor MP03, the gate of the first NMOS transistor MN01 and the input of the inverter INV are connected to an input signal IN.
[0016] The gate of the second PMOS transistor MP02, the gate of the zeroth NMOS transistor MN00 and the output of the inverter INV are connected to a third flip node INB.
[0017] The gate of the fourth PMOS transistor MP04 and the gate of the second NMOS transistor MN02 are connected to the second flip node OUTB.
[0018] The drain of the fourth PMOS transistor MP04 is connected to the drain of the second NMOS transistor MN02 and serves as an output of the driving circuit OUT.
[0019] The sources of the zeroth PMOS transistor MP00, the first PMOS transistor MP01 and the fourth PMOS transistor MP04 are connected to a power supply Power.
[0020] The sources of the zeroth NMOS transistor MN00, the first NMOS transistor MN01 and the second NMOS transistor MN02 are connected to a ground.
[0021] In low voltage mode, the power supply Power is equal to the working power VCC. When the input signal IN switches from low level (ground) to high level (VCC), the third flip node INB is flipped from high level (VCC) to low level (ground) by the inverter INV. The input signal IN flips to high level, which turns on the first NMOS MN01 and turns off the third PMOS MP03. The voltage of the second flip node OUTB is pulled down by the first NMOS MN01, and the zeroth NMOS MN00 is turned off due to the third flip node INB switching to low level (ground). The second PMOS MP02 is turned on. The zeroth PMOS MP00 is turned on due to the voltage of the second flip node OUTB being pulled down. The second PMOS MP02 and the zeroth PMOS MP00 are turned on to pull up the voltage of the first flip node OUTI. The voltage of the second flip node OUTB is pulled low, and the voltage of the output OUT of the driving circuit is pulled high by the fourth PMOS MP04 of the output buffer circuit. When the input signal IN switches from high level (VCC) to low level (ground), the voltage of the third flip node INB is pulled high by the inverter INV. The input signal IN flips to low level (ground), which turns off the first NMOS MN01 and turns on the third PMOS MP03. The voltage of the third flip node INB flips to high level (VCC), the zeroth NMOS MN00 is turned on, and the second PMOS MP02 is turned off. Due to the zeroth NMOS MN00 being turned on, the voltage of the first flip node OUTI is pulled low to low level (ground), which turns on the first PMOS MP01. The first PMOS MP01 and the third PMOS MP03 are turned on to pull up the voltage of the second flip node OUTB to high level (VCC). The voltage of the output OUT of the driving circuit is pulled low to low level (ground) by the second NMOS MN02 of the output buffer circuit.
[0022] In high voltage mode, Power is high voltage power supply, the voltage can be up to 10V. When the input signal IN switches from low level (ground) to high level (VCC), the third flip node INB is driven by the inverter INV from high level (VCC) to low level (ground); the input signal IN flips to high level, the first NMOS MN01 is turned on, and the second flip node OUTB voltage is pulled down. When the second flip node OUTB voltage is pulled down to the high voltage power supply (Power) minus a threshold voltage, the zeroth PMOS MP00 is turned on, and the second PMOS MP02 gate voltage (VCC) is much smaller than the high voltage power supply (Power) 10V. The second PMOS MP02 and the zeroth PMOS MP00 are turned on at the same time to quickly pull up the first flip node OUTI voltage to the high voltage potential 10V, so that the first PMOS MP01 is turned off until the second flip node OUTB voltage is pulled down to low level (ground). After the fourth PMOS MP04 of the output buffer circuit, the drive circuit output end OUT voltage is pulled up to the high voltage potential 10V. When the input signal IN switches from high level (VCC) to low level (ground), the third flip node INB voltage is pulled up by the inverter INV. The input signal IN flips to low level (ground), the first NMOS MN01 is turned off, the third flip node INB voltage flips to high level (VCC), the zeroth NMOS MN00 is turned on, and the first flip node OUTI voltage is pulled down. When the first flip node OUTI voltage is pulled down to the high voltage power supply (Power) minus a threshold voltage, the first PMOS MP01 is turned on, and the third PMOS MP03 gate voltage (VCC) is much smaller than the high voltage power supply (Power) 10V. The first PMOS MP01 and the third PMOS MP03 are turned on to pull up the second flip node OUTB voltage to high level (10V), so that the zeroth PMOS and the fourth PMOS MP04 are turned off, and the drive circuit output end OUT voltage is pulled down to low level (ground) by the second NMOS MN02 of the output buffer circuit.
[0023] In the above two modes, due to the characteristics of the level shifter that needs to be flipped at a positive high voltage (10V), the NMOS drive in the circuit design needs to be much larger than the PMOS, so that the first flip node OUTI or the second flip node OUTB voltage can be easily pulled down and quickly form feedback to flip the output voltage. The buffer circuit needs to drive the load and generally has a large size. Figure 2In the shown traditional circuit, when the circuit flips, the voltage of the second flip node OUTB has a ramping process from high to low and from low to high during the flipping process, especially because the PMOS of the level flip circuit is weak, the ramping time of the voltage of the second flip node OUTB from low to high is relatively long. During the ramping process of the voltage of the second flip node OUTB, the PMOS and the NMOS of the output buffer circuit are in a simultaneous conduction state, the slower the ramping speed, the greater the shoot-through current generated by the simultaneous conduction of the PMOS and the NMOS in the output buffer circuit. Especially when the power supply Power is a high voltage (10V), it takes a longer time for the voltage of the second flip node OUTB to change from a low level (ground) to a high level (10V), and in the high voltage mode, because the gate-drain voltage difference of the PMOS and the NMOS is larger, a larger shoot-through current will be generated. The large current generated on the high voltage power supply will greatly increase the power consumption of the system and reduce the performance of the system. SUMMARY
[0024] The technical problem to be solved by the present application is to provide a bit line selection signal driving circuit, which can eliminate the transient shoot-through current between the PMOS and the NMOS during voltage flipping of the level flip circuit without significantly reducing the flipping speed of the level flip circuit, achieve a low flipping current during the level flipping process, reduce the power consumption of the bit line selection signal driving circuit, and improve the performance of the bit line selection signal driving circuit.
[0025] To solve the above technical problem, the bit line selection signal driving circuit provided by the present application comprises a level flip circuit and an output buffer circuit.
[0026] The level flip circuit comprises a zeroth PMOS MP00, a first PMOS MP01, a second PMOS MP02, a third PMOS MP03, a zeroth NMOS MN00, a first NMOS MN01, and an inverter INV.
[0027] The drain of the zeroth PMOS MP00 is connected to the source of the second PMOS MP02.
[0028] The drain of the second PMOS MP02, the drain of the zeroth NMOS MN00, and the gate of the first PMOS MP01 are connected to a first flip node OUT.
[0029] The drain of the first PMOS MP01 is connected to the source of the third PMOS MP03.
[0030] The drain of the third PMOS MP03, the drain of the first NMOS MN01, and the gate of the zeroth PMOS MP00 are connected to a second flip node OUTB.
[0031] The gate terminal of the third PMOS transistor MP03, the gate terminal of the first NMOS transistor MN01 and the input terminal of the inverter INV are connected to the input signal IN.
[0032] The gate terminal of the second PMOS transistor MP02, the gate terminal of the zeroth NMOS transistor MN00 and the output terminal of the inverter INV are connected to the third flip node INB.
[0033] The source terminals of the zeroth NMOS transistor MN00 and the first NMOS transistor MN01 are connected to the ground.
[0034] The source terminals of the zeroth PMOS transistor MP00 and the first PMOS transistor MP01 are connected to the power supply Power.
[0035] The output buffer circuit comprises a fourteenth PMOS transistor MP14 and a fifteenth PMOS transistor MP15.
[0036] The drain terminal of the fourteenth PMOS transistor MP14 is connected to the source terminal of the fifteenth PMOS transistor MP15.
[0037] The drain terminal of the fifteenth PMOS transistor MP15 is connected to the first flip node OUT.
[0038] The first flip node OUT is used as the output terminal of the bit line strobe signal driving circuit.
[0039] The gate terminals of the fourteenth PMOS transistor MP14 and the fifteenth PMOS transistor MP15 are connected to the third flip node INB and the high voltage isolation signal HVISO respectively.
[0040] The source terminal of the fourteenth PMOS transistor MP14 is used to connect to the working voltage of the output buffer circuit.
[0041] In the low voltage mode, the power supply Power is equal to the working power supply VCC, and the high voltage isolation signal HVISO is at low level.
[0042] In the high voltage mode, the power supply Power is a high voltage power supply, and the high voltage isolation signal HVISO is at high level. The high voltage power supply is higher than the working power supply VCC.
[0043] Preferably, the high level potential is 8-10V, and the working power supply (VCC) is 1.6-4V.
[0044] Preferably, the source terminal, the body region of the zeroth PMOS transistor MP00 and the body region of the second PMOS transistor MP02 are short-circuited.
[0045] Preferably, the source terminal, the body region of the first PMOS transistor MP01 and the body region of the third PMOS transistor MP03 are short-circuited.
[0046] Preferably, the gate terminal of the fourteenth PMOS transistor MP14 is connected to the third flip node INB.
[0047] The gate of the fifteenth PMOS transistor, MP15, is used to connect to the high-voltage isolation signal HVISO.
[0048] The operating voltage of the output buffer circuit connected to the source terminal of the fourteenth PMOS transistor MP14 is the power supply.
[0049] The source and body regions of the fourteenth PMOS transistor MP14 and the body region of the fifteenth PMOS transistor MP15 are shorted.
[0050] Preferably, the gate of the fourteenth PMOS transistor MP14 is connected to the third flip node INB;
[0051] The gate of the fifteenth PMOS transistor, MP15, is used to connect to the high-voltage isolation signal HVISO.
[0052] The operating voltage of the output buffer circuit connected to the source terminal of the fourteenth PMOS transistor MP14 is the operating power supply VCC.
[0053] Both the body regions of the fourteenth PMOS transistor MP14 and the fifteenth PMOS transistor MP15 are connected to the power supply.
[0054] Preferably, the gate of the fourteenth PMOS transistor MP14 is connected to the third flip node INB;
[0055] The gate of the fifteenth PMOS transistor, MP15, is used to connect to the high-voltage isolation signal HVISO.
[0056] The operating voltage of the output buffer circuit connected to the source terminal of the fourteenth PMOS transistor MP14 is the operating power supply VCC.
[0057] The source terminal of the fourteenth PMOS transistor MP14 is shorted in the same-body region;
[0058] The fifteenth PMOS transistor, MP15, is connected to the power supply in its body region.
[0059] Preferably, the gate terminal of the fourteenth PMOS transistor MP14 is connected to the high-voltage isolation signal HVISO;
[0060] The gate of the fifteenth PMOS transistor MP15 is connected to the third flip node INB;
[0061] The operating voltage of the output buffer circuit connected to the source terminal of the fourteenth PMOS transistor MP14 is the power supply.
[0062] The source and body regions of the fourteenth PMOS transistor MP14 and the body region of the fifteenth PMOS transistor MP15 are all connected to the power supply.
[0063] The bit line gating signal driving circuit of this invention, by changing the output buffer circuit structure, achieves a significant improvement in performance during high-voltage mode switching. Because the NMOS driving capability in the previous level shifter is much greater than that of the PMOS, the NMOS can easily pull down the node during switching, enabling feedback in the level shifter and shutting off the contention path. Since the PMOS driving capability is weaker, the series current between the PMOS and NMOS in the level shifter during switching is much smaller than in traditional driving circuit structures. Especially in high-voltage mode, reducing the current consumed by the high-voltage power supply greatly improves the overall system performance, achieving low power consumption. In low-voltage mode, the PMOS of the output buffer circuit outputs a high level, while the NMOS of the level shifter circuit outputs a low level. In high-voltage mode, the PMOS of the output buffer circuit is turned off, and the output is directly driven by the level shifter circuit. Without significantly reducing the switching speed of the level shifter circuit, the circuit eliminates the instantaneous series current that exists when the PMOS and NMOS are simultaneously conducting during voltage switching, thus achieving the goal of low switching current during level switching (especially in high-voltage mode). This reduces the power consumption of the bit line gating signal driving circuit and improves its performance. Attached Figure Description
[0064] To more clearly illustrate the technical solution of the present invention, the accompanying drawings used in the present invention will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0065] Figure 1 This is a schematic diagram of the bit line gating circuit and the generation of the gating signal;
[0066] Figure 2 There is an existing bit line gating signal driving circuit;
[0067] Figure 3 This is the first embodiment of the bit line gating signal driving circuit of the present invention;
[0068] Figure 4 This is the first embodiment of the bit line gating signal driving circuit of the present invention;
[0069] Figure 5 This is the first embodiment of the bit line gating signal driving circuit of the present invention;
[0070] Figure 6This is the first embodiment of the bit line gating signal driving circuit of the present invention. Detailed Implementation
[0071] The technical solutions of the present invention will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.
[0072] Example 1
[0073] like Figure 3 , Figure 4 , Figure 5 , Figure 6 As shown, the bit line strobe signal driving circuit includes a level shifter and an output buffer.
[0074] The level-flipping circuit includes a zero-th PMOS transistor MP00, a first PMOS transistor MP01, a second PMOS transistor MP02, a third PMOS transistor MP03, a zero-th NMOS transistor MN00, a first NMOS transistor MN01, and an inverter INV;
[0075] The drain of the zeroth PMOS transistor MP00 is connected to the source of the second PMOS transistor MP02;
[0076] The drain of the second PMOS transistor MP02, the drain of the zeroth NMOS transistor MN00, and the gate of the first PMOS transistor MP01 are all connected to the first flip node OUT.
[0077] The drain of the first PMOS transistor MP01 is connected to the source of the third PMOS transistor MP03;
[0078] The drain of the third PMOS transistor MP03, the drain of the first NMOS transistor MN01, and the gate of the zeroth PMOS transistor MP00 are all connected to the second flip node OUTB.
[0079] The gate terminal of the third PMOS transistor MP03, the gate terminal of the first NMOS transistor MN01, and the input terminal of the inverter INV are all connected to the input signal IN.
[0080] The gate of the second PMOS transistor MP02, the gate of the zeroth NMOS transistor MN00, and the output of the inverter INV are all connected to the third flip node INB.
[0081] The source terminals of the zeroth NMOS transistor MN00 and the first NMOS transistor MN01 are grounded;
[0082] The source terminals of the zeroth PMOS transistor MP00 and the first PMOS transistor MP01 are connected to the power supply.
[0083] The output buffer circuit includes the fourteenth PMOS transistor MP14 and the fifteenth PMOS transistor MP15;
[0084] The drain of the fourteenth PMOS transistor MP14 is connected to the source of the fifteenth PMOS transistor MP15;
[0085] The drain of the fifteenth PMOS transistor MP15 is connected to the first flip-out node OUT.
[0086] The first flip node OUT serves as the output terminal of the bit line gating signal driving circuit.
[0087] The gate of the fourteenth PMOS transistor MP14 and the gate of the fifteenth PMOS transistor MP15 are connected, one to the third flip node INB and the other to the high-voltage isolation signal HVISO.
[0088] The source terminal of the fourteenth PMOS transistor MP14 is used to connect to the operating voltage of the output buffer circuit.
[0089] In low-voltage mode (read mode), the power supply Power is equal to the operating power supply VCC, and the high-voltage isolation signal HVISO is low (ground potential).
[0090] In high-voltage mode (write mode), the power supply is a high-voltage power supply, and the high-voltage isolation signal HVISO is high; the high-voltage power supply is higher than the operating power supply VCC.
[0091] Ideally, the high-level potential and the high-voltage power supply should both be 8-10V, and the operating power supply VCC should be 1.6-4V.
[0092] Preferably, the source and body regions of the zeroth PMOS transistor MP00 and the body region of the second PMOS transistor MP02 are shorted.
[0093] Preferably, the source and body regions of the first PMOS transistor MP01 and the body region of the third PMOS transistor MP03 are shorted.
[0094] The bit line gating signal driving circuit in Example 1, by changing the output buffer circuit structure, achieves a significant improvement in driving capability during high-voltage switching. This is because the NMOS driving capability in the preceding level shifter is much greater than that of the PMOS (in typical positive voltage level shifting circuit designs, when the input signal applied to the NMOS gate changes, the NMOS competes with its connected PMOS, requiring the NMOS to drive more strongly than the PMOS to ensure normal operation of the level shifting circuit. Generally, the gate-source voltage difference when the NMOS is turned on is the operating power supply VCC voltage, while the gate-source voltage difference of the PMOS at the initial switching is high voltage (10V). To ensure the performance of the high-voltage level shifting circuit, the NMOS driving capability must be much greater than that of the PMOS). During the switching process, the NMOS can easily pull down the node, enabling the level shifter to form feedback and shut off the competing path. Due to the weaker driving capability of the PMOS, the series current between the PMOS and NMOS in the level shifting circuit during switching will be much smaller than in traditional driving circuit structures. Especially in high-voltage mode, reducing the current consumed by the high-voltage power supply will greatly improve the overall system performance and achieve low power consumption. In the bit line gating signal driving circuit of Embodiment 1, under low voltage mode, the PMOS of the output buffer circuit outputs a high level, and the NMOS of the level shifter circuit outputs a low level; under high voltage mode, the PMOS of the output buffer circuit is turned off, and the output is directly driven by the level shifter circuit. Without significantly reducing the switching speed of the level shifter circuit, the instantaneous series current existing between the PMOS and NMOS when the voltage of the level shifter circuit is switched on is eliminated, thereby achieving the purpose of low switching current during the level switching process (especially in high voltage mode), reducing the power consumption of the bit line gating signal driving circuit, and improving the performance of the bit line gating signal driving circuit.
[0095] Example 2
[0096] Based on the bit line gating signal driving circuit of Embodiment 1, such as Figure 3 As shown, the gate of the fourteenth PMOS transistor MP14 is connected to the third flip node INB;
[0097] The gate of the fifteenth PMOS transistor, MP15, is used to connect to the high-voltage isolation signal HVISO.
[0098] The operating voltage of the output buffer circuit connected to the source terminal of the fourteenth PMOS transistor MP14 is the power supply.
[0099] The source and body regions of the fourteenth PMOS transistor MP14 and the body region of the fifteenth PMOS transistor MP15 are shorted.
[0100] The bit line gating signal driving circuit in Example 2 works as follows:
[0101] In low-voltage mode, the power supply Power equals the VCC power supply, and HVISO is low (ground potential). When the input signal IN switches from low (ground) to high (VCC), the third flip node INB is driven by the inverter to flip from high (VCC) to low (ground). When the input signal IN flips to a high level, it turns on the first NMOS transistor MN01 and turns off the third PMOS transistor MP03. The voltage of the second flip node OUTB is pulled down by the first NMOS transistor MN01. At the same time, since the third flip node INB switches to a low potential (ground), the zeroth NMOS transistor MN00 turns off, and the second PMOS transistor MP02 and the fourteenth PMOS transistor MP14 turn on. The zeroth PMOS transistor MP00 also turns on due to the pull-down voltage of the second flip node OUTB. The zeroth PMOS transistor MP00, the second PMOS transistor MP02, the fourteenth PMOS transistor MP14, and the fifteenth PMOS transistor MP15 pull up the voltage of the first flip node OUT (as the output of the drive circuit). The driving capability of the zeroth PMOS transistor MP00 and the second PMOS transistor MP02 is relatively weak, and the voltage of the first flip node OUT... (As the output of the driving circuit) It is mainly driven by the fourteenth PMOS transistor MP14 and the fifteenth PMOS transistor MP15. When the input signal IN switches from high level (VCC) to low level (ground), the voltage of the third flip node INB is pulled high by the inverter INV, and the input signal IN flips to low level (ground), which turns off the first NMOS transistor MN01 and turns on the third PMOS transistor MP03. The voltage of the third flip node INB flips to high level (VCC), the zeroth NMOS transistor MN00 turns on, and the second PMOS transistor MP02 and the fourteenth PMOS transistor MP14 turn off. Since the zeroth NMOS transistor MN00 is turned on, the first flip node OUT (as the output of the driving circuit) is pulled low to low level (ground). The NMOS driving capability in the level flipping circuit is relatively strong and can drive the load.
[0102] In high-voltage mode, the power supply Power is a high-voltage power supply (voltage can reach 10V), and HVISO is high level (10V). When the input signal IN switches from low level (ground) to high level (VCC), the third flip node INB is driven by the inverter INV to flip from high level (VCC) to low level (ground); when the input signal IN flips to high level, the first NMOS transistor MN01 is turned on, and the voltage of the second flip node OUTB is pulled down by the first NMOS transistor MN01. At the same time, since the third flip node INB switches to low level (ground), the zeroth NMOS transistor MN00 is turned off, and the second PMOS transistor MP02 is turned on; when the voltage of the second flip node OUTB is pulled down to the high-voltage power supply minus a threshold voltage, the zeroth PMOS transistor MP00 is turned on, and the second PMOS transistor MP02 and the zeroth PMOS transistor MP00 are turned on at the same time to pull up the voltage of the first flip node OUT (as the output of the drive circuit), while turning off the first PMOS transistor MP01. The gate-source voltage difference between the second PMOS transistor MP02 and the zeroth PMOS transistor MP00 is 10V, which is sufficient to drive the first flip node OUT (as the output of the drive circuit). When the input signal IN switches from high level (VCC) to low level (ground), the voltage of the third flip node INB is pulled high by the inverter INV. When the input signal IN flips to low level (ground), the first NMOS transistor MN01 is turned off, the voltage of the third flip node INB flips to high level (VCC), and the zeroth NMOS transistor MN00 is turned on. Because the zeroth NMOS transistor MN00 is turned on, the first flip node OUT (as the output of the drive circuit) is pulled low to low level (ground). The NMOS driving capability in the level flipping circuit is relatively strong and sufficient to drive the load.
[0103] The bit line strobe signal driving circuit of Embodiment 2 has the corresponding memory operation mode and operating voltage as shown in Table 2.
[0104] Table 2:
[0105]
[0106] Example 3
[0107] Based on the bit line gating signal driving circuit of Embodiment 1, such as Figure 4 As shown, the gate of the fourteenth PMOS transistor MP14 is connected to the third flip node INB;
[0108] The gate of the fifteenth PMOS transistor, MP15, is used to connect to the high-voltage isolation signal HVISO.
[0109] The operating voltage of the output buffer circuit connected to the source terminal of the fourteenth PMOS transistor MP14 is the operating power supply VCC.
[0110] Both the body regions of the fourteenth PMOS transistor MP14 and the fifteenth PMOS transistor MP15 are connected to the power supply.
[0111] Example 4
[0112] Based on the bit line gating signal driving circuit of Embodiment 1, such as Figure 5 As shown, the gate of the fourteenth PMOS transistor MP14 is connected to the third flip node INB;
[0113] The gate of the fifteenth PMOS transistor, MP15, is used to connect to the high-voltage isolation signal HVISO.
[0114] The operating voltage of the output buffer circuit connected to the source terminal of the fourteenth PMOS transistor MP14 is the operating power supply VCC.
[0115] The source terminal of the fourteenth PMOS transistor MP14 is shorted in the same-body region;
[0116] The fifteenth PMOS transistor, MP15, is connected to the power supply in its body region.
[0117] Example 5
[0118] Based on the bit line gating signal driving circuit of Embodiment 1, such as Figure 6 As shown, the gate terminal of the fourteenth PMOS transistor MP14 is connected to the high-voltage isolation signal HVISO;
[0119] The gate of the fifteenth PMOS transistor MP15 is connected to the third flip node INB;
[0120] The operating voltage of the output buffer circuit connected to the source terminal of the fourteenth PMOS transistor MP14 is the power supply.
[0121] The source and body regions of the fourteenth PMOS transistor MP14 and the body region of the fifteenth PMOS transistor MP15 are all connected to the power supply.
[0122] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.
Claims
1. A bit line gating signal driving circuit, characterized in that, It includes a level-flipping circuit and an output buffer circuit; The level-flipping circuit includes a zeroth PMOS transistor (MP00), a first PMOS transistor (MP01), a second PMOS transistor (MP02), a third PMOS transistor (MP03), a zeroth NMOS transistor (MN00), a first NMOS transistor (MN01), and an inverter (INV); The drain of the zeroth PMOS transistor (MP00) is connected to the source of the second PMOS transistor (MP02); The drain of the second PMOS transistor (MP02), the drain of the zeroth NMOS transistor (MN00), and the gate of the first PMOS transistor (MP01) are all connected to the first flip node (OUT). The drain of the first PMOS transistor (MP01) is connected to the source of the third PMOS transistor (MP03); The drain of the third PMOS transistor (MP03), the drain of the first NMOS transistor (MN01), and the gate of the zeroth PMOS transistor (MP00) are all connected to the second flip node (OUTB). The gate of the third PMOS transistor (MP03), the gate of the first NMOS transistor (MN01), and the input of the inverter (INV) are all connected to the input signal (IN); The gate of the second PMOS transistor (MP02), the gate of the zeroth NMOS transistor (MN00), and the output of the inverter (INV) are all connected to the third flip node (INB); The source terminals of the zeroth NMOS transistor (MN00) and the first NMOS transistor (MN01) are grounded; The source terminals of the zeroth PMOS transistor (MP00) and the first PMOS transistor (MP01) are connected to the power supply. The output buffer circuit includes the fourteenth PMOS transistor (MP14) and the fifteenth PMOS transistor (MP15); The drain of the fourteenth PMOS transistor (MP14) is connected to the source of the fifteenth PMOS transistor (MP15); The drain of the fifteenth PMOS transistor (MP15) is connected to the first flip node (OUT); The first flip node (OUT) serves as the output terminal of the bit line gating signal driving circuit; The gate of the fourteenth PMOS transistor (MP14) and the gate of the fifteenth PMOS transistor (MP15) are connected, one of which is connected to the third flip node (INB), and the other is used to connect to the high voltage isolation signal (HVISO). The source terminal of the fourteenth PMOS transistor (MP14) is used to connect to the operating voltage of the output buffer circuit; In low-voltage mode, the power supply (Power) is equal to the operating power supply (VCC), and the high-voltage isolation signal (HVISO) is low. In high-voltage mode, the power supply is a high-voltage power supply, and the high-voltage isolation signal (HVISO) is at a high level; the high-voltage power supply is higher than the operating power supply (VCC).
2. The bit line gating signal driving circuit according to claim 1, characterized in that, The high-level potential is 8-10V, the same as the high-voltage power supply, and the working power supply (VCC) is 1.6-4V.
3. The bit line gating signal driving circuit according to claim 1, characterized in that, The source and body regions of the zeroth PMOS transistor (MP00) and the body region of the second PMOS transistor (MP02) are shorted.
4. The bit line gating signal driving circuit according to claim 1, characterized in that, The source and body regions of the first PMOS transistor (MP01) and the body region of the third PMOS transistor (MP03) are shorted.
5. The bit line gating signal driving circuit according to claim 1, characterized in that, The gate of the fourteenth PMOS transistor (MP14) is connected to the third flip node (INB); The gate of the fifteenth PMOS transistor (MP15) is used to connect to a high-voltage isolation signal (HVISO); The operating voltage of the output buffer circuit connected to the source terminal of the fourteenth PMOS transistor (MP14) is the power supply. The source and body regions of the fourteenth PMOS transistor (MP14) and the body region of the fifteenth PMOS transistor (MP15) are shorted.
6. The bit line gating signal driving circuit according to claim 1, characterized in that, The gate of the fourteenth PMOS transistor (MP14) is connected to the third flip node (INB); The gate of the fifteenth PMOS transistor (MP15) is used to connect to a high-voltage isolation signal (HVISO); The operating voltage of the output buffer circuit connected to the source terminal of the fourteenth PMOS transistor (MP14) is the operating power supply (VCC); Both the body regions of the fourteenth PMOS transistor (MP14) and the fifteenth PMOS transistor (MP15) are connected to the power supply.
7. The bit line gating signal driving circuit according to claim 1, characterized in that, The gate of the fourteenth PMOS transistor (MP14) is connected to the third flip node (INB); The gate of the fifteenth PMOS transistor (MP15) is used to connect to a high-voltage isolation signal (HVISO); The operating voltage of the output buffer circuit connected to the source terminal of the fourteenth PMOS transistor (MP14) is the operating power supply (VCC); The source terminal of the fourteenth PMOS transistor (MP14) is shorted in the same region as the body. The fifteenth PMOS transistor (MP15) is connected to the power supply in the body area.
8. The bit line gating signal driving circuit according to claim 1, characterized in that, The gate of the fourteenth PMOS transistor MP14 is connected to a high-voltage isolation signal (HVISO); The gate of the fifteenth PMOS transistor MP15 is connected to the third flip node (INB); The operating voltage of the output buffer circuit connected to the source terminal of the fourteenth PMOS transistor MP14 is the power supply. The source and body regions of the fourteenth PMOS transistor MP14 and the body region of the fifteenth PMOS transistor MP15 are all connected to the power supply.
Citation Information
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