A memory chip test key protection method, device and equipment

Abstract

The present application proposes a method, device, and equipment for protecting a memory chip test key, specifically comprising: when the chip is powered on again, the target key processing module obtains a pre-stored target key and a target key enable field, wherein the target key enable field includes a port level signal for controlling the activation of the test control module; the target key processing module loads the target key into a target key register that clears data upon power failure; the target key processing module controls the activation of the test control module according to the port level signal of the target key enable field, so that the test control module receives and compares the user input key with the target key to determine whether it is consistent, and determines whether the user input key is correct. The method, device, and equipment for protecting a memory chip test key described in the present application improve the timing complexity and circuit complexity, making it difficult for other organizations or individuals to determine the target key and the target key enable field through circuit analysis.

Description

TECHNICAL FIELD

[0001] The present application relates to the chip key protection technical field, and particularly relates to a memory chip test key protection method, device and equipment. BACKGROUND

[0002] In the memory chip field, different wafer production processes often bring changes in the characteristics of memory cells, so the control method or control precision of the entire memory cell peripheral circuit also changes, including: selection of control precision of analog modules, selection of control method of digital modules, selection of data path, selection of circuit working speed, and selection or configuration of other parts. For example, the target clock of the generation circuit of the chip internal clock oscillator is 50MHz. Considering the process changes or deviations in the production process, the designer usually selects multiple RC parameters for the oscillator. During chip testing, the tester will enter the chip into test mode, find the configuration parameters closest to 50MHz, and then store the selection information in the boot memory.

[0003] When a chip with excellent design has good market sales, other institutions or individuals may open the cover, take photos of the circuit and analyze it, and perform real-time circuit analysis in the test mode. In this case, if the chip test key is simple or the protection strength is low, other institutions or individuals can usually guess the key through shmoo test or infer the key through circuit logic analysis. After obtaining the key, the tester enters the chip test mode through the test machine, obtains the configuration parameters of the chip, and performs a large amount of complex real-time circuit analysis, and finally understands the design idea and design focus of the circuit.

[0004] Therefore, it is very important to protect the test key of the memory chip through circuit design, which can further protect the configuration parameters of the chip circuit after leaving the factory from being rewritten or researched and copied. SUMMARY

[0005] Therefore, the present application provides a memory chip test key protection method, device and equipment, which aims to protect the test key of the memory chip through circuit design.

[0006] In one aspect, the present application provides a memory chip test key protection method, which comprises:

[0007] When the chip is powered on again, the target key processing module obtains the pre-stored target key and target key enable field. The target key is a key other than the initial key input during the initial test of the chip, and the target key enable field includes a port level signal for controlling the activation of the test control module.

[0008] The target key processing module loads the target key into the target key register which is emptied when power is off;

[0009] The target key processing module controls the enablement of the test control module according to the port level signal of the target key enable field, so that the test control module receives and compares the user input key with the target key to determine whether the user input key is correct.

[0010] Optionally, when the chip is powered on again, the target key processing module obtains the pre-stored target key and target key enable field, specifically including:

[0011] The target key and the target key enable field are written into the start storage module;

[0012] When the chip is powered on again, the target key processing module obtains the target key and the target key enable field loaded from the start storage module by the start logic module.

[0013] Optionally, writing the target key and the target key enable field into the start storage module includes:

[0014] The target key and the target key enable field are written into the start storage module by programming instructions, and the number of times of writing the target key and the target key enable field into the start storage module is determined according to the programmable number of times of the start storage module.

[0015] Optionally, the target key processing module loads the target key into the target key register which is emptied when power is off, further including:

[0016] The target key processing module performs data processing on the target key to form a processed target key;

[0017] The processed target key is loaded into the target key register which is emptied when power is off.

[0018] Optionally, the data processing on the target key includes:

[0019] Inverting the target key, and / or adding a fixed value to the target key.

[0020] Optionally, the chip is powered on again in a second stage, and a first stage is further provided before the second stage, and the first stage includes:

[0021] When the chip is powered on for the first time, the test control module compares whether the user input initial key is consistent with the pre-stored initial key, and if so, the test control module enables the chip initial test by the test enable.

[0022] The chip initial test is completed, and a target key and a target key enable field are written into a start storage module by using a programming instruction, so as to wait for the chip to be powered on again.

[0023] In a second aspect, the application further provides a storage chip test key protection device, which comprises a target key processing module, a target key register and a test control module,

[0024] The target key processing module is used to obtain a target key and a target key enable field which are saved in advance when the chip is powered on again, and load the target key into the target key register which is emptied of data during power-off, wherein the target key is a key other than an initial key input during chip initial test, and the target key enable field comprises a port level signal used to control the activation of the test control module;

[0025] The target key processing module is further used to control the activation of the test control module according to the port level signal of the target key enable field, so that the test control module receives and compares a user input key with the target key to determine whether the user input key is correct.

[0026] The test control module is further provided with an input port used for the user input key.

[0027] Optionally, the device further comprises a start storage module and a start logic module,

[0028] The start storage module is used to store the target key and the target key enable field.

[0029] The start logic module is electrically connected with the start storage module and the target key processing module respectively, and is used to load the target key and the target key enable field in the start storage module into the target key processing module.

[0030] Optionally, the chip is powered on again in a second stage, and a first stage is further provided before the second stage, and in the first stage, the device further comprises an initial key module,

[0031] The initial key module is used to save an initial key, so that the test control module compares the saved initial key with a user input initial key when the chip is powered on, and if the initial keys are consistent, the test control module enables the chip initial test through a test enable, so that after the chip initial test is completed, the target key and the target key enable field are written into the start storage module, so as to wait for the chip to be powered on again.

[0032] In a third aspect, the application further provides a storage chip test key protection device, which comprises a storage and a processor, wherein the storage is used to store a computer program, and the processor realizes the above-mentioned storage chip test key protection method when calling the computer program.

[0033] The embodiment of the present application provides a storage chip test key protection method, device and equipment. In the technical scheme of the present application, compared with the prior art, the fixed circuit form that the test control module directly obtains the saved key and compares the user input key is no longer used, and a target key processing module and a target key register are additionally added. After the chip is powered off each time, the target key register data disappears, the target key processing module can obtain the pre-stored target key and target key enable only when the chip is powered on, the timing is relatively complex, the target key processing module loads the target key storage to the target key register which is emptied after power failure, and the target key processing module controls the test control module to be enabled according to the port level signal of the target key enable field. Only when the target key register obtains the target key and the test control module is in the enabled working state, the user input key and the target key saved in the target key register can be compared, and then it is judged whether the chip test circuit can be started. The circuit complexity is improved, so that it is difficult for other organizations or individuals to obtain the target key and the target key enable field through circuit analysis, and the circuit can well protect the two key information of the target key and the target key enable. BRIEF DESCRIPTION OF DRAWINGS

[0034] To make the technical solutions in the embodiments or the prior art clearer, the accompanying drawings needed in the embodiments or the prior art description will be briefly introduced. Obviously, the accompanying drawings in the following description are only some embodiments of the present application, and other accompanying drawings can be obtained by those skilled in the art without any creative effort on the basis of the accompanying drawings.

[0035] Figure 1 A storage chip test key protection method flow chart is provided for the embodiment of the present application.

[0036] Figure 2 A chip initial power-on test control module starting chip test circuit method flow chart is provided for the embodiment of the present application.

[0037] Figure 3 A method flow chart for obtaining pre-stored target key and target key enable is provided for the embodiment of the present application.

[0038] Figure 4 A storage chip test key protection method scene flow chart is provided for the embodiment of the present application.

[0039] Figure 5 A storage chip test key protection device schematic diagram is provided for the embodiment of the present application.

[0040] Figure 6 A storage chip test key protection device schematic diagram is provided for the embodiment of the present application. DETAILED DESCRIPTION

[0041] In the existing storage chip test protection technology, the test control module obtains the pre-stored initial key from the test initial key, and compares the pre-stored initial key with the user input key, the circuit is simple, the storage chip test protection is not safe, the test key can be easily obtained through the shmoo test or through the logic analysis of the camera circuit, and the instruction in the test mode can also be obtained. Once the test key is cracked, other institutions or individuals can randomly do the test experiment required for circuit analysis, and the risk of excellent circuit being copied is relatively large.

[0042] Compared with the prior art, the inventor considers not to use the fixed circuit form of the test control module directly obtaining the saved key and comparing it with the user input key, and adds a target key processing module and a target key register. After each power-off of the chip, the data of the target key register disappears, the target key processing module can obtain the pre-stored target key and the target key enable only when the chip is powered on, the timing is complex, the target key processing module loads the target key storage into the target key register which is emptied after power failure, and the target key processing module controls the test control module to be enabled according to the port level signal of the target key enable field. Only when the target key is obtained in the target key register and the test control module is in the enabled working state, the user input key and the target key saved in the target key register can be compared, and then it is judged whether the chip test circuit can be started. The circuit complexity is improved, so that other institutions or individuals are difficult to obtain the target key and the target key enable field through circuit analysis. Further, the target key processing module can also save the target key to the target key register after data processing, which improves the difficulty of other institutions or individuals to infer the target key through circuit analysis. Further, the target key and the target key enable are written into the start storage module of the chip test circuit through programming instructions, different target keys can be set for different chip batches, and the protection of the target key is improved. If other institutions or individuals forcibly modify the content of the target key register by focusing ion beam (FIB, Focused Ion beam) and the like, but the bit width of the target key register is large, the modification difficulty is large, even if the modification is successful, it is limited to one chip, and far from the number of chips required for test circuit experiment.

[0043] In the embodiment of the application, the hardware device can include:

[0044] An initial key storage for storing an initial key.

[0045] A target key register for temporarily storing a target key on chip power-on.

[0046] A start storage module for storing a target key and a target key enable.

[0047] A chip test circuit for testing a chip, the start storage module is arranged in the chip test circuit.

[0048] A test control module for comparing a key stored in the chip with a key input by a user, if the keys are consistent, the test control module controls the chip test circuit to start the chip test.

[0049] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work fall within the scope of the present application.

[0050] Figure 1 A flow chart of a storage chip test key protection method is provided for the embodiments of the present application, referring to Figure 1 A storage chip test key protection method comprises the following steps.

[0051] In S101, when the chip is powered on again, the target key processing module obtains a pre-stored target key and a target key enable field.

[0052] The target key is a key other than an initial key input for the first test of the chip, and the chip is powered on again in a second stage. Before the second stage, a first stage is arranged. In the first stage, when the chip is powered on for the first time, the target key and the target key enable field are not saved in the chip test circuit, and the initial key is required to control the start of the chip test circuit. After the first stage, the chip is powered on again using the target key.

[0053] The target key enable field comprises a port level signal for controlling the activation of the test control module.

[0054] In S102, the target key processing module loads the target key to a target key register which is emptied of data when powered off.

[0055] The target key register is a target key register which is emptied of data when powered off. When the chip is not powered on, the key cannot be obtained from the target key register emptied of data by the outside world. After the chip is powered on, the target key processing module can perform data processing on the target key, and load the target key after data processing to the target key register. In this way, the difficulty of obtaining the key by analyzing the circuit and reasoning of other organizations or individuals is increased. Of course, the target key processing module can also not perform data processing on the target key.

[0056] S103, the target key processing module controls the enablement of the test control module according to the port level signal of the target key enable field, so that the test control module receives and compares the user input key with the target key to determine whether the user input key is correct.

[0057] When the chip is powered on, the target key processing module acquires the target key enable field, for example, the field is: FINAL KEY EN = 1, and the target key processing module controls the test control module to be in a working state according to the port level indication of the target key enable field, that is, the test control module is enabled at a high level of the target key enable FINAL KEY EN, and then the test control module can compare the user input key with the target key. However, if the chip is not powered on or the target key enable is incorrect, the test control module cannot be enabled.

[0058] The target key processing module and the target key register are provided in the application, and the data of the target key register disappears after the chip is powered off each time. The target key and the target key enable field are pre-stored in the storage of the chip test circuit through programming instructions. When the chip is powered on each time, the target key processing module reacquires the target key and the target key enable. Compared with the known technology, the application no longer only uses the fixed circuit in the first stage, and the target key and the target key enable field need to be called when the chip is powered on, so as to start the test control module to enter the working state. At this time, the user input key can be compared with the key saved in the target key register by the test control module. The timing and circuit complexity are improved, and the difficulty of reasoning out the final key and the final key enable field by circuit analysis and judgment of other institutions or individuals is improved.

[0059] In an embodiment of the application, the above Figure 1 In the step S101, the chip is powered on again in the second stage, and the first stage is further provided before the second stage. In the first stage, when the chip is powered on for the first time and the target key and the target key enable are not pre-stored, the test control module starts the chip test circuit. The implementation mode is described below. It should be noted that the implementation mode given in the following description is only exemplary and does not represent all implementation modes of the application.

[0060] Figure 2 The chip test circuit method flowchart when the test control module starts the chip test circuit when the chip is powered on for the first time is provided in the embodiment of the application, as shown in Figure 2 The first stage includes:

[0061] S201, when the chip is powered on for the first time, the test control module compares the initial key input by the user with the initial key pre-stored to determine whether they are consistent. If they are consistent, the test control module enables the chip initial test through the test enablement.

[0062] The initial key is the initial key set during chip production, and is used when the chip is first started for chip testing before leaving the factory. When the chip is tested for the first time, the initial key test uses a fixed circuit, and the test control module directly compares the initial key entered by the user with the pre-stored initial key, which can quickly obtain the use permission of the chip test circuit and speed up the chip shipment process.

[0063] S202: After the initial chip test is completed, a programming instruction is used to write the target key and the target key enable field into the startup storage module, and the module is used to wait for the chip to be powered on again.

[0064] After the initial chip test is completed and passed, the chip can be shipped. To prevent other organizations or individuals from analyzing and cracking the circuit, the target key and target key enable field are written into the startup storage module inside the chip test circuit, rather than using a fixed circuit with the initial key to determine the correctness of the key. The target key control module controls the test control module through the target key and target key enable field, increasing the complexity of the circuit and making it more difficult for other organizations or individuals to crack the key through circuit analysis and reasoning.

[0065] The initial key setting is to facilitate the quick startup of the chip before leaving the factory. At this time, the chip has not yet left the factory and the chip is safe. The initial key entered by the user can be directly compared with the pre-saved initial key through the test control module to obtain the use permission of the chip test circuit, thereby improving the efficiency of chip leaving the factory; the target key and target key enable fields are used after the chip leaves the factory, in conjunction with the target key processing module, and the target key and target key enable can only be called when the chip is powered on, which increases the circuit timing complexity and the complexity of the circuit, thereby improving the security of the chip test circuit after the chip leaves the factory.

[0066] In another embodiment of the present application, the above Figure 1 The implementation of step S101 is described in detail below. It should be noted that the implementation described below is only for illustrative purposes and does not represent all implementations of the embodiments of the present application.

[0067] Figure 3 The flowchart of the method for obtaining the pre-saved target key and the target key enabling provided in the embodiment of the present application further explains how the target key processing module re-obtains the target key and the target key enabling. Figure 3 When the chip is powered on again, it obtains the pre-saved target key and target key enable, including:

[0068] S301. Write the target key and the target key enable field into the startup storage module.

[0069] The starting storage module is a starting storage module owned by the chip test circuit, and the chip starting can call the stored data and parameters, the target key and the target key enable field are written into the starting storage module through programming instructions, and the writing times of the target key and the target key enable field into the starting storage module are determined according to the programmable times of the starting storage module.

[0070] S302, the chip is re-powered, and the target key processing module obtains the target key and the target key enable field loaded from the starting storage module by the starting logic module.

[0071] The starting logic can be arranged in the chip test circuit connected with the starting storage module, and the starting logic can also be arranged in the target key processing module connected with the starting storage module in the chip test circuit.

[0072] The chip is re-powered, the starting storage module loads the target key and the target key enable field from the starting storage module to the target key processing module, changes the key stored in the fixed position in the prior art, and the test control module can directly call the compared scheme, and finally the key and the target key enable field are stored in the starting storage area, and need to be loaded through the starting logic, the timing is complex, and the difficulty of competitors to analyze and judge the final key and the final key enable field through the circuit is increased.

[0073] The target key and the target key enable field are written into the starting storage module of the chip test circuit through programming instructions, different chip batches can be set with different target keys, the protection of the target key is improved, when the programmable times of the starting storage module are multiple, the target key in the chip can be changed later, the target key is not unique, and the safety of the chip test circuit is improved.

[0074] The above introduces a storage chip test key protection method provided by the embodiment of the application, and the storage chip test key method is exemplarily described in combination with a specific application scenario.

[0075] Figure 4 A storage chip test key protection method provided by the embodiment of the application is provided, and a scene flow chart is shown in Figure 4 A storage chip test key protection method, comprising:

[0076] S401, the test personnel of the chip design original factory inputs an initial key through a test machine, and the test control module compares the input initial key with a pre-stored initial key, if consistent, the test control module starts the chip initial test through the test enable (TEST_EN=1), and the chip initial test includes the test function of the measured circuit, or the opening of the test path, or the identification of the test instruction.

[0077] The circuit for testing the initial key is a fixed circuit and cannot be changed once it is produced.

[0078] S402: After the initial chip test is completed, the target key and the target key enable field can be written into the startup storage module using a programming instruction, provided that the initial key is correctly matched.

[0079] The stored information will not be lost when the storage module loses power.

[0080] The chip configuration parameters can be written into the boot storage module at the same time. When the chip is powered on again, the chip configuration parameters are protected by the target key and target key enable, which can also reduce tampering and plagiarism of the chip configuration parameters by other organizations or individuals.

[0081] S403: When the chip is powered on again, the boot logic module is responsible for loading the target key and the target key enable field of the boot storage module into the target key processing module of the chip control circuit.

[0082] S404, the target key processing module (Final key process) is responsible for performing data processing such as inverting and / or adding a fixed value to the loaded target key to form a processed target key, and loading the processed target key into the target key register (Final key reg). It is also possible to directly load the target key into the target key register (Final key reg) without performing data processing.

[0083] The target key register is responsible for storing the target key. Every time the power is off, the content of the target key register disappears and waits for power to be re-powered on to load the value.

[0084] The target key processing module outputs a target key enable FINAL_KEY_EN=1 to the test control module for controlling the enabling of the test control module (Test control).

[0085] S405: When the target key is enabled, the tester inputs the target key through the test machine. The test control module is responsible for comparing the input target key with the target key to see if they are consistent. If they are consistent, the chip test is started.

[0086] When the chip is powered on for the first time, the test control module is used to compare the pre-stored initial key with the initial key entered by the user to determine whether to turn on the chip test circuit for testing.

[0087] When the chip is powered on for the first time, the starting storage module is configured to store a target key and a target key enablement, and the starting logic is configured to load the target key and the target key enablement stored in the starting storage module to the target key processing module when the chip is powered on, the target key processing module is configured to load the target key to a target key register, and the target key processing module is further configured to enable the test control module through the target key enablement, and the test control module is configured to compare the final password input by a user with a password in a test key, and if the final password input by the user is consistent with the password in the test key, the chip test circuit can be enabled.

[0088] This embodiment can be implemented in combination with the implementation scenarios.

[0089] The above describes some specific implementation manners of the storage chip test key protection method provided by the embodiment of the present application. Based on this, the present application further provides a corresponding device and equipment.

[0090] The device provided by the embodiment of the present application will be described from the perspective of functional modularization.

[0091] Figure 5 A storage chip test key protection device provided by the embodiment of the present application is shown in FIG. 2. The device 200 includes a target key processing module 210, a target key register 220, and a test control module 230.

[0092] The target key processing module 210 is configured to obtain a target key and a target key enablement field saved in advance when the chip is powered on again, and load the target key to the target key register 220 whose data is emptied when powered off. The target key is a key other than an initial key input for the first test of the chip, and the target key enablement field includes a port level signal for controlling the enablement of the test control module 230.

[0093] The target key processing module 210 is further configured to control the enablement of the test control module 230 according to the port level signal of the target key enablement field, so that the test control module 230 receives and compares the user input key with the target key to determine whether the user input key is correct.

[0094] The test control module 230 is further provided with an input port for the user input key.

[0095] Figure 6 A storage chip test key protection device provided by the embodiment of the present application is shown in FIG. 2. The device 200 includes a target key processing module 210, a target key register 220, and a test control module 230. Figure 6 A storage chip test key protection device, further including: a starting storage module 240 and a starting logic module 250,

[0096] The starting storage module 240 is configured to store the target key and a target key enable field (FINAL_KEY_EN=1).

[0097] The starting logic module 250 is electrically connected with the starting storage module and the target key processing module, and is configured to load the target key and the target key enable field in the starting storage module 240 to the target key processing module 210.

[0098] When the target key processing module obtains the target key enable field, the target key processing module starts the test control module 230 in a working state according to the port level indication of the target key enable field, for example, the field is FINAL_KEY_EN=1, so as to compare the user input key with the target key and determine whether the user input key is correct.

[0099] The chip re-powering is a second stage, and a first stage is further arranged before the second stage.

[0100] The initial key module 260 is configured to save an initial key, so that the test control module compares the saved initial key with a user input initial key when the chip is powered on for the first time, and if the initial keys are consistent, the test control module 230 starts a chip initial test through a test enable (TEST_EN=1), so as to write the target key and the target key enable field into the starting storage module 240 after the chip initial test is completed, and wait for the chip re-powering.

[0101] The type of the starting storage module 240 includes any one of a one-time programmable device, a multi-time programmable device and a flash memory.

[0102] The target key processing module 210, the target key register 220 and the test control module 230 are arranged in the chip control circuit.

[0103] The starting storage module 240 is arranged in the chip test circuit, and the starting logic module 250 can be arranged in the chip test circuit or the target key processing module 210.

[0104] The device provided by the embodiment of the application will be described below.

[0105] The application further provides a storage chip test key protection device, which includes a memory and a processor.

[0106] The various embodiments described in the specification are intended to be exemplary only and the scope of the application is not limited to the embodiments described. The same parts are referred to each other for the same or similar parts among the various embodiments. Each embodiment focuses on the difference from other embodiments. Especially, the device embodiments are described simply because they are basically similar to the method embodiments. The relevant parts are referred to the part of the method embodiments. The part or all modules can be selected to achieve the purpose of the embodiments according to the actual needs. Those skilled in the art can understand and implement without creative labor.

[0107] The above only describes exemplary embodiments of the present application, and is not intended to limit the protection scope of the present application.

Claims

1. A storage chip test key protection method, characterized in that: The method comprises: When the chip is powered on again, the target key processing module obtains the pre-stored target key and target key enable field. The target key is a key other than the initial key input during the initial test of the chip. The target key enable field includes a port level signal for controlling the activation of the test control module. The target key processing module loads the target key into the target key register that clears data when power is turned off; The target key processing module controls the enabling of the test control module according to the port level signal of the target key enable field, so that the test control module receives and compares the user input key with the target key to determine whether it is consistent and whether the user input key is correct.

2. The method according to claim 1, characterized in that When the chip is powered on again, the target key processing module obtains the pre-stored target key and target key enable field, specifically including: Writing the target key and the target key enable field into the boot storage module; The chip is powered on again, and the target key processing module obtains the target key and the target key enable field loaded by the startup logic module from the startup storage module.

3. The method according to claim 2, characterized in that Write the target key and target key enable field to the boot storage module, including: The target key and the target key enable field are written into the startup storage module through a programming instruction, and the number of times the target key and the target key enable field are written into the startup storage module is determined according to the programmable number of times of the startup storage module.

4. The method according to claim 1, wherein The target key processing module loads the target key into the target key register that clears data when power is off, further comprising: The target key processing module performs data processing on the target key to form a processed target key; The processed target key is loaded into the target key register which clears the data when power is turned off.

5. The method according to claim 4, characterized in that Perform data processing on the target key, including: The target key is inverted, and / or a fixed value is added to the target key.

6. The method according to claim 1, characterized in that The chip is powered on again in the second stage. Before the second stage, there is a first stage. The first stage includes: When the chip is powered on for the first time, the test control module compares the initial key entered by the user with the pre-saved initial key to see if they are consistent. If they are consistent, the test control module enables the test to start the initial test of the chip; After the initial chip test is completed, the target key and target key enable field are written into the startup storage module using programming instructions, waiting for the chip to be powered on again.

7. A storage chip test key protection device, characterized in that: Target key processing module, target key register and test control module, The target key processing module is used to obtain the pre-saved target key and target key enable field when the chip is powered on again, and load the target key into the target key register that clears data when the power is off. The target key is a key other than the initial key input during the initial test of the chip. The target key enable field includes a port level signal for controlling the activation of the test control module. The target key processing module is further configured to control the enabling of the test control module according to the port level signal of the target key enable field, so that the test control module receives and compares the user input key with the target key to determine whether it is consistent and whether the user input key is correct; The test control module is also provided with an input port for a user to input a key.

8. The device according to claim 7, characterized in that Further including: Start the storage module and start the logic module, The startup storage module is used to store the target key and the target key enable field; The startup logic module is electrically connected to the startup storage module and the target key processing module respectively, and is used to load the target key and the target key enable field in the startup storage module into the target key processing module.

9. The device according to claim 7, characterized in that The chip is powered on again as the second stage. Before the second stage, there is a first stage. In the first stage, the device further includes: an initial key module, The initial key module is used to save the initial key so that the test control module can compare the saved initial key with the initial key input by the user when the chip is powered on for the first time to see if they are consistent. If they are consistent, the test control module starts the initial test of the chip through the test enable, so that after the initial test of the chip is completed, the target key and the target key enable field are written to the startup storage module to wait for the chip to be powered on again.

10. A storage chip test key protection device, characterized in that: The invention comprises a memory and a processor, wherein the memory is used to store a computer program, and when the processor calls the computer program, the method for protecting a storage chip test key according to any one of claims 1 to 6 is implemented.

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