Wafer testing system and testing methods

Abstract

This invention provides a wafer testing system and method, applicable to the field of semiconductor testing technology. Specifically, it expands upon the existing identifier UID (Unique Identifier) ​​obtained using conventional algorithms to uniquely identify each chip by adding multiple sub-dimension data information, thus obtaining a newly proposed multi-dimensional identifier UID. Then, during the testing of the chips contained in the wafer, the multi-dimensional identifier UID formed by this invention is first written into the chip during the testing process. Then, using other testing steps, the identifier UID actually written into the chip during the testing process is finally obtained at the end of the test. Finally, by comparing the multi-dimensional identifier UID with the identifier UID actually written into the chip during the testing process, the uniqueness, accuracy, and security of the identifier UID written into the chip during the testing process can be accurately determined.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and in particular to a wafer testing system and testing method. Background Technology

[0002] Wafer testing, abbreviated as CP testing, is a crucial step in the back-end testing and packaging of integrated circuits. CP testing involves electrical testing of the bare wafer, requiring testing of every single die on the wafer. Dies that pass the test are considered good, while those that fail are considered defective. If the yield meets requirements, the wafer testing passes. If the yield is low, engineers need to intervene to detect problems in the wafer manufacturing process. Defective products are repaired if possible.

[0003] In CP testing, CP test data is a crucial basis for wafer shipment. Therefore, the processing and analysis of CP test data, as well as the methods for handling wafers based on test results, are even more critical. For example, currently, in chips such as bank cards, ID cards, and passports, it is necessary to write UID (Unique Identifier) ​​data for each chip. In existing technologies, the UID information of each chip is extracted one by one from the UID file and then written into qualified chips. Afterwards, the wafer is read and verified during the wafer testing process to ensure that the UID information data to be written to each chip in the wafer is correctly written into the corresponding chip.

[0004] However, existing technologies cannot avoid problems such as file corruption or test machine malfunctions during wafer testing, which can lead to errors in reading the UID information of each chip in the test wafer, resulting in incorrect UID information actually written to the chip. Furthermore, they lack the necessary post-testing and retrieval verification technologies. Summary of the Invention

[0005] The purpose of this invention is to provide a wafer testing method to improve the accuracy and stability of the identifier (UID) written into each chip for unique chip identification during wafer testing.

[0006] In a first aspect, to solve the above-mentioned technical problems, the present invention provides a wafer testing method, comprising the following steps:

[0007] Multiple different batches of wafers are acquired, each batch contains multiple wafers, and each wafer has several chips. The first identifier UID of each chip in each batch of wafers is determined.

[0008] Multi-step testing is performed on the different batches of wafers. In the first step of the test, the first identifier UID corresponding to each chip is written into each chip in each batch of wafers. After the multi-step test, the second identifier UID of each chip in each batch of wafers is obtained.

[0009] For each chip in each batch of wafers, the first identifier UID and the second identifier UID of the chip are compared. If they match, it is determined that the identifier UID written to the chip in this test meets the design requirements.

[0010] Furthermore, the first identifier UID may include 5-dimensional data information.

[0011] Furthermore, the 5D data information may include: the chip's ID, the LotID of the batch wafer to which the chip belongs, the wafer ID of the wafer to which the chip belongs, and the X and Y coordinates of the chip within its wafer.

[0012] Furthermore, after comparing the first identifier UID and the second identifier UID of each chip in each batch of wafers to determine whether the identifier UID written for each chip in this test meets the design requirements, the method may further include:

[0013] For each batch of wafers, count the number of chips in that batch whose identifier UID meets the design requirements, and perform duplicate checking and recycling of the first identifier UID of chips whose identifier UID does not meet the design requirements.

[0014] Secondly, the present invention also provides an electronic device, including a processor, a communication interface, a memory, and a communication bus, wherein the processor, the communication interface, and the memory communicate with each other through the communication bus.

[0015] Memory is used to store computer programs.

[0016] When a processor executes a program stored in memory, it implements the defect detection method steps of a semiconductor device as described above.

[0017] Thirdly, embodiments of the present invention also provide a computer-readable storage medium storing a computer program, which, when executed by a processor, implements the defect detection method steps of any of the above-described semiconductor devices.

[0018] Compared with the prior art, the technical solution of the present invention has at least one of the following beneficial effects:

[0019] This invention provides a wafer testing system and method. Specifically, the wafer testing method provided by this invention expands upon the existing identifier UID (User Identifier) ​​obtained using conventional algorithms to uniquely identify each chip by adding multiple sub-dimensional data information, thus obtaining a newly proposed multi-dimensional identifier UID (first identifier UID). Then, during the testing of the chips contained in the wafer, the multi-dimensional identifier UID (first identifier UID) formed by this invention is first written into the chip. Then, using other testing steps, the identifier UID (second identifier UID) actually written into the chip during the testing process is finally obtained at the end of the test. Finally, by comparing the multi-dimensional identifier UID (first identifier UID) with the identifier UID actually written into the chip during the test, the uniqueness, accuracy, and security of the identifier UID (second identifier UID) written into the chip during the test can be accurately determined.

[0020] Furthermore, in the wafer testing method provided by the present invention, after obtaining a highly accurate first identifier UID from the source using the multi-dimensional identifier formation method of the present invention, it can also use the multi-dimensional identifier UID (first identifier UID) to perform verification, deduplication and recycling functions on the identifiers written to the wafer during the testing process. Attached Figure Description

[0021] Figure 1 This is a schematic flowchart of a wafer testing method provided in one embodiment of the present invention.

[0022] Figure 2 This is a schematic diagram of the structure of the first identifier UID formed using the algorithm provided by the present invention in one embodiment of the present invention.

[0023] Figure 3 This is a schematic diagram of the structure of a wafer testing system provided in one embodiment of the present invention. Detailed Implementation

[0024] As described in the background section, in current chip processing (CP) testing, CP test data is a crucial basis for wafer shipment. Therefore, the processing and analysis of CP test data, and the methods for handling wafers based on test results, are critical. For example, in chips used in bank cards, ID cards, and passports, each chip needs to have its UID (Unique Identifier) ​​data written to it. Current technology extracts the UID information of each chip from a UID file one by one, then writes it to a qualified chip, and then verifies the data during wafer testing to ensure that the UID information intended for each chip is correctly written to the corresponding chip. However, existing technology cannot avoid errors in reading the UID information of each chip in the test wafer due to file corruption or test machine malfunctions during wafer testing, resulting in incorrect UID information actually written to the chip. Furthermore, it lacks necessary post-testing and deduplication verification technologies.

[0025] To address this problem, the researchers of this invention discovered that the fundamental reason for the unavoidable errors in reading the UID information of each chip in the test wafer during wafer testing, such as file corruption or test machine malfunctions, is that the identifier UID formed in existing technologies contains too little data. When a write error occurs during testing, it cannot be accurately verified, retrieved, or deduplicated subsequently. Based on this, the researchers of this invention propose a wafer testing system and method to improve the accuracy and stability of the identifier UID written to each chip during wafer testing.

[0026] The wafer testing system and testing method proposed in this invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of this invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of this invention. Many specific details are set forth in the following description to provide a thorough understanding of this invention; however, this invention may also be implemented in other ways different from those described herein, and therefore this invention is not limited to the specific embodiments disclosed below.

[0027] As shown in this application and claims, unless the context clearly indicates otherwise, the words "a," "an," "an," and / or "the" do not specifically refer to the singular and may also include the plural. Generally speaking, the terms "comprising" and "including" only indicate the inclusion of explicitly identified steps and elements, which do not constitute an exclusive list, and the method or apparatus may also include other steps or elements. In detailing the embodiments of the present invention, for ease of explanation, the cross-sectional views showing the device structure may be partially enlarged without adhering to the general scale, and the schematic diagrams are merely examples and should not limit the scope of protection of the present invention. Furthermore, in actual manufacturing, the three-dimensional spatial dimensions of length, width, and depth should be included.

[0028] The following section provides a detailed description of a wafer testing method provided by this invention.

[0029] Specific reference Figure 1 , Figure 1 This is a schematic flowchart of a wafer testing method provided by an embodiment of the present invention. Specifically, the wafer testing method includes at least the following steps:

[0030] Step S100: Obtain multiple different batches of wafers, each batch containing multiple wafers, each wafer having several chips, and determine the first identifier UID of each chip in each batch of wafers.

[0031] In this embodiment, multiple batches of wafers (wafers) can be provided, each wafer containing multiple chips, for example, 20 chips. All chips on the wafer have various patterns, some identical and some different. Typically, in existing semiconductor processes, chips with patterned structures undergo a series of tests before leaving the factory for customer delivery to ensure a high pass rate. During testing, to distinguish between different chips on the same wafer, it is usually necessary to assign a unique identifier (UID) to each chip, which is then written into the chip during testing. In this invention, a specific algorithm is used to expand the dimensions of the existing UID, thereby forming a multi-dimensional identifier UID proposed in this invention, namely, the first identifier UID.

[0032] As an example, the first identifier UID provided in this invention may include 5-dimensional data information, specifically the chip ID, the LotID of the batch wafer to which the chip belongs, the wafer ID of the wafer to which the chip belongs, and the X and Y coordinates of the chip within its wafer. The following specific example illustrates the specific data information contained in the first identifier UID proposed in this invention. Figure 2As shown, 1, 2, 3, 4 and 5 represent the 5 dimensions of the first identifier UID, where 1, for example, 00000001 is the chip ID, 2, for example, C00001 is the LotID of the batch wafer to which the chip belongs, 3, for example, #1 is the wafer ID of the wafer to which the chip belongs, 4, for example, 01 is the X coordinate of the chip within its wafer, and 5, for example, 01 is the Y coordinate of the chip within its wafer.

[0033] Step S200: Perform multi-step tests on the different batches of wafers, so that in the first step test, the first identifier UID corresponding to each chip is written into each chip in each batch of wafers, and after the multi-step tests, the second identifier UID of each chip in each batch of wafers is obtained.

[0034] In this embodiment, when testing different batches of wafers, each chip in each wafer can be tested, or a subset of chips (samples) can be selected from the wafer for testing. Specifically, during the wafer testing process, the first identifier UID, which uniquely and accurately identifies the chip using the multi-dimensional method formed by this invention, can be written into each chip in each batch of wafers. Then, each chip is subjected to subsequent multi-step testing with its corresponding first identifier UID to test each different function of the chip. After the final test step of this or round of wafer testing, in addition to the multiple test functions performed on the tested wafer, the results also include the identifier (second identifier UID) actually written by the test equipment during this or round of testing.

[0035] Step S300: For each chip in each batch of wafers, compare the first identifier UID and the second identifier UID of the chip. If they match, it is determined that the identifier UID written to the chip in this test meets the design requirements.

[0036] In this embodiment, after obtaining the first identifier UID and the second identifier UID of each chip in step S200, the first identifier UID and the second identifier UID of the chip can be compared. If the comparison result is consistent, it indicates that no chip identifier writing error or identifier error caused by multi-step testing occurred during this test or round of testing; otherwise, it indicates that a chip identifier writing error or identifier error caused by multi-step testing occurred during this test or round of testing. For these chips that have erroneous results, this embodiment of the invention further provides subsequent steps for deduplication and recycling.

[0037] Specifically, after comparing the first identifier UID and the second identifier UID of each chip in each batch of wafers to determine whether the identifier UID written for each chip in this test meets the design requirements, the method may further include the following steps:

[0038] For each batch of wafers, count the number of chips in that batch whose identifier UID meets the design requirements, and perform duplicate checking and recycling of the first identifier UID of chips whose identifier UID does not meet the design requirements.

[0039] In this embodiment, after determining in step S300 that at least one chip in different batches of wafers has encountered problems such as chip identifier writing errors and identifier errors caused by multi-step testing, it is possible to first check which dimensions of the second identifier UID written in the chip have sent errors compared to the first identifier UID pre-set by the present invention, that is, to achieve the function of deduplication. Then, the unused first identifier UID is recycled, thus achieving the function of recycling.

[0040] Based on the same inventive concept, the present invention also provides a wafer testing system, which may specifically include the following modules:

[0041] The first identifier UID determination module 310 is used to acquire multiple different batches of wafers, each batch containing multiple wafers, each wafer having several chips, and to determine the first identifier UID of each chip in each batch of wafers;

[0042] The test module 320 is used to perform multi-step tests on the different batches of wafers, so as to write the first identifier UID corresponding to each chip into each chip in each batch of wafers in the first step test, and obtain the second identifier UID of each chip in each batch of wafers after the multi-step test.

[0043] The identifier UID comparison module 330 is used to compare the first identifier UID and the second identifier UID of each chip in each batch of wafers. If the comparison is consistent, it is determined that the identifier UID written to the chip in this test meets the design requirements.

[0044] The first identifier, UID, can include 5-dimensional data information. Specifically, the 5-dimensional data information can include: the chip's ID, the LotID of the batch wafer to which the chip belongs, the wafer ID of the wafer to which the chip belongs, and the X and Y coordinates of the chip within its wafer.

[0045] In addition to the above, the wafer testing system provided by this invention may also include:

[0046] The recycling module is used to count the number of chips in each batch of wafers whose identifier UID meets the design requirements, and to perform duplicate checking and recycling of the first identifier UID of chips whose identifier UID does not meet the design requirements.

[0047] In summary, this invention provides a wafer testing system and method. Specifically, the wafer testing method provided by this invention expands upon the UID (Unique Identifier) ​​obtained using conventional algorithms in the prior art, which can uniquely identify each chip, by adding multiple sub-dimensional data information to obtain a newly proposed multi-dimensional identifier UID (first identifier UID). Then, during the testing of the chips contained in the wafer, the multi-dimensional identifier UID (first identifier UID) formed by this invention is first written into the chip. Then, using other testing steps, the identifier UID (second identifier UID) actually written into the chip during the testing process is finally obtained at the end of the test. Finally, by comparing the multi-dimensional identifier UID (first identifier UID) with the identifier UID actually written into the chip during the testing process, the uniqueness, accuracy, and security of the identifier UID (second identifier UID) written into the chip during the testing process can be accurately determined.

[0048] Furthermore, in the wafer testing method provided by the present invention, after obtaining a highly accurate first identifier UID from the source using the multi-dimensional identifier formation method of the present invention, it can also use the multi-dimensional identifier UID (first identifier UID) to perform verification, deduplication and recycling functions on the identifiers written to the wafer during the testing process.

[0049] Furthermore, embodiments of the present invention also provide an electronic device, including a processor, a communication interface, a memory, and a communication bus, wherein the processor, the communication interface, and the memory communicate with each other via the communication bus.

[0050] Memory, used to store computer programs;

[0051] The processor, when executing a program stored in memory, implements a wafer testing method provided in this embodiment of the invention.

[0052] Specifically, the above-mentioned wafer testing method includes: acquiring multiple different batches of wafers, each batch containing multiple wafers, each wafer having several chips, and determining a first identifier UID for each chip in each batch of wafers;

[0053] Multi-step testing is performed on the different batches of wafers. In the first step of the test, the first identifier UID corresponding to each chip is written into each chip in each batch of wafers. After the multi-step test, the second identifier UID of each chip in each batch of wafers is obtained.

[0054] For each chip in each batch of wafers, the first identifier UID and the second identifier UID of the chip are compared. If they match, it is determined that the identifier UID written to the chip in this test meets the design requirements.

[0055] For details on the implementation of each step of this method and related explanations, please refer to the above. Figure 1 The method embodiments shown are not described in detail here.

[0056] In addition, other implementations of a wafer testing method implemented by the processor executing a program stored in the memory are the same as those mentioned in the aforementioned method embodiment section, and will not be repeated here.

[0057] The communication bus mentioned in the above electronic devices can be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. This communication bus can be divided into address bus, data bus, control bus, etc. For ease of illustration, only one thick line is used to represent it in the diagram, but this does not mean that there is only one bus or one type of bus.

[0058] The communication interface is used for communication between the aforementioned electronic devices and other devices.

[0059] The memory may include random access memory (RAM) or non-volatile memory (NVM), such as at least one disk storage device. Optionally, the memory may also be at least one storage device located remotely from the aforementioned processor.

[0060] The processors mentioned above can be general-purpose processors, including central processing units (CPUs), network processors (NPs), etc.; they can also be digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components.

[0061] In another embodiment of the present invention, a computer-readable storage medium is also provided, which stores instructions that, when executed on a computer, cause the computer to perform any of the wafer testing methods described in the above embodiments.

[0062] In the above embodiments, implementation can be achieved entirely or partially through software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented entirely or partially in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of the present invention are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that integrates one or more available media. The available medium can be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., solid state disk (SSD)).

[0063] It should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply the existence of any such actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or device comprising the element.

[0064] The various embodiments in this specification are described in a related manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, the embodiments of apparatus, electronic devices, and computer-readable storage media are basically similar to the method embodiments, and therefore the descriptions are relatively simple; relevant parts can be referred to the descriptions of the method embodiments.

[0065] The above description is merely a preferred embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention are included within the scope of protection of the present invention.

Claims

1. A wafer testing method, characterized in that, Includes the following steps: Multiple different batches of wafers are acquired, each batch contains multiple wafers, and each wafer has several chips. The first identifier UID of each chip in each batch of wafers is determined. Multi-step testing is performed on the different batches of wafers. In the first step of the test, the first identifier UID corresponding to each chip is written into each chip in each batch of wafers. After the multi-step test, the second identifier UID of each chip in each batch of wafers is obtained. The second identifier, UID, was actually written using the test equipment; For each chip in each batch of wafers, the first identifier UID and the second identifier UID of the chip are compared. If they match, it is determined that the identifier UID written to the chip in this test meets the design requirements.

2. The wafer testing method as described in claim 1, characterized in that, The first identifier UID includes 5-dimensional data information.

3. The wafer testing method as described in claim 2, characterized in that, The 5D data information includes: the chip's ID, the Lot ID of the batch wafer to which the chip belongs, the wafer ID of the wafer to which the chip belongs, and the X and Y coordinates of the chip within its wafer.

4. The wafer testing method as described in claim 3, characterized in that, After comparing the first identifier UID and the second identifier UID of each chip in each batch of wafers to determine whether the identifier UID written for each chip in this test meets the design requirements, the method further includes: For each batch of wafers, count the number of chips in that batch whose identifier UID meets the design requirements, and perform duplicate checking and recycling of the first identifier UID of chips whose identifier UID does not meet the design requirements.

5. A wafer testing system, characterized in that, include: The first identifier UID determination module is used to obtain multiple different batches of wafers, each batch containing multiple wafers, each wafer having several chips, and to determine the first identifier UID of each chip in each batch of wafers; The testing module is used to perform multi-step testing on the different batches of wafers, so that in the first step of the test, the first identifier UID corresponding to each chip is written into each chip in each batch of wafers, and after the multi-step test, the second identifier UID of each chip in each batch of wafers is obtained. The second identifier, UID, was actually written using the test equipment; The identifier UID comparison module is used to compare the first identifier UID and the second identifier UID of each chip in each batch of wafers. If the comparison is consistent, it is determined that the identifier UID written to the chip in this test meets the design requirements.

6. The wafer testing system as described in claim 5, characterized in that, The first identifier UID includes 5-dimensional data information.

7. The wafer testing system as described in claim 6, characterized in that, The 5D data information includes: the chip's ID, the Lot ID of the batch wafer to which the chip belongs, the wafer ID of the wafer to which the chip belongs, and the X and Y coordinates of the chip within its wafer.

8. The wafer testing system as described in claim 5, characterized in that, The wafer testing system also includes: The recycling module is used to count the number of chips in each batch of wafers whose identifier UID meets the design requirements, and to perform duplicate checking and recycling of the first identifier UID of chips whose identifier UID does not meet the design requirements.

9. An electronic device, characterized in that, It includes a processor, a communication interface, a memory, and a communication bus, wherein the processor, the communication interface, and the memory communicate with each other through the communication bus; Memory, used to store computer programs; When a processor executes a program stored in memory, it implements the wafer testing method steps according to any one of claims 1-4.

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